ARM: tegra: remove vpr refetch call from kernel
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2014 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_fdt.h>
35 #include <linux/pstore_ram.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/sys_soc.h>
38 #include <linux/tegra-pmc.h>
39 #if defined(CONFIG_SMSC911X)
40 #include <linux/smsc911x.h>
41 #endif
42 #include <linux/pm.h>
43 #include <linux/tegra-powergate.h>
44
45 #include <linux/export.h>
46 #include <linux/bootmem.h>
47 #include <linux/tegra-soc.h>
48 #include <linux/dma-contiguous.h>
49 #include <linux/tegra-fuse.h>
50 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
51 #include <linux/ote_protocol.h>
52 #endif
53 #include <linux/gk20a.h>
54
55 #ifdef CONFIG_ARM64
56 #include <linux/irqchip/arm-gic.h>
57 #include <asm/system_info.h>
58 #else
59 #include <asm/system.h>
60 #include <asm/hardware/cache-l2x0.h>
61 #endif
62 #include <asm/dma-mapping.h>
63
64 #include <mach/tegra_smmu.h>
65 #include <mach/nct.h>
66 #include <mach/dc.h>
67
68 #include "apbio.h"
69 #include "board.h"
70 #include "clock.h"
71 #include "common.h"
72 #include "dvfs.h"
73 #include "iomap.h"
74 #include "pm.h"
75 #include "sleep.h"
76 #include "reset.h"
77 #include "devices.h"
78
79 #define MC_SECURITY_CFG2        0x7c
80
81 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
82 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
83 #define   PRIORITY_SELECT_USB   BIT(6)
84 #define   PRIORITY_SELECT_USB2  BIT(18)
85 #define   PRIORITY_SELECT_USB3  BIT(17)
86 #define   PRIORITY_SELECT_SE BIT(14)
87
88 #define AHB_GIZMO_AHB_MEM               0xc
89 #define   ENB_FAST_REARBITRATE  BIT(2)
90 #define   DONT_SPLIT_AHB_WR     BIT(7)
91 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
92 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
93
94 #define   RECOVERY_MODE BIT(31)
95 #define   BOOTLOADER_MODE       BIT(30)
96 #define   FORCED_RECOVERY_MODE  BIT(1)
97
98 #define AHB_GIZMO_USB           0x1c
99 #define AHB_GIZMO_USB2          0x78
100 #define AHB_GIZMO_USB3          0x7c
101 #define AHB_GIZMO_SE            0x4c
102 #define   IMMEDIATE     BIT(18)
103
104 #define AHB_MEM_PREFETCH_CFG5   0xc8
105 #define AHB_MEM_PREFETCH_CFG3   0xe0
106 #define AHB_MEM_PREFETCH_CFG4   0xe4
107 #define AHB_MEM_PREFETCH_CFG1   0xec
108 #define AHB_MEM_PREFETCH_CFG2   0xf0
109 #define AHB_MEM_PREFETCH_CFG6   0xcc
110 #define   PREFETCH_ENB  BIT(31)
111 #define   MST_ID(x)     (((x) & 0x1f) << 26)
112 #define   AHBDMA_MST_ID MST_ID(5)
113 #define   USB_MST_ID    MST_ID(6)
114 #define SDMMC4_MST_ID   MST_ID(12)
115 #define   USB2_MST_ID   MST_ID(18)
116 #define   USB3_MST_ID   MST_ID(17)
117 #define   SE_MST_ID     MST_ID(14)
118 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
119 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
120
121 #ifdef CONFIG_PSTORE_RAM
122 #define RAMOOPS_MEM_SIZE SZ_2M
123 #define FTRACE_MEM_SIZE SZ_1M
124 #endif
125
126 phys_addr_t tegra_bootloader_fb_start;
127 phys_addr_t tegra_bootloader_fb_size;
128 phys_addr_t tegra_bootloader_fb2_start;
129 phys_addr_t tegra_bootloader_fb2_size;
130 phys_addr_t tegra_fb_start;
131 phys_addr_t tegra_fb_size;
132 phys_addr_t tegra_fb2_start;
133 phys_addr_t tegra_fb2_size;
134 phys_addr_t tegra_carveout_start;
135 phys_addr_t tegra_carveout_size;
136 phys_addr_t tegra_vpr_start;
137 phys_addr_t tegra_vpr_size;
138 phys_addr_t tegra_tsec_start;
139 phys_addr_t tegra_tsec_size;
140 phys_addr_t tegra_lp0_vec_start;
141 phys_addr_t tegra_lp0_vec_size;
142 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
143 phys_addr_t tegra_wb0_params_address;
144 phys_addr_t tegra_wb0_params_instances;
145 phys_addr_t tegra_wb0_params_block_size;
146 #endif
147
148 #ifdef CONFIG_TEGRA_NVDUMPER
149 unsigned long nvdumper_reserved;
150 #endif
151 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
152 unsigned long tegra_tzram_start;
153 unsigned long tegra_tzram_size;
154 #endif
155 bool tegra_lp0_vec_relocate;
156 unsigned long tegra_grhost_aperture = ~0ul;
157 static   bool is_tegra_debug_uart_hsport;
158 static struct board_info main_board_info;
159 static struct board_info pmu_board_info;
160 static struct board_info display_board_info;
161 static int panel_id;
162 static struct board_info camera_board_info;
163 static int touch_vendor_id;
164 static int touch_panel_id;
165 static struct board_info io_board_info;
166 static struct board_info button_board_info;
167 static struct board_info joystick_board_info;
168 static struct board_info rightspeaker_board_info;
169 static struct board_info leftspeaker_board_info;
170 #ifdef CONFIG_TEGRA_USE_NCT
171 unsigned long tegra_nck_start;
172 unsigned long tegra_nck_size;
173 #endif
174
175 int tegra_with_secure_firmware;
176
177 static int pmu_core_edp;
178 static int board_panel_type;
179 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
180 static int pwr_i2c_clk = 400;
181 static u8 power_config;
182 static u8 display_config;
183
184 static int tegra_split_mem_set;
185
186 struct device tegra_generic_cma_dev;
187 struct device tegra_vpr_cma_dev;
188
189 struct device tegra_generic_dev;
190
191 struct device tegra_vpr_dev;
192 EXPORT_SYMBOL(tegra_vpr_dev);
193
194 struct device tegra_iram_dev;
195 EXPORT_SYMBOL(tegra_iram_dev);
196
197 #define CREATE_TRACE_POINTS
198 #include <trace/events/nvsecurity.h>
199
200 static void tegra_update_resize_cfg(phys_addr_t base , size_t size)
201 {
202 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
203         int err = 0;
204
205         err = gk20a_do_idle();
206         if (!err) {
207                 /* Config VPR_BOM/_SIZE in MC */
208                 te_set_vpr_params((void *)(uintptr_t)base, size);
209                 gk20a_do_unidle();
210         }
211 #endif
212 }
213
214 struct dma_resize_notifier_ops vpr_dev_ops = {
215         .resize = tegra_update_resize_cfg
216 };
217
218 u32 notrace tegra_read_cycle(void)
219 {
220         u32 cycle_count;
221
222 #ifdef CONFIG_ARM64
223         asm volatile("mrs %0, pmccntr_el0" : "=r"(cycle_count));
224 #else
225         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cycle_count));
226 #endif
227
228         return cycle_count;
229 }
230
231 /*
232  * Storage for debug-macro.S's state.
233  *
234  * This must be in .data not .bss so that it gets initialized each time the
235  * kernel is loaded. The data is declared here rather than debug-macro.S so
236  * that multiple inclusions of debug-macro.S point at the same data.
237  */
238 u32 tegra_uart_config[4] = {
239         /* Debug UART initialization required */
240         1,
241         /* Debug UART physical address */
242         0,
243         /* Debug UART virtual address */
244         0,
245         /* Scratch space for debug macro */
246         0,
247 };
248
249
250 #define NEVER_RESET 0
251 static DEFINE_SPINLOCK(ahb_lock);
252
253 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
254 {
255         unsigned long check;
256         int retry = 10;
257         unsigned long flags;
258
259         /* Read and check if write is successful,
260          * if val doesn't match with read, retry write.
261          */
262         spin_lock_irqsave(&ahb_lock, flags);
263         do {
264                 writel(val, reg);
265                 check = readl(reg);
266                 if (likely(check == val))
267                         break;
268                 else
269                         pr_err("AHB register access fail for reg\n");
270         } while (--retry);
271         spin_unlock_irqrestore(&ahb_lock, flags);
272 }
273
274 void tegra_assert_system_reset(char mode, const char *cmd)
275 {
276         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
277         u32 reg;
278         bool empty_command = false;
279
280         if (tegra_platform_is_fpga() || NEVER_RESET) {
281                 pr_info("tegra_assert_system_reset() ignored.....");
282                 do { } while (1);
283         }
284
285         reg = readl_relaxed(reset + PMC_SCRATCH0);
286         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
287         if (cmd) {
288                 if (!strcmp(cmd, "recovery"))
289                         reg |= RECOVERY_MODE;
290                 else if (!strcmp(cmd, "bootloader"))
291                         reg |= BOOTLOADER_MODE;
292                 else if (!strcmp(cmd, "forced-recovery"))
293                         reg |= FORCED_RECOVERY_MODE;
294                 else {
295                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
296                         empty_command = true;
297                 }
298         }
299         else {
300                 /* Clearing SCRATCH0 31:30:1 on default reboot */
301                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
302         }
303         writel_relaxed(reg, reset + PMC_SCRATCH0);
304         if ((!cmd || empty_command) && pm_power_reset) {
305                 pm_power_reset();
306         } else {
307                 reg = readl_relaxed(reset);
308                 reg |= 0x10;
309                 writel_relaxed(reg, reset);
310         }
311 }
312 static int modem_id;
313 static int commchip_id;
314 static int sku_override;
315 static int debug_uart_port_id;
316 static bool uart_over_sd;
317 static enum audio_codec_type audio_codec_name;
318 static enum image_type board_image_type = system_image;
319 static int max_cpu_current;
320 static int max_core_current;
321 static int emc_max_dvfs;
322 static unsigned int memory_type;
323 static int usb_port_owner_info;
324 static int lane_owner_info;
325
326 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
327 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
328         /* name         parent          rate            enabled */
329         { "clk_m",      NULL,           0,              true },
330         { "emc",        NULL,           0,              true },
331         { "cpu",        NULL,           0,              true },
332         { "kfuse",      NULL,           0,              true },
333         { "fuse",       NULL,           0,              true },
334         { "sclk",       NULL,           0,              true },
335         { "pll_p",      NULL,           0,              true },
336         { "pll_p_out1", "pll_p",        0,              false },
337         { "pll_p_out3", "pll_p",        0,              false },
338 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
339         { "pll_m_out1", "pll_m",        275000000,      false },
340         { "pll_p_out2",  "pll_p",       102000000,      false },
341         { "sclk",        "pll_p_out2",  102000000,      true },
342         { "pll_p_out4",  "pll_p",       204000000,      true },
343         { "hclk",       "sclk",         102000000,      true },
344         { "pclk",       "hclk",         51000000,       true },
345         { "mselect",    "pll_p",        102000000,      true },
346         { "host1x",     "pll_p",        102000000,      false },
347         { "cl_dvfs_ref", "pll_p",       51000000,       true },
348         { "cl_dvfs_soc", "pll_p",       51000000,       true },
349         { "dsialp", "pll_p",    70000000,       false },
350         { "dsiblp", "pll_p",    70000000,       false },
351 #else
352         { "pll_m_out1", "pll_m",        275000000,      true },
353         { "pll_p_out2", "pll_p",        108000000,      false },
354         { "sclk",       "pll_p_out2",   108000000,      true },
355         { "pll_p_out4", "pll_p",        216000000,      true },
356         { "hclk",       "sclk",         108000000,      true },
357         { "pclk",       "hclk",         54000000,       true },
358         { "mselect",    "pll_p",        108000000,      true },
359         { "host1x",     "pll_p",        108000000,      false },
360         { "cl_dvfs_ref", "clk_m",       13000000,       false },
361         { "cl_dvfs_soc", "clk_m",       13000000,       false },
362 #endif
363 #ifdef CONFIG_TEGRA_SLOW_CSITE
364         { "csite",      "clk_m",        1000000,        true },
365 #else
366         { "csite",      NULL,           0,              true },
367 #endif
368         { "pll_u",      NULL,           480000000,      true },
369         { "pll_re_vco", NULL,           612000000,      true },
370         { "xusb_falcon_src",    "pll_p",        204000000,      false},
371         { "xusb_host_src",      "pll_p",        102000000,      false},
372         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
373         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
374         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
375         { "sdmmc1",     "pll_p",        48000000,       false},
376         { "sdmmc3",     "pll_p",        48000000,       false},
377         { "sdmmc4",     "pll_p",        48000000,       false},
378         { "sbc1.sclk",  NULL,           40000000,       false},
379         { "sbc2.sclk",  NULL,           40000000,       false},
380         { "sbc3.sclk",  NULL,           40000000,       false},
381         { "sbc4.sclk",  NULL,           40000000,       false},
382         { "sbc5.sclk",  NULL,           40000000,       false},
383         { "sbc6.sclk",  NULL,           40000000,       false},
384 #ifdef CONFIG_TEGRA_DUAL_CBUS
385         { "c2bus",      "pll_c2",       250000000,      false },
386         { "c3bus",      "pll_c3",       250000000,      false },
387         { "pll_c",      NULL,           624000000,      false },
388 #else
389         { "cbus",       "pll_c",        250000000,      false },
390 #endif
391         { "pll_c_out1", "pll_c",        150000000,      false },
392 #ifdef CONFIG_TEGRA_PLLM_SCALED
393         { "vi",         "pll_p",        0,              false},
394 #endif
395 #ifdef CONFIG_TEGRA_SOCTHERM
396         { "soc_therm",  "pll_p",        136000000,      false },
397         { "tsensor",    "clk_m",        500000,         false },
398 #endif
399         { "csite",      NULL,           0,              true },
400         { NULL,         NULL,           0,              0},
401 };
402 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
403 #ifdef CONFIG_TEGRA_DUAL_CBUS
404         { "c2bus",      "pll_c2",       250000000,      false },
405         { "c3bus",      "pll_c3",       250000000,      false },
406         { "pll_c",      NULL,           624000000,      false },
407 #else
408         { "cbus",       "pll_c",        250000000,      false },
409 #endif
410         { "pll_c_out1", "pll_c",        150000000,      false },
411         { NULL,         NULL,           0,              0},
412 };
413 #endif
414 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
415 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
416         /* name         parent          rate            enabled */
417         { "clk_m",      NULL,           0,              true },
418         { "mc",         NULL,           0,              true },
419         { "cpu",        NULL,           0,              true },
420         { "kfuse",      NULL,           0,              true },
421         { "fuse",       NULL,           0,              true },
422         { "sclk",       NULL,           0,              true },
423         { "pll_p",      NULL,           0,              true,
424                 TEGRA_CLK_INIT_PLATFORM_SI },
425         { "pll_p_out1", "pll_p",        0,              false,
426                 TEGRA_CLK_INIT_PLATFORM_SI },
427         { "pll_p_out3", "pll_p",        0,              true,
428                 TEGRA_CLK_INIT_PLATFORM_SI },
429         { "pll_m_out1", "pll_m",        275000000,      false,
430                 TEGRA_CLK_INIT_PLATFORM_SI },
431         { "pll_p_out2", "pll_p",        102000000,      false,
432                 TEGRA_CLK_INIT_PLATFORM_SI },
433         { "sclk",       "pll_p_out2",   102000000,      true,
434                 TEGRA_CLK_INIT_PLATFORM_SI },
435         { "pll_p_out4", "pll_p",        204000000,      true,
436                 TEGRA_CLK_INIT_PLATFORM_SI },
437         { "host1x",     "pll_p",        102000000,      false,
438                 TEGRA_CLK_INIT_PLATFORM_SI },
439         { "cl_dvfs_ref", "pll_p",       54000000,       true,
440                 TEGRA_CLK_INIT_PLATFORM_SI },
441         { "cl_dvfs_soc", "pll_p",       54000000,       true,
442                 TEGRA_CLK_INIT_PLATFORM_SI },
443         { "hclk",       "sclk",         102000000,      true,
444                 TEGRA_CLK_INIT_PLATFORM_SI },
445         { "pclk",       "hclk",         51000000,       true,
446                 TEGRA_CLK_INIT_PLATFORM_SI },
447         { "wake.sclk",  NULL,           40000000,       true,
448                 TEGRA_CLK_INIT_PLATFORM_SI },
449         { "mselect",    "pll_p",        102000000,      true,
450                 TEGRA_CLK_INIT_PLATFORM_SI },
451         { "pll_p_out5", "pll_p",        102000000,      true,
452                 TEGRA_CLK_INIT_PLATFORM_SI },
453 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
454         { "pll_m_out1", "pll_m",        275000000,      true,
455                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
456         { "pll_p_out2", "pll_p",        108000000,      false,
457                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
458         { "sclk",       "pll_p_out2",   108000000,      true,
459                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
460         { "pll_p_out4", "pll_p",        216000000,      true,
461                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
462         { "hclk",       "sclk",         108000000,      true,
463                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
464         { "pclk",       "hclk",         54000000,       true,
465                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
466         { "mselect",    "pll_p",        108000000,      true,
467                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
468         { "host1x",     "pll_p",        108000000,      false,
469                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
470         { "cl_dvfs_ref", "clk_m",       13000000,       false,
471                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
472         { "cl_dvfs_soc", "clk_m",       13000000,       false,
473                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
474         { "vde",        "pll_c3",       48400000,       true,
475                 TEGRA_CLK_INIT_CPU_ASIM},
476 #endif
477 #ifdef CONFIG_TEGRA_SLOW_CSITE
478         { "csite",      "clk_m",        1000000,        true },
479 #else
480         { "csite",      NULL,           0,              true },
481 #endif
482         { "pll_u",      NULL,           480000000,      true },
483         { "pll_re_vco", NULL,           672000000,      true },
484         { "xusb_falcon_src",    "pll_re_out",   224000000,      false},
485         { "xusb_host_src",      "pll_re_out",   112000000,      false},
486         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
487         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
488         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
489         { "sdmmc1",     "pll_p",        48000000,       false},
490         { "sdmmc3",     "pll_p",        48000000,       false},
491         { "sdmmc4",     "pll_p",        48000000,       false},
492         { "sdmmc1_ddr", "pll_p",        48000000,       false},
493         { "sdmmc3_ddr", "pll_p",        48000000,       false},
494         { "sdmmc4_ddr", "pll_p",        48000000,       false},
495         { "sbc1.sclk",  NULL,           40000000,       false},
496         { "sbc2.sclk",  NULL,           40000000,       false},
497         { "sbc3.sclk",  NULL,           40000000,       false},
498         { "sbc4.sclk",  NULL,           40000000,       false},
499         { "sbc5.sclk",  NULL,           40000000,       false},
500         { "sbc6.sclk",  NULL,           40000000,       false},
501         { "cpu.mselect", NULL,          102000000,      true},
502         { "gpu_ref",    NULL,           0,              true},
503         { "gk20a.gbus", NULL,           252000000,      false},
504 #ifdef CONFIG_TEGRA_PLLM_SCALED
505         { "vi",         "pll_p",        0,              false},
506         { "isp",        "pll_p",        0,              false},
507 #endif
508 #ifdef CONFIG_TEGRA_SOCTHERM
509         { "soc_therm",  "pll_p",        51000000,       false },
510         { "tsensor",    "clk_m",        500000,         false },
511 #endif
512         { "pll_d",      NULL,           0,              true },
513         { "dsialp",     "pll_p",        70000000,       false },
514         { "dsiblp",     "pll_p",        70000000,       false },
515         { NULL,         NULL,           0,              0},
516 };
517 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
518         /* Initialize c2bus, c3bus, or cbus at the end of the list
519          * after all the clocks are moved under the proper parents.
520          */
521 #ifdef CONFIG_TEGRA_DUAL_CBUS
522         { "c2bus",      "pll_c2",       250000000,      false },
523         { "c3bus",      "pll_c3",       250000000,      false },
524         { "pll_c",      NULL,           600000000,      false },
525 #else
526         { "cbus",       "pll_c",        200000000,      false },
527 #endif
528         { "pll_c_out1", "pll_c",        100000000,      false },
529         { "c4bus",      "pll_c4",       200000000,      false },
530         { NULL,         NULL,           0,              0},
531 };
532 #endif
533
534 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
535 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
536         /* name         parent          rate            enabled */
537         { "osc",        NULL,           0,              true },
538         { "clk_m",      "osc",          0,              true },
539         { "emc",        NULL,           0,              true },
540         { "cpu",        NULL,           0,              true },
541         { "kfuse",      NULL,           0,              true },
542         { "fuse",       NULL,           0,              true },
543         { "sclk",       NULL,           0,              true },
544 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
545         { "pll_p",      NULL,           0,              true },
546         { "pll_p_out1", "pll_p",        0,              false },
547         { "pll_p_out3", "pll_p",        0,              true },
548         { "pll_m_out1", "pll_m",        275000000,      false },
549         { "pll_p_out2",  "pll_p",       102000000,      false },
550         { "sclk",        "pll_p_out2",  102000000,      true },
551         { "pll_p_out4",  "pll_p",       204000000,      true },
552         { "hclk",       "sclk",         102000000,      true },
553         { "pclk",       "hclk",         51000000,       true },
554         { "mselect",    "pll_p",        102000000,      true },
555         { "host1x",     "pll_p",        102000000,      false },
556         { "cl_dvfs_ref", "pll_p",       51000000,       true },
557         { "cl_dvfs_soc", "pll_p",       51000000,       true },
558 #else
559         { "pll_p",      NULL,           0,              true },
560         { "pll_p_out1", "pll_p",        0,              false },
561         { "pll_p_out3", "pll_p",        0,              true },
562         { "pll_m_out1", "pll_m",        275000000,      true },
563         { "pll_p_out2", "pll_p",        108000000,      false },
564         { "sclk",       "pll_p_out2",   108000000,      true },
565         { "pll_p_out4", "pll_p",        216000000,      true },
566         { "host1x",     "pll_p",        108000000,      false },
567         { "cl_dvfs_ref", "clk_m",       13000000,       false },
568         { "cl_dvfs_soc", "clk_m",       13000000,       false },
569         { "hclk",       "sclk",         108000000,      true },
570         { "pclk",       "hclk",         54000000,       true },
571         { "wake.sclk",  NULL,           250000000,      true },
572         { "mselect",    "pll_p",        108000000,      true },
573 #endif
574 #ifdef CONFIG_TEGRA_SLOW_CSITE
575         { "csite",      "clk_m",        1000000,        true },
576 #else
577         { "csite",      NULL,           0,              true },
578 #endif
579         { "pll_u",      NULL,           480000000,      false },
580         { "sdmmc1",     "pll_p",        48000000,       false},
581         { "sdmmc3",     "pll_p",        48000000,       false},
582         { "sdmmc4",     "pll_p",        48000000,       false},
583         { "mon.avp",    NULL,           80000000,       true },
584         { "sbc1.sclk",  NULL,           20000000,       false},
585         { "sbc2.sclk",  NULL,           20000000,       false},
586         { "sbc3.sclk",  NULL,           20000000,       false},
587         { "msenc",      "pll_p",        108000000,      false },
588         { "tsec",       "pll_p",        108000000,      false },
589         { "mc_capa",    "emc",          0,              true },
590         { "mc_cbpa",    "emc",          0,              true },
591 #ifdef CONFIG_TEGRA_SOCTHERM
592         { "soc_therm",  "pll_p",        51000000,       false },
593         { "tsensor",    "clk_m",        400000,         false },
594 #endif
595         { NULL,         NULL,           0,              0},
596 };
597 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
598         /* Initialize c2bus, c3bus, or cbus at the end of the list
599          * after all the clocks are moved under the proper parents.
600          */
601 #ifdef CONFIG_TEGRA_DUAL_CBUS
602         { "c2bus",      "pll_c2",       200000000,      false },
603         { "c3bus",      "pll_c3",       200000000,      false },
604         { "pll_c",      NULL,           768000000,      false },
605 #else
606         { "cbus",       "pll_c",        200000000,      false },
607 #endif
608         { "pll_c_out1", "pll_c",        100000000,      false },
609         { NULL,         NULL,           0,              0},
610 };
611 #endif
612
613 #ifdef CONFIG_CACHE_L2X0
614 static void tegra_cache_smc(bool enable, u32 arg)
615 {
616         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
617         bool need_affinity_switch;
618         bool can_switch_affinity;
619         bool l2x0_enabled;
620         cpumask_t local_cpu_mask;
621         cpumask_t saved_cpu_mask;
622         unsigned long flags;
623         long ret;
624
625         /*
626          * ISSUE : Some registers of PL310 controler must be written
627          *              from Secure context (and from CPU0)!
628          *
629          * When called form Normal we obtain an abort or do nothing.
630          * Instructions that must be called in Secure:
631          *      - Write to Control register (L2X0_CTRL==0x100)
632          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
633          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
634          *              mandatory at boot time.
635          *      - Tag and Data RAM Latency Control Registers
636          *              (0x108 & 0x10C) must be written in Secure.
637          */
638         need_affinity_switch = (smp_processor_id() != 0);
639         can_switch_affinity = !irqs_disabled();
640
641         WARN_ON(need_affinity_switch && !can_switch_affinity);
642         if (need_affinity_switch && can_switch_affinity) {
643                 cpu_set(0, local_cpu_mask);
644                 sched_getaffinity(0, &saved_cpu_mask);
645                 ret = sched_setaffinity(0, &local_cpu_mask);
646                 WARN_ON(ret != 0);
647         }
648
649         local_irq_save(flags);
650         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
651         if (enable && !l2x0_enabled)
652                 tegra_generic_smc(0x82000002, 0x00000001, arg);
653         else if (!enable && l2x0_enabled)
654                 tegra_generic_smc(0x82000002, 0x00000002, arg);
655         local_irq_restore(flags);
656
657         if (need_affinity_switch && can_switch_affinity) {
658                 ret = sched_setaffinity(0, &saved_cpu_mask);
659                 WARN_ON(ret != 0);
660         }
661 }
662
663 static void tegra_l2x0_disable(void)
664 {
665         unsigned long flags;
666         static u32 l2x0_way_mask;
667
668         if (!l2x0_way_mask) {
669                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
670                 u32 aux_ctrl;
671                 u32 ways;
672
673                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
674                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
675                 l2x0_way_mask = (1 << ways) - 1;
676         }
677
678         local_irq_save(flags);
679         tegra_cache_smc(false, l2x0_way_mask);
680         local_irq_restore(flags);
681 }
682
683 void tegra_init_cache(bool init)
684 {
685         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
686         u32 aux_ctrl;
687         u32 cache_type;
688         u32 tag_latency, data_latency;
689
690         if (tegra_cpu_is_secure()) {
691                 /* issue the SMC to enable the L2 */
692                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
693                 trace_smc_init_cache(NVSEC_SMC_START);
694                 tegra_cache_smc(true, aux_ctrl);
695                 trace_smc_init_cache(NVSEC_SMC_DONE);
696
697                 /* after init, reread aux_ctrl and register handlers */
698                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
699                 l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
700
701                 /* override outer_disable() with our disable */
702                 outer_cache.disable = tegra_l2x0_disable;
703         } else {
704 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
705                 tag_latency = 0x331;
706                 data_latency = 0x441;
707 #else
708                 if (!tegra_platform_is_silicon()) {
709                         tag_latency = 0x770;
710                         data_latency = 0x770;
711                 } else if (is_lp_cluster()) {
712                         tag_latency = tegra_cpu_c1_l2_tag_latency;
713                         data_latency = tegra_cpu_c1_l2_data_latency;
714                 } else {
715                         tag_latency = tegra_cpu_c0_l2_tag_latency;
716                         data_latency = tegra_cpu_c0_l2_data_latency;
717                 }
718 #endif
719                 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
720                 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
721
722 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
723                 if (!tegra_platform_is_fpga()) {
724 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
725                         /* Enable double line fill */
726                         writel(0x40000007, p + L2X0_PREFETCH_CTRL);
727 #else
728                         writel(0x7, p + L2X0_PREFETCH_CTRL);
729 #endif
730                         writel(0x3, p + L2X0_POWER_CTRL);
731                 }
732 #endif
733                 cache_type = readl(p + L2X0_CACHE_TYPE);
734                 aux_ctrl = (cache_type & 0x700) << (17-8);
735                 aux_ctrl |= 0x7C400001;
736                 if (init) {
737                         l2x0_init(p, aux_ctrl, 0x8200c3fe);
738                 } else {
739                         u32 tmp;
740
741                         tmp = aux_ctrl;
742                         aux_ctrl = readl(p + L2X0_AUX_CTRL);
743                         aux_ctrl &= 0x8200c3fe;
744                         aux_ctrl |= tmp;
745                         writel(aux_ctrl, p + L2X0_AUX_CTRL);
746                 }
747                 l2x0_enable();
748         }
749 }
750 #endif
751
752 static void __init tegra_perf_init(void)
753 {
754         u32 reg;
755
756 #ifdef CONFIG_ARM64
757         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
758         reg >>= 11;
759         reg = (1 << (reg & 0x1f))-1;
760         reg |= 0x80000000;
761         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
762         reg = 1;
763         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
764 #else
765         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
766         reg >>= 11;
767         reg = (1 << (reg & 0x1f))-1;
768         reg |= 0x80000000;
769         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
770         reg = 1;
771         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
772 #endif
773 }
774
775 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
776 static void __init tegra_ramrepair_init(void)
777 {
778 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
779         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
780 #endif
781                 u32 reg;
782                 reg = readl(FLOW_CTRL_RAM_REPAIR);
783                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
784                 writel(reg, FLOW_CTRL_RAM_REPAIR);
785 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
786         }
787 #endif
788 }
789 #endif
790
791 static void __init tegra_init_power(void)
792 {
793 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
794         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
795 #endif
796 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
797         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
798 #endif
799
800 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
801         /* powergate xusb partitions by default */
802         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
803         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
804         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
805 #endif
806
807 }
808
809 static inline unsigned long gizmo_readl(unsigned long offset)
810 {
811         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
812 }
813
814 static inline void gizmo_writel(unsigned long value, unsigned long offset)
815 {
816         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
817 }
818
819 static void __init tegra_init_ahb_gizmo_settings(void)
820 {
821         unsigned long val;
822
823         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
824         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
825
826         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
827                 val |= WR_WAIT_COMMIT_ON_1K;
828 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
829         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
830 #endif
831         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
832
833         val = gizmo_readl(AHB_GIZMO_USB);
834         val |= IMMEDIATE;
835         gizmo_writel(val, AHB_GIZMO_USB);
836
837         val = gizmo_readl(AHB_GIZMO_USB2);
838         val |= IMMEDIATE;
839         gizmo_writel(val, AHB_GIZMO_USB2);
840
841         val = gizmo_readl(AHB_GIZMO_USB3);
842         val |= IMMEDIATE;
843         gizmo_writel(val, AHB_GIZMO_USB3);
844
845         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
846         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
847                                 | AHB_PRIORITY_WEIGHT(7);
848 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
849         val |= PRIORITY_SELECT_SE;
850 #endif
851
852         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
853
854         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
855         val &= ~MST_ID(~0);
856         val |= PREFETCH_ENB | AHBDMA_MST_ID |
857                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
858         ahb_gizmo_writel(val,
859                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
860
861         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
862         val &= ~MST_ID(~0);
863         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
864                 INACTIVITY_TIMEOUT(0x1000);
865         ahb_gizmo_writel(val,
866                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
867
868         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
869         val &= ~MST_ID(~0);
870         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
871                 INACTIVITY_TIMEOUT(0x1000);
872         ahb_gizmo_writel(val,
873                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
874
875         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
876         val &= ~MST_ID(~0);
877         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
878                 INACTIVITY_TIMEOUT(0x1000);
879         ahb_gizmo_writel(val,
880                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
881
882         /*
883          * SDMMC controller is removed from AHB interface in T124 and
884          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
885          * in T11x and T14x SOCs.
886          */
887 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
888         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
889         val &= ~MST_ID(~0);
890         val |= PREFETCH_ENB | SDMMC4_MST_ID;
891         val &= ~SDMMC4_MST_ID;
892         ahb_gizmo_writel(val,
893                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
894 #endif
895
896 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
897         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
898         val &= ~MST_ID(~0);
899         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
900                 INACTIVITY_TIMEOUT(0x1000);
901         ahb_gizmo_writel(val,
902                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
903 #endif
904 }
905
906 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
907 void __init tegra20_init_early(void)
908 {
909         tegra_apb_io_init();
910         tegra_perf_init();
911         tegra_init_fuse();
912         tegra_init_cache(true);
913         tegra_powergate_init();
914         tegra20_hotplug_init();
915         tegra_init_power();
916         tegra_init_ahb_gizmo_settings();
917         tegra_init_debug_uart_rate();
918 }
919 #endif
920 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
921 void __init tegra30_init_early(void)
922 {
923         u32 speedo;
924         u32 tag_latency, data_latency;
925
926         display_tegra_dt_info();
927         tegra_apb_io_init();
928         tegra_perf_init();
929         tegra_init_fuse();
930         /*
931          * Store G/LP cluster L2 latencies to IRAM and DRAM
932          */
933         tegra_cpu_c1_l2_tag_latency = 0x221;
934         tegra_cpu_c1_l2_data_latency = 0x221;
935         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
936         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
937         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
938         speedo = tegra_cpu_speedo_id();
939         if (speedo == 4 || speedo == 5 || speedo == 6 ||
940             speedo == 12 || speedo == 13) {
941                 tag_latency = 0x442;
942                 data_latency = 0x552;
943         } else {
944                 tag_latency = 0x441;
945                 data_latency = 0x551;
946         }
947         tegra_cpu_c0_l2_tag_latency = tag_latency;
948         tegra_cpu_c0_l2_data_latency = data_latency;
949         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
950         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
951         tegra_init_cache(true);
952         tegra_powergate_init();
953         tegra30_hotplug_init();
954         tegra_init_power();
955         tegra_init_ahb_gizmo_settings();
956         tegra_init_debug_uart_rate();
957
958         init_dma_coherent_pool_size(SZ_1M);
959 }
960 #endif
961 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
962 void __init tegra11x_init_early(void)
963 {
964         display_tegra_dt_info();
965         tegra_apb_io_init();
966         tegra_perf_init();
967         tegra_init_fuse();
968         tegra_ramrepair_init();
969         tegra11x_init_clocks();
970         tegra11x_init_dvfs();
971         tegra_common_init_clock();
972         tegra_clk_init_from_table(tegra11x_clk_init_table);
973         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
974         tegra11x_clk_init_la();
975         tegra_powergate_init();
976         tegra30_hotplug_init();
977         tegra_init_power();
978         tegra_init_ahb_gizmo_settings();
979         tegra_init_debug_uart_rate();
980
981         init_dma_coherent_pool_size(SZ_2M);
982 }
983 #endif
984 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
985 void __init tegra12x_init_early(void)
986 {
987         if (of_find_compatible_node(NULL, NULL, "arm,psci"))
988                 tegra_with_secure_firmware = 1;
989
990         display_tegra_dt_info();
991         tegra_apb_io_init();
992         tegra_perf_init();
993         tegra_init_fuse();
994         tegra_ramrepair_init();
995         tegra12x_init_clocks();
996 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
997         tegra13x_init_dvfs();
998 #else
999         tegra12x_init_dvfs();
1000 #endif
1001         tegra_common_init_clock();
1002         tegra_clk_init_from_table(tegra12x_clk_init_table);
1003         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
1004         tegra_powergate_init();
1005 #ifndef CONFIG_ARM64
1006         tegra30_hotplug_init();
1007 #endif
1008         tegra_init_power();
1009         tegra_init_ahb_gizmo_settings();
1010         tegra_init_debug_uart_rate();
1011 }
1012 #endif
1013 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
1014 void __init tegra14x_init_early(void)
1015 {
1016         display_tegra_dt_info();
1017         tegra_apb_io_init();
1018         tegra_perf_init();
1019         tegra_init_fuse();
1020         tegra_ramrepair_init();
1021         tegra14x_init_clocks();
1022         tegra14x_init_dvfs();
1023         tegra_common_init_clock();
1024         tegra_clk_init_from_table(tegra14x_clk_init_table);
1025         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
1026         tegra_cpu_c1_l2_tag_latency = 0x110;
1027         tegra_cpu_c1_l2_data_latency = 0x331;
1028         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
1029         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
1030         tegra_cpu_c0_l2_tag_latency = 0x111;
1031         tegra_cpu_c0_l2_data_latency = 0x441;
1032         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
1033         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
1034         tegra_init_cache(true);
1035         tegra_powergate_init();
1036         tegra30_hotplug_init();
1037         tegra_init_power();
1038         tegra_init_ahb_gizmo_settings();
1039         tegra_init_debug_uart_rate();
1040 }
1041 #endif
1042 static int __init tegra_lp0_vec_arg(char *options)
1043 {
1044         char *p = options;
1045
1046         tegra_lp0_vec_size = memparse(p, &p);
1047         if (*p == '@')
1048                 tegra_lp0_vec_start = memparse(p+1, &p);
1049         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1050                 tegra_lp0_vec_size = 0;
1051                 tegra_lp0_vec_start = 0;
1052         }
1053
1054         return 0;
1055 }
1056 early_param("lp0_vec", tegra_lp0_vec_arg);
1057
1058 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1059 static int __init tegra_wb0_params_arg(char *options)
1060 {
1061         char *p = options;
1062
1063         tegra_wb0_params_address = memparse(p, &p);
1064         if (*p == ',')
1065                 tegra_wb0_params_instances = memparse(p+1, &p);
1066         if (*p == ',')
1067                 tegra_wb0_params_block_size = memparse(p+1, &p);
1068
1069         return 0;
1070 }
1071 early_param("wb0_params", tegra_wb0_params_arg);
1072 #endif
1073
1074 #ifdef CONFIG_TEGRA_NVDUMPER
1075 static int __init tegra_nvdumper_arg(char *options)
1076 {
1077         char *p = options;
1078
1079         nvdumper_reserved = memparse(p, &p);
1080         return 0;
1081 }
1082 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1083 #endif
1084
1085 static int __init tegra_bootloader_fb_arg(char *options)
1086 {
1087         char *p = options;
1088
1089         tegra_bootloader_fb_size = memparse(p, &p);
1090         if (*p == '@')
1091                 tegra_bootloader_fb_start = memparse(p+1, &p);
1092
1093         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1094                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1095
1096         return 0;
1097 }
1098 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1099
1100 static int __init tegra_bootloader_fb2_arg(char *options)
1101 {
1102         char *p = options;
1103
1104         tegra_bootloader_fb2_size = memparse(p, &p);
1105         if (*p == '@')
1106                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1107
1108         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1109                 (u64)tegra_bootloader_fb2_size,
1110                 (u64)tegra_bootloader_fb2_start);
1111
1112         return 0;
1113 }
1114 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1115
1116 static int __init tegra_sku_override(char *id)
1117 {
1118         char *p = id;
1119
1120         sku_override = memparse(p, &p);
1121
1122         return 0;
1123 }
1124 early_param("sku_override", tegra_sku_override);
1125
1126 int tegra_get_sku_override(void)
1127 {
1128         return sku_override;
1129 }
1130
1131 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1132 static int __init tegra_vpr_arg(char *options)
1133 {
1134         char *p = options;
1135
1136         tegra_vpr_size = memparse(p, &p);
1137         if (*p == '@')
1138                 tegra_vpr_start = memparse(p+1, &p);
1139         pr_info("Found vpr, start=0x%llx size=%llx",
1140                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1141         return 0;
1142 }
1143 early_param("vpr", tegra_vpr_arg);
1144 #endif
1145
1146 static int __init tegra_tsec_arg(char *options)
1147 {
1148         char *p = options;
1149
1150         tegra_tsec_size = memparse(p, &p);
1151         if (*p == '@')
1152                 tegra_tsec_start = memparse(p+1, &p);
1153         pr_info("Found tsec, start=0x%llx size=%llx",
1154                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1155         return 0;
1156 }
1157 early_param("tsec", tegra_tsec_arg);
1158
1159 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
1160 static int __init tegra_tzram_arg(char *options)
1161 {
1162         char *p = options;
1163
1164         tegra_tzram_size = memparse(p, &p);
1165         if (*p == '@')
1166                 tegra_tzram_start = memparse(p + 1, &p);
1167         return 0;
1168 }
1169 early_param("tzram", tegra_tzram_arg);
1170 #endif
1171
1172 #ifdef CONFIG_TEGRA_USE_NCT
1173 static int __init tegra_nck_arg(char *options)
1174 {
1175         char *p = options;
1176
1177         tegra_nck_size = memparse(p, &p);
1178         if (*p == '@')
1179                 tegra_nck_start = memparse(p+1, &p);
1180         if (!tegra_nck_size || !tegra_nck_start) {
1181                 tegra_nck_size = 0;
1182                 tegra_nck_start = 0;
1183         }
1184
1185         return 0;
1186 }
1187 early_param("nck", tegra_nck_arg);
1188 #endif  /* CONFIG_TEGRA_USE_NCT */
1189
1190 enum panel_type get_panel_type(void)
1191 {
1192         return board_panel_type;
1193 }
1194 static int __init tegra_board_panel_type(char *options)
1195 {
1196         if (!strcmp(options, "lvds"))
1197                 board_panel_type = panel_type_lvds;
1198         else if (!strcmp(options, "dsi"))
1199                 board_panel_type = panel_type_dsi;
1200         else
1201                 return 0;
1202         return 1;
1203 }
1204 __setup("panel=", tegra_board_panel_type);
1205
1206 int tegra_get_board_panel_id(void)
1207 {
1208         return panel_id;
1209 }
1210 static int __init tegra_board_panel_id(char *options)
1211 {
1212         char *p = options;
1213         panel_id = memparse(p, &p);
1214         return panel_id;
1215 }
1216 __setup("display_panel=", tegra_board_panel_id);
1217
1218 int tegra_get_touch_vendor_id(void)
1219 {
1220         return touch_vendor_id;
1221 }
1222 int tegra_get_touch_panel_id(void)
1223 {
1224         return touch_panel_id;
1225 }
1226 static int __init tegra_touch_id(char *options)
1227 {
1228         char *p = options;
1229         touch_vendor_id = memparse(p, &p);
1230         if (*p == '@')
1231                 touch_panel_id = memparse(p+1, &p);
1232         return 1;
1233 }
1234 __setup("touch_id=", tegra_touch_id);
1235
1236 u8 get_power_config(void)
1237 {
1238         return power_config;
1239 }
1240 static int __init tegra_board_power_config(char *options)
1241 {
1242         char *p = options;
1243         power_config = memparse(p, &p);
1244         return 1;
1245 }
1246 __setup("power-config=", tegra_board_power_config);
1247
1248 u8 get_display_config(void)
1249 {
1250         return display_config;
1251 }
1252 static int __init tegra_board_display_config(char *options)
1253 {
1254         char *p = options;
1255         display_config = memparse(p, &p);
1256         return 1;
1257 }
1258 __setup("display-config=", tegra_board_display_config);
1259
1260 enum power_supply_type get_power_supply_type(void)
1261 {
1262         return pow_supply_type;
1263 }
1264 static int __init tegra_board_power_supply_type(char *options)
1265 {
1266         if (!strcmp(options, "Adapter"))
1267                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1268         if (!strcmp(options, "Mains"))
1269                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1270         else if (!strcmp(options, "Battery"))
1271                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1272         else
1273                 return 0;
1274         return 1;
1275 }
1276 __setup("power_supply=", tegra_board_power_supply_type);
1277
1278 int get_core_edp(void)
1279 {
1280         return pmu_core_edp;
1281 }
1282 static int __init tegra_pmu_core_edp(char *options)
1283 {
1284         char *p = options;
1285         int core_edp = memparse(p, &p);
1286         if (core_edp != 0)
1287                 pmu_core_edp = core_edp;
1288         return 0;
1289 }
1290 early_param("core_edp_mv", tegra_pmu_core_edp);
1291
1292 int get_maximum_cpu_current_supported(void)
1293 {
1294         return max_cpu_current;
1295 }
1296 static int __init tegra_max_cpu_current(char *options)
1297 {
1298         char *p = options;
1299         max_cpu_current = memparse(p, &p);
1300         return 1;
1301 }
1302 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1303
1304 int get_maximum_core_current_supported(void)
1305 {
1306         return max_core_current;
1307 }
1308 static int __init tegra_max_core_current(char *options)
1309 {
1310         char *p = options;
1311         max_core_current = memparse(p, &p);
1312         return 0;
1313 }
1314 early_param("core_edp_ma", tegra_max_core_current);
1315
1316 int get_emc_max_dvfs(void)
1317 {
1318         return emc_max_dvfs;
1319 }
1320 static int __init tegra_emc_max_dvfs(char *options)
1321 {
1322         char *p = options;
1323         emc_max_dvfs = memparse(p, &p);
1324         return 1;
1325 }
1326 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1327
1328 int tegra_get_memory_type(void)
1329 {
1330         return memory_type;
1331 }
1332 static int __init tegra_memory_type(char *options)
1333 {
1334         char *p = options;
1335         memory_type = memparse(p, &p);
1336         return 1;
1337 }
1338 __setup("memtype=", tegra_memory_type);
1339
1340 static int __init tegra_debug_uartport(char *info)
1341 {
1342         char *p = info;
1343         unsigned long long port_id;
1344         if (!strncmp(p, "hsport", 6))
1345                 is_tegra_debug_uart_hsport = true;
1346         else if (!strncmp(p, "lsport", 6))
1347                 is_tegra_debug_uart_hsport = false;
1348
1349         if (p[6] == ',') {
1350                 if (p[7] == '-') {
1351                         debug_uart_port_id = -1;
1352                 } else {
1353                         port_id = memparse(p + 7, &p);
1354                         debug_uart_port_id = (int) port_id;
1355                         if (debug_uart_port_id == 5)
1356                                 uart_over_sd = true;
1357                 }
1358         } else {
1359                 debug_uart_port_id = -1;
1360         }
1361
1362         return 1;
1363 }
1364
1365 bool is_tegra_debug_uartport_hs(void)
1366 {
1367         return is_tegra_debug_uart_hsport;
1368 }
1369
1370 bool is_uart_over_sd_enabled(void)
1371 {
1372         return uart_over_sd;
1373 }
1374
1375 void set_sd_uart_port_id(int port_id)
1376 {
1377         debug_uart_port_id = port_id;
1378 }
1379
1380 int get_tegra_uart_debug_port_id(void)
1381 {
1382         return debug_uart_port_id;
1383 }
1384 __setup("debug_uartport=", tegra_debug_uartport);
1385
1386 static int __init tegra_image_type(char *options)
1387 {
1388         if (!strcmp(options, "RCK"))
1389                 board_image_type = rck_image;
1390
1391         return 0;
1392 }
1393
1394 enum image_type get_tegra_image_type(void)
1395 {
1396         return board_image_type;
1397 }
1398
1399 __setup("image=", tegra_image_type);
1400
1401 static int __init tegra_audio_codec_type(char *info)
1402 {
1403         char *p = info;
1404         if (!strncmp(p, "wm8903", 6))
1405                 audio_codec_name = audio_codec_wm8903;
1406         else
1407                 audio_codec_name = audio_codec_none;
1408
1409         return 1;
1410 }
1411
1412 enum audio_codec_type get_audio_codec_type(void)
1413 {
1414         return audio_codec_name;
1415 }
1416 __setup("audio_codec=", tegra_audio_codec_type);
1417
1418 static int tegra_get_pwr_i2c_clk_rate(char *options)
1419 {
1420         int clk = simple_strtol(options, NULL, 16);
1421         if (clk != 0)
1422                 pwr_i2c_clk = clk;
1423         return 0;
1424 }
1425
1426 int get_pwr_i2c_clk_rate(void)
1427 {
1428         return pwr_i2c_clk;
1429 }
1430 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1431
1432 static bool pmic_wdt_disable;
1433 bool is_pmic_wdt_disabled_at_boot(void)
1434 {
1435         return pmic_wdt_disable;
1436 }
1437
1438 static int parse_arg_pmic_wdt_disable(char *options)
1439 {
1440         /* no kernel command line argument "watchdog" interpreted as
1441          * watchdog enable
1442          */
1443         pmic_wdt_disable = false;
1444         if (!(strcmp(options, "enable")))
1445                 pmic_wdt_disable = false;
1446         else if (!(strcmp(options, "disable")))
1447                 pmic_wdt_disable = true;
1448         /* kernel command line from fastboot does not support
1449          * other values
1450          */
1451
1452         return 0;
1453 }
1454 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1455
1456 void tegra_get_board_info(struct board_info *bi)
1457 {
1458 #ifdef CONFIG_OF
1459         struct device_node *board_info;
1460         u32 prop_val;
1461         int err;
1462
1463         board_info = of_find_node_by_path("/chosen/board_info");
1464         if (!IS_ERR_OR_NULL(board_info)) {
1465                 memset(bi, 0, sizeof(*bi));
1466
1467                 err = of_property_read_u32(board_info, "id", &prop_val);
1468                 if (err)
1469                         pr_err("failed to read /chosen/board_info/id\n");
1470                 else
1471                         bi->board_id = prop_val;
1472
1473                 err = of_property_read_u32(board_info, "sku", &prop_val);
1474                 if (err)
1475                         pr_err("failed to read /chosen/board_info/sku\n");
1476                 else
1477                         bi->sku = prop_val;
1478
1479                 err = of_property_read_u32(board_info, "fab", &prop_val);
1480                 if (err)
1481                         pr_err("failed to read /chosen/board_info/fab\n");
1482                 else
1483                         bi->fab = prop_val;
1484
1485                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1486                 if (err)
1487                         pr_err("failed to read /chosen/board_info/major_revision\n");
1488                 else
1489                         bi->major_revision = prop_val;
1490
1491                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1492                 if (err)
1493                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1494                 else
1495                         bi->minor_revision = prop_val;
1496                 system_serial_high = (bi->board_id << 16) | bi->sku;
1497                 system_serial_low = (bi->fab << 24) |
1498                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1499         } else {
1500 #endif
1501                 if (system_serial_high || system_serial_low) {
1502                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1503                         bi->sku = (system_serial_high) & 0xFFFF;
1504                         bi->fab = (system_serial_low >> 24) & 0xFF;
1505                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1506                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1507                 } else {
1508                         memcpy(bi, &main_board_info, sizeof(struct board_info));
1509                 }
1510 #ifdef CONFIG_OF
1511         }
1512 #endif
1513 }
1514
1515 #ifdef CONFIG_OF
1516 void find_dc_node(struct device_node **dc1_node,
1517                 struct device_node **dc2_node) {
1518         *dc1_node =
1519                 of_find_node_by_path("/host1x/dc@54200000");
1520         *dc2_node =
1521                 of_find_node_by_path("/host1x/dc@54240000");
1522 }
1523 #else
1524 void find_dc_node(struct device_node *dc1_node,
1525                 struct device_node *dc2_node) {
1526         return;
1527 }
1528 #endif
1529
1530 static int __init tegra_main_board_info(char *info)
1531 {
1532         char *p = info;
1533         main_board_info.board_id = memparse(p, &p);
1534         main_board_info.sku = memparse(p+1, &p);
1535         main_board_info.fab = memparse(p+1, &p);
1536         main_board_info.major_revision = memparse(p+1, &p);
1537         main_board_info.minor_revision = memparse(p+1, &p);
1538         return 1;
1539 }
1540
1541 __setup("board_info=", tegra_main_board_info);
1542
1543 static int __init tegra_pmu_board_info(char *info)
1544 {
1545         char *p = info;
1546         pmu_board_info.board_id = memparse(p, &p);
1547         pmu_board_info.sku = memparse(p+1, &p);
1548         pmu_board_info.fab = memparse(p+1, &p);
1549         pmu_board_info.major_revision = memparse(p+1, &p);
1550         pmu_board_info.minor_revision = memparse(p+1, &p);
1551         return 0;
1552 }
1553
1554 void tegra_get_pmu_board_info(struct board_info *bi)
1555 {
1556         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1557 }
1558
1559 early_param("pmuboard", tegra_pmu_board_info);
1560
1561 static int __init tegra_display_board_info(char *info)
1562 {
1563         char *p = info;
1564         display_board_info.board_id = memparse(p, &p);
1565         display_board_info.sku = memparse(p+1, &p);
1566         display_board_info.fab = memparse(p+1, &p);
1567         display_board_info.major_revision = memparse(p+1, &p);
1568         display_board_info.minor_revision = memparse(p+1, &p);
1569         return 1;
1570 }
1571
1572 void tegra_get_display_board_info(struct board_info *bi)
1573 {
1574         memcpy(bi, &display_board_info, sizeof(struct board_info));
1575 }
1576
1577 __setup("displayboard=", tegra_display_board_info);
1578
1579 static int __init tegra_camera_board_info(char *info)
1580 {
1581         char *p = info;
1582         camera_board_info.board_id = memparse(p, &p);
1583         camera_board_info.sku = memparse(p+1, &p);
1584         camera_board_info.fab = memparse(p+1, &p);
1585         camera_board_info.major_revision = memparse(p+1, &p);
1586         camera_board_info.minor_revision = memparse(p+1, &p);
1587         return 1;
1588 }
1589
1590 void tegra_get_camera_board_info(struct board_info *bi)
1591 {
1592         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1593 }
1594
1595 __setup("cameraboard=", tegra_camera_board_info);
1596
1597 static int __init tegra_leftspeaker_board_info(char *info)
1598 {
1599         char *p = info;
1600         leftspeaker_board_info.board_id = memparse(p, &p);
1601         leftspeaker_board_info.sku = memparse(p+1, &p);
1602         leftspeaker_board_info.fab = memparse(p+1, &p);
1603         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1604         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1605         return 1;
1606 }
1607
1608 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1609 {
1610         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1611 }
1612
1613 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1614
1615 static int __init tegra_rightspeaker_board_info(char *info)
1616 {
1617         char *p = info;
1618         rightspeaker_board_info.board_id = memparse(p, &p);
1619         rightspeaker_board_info.sku = memparse(p+1, &p);
1620         rightspeaker_board_info.fab = memparse(p+1, &p);
1621         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1622         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1623         return 1;
1624 }
1625
1626 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1627 {
1628         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1629 }
1630
1631 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1632
1633 static int __init tegra_joystick_board_info(char *info)
1634 {
1635         char *p = info;
1636         joystick_board_info.board_id = memparse(p, &p);
1637         joystick_board_info.sku = memparse(p+1, &p);
1638         joystick_board_info.fab = memparse(p+1, &p);
1639         joystick_board_info.major_revision = memparse(p+1, &p);
1640         joystick_board_info.minor_revision = memparse(p+1, &p);
1641         return 1;
1642 }
1643
1644 void tegra_get_joystick_board_info(struct board_info *bi)
1645 {
1646         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1647 }
1648
1649 __setup("joystickboard=", tegra_joystick_board_info);
1650
1651 static int __init tegra_button_board_info(char *info)
1652 {
1653         char *p = info;
1654         button_board_info.board_id = memparse(p, &p);
1655         button_board_info.sku = memparse(p+1, &p);
1656         button_board_info.fab = memparse(p+1, &p);
1657         button_board_info.major_revision = memparse(p+1, &p);
1658         button_board_info.minor_revision = memparse(p+1, &p);
1659         return 1;
1660 }
1661
1662 void tegra_get_button_board_info(struct board_info *bi)
1663 {
1664         memcpy(bi, &button_board_info, sizeof(struct board_info));
1665 }
1666
1667 __setup("buttonboard=", tegra_button_board_info);
1668
1669 static int __init tegra_io_board_info(char *info)
1670 {
1671         char *p = info;
1672         io_board_info.board_id = memparse(p, &p);
1673         io_board_info.sku = memparse(p+1, &p);
1674         io_board_info.fab = memparse(p+1, &p);
1675         io_board_info.major_revision = memparse(p+1, &p);
1676         io_board_info.minor_revision = memparse(p+1, &p);
1677         return 1;
1678 }
1679
1680 void tegra_get_io_board_info(struct board_info *bi)
1681 {
1682         memcpy(bi, &io_board_info, sizeof(struct board_info));
1683 }
1684
1685 __setup("ioboard=", tegra_io_board_info);
1686
1687 static int __init tegra_modem_id(char *id)
1688 {
1689         char *p = id;
1690
1691         modem_id = memparse(p, &p);
1692         return 1;
1693 }
1694
1695 int tegra_get_modem_id(void)
1696 {
1697         return modem_id;
1698 }
1699
1700 __setup("modem_id=", tegra_modem_id);
1701
1702 static int __init tegra_usb_port_owner_info(char *id)
1703 {
1704         char *p = id;
1705
1706         usb_port_owner_info = memparse(p, &p);
1707         return 1;
1708 }
1709
1710 int tegra_get_usb_port_owner_info(void)
1711 {
1712         return usb_port_owner_info;
1713 }
1714
1715 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1716
1717 static int __init tegra_lane_owner_info(char *id)
1718 {
1719         char *p = id;
1720
1721         lane_owner_info = memparse(p, &p);
1722         return 1;
1723 }
1724
1725 int tegra_get_lane_owner_info(void)
1726 {
1727         return lane_owner_info;
1728 }
1729
1730 __setup("lane_owner_info=", tegra_lane_owner_info);
1731
1732 static int __init tegra_commchip_id(char *id)
1733 {
1734         char *p = id;
1735
1736         if (get_option(&p, &commchip_id) != 1)
1737                 return 0;
1738         return 1;
1739 }
1740
1741 int tegra_get_commchip_id(void)
1742 {
1743         return commchip_id;
1744 }
1745
1746 __setup("commchip_id=", tegra_commchip_id);
1747
1748 /*
1749  * Tegra has a protected aperture that prevents access by most non-CPU
1750  * memory masters to addresses above the aperture value.  Enabling it
1751  * secures the CPU's memory from the GPU, except through the GART.
1752  */
1753 void __init tegra_protected_aperture_init(unsigned long aperture)
1754 {
1755         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1756         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1757         writel(aperture, mc_base + MC_SECURITY_CFG2);
1758 }
1759
1760 /*
1761  * Due to conflicting restrictions on the placement of the framebuffer,
1762  * the bootloader is likely to leave the framebuffer pointed at a location
1763  * in memory that is outside the grhost aperture.  This function will move
1764  * the framebuffer contents from a physical address that is anywhere (lowmem,
1765  * highmem, or outside the memory map) to a physical address that is outside
1766  * the memory map.
1767  */
1768 void __tegra_move_framebuffer(struct platform_device *pdev,
1769         phys_addr_t to, phys_addr_t from,
1770         size_t size)
1771 {
1772         struct page *page;
1773         void __iomem *to_io;
1774         void *from_virt;
1775         unsigned long i;
1776
1777         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1778         BUG_ON(PAGE_ALIGN(from) != from);
1779         BUG_ON(PAGE_ALIGN(size) != size);
1780
1781         to_io = ioremap_wc(to, size);
1782         if (!to_io) {
1783                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1784                 return;
1785         }
1786
1787         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1788                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1789                         page = phys_to_page(from + i);
1790                         from_virt = kmap(page);
1791                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1792                         kunmap(page);
1793                 }
1794         } else if (from) {
1795                 void __iomem *from_io = ioremap_wc(from, size);
1796                 if (!from_io) {
1797                         pr_err("%s: Failed to map source framebuffer\n",
1798                                 __func__);
1799                         goto out;
1800                 }
1801
1802                 for (i = 0; i < size; i += 4)
1803                         writel_relaxed(readl_relaxed(from_io + i), to_io + i);
1804                 dmb();
1805
1806                 iounmap(from_io);
1807         }
1808
1809 out:
1810         iounmap(to_io);
1811 }
1812
1813 void __tegra_clear_framebuffer(struct platform_device *pdev,
1814                                unsigned long to, unsigned long size)
1815 {
1816         void __iomem *to_io;
1817         unsigned long i;
1818
1819         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1820         BUG_ON(PAGE_ALIGN(size) != size);
1821
1822         to_io = ioremap_wc(to, size);
1823         if (!to_io) {
1824                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1825                 return;
1826         }
1827
1828         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1829                 for (i = 0 ; i < size; i += PAGE_SIZE)
1830                         memset(to_io + i, 0, PAGE_SIZE);
1831         } else {
1832                 for (i = 0; i < size; i += 4)
1833                         writel_relaxed(0, to_io + i);
1834                 dmb();
1835         }
1836
1837         iounmap(to_io);
1838 }
1839
1840 #ifdef CONFIG_PSTORE_RAM
1841 static struct ramoops_platform_data ramoops_data;
1842
1843 static struct platform_device ramoops_dev  = {
1844         .name = "ramoops",
1845         .dev = {
1846                 .platform_data = &ramoops_data,
1847         },
1848 };
1849
1850
1851 static void __init tegra_reserve_ramoops_memory(unsigned long reserve_size)
1852 {
1853         ramoops_data.mem_size = reserve_size;
1854         ramoops_data.mem_address = memblock_end_of_4G() - reserve_size;
1855         ramoops_data.console_size = reserve_size - FTRACE_MEM_SIZE;
1856         ramoops_data.ftrace_size = FTRACE_MEM_SIZE;
1857         ramoops_data.dump_oops = 1;
1858         memblock_reserve(ramoops_data.mem_address, ramoops_data.mem_size);
1859 }
1860
1861 static int __init tegra_register_ramoops_device(void)
1862 {
1863         int ret = platform_device_register(&ramoops_dev);
1864         if (ret) {
1865                 pr_info("Unable to register ramoops platform device\n");
1866                 return ret;
1867         }
1868         return ret;
1869 }
1870 core_initcall(tegra_register_ramoops_device);
1871 #endif
1872
1873 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1874         unsigned long fb2_size)
1875 {
1876         struct iommu_linear_map map[4];
1877
1878 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1879         if (carveout_size) {
1880                 /*
1881                  * Place the carveout below the 4 GB physical address limit
1882                  * because IOVAs are only 32 bit wide.
1883                  */
1884                 BUG_ON(memblock_end_of_4G() == 0);
1885                 tegra_carveout_start = memblock_end_of_4G() - carveout_size;
1886                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1887                         pr_err("Failed to remove carveout %08lx@%08llx "
1888                                 "from memory map\n",
1889                                 carveout_size, (u64)tegra_carveout_start);
1890                         tegra_carveout_start = 0;
1891                         tegra_carveout_size = 0;
1892                 } else
1893                         tegra_carveout_size = carveout_size;
1894         }
1895 #endif
1896
1897         if (fb2_size) {
1898                 /*
1899                  * Place fb2 below the 4 GB physical address limit because
1900                  * IOVAs are only 32 bit wide.
1901                  */
1902                 BUG_ON(memblock_end_of_4G() == 0);
1903                 tegra_fb2_start = memblock_end_of_4G() - fb2_size;
1904                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1905                         pr_err("Failed to remove second framebuffer "
1906                                 "%08lx@%08llx from memory map\n",
1907                                 fb2_size, (u64)tegra_fb2_start);
1908                         tegra_fb2_start = 0;
1909                         tegra_fb2_size = 0;
1910                 } else
1911                         tegra_fb2_size = fb2_size;
1912         }
1913
1914         if (fb_size) {
1915                 /*
1916                  * Place fb below the 4 GB physical address limit because
1917                  * IOVAs are only 32 bit wide.
1918                  */
1919                 BUG_ON(memblock_end_of_4G() == 0);
1920                 tegra_fb_start = memblock_end_of_4G() - fb_size;
1921                 if (memblock_remove(tegra_fb_start, fb_size)) {
1922                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1923                                 "from memory map\n",
1924                                 fb_size, (u64)tegra_fb_start);
1925                         tegra_fb_start = 0;
1926                         tegra_fb_size = 0;
1927                 } else
1928                         tegra_fb_size = fb_size;
1929         }
1930
1931         if (tegra_cpu_is_asim()) {
1932                 if (tegra_split_mem_active()) {
1933                         tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1934                         tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1935
1936                         if (tegra_vpr_size == 0) {
1937                                 tegra_carveout_start =
1938                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1939                                 tegra_carveout_size =
1940                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1941                         } else if (
1942                                     (tegra_vpr_start <
1943                                      TEGRA_ASIM_QT_FB_START +
1944                                      TEGRA_ASIM_QT_FB_SIZE) ||
1945                                      (tegra_vpr_start + tegra_vpr_size - 1 >
1946                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1947                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1948                                 /*
1949                                  * On ASIM/ASIM + QT with
1950                                  * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1951                                  * the VPR region needs to be within the front
1952                                  * door memory region. Moreover, the VPR region
1953                                  * can't exist where the framebuffer resides.
1954                                  */
1955                                 BUG();
1956                         } else if (
1957                                         (tegra_vpr_start -
1958                                          (TEGRA_ASIM_QT_FB_START +
1959                                           TEGRA_ASIM_QT_FB_SIZE) <
1960                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1961                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1962                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1963                                          (tegra_vpr_start + tegra_vpr_size) <
1964                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1965                                 /*
1966                                  * The tegra ASIM/QT carveout has a min size:-
1967                                  * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1968                                  * regions in front door mem are smaller than
1969                                  * the min carveout size. Therefore, we can't
1970                                  * fit the carveout in front door mem.
1971                                  */
1972                                 BUG();
1973                         } else if (
1974                                         (tegra_vpr_start -
1975                                          (TEGRA_ASIM_QT_FB_START +
1976                                           TEGRA_ASIM_QT_FB_SIZE)) >=
1977                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1978                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1979                                          (tegra_vpr_start + tegra_vpr_size))) {
1980                                 /*
1981                                  * Place the tegra ASIM/QT carveout between the
1982                                  * framebuffer and VPR.
1983                                  */
1984                                 tegra_carveout_start =
1985                                   TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1986                                 tegra_carveout_size = tegra_vpr_start -
1987                                         (TEGRA_ASIM_QT_FB_START +
1988                                          TEGRA_ASIM_QT_FB_SIZE);
1989                         } else {
1990                                 /*
1991                                  * Place the tegra ASIM/QT carveout after VPR.
1992                                  */
1993                                 tegra_carveout_start = tegra_vpr_start +
1994                                                          tegra_vpr_size;
1995                                 tegra_carveout_size =
1996                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1997                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1998                                         (tegra_vpr_start + tegra_vpr_size);
1999                         }
2000                 } else if (tegra_vpr_size != 0) {
2001                         /*
2002                          * VPR cannot work on ASIM/ASIM + QT if split mem is not
2003                          * enabled.
2004                          */
2005                         BUG();
2006                 }
2007         }
2008
2009         if (tegra_fb_size)
2010                 tegra_grhost_aperture = tegra_fb_start;
2011
2012         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
2013                 tegra_grhost_aperture = tegra_fb2_start;
2014
2015         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
2016                 tegra_grhost_aperture = tegra_carveout_start;
2017
2018         if (tegra_lp0_vec_size &&
2019            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
2020                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
2021                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
2022                                 (u64)tegra_lp0_vec_size,
2023                                 (u64)tegra_lp0_vec_start);
2024                         tegra_lp0_vec_start = 0;
2025                         tegra_lp0_vec_size = 0;
2026                 }
2027                 tegra_lp0_vec_relocate = false;
2028         } else
2029                 tegra_lp0_vec_relocate = true;
2030
2031 #ifdef CONFIG_TEGRA_NVDUMPER
2032         if (nvdumper_reserved) {
2033                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
2034                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
2035                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
2036                         nvdumper_reserved = 0;
2037                 }
2038         }
2039 #endif
2040
2041 #ifdef CONFIG_TEGRA_USE_NCT
2042         if (tegra_nck_size &&
2043            (tegra_nck_start < memblock_end_of_DRAM())) {
2044                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
2045                         pr_err("Failed to reserve nck %08lx@%08lx\n",
2046                                 tegra_nck_size, tegra_nck_start);
2047                         tegra_nck_start = 0;
2048                         tegra_nck_size = 0;
2049                 }
2050         }
2051 #endif
2052
2053         /*
2054          * We copy the bootloader's framebuffer to the framebuffer allocated
2055          * above, and then free this one.
2056          * */
2057         if (tegra_bootloader_fb_size) {
2058                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
2059                 if (memblock_reserve(tegra_bootloader_fb_start,
2060                                 tegra_bootloader_fb_size)) {
2061                         pr_err("Failed to reserve bootloader frame buffer "
2062                                 "%08llx@%08llx\n",
2063                                 (u64)tegra_bootloader_fb_size,
2064                                 (u64)tegra_bootloader_fb_start);
2065                         tegra_bootloader_fb_start = 0;
2066                         tegra_bootloader_fb_size = 0;
2067                 }
2068         }
2069
2070         if (tegra_bootloader_fb2_size) {
2071                 tegra_bootloader_fb2_size =
2072                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2073                 if (memblock_reserve(tegra_bootloader_fb2_start,
2074                                 tegra_bootloader_fb2_size)) {
2075                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2076                                 (u64)tegra_bootloader_fb2_size,
2077                                 (u64)tegra_bootloader_fb2_start);
2078                         tegra_bootloader_fb2_start = 0;
2079                         tegra_bootloader_fb2_size = 0;
2080                 }
2081         }
2082
2083         pr_info("Tegra reserved memory:\n"
2084                 "LP0:                    %08llx - %08llx\n"
2085                 "Bootloader framebuffer: %08llx - %08llx\n"
2086                 "Bootloader framebuffer2: %08llx - %08llx\n"
2087                 "Framebuffer:            %08llx - %08llx\n"
2088                 "2nd Framebuffer:        %08llx - %08llx\n"
2089 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2090                 "Carveout:               %08llx - %08llx\n"
2091                 "Vpr:                    %08llx - %08llx\n"
2092 #endif
2093                 "Tsec:                   %08llx - %08llx\n",
2094                 (u64)tegra_lp0_vec_start,
2095                 (u64)(tegra_lp0_vec_size ?
2096                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2097                 (u64)tegra_bootloader_fb_start,
2098                 (u64)(tegra_bootloader_fb_size ?
2099                         tegra_bootloader_fb_start +
2100                         tegra_bootloader_fb_size - 1 : 0),
2101                 (u64)tegra_bootloader_fb2_start,
2102                 (u64)(tegra_bootloader_fb2_size ?
2103                         tegra_bootloader_fb2_start +
2104                         tegra_bootloader_fb2_size - 1 : 0),
2105                 (u64)tegra_fb_start,
2106                 (u64)(tegra_fb_size ?
2107                         tegra_fb_start + tegra_fb_size - 1 : 0),
2108                 (u64)tegra_fb2_start,
2109                 (u64)(tegra_fb2_size ?
2110                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2111 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2112                 (u64)tegra_carveout_start,
2113                 (u64)(tegra_carveout_size ?
2114                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2115                 (u64)tegra_vpr_start,
2116                 (u64)(tegra_vpr_size ?
2117                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2118 #endif
2119                 (u64)tegra_tsec_start,
2120                 (u64)(tegra_tsec_size ?
2121                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
2122
2123
2124 #ifdef CONFIG_TEGRA_NVDUMPER
2125         if (nvdumper_reserved) {
2126                 pr_info("Nvdumper:               %08lx - %08lx\n",
2127                         nvdumper_reserved,
2128                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2129         }
2130 #endif
2131
2132 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
2133         pr_info("Tzram:               %08lx - %08lx\n",
2134                 tegra_tzram_start,
2135                 tegra_tzram_size ?
2136                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2137 #endif
2138
2139 #ifdef CONFIG_TEGRA_USE_NCT
2140         if (tegra_nck_size) {
2141                 pr_info("Nck:                    %08lx - %08lx\n",
2142                         tegra_nck_start,
2143                         tegra_nck_size ?
2144                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2145         }
2146 #endif
2147
2148 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2149         /* Keep these at the end */
2150         if (carveout_size) {
2151                 if (dma_declare_contiguous(&tegra_generic_cma_dev,
2152                         carveout_size, 0, memblock_end_of_4G()))
2153                         pr_err("dma_declare_contiguous failed for generic\n");
2154                 tegra_carveout_size = carveout_size;
2155         }
2156
2157         if (tegra_vpr_size)
2158                 if (dma_declare_contiguous(&tegra_vpr_cma_dev,
2159                         tegra_vpr_size, 0, memblock_end_of_4G()))
2160                         pr_err("dma_declare_contiguous failed VPR carveout\n");
2161 #endif
2162
2163         tegra_fb_linear_set(map);
2164 #ifdef CONFIG_PSTORE_RAM
2165         tegra_reserve_ramoops_memory(RAMOOPS_MEM_SIZE);
2166 #endif
2167 }
2168
2169 void tegra_reserve4(ulong carveout_size, ulong fb_size,
2170                        ulong fb2_size, ulong vpr_size)
2171 {
2172 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2173         tegra_vpr_start = 0;
2174         tegra_vpr_size = vpr_size;
2175 #endif
2176         tegra_reserve(carveout_size, fb_size, fb2_size);
2177 }
2178
2179 void tegra_get_fb_resource(struct resource *fb_res)
2180 {
2181         fb_res->start = (resource_size_t) tegra_fb_start;
2182         fb_res->end = fb_res->start +
2183                         (resource_size_t) tegra_fb_size - 1;
2184 }
2185
2186 void tegra_get_fb2_resource(struct resource *fb2_res)
2187 {
2188         fb2_res->start = (resource_size_t) tegra_fb2_start;
2189         fb2_res->end = fb2_res->start +
2190                         (resource_size_t) tegra_fb2_size - 1;
2191 }
2192
2193
2194
2195 int __init tegra_register_fuse(void)
2196 {
2197         return platform_device_register(&tegra_fuse_device);
2198 }
2199
2200 int __init tegra_release_bootloader_fb(void)
2201 {
2202         /* Since bootloader fb is reserved in common.c, it is freed here. */
2203         if (tegra_bootloader_fb_size) {
2204                 if (memblock_free(tegra_bootloader_fb_start,
2205                                                 tegra_bootloader_fb_size))
2206                         pr_err("Failed to free bootloader fb.\n");
2207                 else
2208                         free_bootmem_late(tegra_bootloader_fb_start,
2209                                                 tegra_bootloader_fb_size);
2210         }
2211         if (tegra_bootloader_fb2_size) {
2212                 if (memblock_free(tegra_bootloader_fb2_start,
2213                                                 tegra_bootloader_fb2_size))
2214                         pr_err("Failed to free bootloader fb2.\n");
2215                 else
2216                         free_bootmem_late(tegra_bootloader_fb2_start,
2217                                                 tegra_bootloader_fb2_size);
2218         }
2219         return 0;
2220 }
2221 late_initcall(tegra_release_bootloader_fb);
2222
2223 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2224         [TEGRA_REVISION_UNKNOWN] = "unknown",
2225         [TEGRA_REVISION_A01]     = "A01",
2226         [TEGRA_REVISION_A02]     = "A02",
2227         [TEGRA_REVISION_A03]     = "A03",
2228         [TEGRA_REVISION_A03p]    = "A03 prime",
2229         [TEGRA_REVISION_A04]     = "A04",
2230         [TEGRA_REVISION_A04p]    = "A04 prime",
2231 };
2232
2233 static const char * __init tegra_get_revision(void)
2234 {
2235         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2236 }
2237
2238 static const char * __init tegra_get_family(void)
2239 {
2240         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2241         u32 cid = readl(chip_id);
2242         cid = (cid >> 8) & 0xFF;
2243
2244         switch (cid) {
2245         case TEGRA_CHIPID_TEGRA2:
2246                 cid = 2;
2247                 break;
2248         case TEGRA_CHIPID_TEGRA3:
2249                 cid = 3;
2250                 break;
2251         case TEGRA_CHIPID_TEGRA11:
2252                 cid = 11;
2253                 break;
2254         case TEGRA_CHIPID_TEGRA12:
2255                 cid = 12;
2256                 break;
2257         case TEGRA_CHIPID_TEGRA13:
2258                 cid = 13;
2259                 break;
2260         case TEGRA_CHIPID_TEGRA14:
2261                 cid = 14;
2262                 break;
2263
2264         case TEGRA_CHIPID_UNKNOWN:
2265         default:
2266                 cid = 0;
2267         }
2268         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2269 }
2270
2271 static const char * __init tegra_get_soc_id(void)
2272 {
2273         int package_id = tegra_package_id();
2274
2275         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2276                 tegra_revision_name[tegra_revision],
2277                 tegra_get_sku_id(), package_id);
2278 }
2279
2280 static void __init tegra_soc_info_populate(struct soc_device_attribute
2281         *soc_dev_attr, const char *machine)
2282 {
2283         soc_dev_attr->soc_id = tegra_get_soc_id();
2284         soc_dev_attr->machine  = machine;
2285         soc_dev_attr->family   = tegra_get_family();
2286         soc_dev_attr->revision = tegra_get_revision();
2287 }
2288
2289 int __init tegra_soc_device_init(const char *machine)
2290 {
2291         struct soc_device *soc_dev;
2292         struct soc_device_attribute *soc_dev_attr;
2293
2294         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2295         if (!soc_dev_attr)
2296                 return -ENOMEM;
2297
2298         tegra_soc_info_populate(soc_dev_attr, machine);
2299
2300         soc_dev = soc_device_register(soc_dev_attr);
2301         if (IS_ERR_OR_NULL(soc_dev)) {
2302                 kfree(soc_dev_attr);
2303                 return -1;
2304         }
2305
2306         return 0;
2307 }
2308
2309 void __init tegra_init_late(void)
2310 {
2311 #ifndef CONFIG_COMMON_CLK
2312         tegra_clk_debugfs_init();
2313 #endif
2314         tegra_powergate_debugfs_init();
2315 }
2316
2317 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2318 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2319
2320 static void asim_power_off(void)
2321 {
2322         pr_err("ASIM Powering off the device\n");
2323         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2324         while (1)
2325                 ;
2326 }
2327
2328 static int __init asim_power_off_init(void)
2329 {
2330         if (tegra_cpu_is_asim())
2331                 pm_power_off = asim_power_off;
2332         return 0;
2333 }
2334
2335 arch_initcall(asim_power_off_init);
2336
2337 #if defined(CONFIG_SMC91X)
2338 static struct resource tegra_asim_smc91x_resources[] = {
2339         [0] = {
2340                 .start          = TEGRA_SIM_ETH_BASE,
2341                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2342                 .flags          = IORESOURCE_MEM,
2343         },
2344         [1] = {
2345                 .start          = IRQ_ETH,
2346                 .end            = IRQ_ETH,
2347                 .flags          = IORESOURCE_IRQ,
2348         },
2349 };
2350
2351 static struct platform_device tegra_asim_smc91x_device = {
2352         .name           = "smc91x",
2353         .id             = 0,
2354         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2355         .resource       = tegra_asim_smc91x_resources,
2356 };
2357
2358 static int __init asim_enet_smc91x_init(void)
2359 {
2360         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2361                 platform_device_register(&tegra_asim_smc91x_device);
2362         return 0;
2363 }
2364
2365 rootfs_initcall(asim_enet_smc91x_init);
2366 #endif
2367 #endif
2368
2369 #if defined(CONFIG_SMSC911X)
2370 static struct resource tegra_smsc911x_resources[] = {
2371         [0] = {
2372                 .start          = 0x4E000000,
2373                 .end            = 0x4E000000 + SZ_64K - 1,
2374                 .flags          = IORESOURCE_MEM,
2375         },
2376         [1] = {
2377                 .start          = IRQ_ETH,
2378                 .end            = IRQ_ETH,
2379                 .flags          = IORESOURCE_IRQ,
2380         },
2381 };
2382
2383 static struct smsc911x_platform_config tegra_smsc911x_config = {
2384         .flags          = SMSC911X_USE_32BIT,
2385         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2386         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2387         .phy_interface  = PHY_INTERFACE_MODE_MII,
2388 };
2389
2390 static struct platform_device tegra_smsc911x_device = {
2391         .name              = "smsc911x",
2392         .id                = 0,
2393         .resource          = tegra_smsc911x_resources,
2394         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2395         .dev.platform_data = &tegra_smsc911x_config,
2396 };
2397
2398 static int __init enet_smsc911x_init(void)
2399 {
2400         if (!tegra_cpu_is_dsim() && !tegra_platform_is_qt())
2401                 platform_device_register(&tegra_smsc911x_device);
2402         return 0;
2403 }
2404
2405 rootfs_initcall(enet_smsc911x_init);
2406 #endif
2407
2408 int tegra_split_mem_active(void)
2409 {
2410         return tegra_split_mem_set;
2411 }
2412
2413 static int __init set_tegra_split_mem(char *options)
2414 {
2415         tegra_split_mem_set = 1;
2416         return 0;
2417 }
2418 early_param("tegra_split_mem", set_tegra_split_mem);
2419
2420 #define FUSE_SKU_INFO       0x110
2421 #define STRAP_OPT 0x008
2422 #define GMI_AD0 BIT(4)
2423 #define GMI_AD1 BIT(5)
2424 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
2425 #define RAM_CODE_SHIFT 4
2426
2427 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2428 static enum tegra_platform tegra_platform;
2429 static bool cpu_is_asim;
2430 static bool cpu_is_dsim;
2431 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
2432         [TEGRA_PLATFORM_SILICON] = "silicon",
2433         [TEGRA_PLATFORM_QT]      = "quickturn",
2434         [TEGRA_PLATFORM_LINSIM]  = "linsim",
2435         [TEGRA_PLATFORM_FPGA]    = "fpga",
2436 };
2437 #endif
2438
2439 static u32 tegra_chip_sku_id;
2440 static u32 tegra_chip_id;
2441 static u32 tegra_chip_bct_strapping;
2442 enum tegra_revision tegra_revision;
2443
2444 u32 tegra_read_pmc_reg(int offset)
2445 {
2446         return readl(IO_ADDRESS(TEGRA_PMC_BASE) + offset);
2447 }
2448
2449 u32 tegra_read_clk_ctrl_reg(int offset)
2450 {
2451         return readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + offset);
2452 }
2453
2454 u32 tegra_read_apb_misc_reg(int offset)
2455 {
2456         return readl(IO_ADDRESS(TEGRA_APB_MISC_BASE) + offset);
2457 }
2458
2459 u32 tegra_fuse_readl(unsigned long offset)
2460 {
2461         return readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2462 }
2463
2464 void tegra_fuse_writel(u32 val, unsigned long offset)
2465 {
2466         writel(val, IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2467 }
2468
2469 u32 tegra_read_chipid(void)
2470 {
2471         return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE)
2472                         + 0x804);
2473 }
2474
2475 static void tegra_set_sku_id(void)
2476 {
2477         u32 reg;
2478
2479         reg = tegra_fuse_readl(FUSE_SKU_INFO);
2480         tegra_chip_sku_id = reg & 0xFF;
2481 }
2482
2483 static void tegra_set_chip_id(void)
2484 {
2485         u32 id;
2486
2487         id = tegra_read_chipid();
2488         tegra_chip_id = (id >> 8) & 0xff;
2489 }
2490
2491 static void tegra_set_bct_strapping(void)
2492 {
2493         u32 reg;
2494
2495         reg = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + STRAP_OPT));
2496         tegra_chip_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
2497 }
2498
2499 u32 tegra_get_sku_id(void)
2500 {
2501         return tegra_chip_sku_id;
2502 }
2503
2504 u32 tegra_get_chip_id(void)
2505 {
2506         return tegra_chip_id;
2507 }
2508
2509 u32 tegra_get_bct_strapping(void)
2510 {
2511         return tegra_chip_bct_strapping;
2512 }
2513
2514 static void tegra_fuse_cfg_reg_visible(void)
2515 {
2516         /* Make all fuse registers visible */
2517         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2518         reg |= BIT(28);
2519         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2520 }
2521
2522 void tegra_init_fuse(void)
2523 {
2524         u32 sku_id;
2525
2526         tegra_fuse_cfg_reg_visible();
2527         tegra_set_sku_id();
2528         sku_id = tegra_get_sku_id();
2529         tegra_set_bct_strapping();
2530         tegra_set_chip_id();
2531         tegra_revision = tegra_chip_get_revision();
2532         tegra_init_speedo_data();
2533         pr_info("Tegra Revision: %s SKU: 0x%x CPU Process: %d Core Process: %d\n",
2534                 tegra_revision_name[tegra_revision],
2535                 sku_id, tegra_cpu_process_id(),
2536                 tegra_core_process_id());
2537 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2538         if (!tegra_platform_is_silicon()) {
2539                 pr_info("Tegra Platform: %s%s%s\n",
2540                         tegra_cpu_is_asim() ? "ASIM+" : "",
2541                         tegra_cpu_is_dsim() ? "DSIM+" : "",
2542                         tegra_platform_name[tegra_platform]);
2543         }
2544 #endif
2545 }
2546
2547 void __init display_tegra_dt_info(void)
2548 {
2549         unsigned long dt_root;
2550         const char *dts_fname;
2551
2552
2553         dt_root = of_get_flat_dt_root();
2554
2555         dts_fname = of_get_flat_dt_prop(dt_root, "nvidia,dtsfilename", NULL);
2556         if (dts_fname)
2557                 pr_info("DTS File Name: %s\n", dts_fname);
2558         else
2559                 pr_info("DTS File Name: <unknown>\n");
2560 }
2561
2562 static int __init tegra_get_last_reset_reason(void)
2563 {
2564 #define PMC_RST_STATUS 0x1b4
2565 #define RESET_STR(REASON) "last reset is due to "#REASON"\n"
2566         char *reset_reason[] = {
2567                 RESET_STR(power on reset),
2568                 RESET_STR(watchdog timeout),
2569                 RESET_STR(sensor),
2570                 RESET_STR(software reset),
2571                 RESET_STR(deep sleep reset),
2572         };
2573
2574         u32 val = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_RST_STATUS) & 0x7;
2575         if (val >= ARRAY_SIZE(reset_reason))
2576                 pr_info("last reset value is invalid 0x%x\n", val);
2577         else
2578                 pr_info("%s\n", reset_reason[val]);
2579         return 0;
2580 }
2581 late_initcall(tegra_get_last_reset_reason);