ARM: tegra: reserve memory for ramoops by default
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2014 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_fdt.h>
35 #include <linux/pstore_ram.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/sys_soc.h>
38 #if defined(CONFIG_SMSC911X)
39 #include <linux/smsc911x.h>
40 #endif
41 #include <linux/pm.h>
42 #include <linux/tegra-powergate.h>
43
44 #include <linux/export.h>
45 #include <linux/bootmem.h>
46 #include <linux/tegra-soc.h>
47 #include <linux/dma-contiguous.h>
48 #include <linux/tegra-fuse.h>
49
50 #ifdef CONFIG_ARM64
51 #include <linux/irqchip/gic.h>
52 #else
53 #include <asm/system.h>
54 #include <asm/hardware/cache-l2x0.h>
55 #endif
56 #include <asm/dma-mapping.h>
57
58 #include <mach/tegra_smmu.h>
59 #include <mach/nct.h>
60 #include <mach/dc.h>
61
62 #include "apbio.h"
63 #include "board.h"
64 #include "clock.h"
65 #include "common.h"
66 #include "dvfs.h"
67 #include "iomap.h"
68 #include "pm.h"
69 #include "sleep.h"
70 #include "reset.h"
71 #include "devices.h"
72 #include "pmc.h"
73
74 #define MC_SECURITY_CFG2        0x7c
75
76 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
77 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
78 #define   PRIORITY_SELECT_USB   BIT(6)
79 #define   PRIORITY_SELECT_USB2  BIT(18)
80 #define   PRIORITY_SELECT_USB3  BIT(17)
81 #define   PRIORITY_SELECT_SE BIT(14)
82
83 #define AHB_GIZMO_AHB_MEM               0xc
84 #define   ENB_FAST_REARBITRATE  BIT(2)
85 #define   DONT_SPLIT_AHB_WR     BIT(7)
86 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
87 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
88
89 #define   RECOVERY_MODE BIT(31)
90 #define   BOOTLOADER_MODE       BIT(30)
91 #define   FORCED_RECOVERY_MODE  BIT(1)
92
93 #define AHB_GIZMO_USB           0x1c
94 #define AHB_GIZMO_USB2          0x78
95 #define AHB_GIZMO_USB3          0x7c
96 #define AHB_GIZMO_SE            0x4c
97 #define   IMMEDIATE     BIT(18)
98
99 #define AHB_MEM_PREFETCH_CFG5   0xc8
100 #define AHB_MEM_PREFETCH_CFG3   0xe0
101 #define AHB_MEM_PREFETCH_CFG4   0xe4
102 #define AHB_MEM_PREFETCH_CFG1   0xec
103 #define AHB_MEM_PREFETCH_CFG2   0xf0
104 #define AHB_MEM_PREFETCH_CFG6   0xcc
105 #define   PREFETCH_ENB  BIT(31)
106 #define   MST_ID(x)     (((x) & 0x1f) << 26)
107 #define   AHBDMA_MST_ID MST_ID(5)
108 #define   USB_MST_ID    MST_ID(6)
109 #define SDMMC4_MST_ID   MST_ID(12)
110 #define   USB2_MST_ID   MST_ID(18)
111 #define   USB3_MST_ID   MST_ID(17)
112 #define   SE_MST_ID     MST_ID(14)
113 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
114 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
115
116 phys_addr_t tegra_bootloader_fb_start;
117 phys_addr_t tegra_bootloader_fb_size;
118 phys_addr_t tegra_bootloader_fb2_start;
119 phys_addr_t tegra_bootloader_fb2_size;
120 phys_addr_t tegra_fb_start;
121 phys_addr_t tegra_fb_size;
122 phys_addr_t tegra_fb2_start;
123 phys_addr_t tegra_fb2_size;
124 phys_addr_t tegra_carveout_start;
125 phys_addr_t tegra_carveout_size;
126 phys_addr_t tegra_vpr_start;
127 phys_addr_t tegra_vpr_size;
128 phys_addr_t tegra_tsec_start;
129 phys_addr_t tegra_tsec_size;
130 phys_addr_t tegra_lp0_vec_start;
131 phys_addr_t tegra_lp0_vec_size;
132 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
133 phys_addr_t tegra_wb0_params_address;
134 phys_addr_t tegra_wb0_params_instances;
135 phys_addr_t tegra_wb0_params_block_size;
136 #endif
137
138 #ifdef CONFIG_TEGRA_NVDUMPER
139 unsigned long nvdumper_reserved;
140 #endif
141 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
142 unsigned long tegra_tzram_start;
143 unsigned long tegra_tzram_size;
144 #endif
145 bool tegra_lp0_vec_relocate;
146 unsigned long tegra_grhost_aperture = ~0ul;
147 static   bool is_tegra_debug_uart_hsport;
148 static struct board_info main_board_info;
149 static struct board_info pmu_board_info;
150 static struct board_info display_board_info;
151 static int panel_id;
152 static struct board_info camera_board_info;
153 static int touch_vendor_id;
154 static int touch_panel_id;
155 static struct board_info io_board_info;
156 static struct board_info button_board_info;
157 static struct board_info joystick_board_info;
158 static struct board_info rightspeaker_board_info;
159 static struct board_info leftspeaker_board_info;
160 #ifdef CONFIG_TEGRA_USE_NCT
161 unsigned long tegra_nck_start;
162 unsigned long tegra_nck_size;
163 #endif
164
165 static int pmu_core_edp;
166 static int board_panel_type;
167 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
168 static int pwr_i2c_clk = 400;
169 static u8 power_config;
170 static u8 display_config;
171
172 static int tegra_split_mem_set;
173
174 struct device tegra_generic_cma_dev;
175 struct device tegra_vpr_cma_dev;
176
177 #define CREATE_TRACE_POINTS
178 #include <trace/events/nvsecurity.h>
179
180 u32 notrace tegra_read_cycle(void)
181 {
182         u32 cycle_count;
183
184         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cycle_count));
185
186         return cycle_count;
187 }
188
189 /*
190  * Storage for debug-macro.S's state.
191  *
192  * This must be in .data not .bss so that it gets initialized each time the
193  * kernel is loaded. The data is declared here rather than debug-macro.S so
194  * that multiple inclusions of debug-macro.S point at the same data.
195  */
196 u32 tegra_uart_config[4] = {
197         /* Debug UART initialization required */
198         1,
199         /* Debug UART physical address */
200         0,
201         /* Debug UART virtual address */
202         0,
203         /* Scratch space for debug macro */
204         0,
205 };
206
207
208 #define NEVER_RESET 0
209 static DEFINE_SPINLOCK(ahb_lock);
210
211 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
212 {
213         unsigned long check;
214         int retry = 10;
215         unsigned long flags;
216
217         /* Read and check if write is successful,
218          * if val doesn't match with read, retry write.
219          */
220         spin_lock_irqsave(&ahb_lock, flags);
221         do {
222                 writel(val, reg);
223                 check = readl(reg);
224                 if (likely(check == val))
225                         break;
226                 else
227                         pr_err("AHB register access fail for reg\n");
228         } while (--retry);
229         spin_unlock_irqrestore(&ahb_lock, flags);
230 }
231
232 void tegra_assert_system_reset(char mode, const char *cmd)
233 {
234         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
235         u32 reg;
236         bool empty_command = false;
237
238         if (tegra_platform_is_fpga() || NEVER_RESET) {
239                 pr_info("tegra_assert_system_reset() ignored.....");
240                 do { } while (1);
241         }
242
243         reg = readl_relaxed(reset + PMC_SCRATCH0);
244         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
245         if (cmd) {
246                 if (!strcmp(cmd, "recovery"))
247                         reg |= RECOVERY_MODE;
248                 else if (!strcmp(cmd, "bootloader"))
249                         reg |= BOOTLOADER_MODE;
250                 else if (!strcmp(cmd, "forced-recovery"))
251                         reg |= FORCED_RECOVERY_MODE;
252                 else {
253                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
254                         empty_command = true;
255                 }
256         }
257         else {
258                 /* Clearing SCRATCH0 31:30:1 on default reboot */
259                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
260         }
261         writel_relaxed(reg, reset + PMC_SCRATCH0);
262         if ((!cmd || empty_command) && pm_power_reset) {
263                 pm_power_reset();
264         } else {
265                 reg = readl_relaxed(reset);
266                 reg |= 0x10;
267                 writel_relaxed(reg, reset);
268         }
269 }
270 static int modem_id;
271 static int commchip_id;
272 static int sku_override;
273 static int debug_uart_port_id;
274 static bool uart_over_sd;
275 static enum audio_codec_type audio_codec_name;
276 static enum image_type board_image_type = system_image;
277 static int max_cpu_current;
278 static int max_core_current;
279 static int emc_max_dvfs;
280 static unsigned int memory_type;
281 static int usb_port_owner_info;
282 static int lane_owner_info;
283
284 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
285 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
286         /* name         parent          rate            enabled */
287         { "clk_m",      NULL,           0,              true },
288         { "emc",        NULL,           0,              true },
289         { "cpu",        NULL,           0,              true },
290         { "kfuse",      NULL,           0,              true },
291         { "fuse",       NULL,           0,              true },
292         { "sclk",       NULL,           0,              true },
293         { "pll_p",      NULL,           0,              true },
294         { "pll_p_out1", "pll_p",        0,              false },
295         { "pll_p_out3", "pll_p",        0,              false },
296 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
297         { "pll_m_out1", "pll_m",        275000000,      false },
298         { "pll_p_out2",  "pll_p",       102000000,      false },
299         { "sclk",        "pll_p_out2",  102000000,      true },
300         { "pll_p_out4",  "pll_p",       204000000,      true },
301         { "hclk",       "sclk",         102000000,      true },
302         { "pclk",       "hclk",         51000000,       true },
303         { "mselect",    "pll_p",        102000000,      true },
304         { "host1x",     "pll_p",        102000000,      false },
305         { "cl_dvfs_ref", "pll_p",       51000000,       true },
306         { "cl_dvfs_soc", "pll_p",       51000000,       true },
307         { "dsialp", "pll_p",    70000000,       false },
308         { "dsiblp", "pll_p",    70000000,       false },
309 #else
310         { "pll_m_out1", "pll_m",        275000000,      true },
311         { "pll_p_out2", "pll_p",        108000000,      false },
312         { "sclk",       "pll_p_out2",   108000000,      true },
313         { "pll_p_out4", "pll_p",        216000000,      true },
314         { "hclk",       "sclk",         108000000,      true },
315         { "pclk",       "hclk",         54000000,       true },
316         { "mselect",    "pll_p",        108000000,      true },
317         { "host1x",     "pll_p",        108000000,      false },
318         { "cl_dvfs_ref", "clk_m",       13000000,       false },
319         { "cl_dvfs_soc", "clk_m",       13000000,       false },
320 #endif
321 #ifdef CONFIG_TEGRA_SLOW_CSITE
322         { "csite",      "clk_m",        1000000,        true },
323 #else
324         { "csite",      NULL,           0,              true },
325 #endif
326         { "pll_u",      NULL,           480000000,      true },
327         { "pll_re_vco", NULL,           612000000,      true },
328         { "xusb_falcon_src",    "pll_p",        204000000,      false},
329         { "xusb_host_src",      "pll_p",        102000000,      false},
330         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
331         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
332         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
333         { "sdmmc1",     "pll_p",        48000000,       false},
334         { "sdmmc3",     "pll_p",        48000000,       false},
335         { "sdmmc4",     "pll_p",        48000000,       false},
336         { "sbc1.sclk",  NULL,           40000000,       false},
337         { "sbc2.sclk",  NULL,           40000000,       false},
338         { "sbc3.sclk",  NULL,           40000000,       false},
339         { "sbc4.sclk",  NULL,           40000000,       false},
340         { "sbc5.sclk",  NULL,           40000000,       false},
341         { "sbc6.sclk",  NULL,           40000000,       false},
342 #ifdef CONFIG_TEGRA_DUAL_CBUS
343         { "c2bus",      "pll_c2",       250000000,      false },
344         { "c3bus",      "pll_c3",       250000000,      false },
345         { "pll_c",      NULL,           624000000,      false },
346 #else
347         { "cbus",       "pll_c",        250000000,      false },
348 #endif
349         { "pll_c_out1", "pll_c",        150000000,      false },
350 #ifdef CONFIG_TEGRA_PLLM_SCALED
351         { "vi",         "pll_p",        0,              false},
352 #endif
353 #ifdef CONFIG_TEGRA_SOCTHERM
354         { "soc_therm",  "pll_p",        136000000,      false },
355         { "tsensor",    "clk_m",        500000,         false },
356 #endif
357         { "csite",      NULL,           0,              true },
358         { NULL,         NULL,           0,              0},
359 };
360 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
361 #ifdef CONFIG_TEGRA_DUAL_CBUS
362         { "c2bus",      "pll_c2",       250000000,      false },
363         { "c3bus",      "pll_c3",       250000000,      false },
364         { "pll_c",      NULL,           624000000,      false },
365 #else
366         { "cbus",       "pll_c",        250000000,      false },
367 #endif
368         { "pll_c_out1", "pll_c",        150000000,      false },
369         { NULL,         NULL,           0,              0},
370 };
371 #endif
372 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
373 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
374         /* name         parent          rate            enabled */
375         { "clk_m",      NULL,           0,              true },
376         { "mc",         NULL,           0,              true },
377         { "cpu",        NULL,           0,              true },
378         { "kfuse",      NULL,           0,              true },
379         { "fuse",       NULL,           0,              true },
380         { "sclk",       NULL,           0,              true },
381         { "pll_p",      NULL,           0,              true,
382                 TEGRA_CLK_INIT_PLATFORM_SI },
383         { "pll_p_out1", "pll_p",        0,              false,
384                 TEGRA_CLK_INIT_PLATFORM_SI },
385         { "pll_p_out3", "pll_p",        0,              true,
386                 TEGRA_CLK_INIT_PLATFORM_SI },
387         { "pll_m_out1", "pll_m",        275000000,      false,
388                 TEGRA_CLK_INIT_PLATFORM_SI },
389         { "pll_p_out2", "pll_p",        102000000,      false,
390                 TEGRA_CLK_INIT_PLATFORM_SI },
391         { "sclk",       "pll_p_out2",   102000000,      true,
392                 TEGRA_CLK_INIT_PLATFORM_SI },
393         { "pll_p_out4", "pll_p",        204000000,      true,
394                 TEGRA_CLK_INIT_PLATFORM_SI },
395         { "host1x",     "pll_p",        102000000,      false,
396                 TEGRA_CLK_INIT_PLATFORM_SI },
397         { "cl_dvfs_ref", "pll_p",       54000000,       true,
398                 TEGRA_CLK_INIT_PLATFORM_SI },
399         { "cl_dvfs_soc", "pll_p",       54000000,       true,
400                 TEGRA_CLK_INIT_PLATFORM_SI },
401         { "hclk",       "sclk",         102000000,      true,
402                 TEGRA_CLK_INIT_PLATFORM_SI },
403         { "pclk",       "hclk",         51000000,       true,
404                 TEGRA_CLK_INIT_PLATFORM_SI },
405         { "wake.sclk",  NULL,           40000000,       true,
406                 TEGRA_CLK_INIT_PLATFORM_SI },
407         { "mselect",    "pll_p",        102000000,      true,
408                 TEGRA_CLK_INIT_PLATFORM_SI },
409         { "pll_p_out5", "pll_p",        102000000,      true,
410                 TEGRA_CLK_INIT_PLATFORM_SI },
411 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
412         { "pll_m_out1", "pll_m",        275000000,      true,
413                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
414         { "pll_p_out2", "pll_p",        108000000,      false,
415                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
416         { "sclk",       "pll_p_out2",   108000000,      true,
417                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
418         { "pll_p_out4", "pll_p",        216000000,      true,
419                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
420         { "hclk",       "sclk",         108000000,      true,
421                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
422         { "pclk",       "hclk",         54000000,       true,
423                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
424         { "mselect",    "pll_p",        108000000,      true,
425                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
426         { "host1x",     "pll_p",        108000000,      false,
427                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
428         { "cl_dvfs_ref", "clk_m",       13000000,       false,
429                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
430         { "cl_dvfs_soc", "clk_m",       13000000,       false,
431                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
432         { "vde",        "pll_c3",       48400000,       true,
433                 TEGRA_CLK_INIT_CPU_ASIM},
434 #endif
435 #ifdef CONFIG_TEGRA_SLOW_CSITE
436         { "csite",      "clk_m",        1000000,        true },
437 #else
438         { "csite",      NULL,           0,              true },
439 #endif
440         { "pll_u",      NULL,           480000000,      true },
441         { "pll_re_vco", NULL,           672000000,      true },
442         { "xusb_falcon_src",    "pll_re_out",   224000000,      false},
443         { "xusb_host_src",      "pll_re_out",   112000000,      false},
444         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
445         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
446         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
447         { "sdmmc1",     "pll_p",        48000000,       false},
448         { "sdmmc3",     "pll_p",        48000000,       false},
449         { "sdmmc4",     "pll_p",        48000000,       false},
450         { "sdmmc1_ddr", "pll_p",        48000000,       false},
451         { "sdmmc3_ddr", "pll_p",        48000000,       false},
452         { "sdmmc4_ddr", "pll_p",        48000000,       false},
453         { "sbc1.sclk",  NULL,           40000000,       false},
454         { "sbc2.sclk",  NULL,           40000000,       false},
455         { "sbc3.sclk",  NULL,           40000000,       false},
456         { "sbc4.sclk",  NULL,           40000000,       false},
457         { "sbc5.sclk",  NULL,           40000000,       false},
458         { "sbc6.sclk",  NULL,           40000000,       false},
459         { "cpu.mselect", NULL,          102000000,      true},
460         { "gpu_ref",    NULL,           0,              true},
461         { "gk20a.gbus", NULL,           252000000,      false},
462 #ifdef CONFIG_TEGRA_PLLM_SCALED
463         { "vi",         "pll_p",        0,              false},
464         { "isp",        "pll_p",        0,              false},
465 #endif
466 #ifdef CONFIG_TEGRA_SOCTHERM
467         { "soc_therm",  "pll_p",        51000000,       false },
468         { "tsensor",    "clk_m",        500000,         false },
469 #endif
470         { NULL,         NULL,           0,              0},
471 };
472 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
473         /* Initialize c2bus, c3bus, or cbus at the end of the list
474          * after all the clocks are moved under the proper parents.
475          */
476 #ifdef CONFIG_TEGRA_DUAL_CBUS
477         { "c2bus",      "pll_c2",       250000000,      false },
478         { "c3bus",      "pll_c3",       250000000,      false },
479         { "pll_c",      NULL,           600000000,      false },
480 #else
481         { "cbus",       "pll_c",        200000000,      false },
482 #endif
483         { "pll_c_out1", "pll_c",        100000000,      false },
484         { "c4bus",      "pll_c4",       200000000,      false },
485         { NULL,         NULL,           0,              0},
486 };
487 #endif
488
489 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
490 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
491         /* name         parent          rate            enabled */
492         { "osc",        NULL,           0,              true },
493         { "clk_m",      "osc",          0,              true },
494         { "emc",        NULL,           0,              true },
495         { "cpu",        NULL,           0,              true },
496         { "kfuse",      NULL,           0,              true },
497         { "fuse",       NULL,           0,              true },
498         { "sclk",       NULL,           0,              true },
499 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
500         { "pll_p",      NULL,           0,              true },
501         { "pll_p_out1", "pll_p",        0,              false },
502         { "pll_p_out3", "pll_p",        0,              true },
503         { "pll_m_out1", "pll_m",        275000000,      false },
504         { "pll_p_out2",  "pll_p",       102000000,      false },
505         { "sclk",        "pll_p_out2",  102000000,      true },
506         { "pll_p_out4",  "pll_p",       204000000,      true },
507         { "hclk",       "sclk",         102000000,      true },
508         { "pclk",       "hclk",         51000000,       true },
509         { "mselect",    "pll_p",        102000000,      true },
510         { "host1x",     "pll_p",        102000000,      false },
511         { "cl_dvfs_ref", "pll_p",       51000000,       true },
512         { "cl_dvfs_soc", "pll_p",       51000000,       true },
513 #else
514         { "pll_p",      NULL,           0,              true },
515         { "pll_p_out1", "pll_p",        0,              false },
516         { "pll_p_out3", "pll_p",        0,              true },
517         { "pll_m_out1", "pll_m",        275000000,      true },
518         { "pll_p_out2", "pll_p",        108000000,      false },
519         { "sclk",       "pll_p_out2",   108000000,      true },
520         { "pll_p_out4", "pll_p",        216000000,      true },
521         { "host1x",     "pll_p",        108000000,      false },
522         { "cl_dvfs_ref", "clk_m",       13000000,       false },
523         { "cl_dvfs_soc", "clk_m",       13000000,       false },
524         { "hclk",       "sclk",         108000000,      true },
525         { "pclk",       "hclk",         54000000,       true },
526         { "wake.sclk",  NULL,           250000000,      true },
527         { "mselect",    "pll_p",        108000000,      true },
528 #endif
529 #ifdef CONFIG_TEGRA_SLOW_CSITE
530         { "csite",      "clk_m",        1000000,        true },
531 #else
532         { "csite",      NULL,           0,              true },
533 #endif
534         { "pll_u",      NULL,           480000000,      false },
535         { "sdmmc1",     "pll_p",        48000000,       false},
536         { "sdmmc3",     "pll_p",        48000000,       false},
537         { "sdmmc4",     "pll_p",        48000000,       false},
538         { "mon.avp",    NULL,           80000000,       true },
539         { "sbc1.sclk",  NULL,           20000000,       false},
540         { "sbc2.sclk",  NULL,           20000000,       false},
541         { "sbc3.sclk",  NULL,           20000000,       false},
542         { "msenc",      "pll_p",        108000000,      false },
543         { "tsec",       "pll_p",        108000000,      false },
544         { "mc_capa",    "emc",          0,              true },
545         { "mc_cbpa",    "emc",          0,              true },
546 #ifdef CONFIG_TEGRA_SOCTHERM
547         { "soc_therm",  "pll_p",        51000000,       false },
548         { "tsensor",    "clk_m",        400000,         false },
549 #endif
550         { NULL,         NULL,           0,              0},
551 };
552 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
553         /* Initialize c2bus, c3bus, or cbus at the end of the list
554          * after all the clocks are moved under the proper parents.
555          */
556 #ifdef CONFIG_TEGRA_DUAL_CBUS
557         { "c2bus",      "pll_c2",       200000000,      false },
558         { "c3bus",      "pll_c3",       200000000,      false },
559         { "pll_c",      NULL,           768000000,      false },
560 #else
561         { "cbus",       "pll_c",        200000000,      false },
562 #endif
563         { "pll_c_out1", "pll_c",        100000000,      false },
564         { NULL,         NULL,           0,              0},
565 };
566 #endif
567
568 #ifdef CONFIG_CACHE_L2X0
569 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
570 static void tegra_cache_smc(bool enable, u32 arg)
571 {
572         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
573         bool need_affinity_switch;
574         bool can_switch_affinity;
575         bool l2x0_enabled;
576         cpumask_t local_cpu_mask;
577         cpumask_t saved_cpu_mask;
578         unsigned long flags;
579         long ret;
580
581         /*
582          * ISSUE : Some registers of PL310 controler must be written
583          *              from Secure context (and from CPU0)!
584          *
585          * When called form Normal we obtain an abort or do nothing.
586          * Instructions that must be called in Secure:
587          *      - Write to Control register (L2X0_CTRL==0x100)
588          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
589          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
590          *              mandatory at boot time.
591          *      - Tag and Data RAM Latency Control Registers
592          *              (0x108 & 0x10C) must be written in Secure.
593          */
594         need_affinity_switch = (smp_processor_id() != 0);
595         can_switch_affinity = !irqs_disabled();
596
597         WARN_ON(need_affinity_switch && !can_switch_affinity);
598         if (need_affinity_switch && can_switch_affinity) {
599                 cpu_set(0, local_cpu_mask);
600                 sched_getaffinity(0, &saved_cpu_mask);
601                 ret = sched_setaffinity(0, &local_cpu_mask);
602                 WARN_ON(ret != 0);
603         }
604
605         local_irq_save(flags);
606         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
607         if (enable && !l2x0_enabled)
608                 tegra_generic_smc(0x82000002, 0x00000001, arg);
609         else if (!enable && l2x0_enabled)
610                 tegra_generic_smc(0x82000002, 0x00000002, arg);
611         local_irq_restore(flags);
612
613         if (need_affinity_switch && can_switch_affinity) {
614                 ret = sched_setaffinity(0, &saved_cpu_mask);
615                 WARN_ON(ret != 0);
616         }
617 }
618
619 static void tegra_l2x0_disable(void)
620 {
621         unsigned long flags;
622         static u32 l2x0_way_mask;
623
624         if (!l2x0_way_mask) {
625                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
626                 u32 aux_ctrl;
627                 u32 ways;
628
629                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
630                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
631                 l2x0_way_mask = (1 << ways) - 1;
632         }
633
634         local_irq_save(flags);
635         tegra_cache_smc(false, l2x0_way_mask);
636         local_irq_restore(flags);
637 }
638 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
639
640 void tegra_init_cache(bool init)
641 {
642         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
643         u32 aux_ctrl;
644 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
645         u32 cache_type;
646         u32 tag_latency, data_latency;
647 #endif
648
649 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
650         /* issue the SMC to enable the L2 */
651         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
652         trace_smc_init_cache(NVSEC_SMC_START);
653         tegra_cache_smc(true, aux_ctrl);
654         trace_smc_init_cache(NVSEC_SMC_DONE);
655
656         /* after init, reread aux_ctrl and register handlers */
657         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
658         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
659
660         /* override outer_disable() with our disable */
661         outer_cache.disable = tegra_l2x0_disable;
662 #else
663 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
664         tag_latency = 0x331;
665         data_latency = 0x441;
666 #else
667         if (!tegra_platform_is_silicon()) {
668                 tag_latency = 0x770;
669                 data_latency = 0x770;
670         } else if (is_lp_cluster()) {
671                 tag_latency = tegra_cpu_c1_l2_tag_latency;
672                 data_latency = tegra_cpu_c1_l2_data_latency;
673         } else {
674                 tag_latency = tegra_cpu_c0_l2_tag_latency;
675                 data_latency = tegra_cpu_c0_l2_data_latency;
676         }
677 #endif
678         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
679         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
680
681 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
682         if (!tegra_platform_is_fpga()) {
683 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
684                 /* Enable double line fill */
685                 writel(0x40000007, p + L2X0_PREFETCH_CTRL);
686 #else
687                 writel(0x7, p + L2X0_PREFETCH_CTRL);
688 #endif
689                 writel(0x3, p + L2X0_POWER_CTRL);
690         }
691 #endif
692         cache_type = readl(p + L2X0_CACHE_TYPE);
693         aux_ctrl = (cache_type & 0x700) << (17-8);
694         aux_ctrl |= 0x7C400001;
695         if (init) {
696                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
697         } else {
698                 u32 tmp;
699
700                 tmp = aux_ctrl;
701                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
702                 aux_ctrl &= 0x8200c3fe;
703                 aux_ctrl |= tmp;
704                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
705         }
706         l2x0_enable();
707 #endif
708 }
709 #endif
710
711 static void __init tegra_perf_init(void)
712 {
713         u32 reg;
714
715 #ifdef CONFIG_ARM64
716         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
717         reg >>= 11;
718         reg = (1 << (reg & 0x1f))-1;
719         reg |= 0x80000000;
720         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
721         reg = 1;
722         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
723 #else
724         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
725         reg >>= 11;
726         reg = (1 << (reg & 0x1f))-1;
727         reg |= 0x80000000;
728         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
729         reg = 1;
730         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
731 #endif
732 }
733
734 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
735 static void __init tegra_ramrepair_init(void)
736 {
737 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
738         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
739 #endif
740                 u32 reg;
741                 reg = readl(FLOW_CTRL_RAM_REPAIR);
742                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
743                 writel(reg, FLOW_CTRL_RAM_REPAIR);
744 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
745         }
746 #endif
747 }
748 #endif
749
750 static void __init tegra_init_power(void)
751 {
752 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
753         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
754 #endif
755 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
756         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
757 #endif
758
759 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
760         /* powergate xusb partitions by default */
761         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
762         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
763         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
764 #endif
765
766 }
767
768 static inline unsigned long gizmo_readl(unsigned long offset)
769 {
770         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
771 }
772
773 static inline void gizmo_writel(unsigned long value, unsigned long offset)
774 {
775         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
776 }
777
778 static void __init tegra_init_ahb_gizmo_settings(void)
779 {
780         unsigned long val;
781
782         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
783         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
784
785         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
786                 val |= WR_WAIT_COMMIT_ON_1K;
787 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
788         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
789 #endif
790         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
791
792         val = gizmo_readl(AHB_GIZMO_USB);
793         val |= IMMEDIATE;
794         gizmo_writel(val, AHB_GIZMO_USB);
795
796         val = gizmo_readl(AHB_GIZMO_USB2);
797         val |= IMMEDIATE;
798         gizmo_writel(val, AHB_GIZMO_USB2);
799
800         val = gizmo_readl(AHB_GIZMO_USB3);
801         val |= IMMEDIATE;
802         gizmo_writel(val, AHB_GIZMO_USB3);
803
804         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
805         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
806                                 | AHB_PRIORITY_WEIGHT(7);
807 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
808         val |= PRIORITY_SELECT_SE;
809 #endif
810
811         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
812
813         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
814         val &= ~MST_ID(~0);
815         val |= PREFETCH_ENB | AHBDMA_MST_ID |
816                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
817         ahb_gizmo_writel(val,
818                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
819
820         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
821         val &= ~MST_ID(~0);
822         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
823                 INACTIVITY_TIMEOUT(0x1000);
824         ahb_gizmo_writel(val,
825                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
826
827         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
828         val &= ~MST_ID(~0);
829         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
830                 INACTIVITY_TIMEOUT(0x1000);
831         ahb_gizmo_writel(val,
832                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
833
834         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
835         val &= ~MST_ID(~0);
836         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
837                 INACTIVITY_TIMEOUT(0x1000);
838         ahb_gizmo_writel(val,
839                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
840
841         /*
842          * SDMMC controller is removed from AHB interface in T124 and
843          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
844          * in T11x and T14x SOCs.
845          */
846 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
847         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
848         val &= ~MST_ID(~0);
849         val |= PREFETCH_ENB | SDMMC4_MST_ID;
850         val &= ~SDMMC4_MST_ID;
851         ahb_gizmo_writel(val,
852                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
853 #endif
854
855 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
856         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
857         val &= ~MST_ID(~0);
858         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
859                 INACTIVITY_TIMEOUT(0x1000);
860         ahb_gizmo_writel(val,
861                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
862 #endif
863 }
864
865 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
866 void __init tegra20_init_early(void)
867 {
868 #ifndef CONFIG_SMP
869         /* For SMP system, initializing the reset handler here is too
870            late. For non-SMP systems, the function that calls the reset
871            handler initializer is not called, so do it here for non-SMP. */
872         tegra_cpu_reset_handler_init();
873 #endif
874         tegra_apb_io_init();
875         tegra_perf_init();
876         tegra_init_fuse();
877         tegra_init_cache(true);
878         tegra_pmc_init();
879         tegra_powergate_init();
880         tegra20_hotplug_init();
881         tegra_init_power();
882         tegra_init_ahb_gizmo_settings();
883         tegra_init_debug_uart_rate();
884 }
885 #endif
886 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
887 void __init tegra30_init_early(void)
888 {
889         u32 speedo;
890         u32 tag_latency, data_latency;
891
892         display_tegra_dt_info();
893 #ifndef CONFIG_SMP
894         /* For SMP system, initializing the reset handler here is too
895            late. For non-SMP systems, the function that calls the reset
896            handler initializer is not called, so do it here for non-SMP. */
897         tegra_cpu_reset_handler_init();
898 #endif
899         tegra_apb_io_init();
900         tegra_perf_init();
901         tegra_init_fuse();
902         /*
903          * Store G/LP cluster L2 latencies to IRAM and DRAM
904          */
905         tegra_cpu_c1_l2_tag_latency = 0x221;
906         tegra_cpu_c1_l2_data_latency = 0x221;
907         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
908         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
909         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
910         speedo = tegra_cpu_speedo_id();
911         if (speedo == 4 || speedo == 5 || speedo == 6 ||
912             speedo == 12 || speedo == 13) {
913                 tag_latency = 0x442;
914                 data_latency = 0x552;
915         } else {
916                 tag_latency = 0x441;
917                 data_latency = 0x551;
918         }
919         tegra_cpu_c0_l2_tag_latency = tag_latency;
920         tegra_cpu_c0_l2_data_latency = data_latency;
921         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
922         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
923         tegra_init_cache(true);
924         tegra_pmc_init();
925         tegra_powergate_init();
926         tegra30_hotplug_init();
927         tegra_init_power();
928         tegra_init_ahb_gizmo_settings();
929         tegra_init_debug_uart_rate();
930
931         init_dma_coherent_pool_size(SZ_1M);
932 }
933 #endif
934 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
935 void __init tegra11x_init_early(void)
936 {
937         display_tegra_dt_info();
938 #ifndef CONFIG_SMP
939         /* For SMP system, initializing the reset handler here is too
940            late. For non-SMP systems, the function that calls the reset
941            handler initializer is not called, so do it here for non-SMP. */
942         tegra_cpu_reset_handler_init();
943 #endif
944         tegra_apb_io_init();
945         tegra_perf_init();
946         tegra_init_fuse();
947         tegra_ramrepair_init();
948         tegra11x_init_clocks();
949         tegra11x_init_dvfs();
950         tegra_common_init_clock();
951         tegra_clk_init_from_table(tegra11x_clk_init_table);
952         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
953         tegra11x_clk_init_la();
954         tegra_pmc_init();
955         tegra_powergate_init();
956         tegra30_hotplug_init();
957         tegra_init_power();
958         tegra_init_ahb_gizmo_settings();
959         tegra_init_debug_uart_rate();
960
961         init_dma_coherent_pool_size(SZ_2M);
962 }
963 #endif
964 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
965 void __init tegra12x_init_early(void)
966 {
967         display_tegra_dt_info();
968 #ifndef CONFIG_SMP
969         /* For SMP system, initializing the reset handler here is too
970            late. For non-SMP systems, the function that calls the reset
971            handler initializer is not called, so do it here for non-SMP. */
972         tegra_cpu_reset_handler_init();
973 #endif
974         tegra_apb_io_init();
975         tegra_perf_init();
976         tegra_init_fuse();
977         tegra_ramrepair_init();
978         tegra12x_init_clocks();
979         tegra12x_init_dvfs();
980         tegra_common_init_clock();
981         tegra_clk_init_from_table(tegra12x_clk_init_table);
982         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
983         tegra_pmc_init();
984         tegra_powergate_init();
985         tegra30_hotplug_init();
986         tegra_init_power();
987         tegra_init_ahb_gizmo_settings();
988         tegra_init_debug_uart_rate();
989 }
990 #endif
991 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
992 void __init tegra14x_init_early(void)
993 {
994         display_tegra_dt_info();
995 #ifndef CONFIG_SMP
996         /* For SMP system, initializing the reset handler here is too
997            late. For non-SMP systems, the function that calls the reset
998            handler initializer is not called, so do it here for non-SMP. */
999         tegra_cpu_reset_handler_init();
1000 #endif
1001         tegra_apb_io_init();
1002         tegra_perf_init();
1003         tegra_init_fuse();
1004         tegra_ramrepair_init();
1005         tegra14x_init_clocks();
1006         tegra14x_init_dvfs();
1007         tegra_common_init_clock();
1008         tegra_clk_init_from_table(tegra14x_clk_init_table);
1009         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
1010         tegra_cpu_c1_l2_tag_latency = 0x110;
1011         tegra_cpu_c1_l2_data_latency = 0x331;
1012         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
1013         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
1014         tegra_cpu_c0_l2_tag_latency = 0x111;
1015         tegra_cpu_c0_l2_data_latency = 0x441;
1016         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
1017         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
1018         tegra_init_cache(true);
1019         tegra_pmc_init();
1020         tegra_powergate_init();
1021         tegra30_hotplug_init();
1022         tegra_init_power();
1023         tegra_init_ahb_gizmo_settings();
1024         tegra_init_debug_uart_rate();
1025 }
1026 #endif
1027 static int __init tegra_lp0_vec_arg(char *options)
1028 {
1029         char *p = options;
1030
1031         tegra_lp0_vec_size = memparse(p, &p);
1032         if (*p == '@')
1033                 tegra_lp0_vec_start = memparse(p+1, &p);
1034         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1035                 tegra_lp0_vec_size = 0;
1036                 tegra_lp0_vec_start = 0;
1037         }
1038
1039         return 0;
1040 }
1041 early_param("lp0_vec", tegra_lp0_vec_arg);
1042
1043 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1044 static int __init tegra_wb0_params_arg(char *options)
1045 {
1046         char *p = options;
1047
1048         tegra_wb0_params_address = memparse(p, &p);
1049         if (*p == ',')
1050                 tegra_wb0_params_instances = memparse(p+1, &p);
1051         if (*p == ',')
1052                 tegra_wb0_params_block_size = memparse(p+1, &p);
1053
1054         return 0;
1055 }
1056 early_param("wb0_params", tegra_wb0_params_arg);
1057 #endif
1058
1059 #ifdef CONFIG_TEGRA_NVDUMPER
1060 static int __init tegra_nvdumper_arg(char *options)
1061 {
1062         char *p = options;
1063
1064         nvdumper_reserved = memparse(p, &p);
1065         return 0;
1066 }
1067 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1068 #endif
1069
1070 static int __init tegra_bootloader_fb_arg(char *options)
1071 {
1072         char *p = options;
1073
1074         tegra_bootloader_fb_size = memparse(p, &p);
1075         if (*p == '@')
1076                 tegra_bootloader_fb_start = memparse(p+1, &p);
1077
1078         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1079                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1080
1081         return 0;
1082 }
1083 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1084
1085 static int __init tegra_bootloader_fb2_arg(char *options)
1086 {
1087         char *p = options;
1088
1089         tegra_bootloader_fb2_size = memparse(p, &p);
1090         if (*p == '@')
1091                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1092
1093         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1094                 (u64)tegra_bootloader_fb2_size,
1095                 (u64)tegra_bootloader_fb2_start);
1096
1097         return 0;
1098 }
1099 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1100
1101 static int __init tegra_sku_override(char *id)
1102 {
1103         char *p = id;
1104
1105         sku_override = memparse(p, &p);
1106
1107         return 0;
1108 }
1109 early_param("sku_override", tegra_sku_override);
1110
1111 int tegra_get_sku_override(void)
1112 {
1113         return sku_override;
1114 }
1115
1116 static int __init tegra_vpr_arg(char *options)
1117 {
1118         char *p = options;
1119
1120         tegra_vpr_size = memparse(p, &p);
1121         if (*p == '@')
1122                 tegra_vpr_start = memparse(p+1, &p);
1123         pr_info("Found vpr, start=0x%llx size=%llx",
1124                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1125         return 0;
1126 }
1127 early_param("vpr", tegra_vpr_arg);
1128
1129 static int __init tegra_tsec_arg(char *options)
1130 {
1131         char *p = options;
1132
1133         tegra_tsec_size = memparse(p, &p);
1134         if (*p == '@')
1135                 tegra_tsec_start = memparse(p+1, &p);
1136         pr_info("Found tsec, start=0x%llx size=%llx",
1137                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1138         return 0;
1139 }
1140 early_param("tsec", tegra_tsec_arg);
1141
1142 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1143 static int __init tegra_tzram_arg(char *options)
1144 {
1145         char *p = options;
1146
1147         tegra_tzram_size = memparse(p, &p);
1148         if (*p == '@')
1149                 tegra_tzram_start = memparse(p + 1, &p);
1150         return 0;
1151 }
1152 early_param("tzram", tegra_tzram_arg);
1153 #endif
1154
1155 #ifdef CONFIG_TEGRA_USE_NCT
1156 static int __init tegra_nck_arg(char *options)
1157 {
1158         char *p = options;
1159
1160         tegra_nck_size = memparse(p, &p);
1161         if (*p == '@')
1162                 tegra_nck_start = memparse(p+1, &p);
1163         if (!tegra_nck_size || !tegra_nck_start) {
1164                 tegra_nck_size = 0;
1165                 tegra_nck_start = 0;
1166         }
1167
1168         return 0;
1169 }
1170 early_param("nck", tegra_nck_arg);
1171 #endif  /* CONFIG_TEGRA_USE_NCT */
1172
1173 enum panel_type get_panel_type(void)
1174 {
1175         return board_panel_type;
1176 }
1177 static int __init tegra_board_panel_type(char *options)
1178 {
1179         if (!strcmp(options, "lvds"))
1180                 board_panel_type = panel_type_lvds;
1181         else if (!strcmp(options, "dsi"))
1182                 board_panel_type = panel_type_dsi;
1183         else
1184                 return 0;
1185         return 1;
1186 }
1187 __setup("panel=", tegra_board_panel_type);
1188
1189 int tegra_get_board_panel_id(void)
1190 {
1191         return panel_id;
1192 }
1193 static int __init tegra_board_panel_id(char *options)
1194 {
1195         char *p = options;
1196         panel_id = memparse(p, &p);
1197         return panel_id;
1198 }
1199 __setup("display_panel=", tegra_board_panel_id);
1200
1201 int tegra_get_touch_vendor_id(void)
1202 {
1203         return touch_vendor_id;
1204 }
1205 int tegra_get_touch_panel_id(void)
1206 {
1207         return touch_panel_id;
1208 }
1209 static int __init tegra_touch_id(char *options)
1210 {
1211         char *p = options;
1212         touch_vendor_id = memparse(p, &p);
1213         if (*p == '@')
1214                 touch_panel_id = memparse(p+1, &p);
1215         return 1;
1216 }
1217 __setup("touch_id=", tegra_touch_id);
1218
1219 u8 get_power_config(void)
1220 {
1221         return power_config;
1222 }
1223 static int __init tegra_board_power_config(char *options)
1224 {
1225         char *p = options;
1226         power_config = memparse(p, &p);
1227         return 1;
1228 }
1229 __setup("power-config=", tegra_board_power_config);
1230
1231 u8 get_display_config(void)
1232 {
1233         return display_config;
1234 }
1235 static int __init tegra_board_display_config(char *options)
1236 {
1237         char *p = options;
1238         display_config = memparse(p, &p);
1239         return 1;
1240 }
1241 __setup("display-config=", tegra_board_display_config);
1242
1243 enum power_supply_type get_power_supply_type(void)
1244 {
1245         return pow_supply_type;
1246 }
1247 static int __init tegra_board_power_supply_type(char *options)
1248 {
1249         if (!strcmp(options, "Adapter"))
1250                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1251         if (!strcmp(options, "Mains"))
1252                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1253         else if (!strcmp(options, "Battery"))
1254                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1255         else
1256                 return 0;
1257         return 1;
1258 }
1259 __setup("power_supply=", tegra_board_power_supply_type);
1260
1261 int get_core_edp(void)
1262 {
1263         return pmu_core_edp;
1264 }
1265 static int __init tegra_pmu_core_edp(char *options)
1266 {
1267         char *p = options;
1268         int core_edp = memparse(p, &p);
1269         if (core_edp != 0)
1270                 pmu_core_edp = core_edp;
1271         return 0;
1272 }
1273 early_param("core_edp_mv", tegra_pmu_core_edp);
1274
1275 int get_maximum_cpu_current_supported(void)
1276 {
1277         return max_cpu_current;
1278 }
1279 static int __init tegra_max_cpu_current(char *options)
1280 {
1281         char *p = options;
1282         max_cpu_current = memparse(p, &p);
1283         return 1;
1284 }
1285 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1286
1287 int get_maximum_core_current_supported(void)
1288 {
1289         return max_core_current;
1290 }
1291 static int __init tegra_max_core_current(char *options)
1292 {
1293         char *p = options;
1294         max_core_current = memparse(p, &p);
1295         return 0;
1296 }
1297 early_param("core_edp_ma", tegra_max_core_current);
1298
1299 int get_emc_max_dvfs(void)
1300 {
1301         return emc_max_dvfs;
1302 }
1303 static int __init tegra_emc_max_dvfs(char *options)
1304 {
1305         char *p = options;
1306         emc_max_dvfs = memparse(p, &p);
1307         return 1;
1308 }
1309 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1310
1311 int tegra_get_memory_type(void)
1312 {
1313         return memory_type;
1314 }
1315 static int __init tegra_memory_type(char *options)
1316 {
1317         char *p = options;
1318         memory_type = memparse(p, &p);
1319         return 1;
1320 }
1321 __setup("memtype=", tegra_memory_type);
1322
1323 static int __init tegra_debug_uartport(char *info)
1324 {
1325         char *p = info;
1326         unsigned long long port_id;
1327         if (!strncmp(p, "hsport", 6))
1328                 is_tegra_debug_uart_hsport = true;
1329         else if (!strncmp(p, "lsport", 6))
1330                 is_tegra_debug_uart_hsport = false;
1331
1332         if (p[6] == ',') {
1333                 if (p[7] == '-') {
1334                         debug_uart_port_id = -1;
1335                 } else {
1336                         port_id = memparse(p + 7, &p);
1337                         debug_uart_port_id = (int) port_id;
1338                         if (debug_uart_port_id == 5)
1339                                 uart_over_sd = true;
1340                 }
1341         } else {
1342                 debug_uart_port_id = -1;
1343         }
1344
1345         return 1;
1346 }
1347
1348 bool is_tegra_debug_uartport_hs(void)
1349 {
1350         return is_tegra_debug_uart_hsport;
1351 }
1352
1353 bool is_uart_over_sd_enabled(void)
1354 {
1355         return uart_over_sd;
1356 }
1357
1358 void set_sd_uart_port_id(int port_id)
1359 {
1360         debug_uart_port_id = port_id;
1361 }
1362
1363 int get_tegra_uart_debug_port_id(void)
1364 {
1365         return debug_uart_port_id;
1366 }
1367 __setup("debug_uartport=", tegra_debug_uartport);
1368
1369 static int __init tegra_image_type(char *options)
1370 {
1371         if (!strcmp(options, "RCK"))
1372                 board_image_type = rck_image;
1373
1374         return 0;
1375 }
1376
1377 enum image_type get_tegra_image_type(void)
1378 {
1379         return board_image_type;
1380 }
1381
1382 __setup("image=", tegra_image_type);
1383
1384 static int __init tegra_audio_codec_type(char *info)
1385 {
1386         char *p = info;
1387         if (!strncmp(p, "wm8903", 6))
1388                 audio_codec_name = audio_codec_wm8903;
1389         else
1390                 audio_codec_name = audio_codec_none;
1391
1392         return 1;
1393 }
1394
1395 enum audio_codec_type get_audio_codec_type(void)
1396 {
1397         return audio_codec_name;
1398 }
1399 __setup("audio_codec=", tegra_audio_codec_type);
1400
1401 static int tegra_get_pwr_i2c_clk_rate(char *options)
1402 {
1403         int clk = simple_strtol(options, NULL, 16);
1404         if (clk != 0)
1405                 pwr_i2c_clk = clk;
1406         return 0;
1407 }
1408
1409 int get_pwr_i2c_clk_rate(void)
1410 {
1411         return pwr_i2c_clk;
1412 }
1413 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1414
1415 static bool pmic_wdt_disable;
1416 bool is_pmic_wdt_disabled_at_boot(void)
1417 {
1418         return pmic_wdt_disable;
1419 }
1420
1421 static int parse_arg_pmic_wdt_disable(char *options)
1422 {
1423         /* no kernel command line argument "watchdog" interpreted as
1424          * watchdog enable
1425          */
1426         pmic_wdt_disable = false;
1427         if (!(strcmp(options, "enable")))
1428                 pmic_wdt_disable = false;
1429         else if (!(strcmp(options, "disable")))
1430                 pmic_wdt_disable = true;
1431         /* kernel command line from fastboot does not support
1432          * other values
1433          */
1434
1435         return 0;
1436 }
1437 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1438
1439 void tegra_get_board_info(struct board_info *bi)
1440 {
1441 #ifdef CONFIG_OF
1442         struct device_node *board_info;
1443         u32 prop_val;
1444         int err;
1445
1446         board_info = of_find_node_by_path("/chosen/board_info");
1447         if (!IS_ERR_OR_NULL(board_info)) {
1448                 memset(bi, 0, sizeof(*bi));
1449
1450                 err = of_property_read_u32(board_info, "id", &prop_val);
1451                 if (err)
1452                         pr_err("failed to read /chosen/board_info/id\n");
1453                 else
1454                         bi->board_id = prop_val;
1455
1456                 err = of_property_read_u32(board_info, "sku", &prop_val);
1457                 if (err)
1458                         pr_err("failed to read /chosen/board_info/sku\n");
1459                 else
1460                         bi->sku = prop_val;
1461
1462                 err = of_property_read_u32(board_info, "fab", &prop_val);
1463                 if (err)
1464                         pr_err("failed to read /chosen/board_info/fab\n");
1465                 else
1466                         bi->fab = prop_val;
1467
1468                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1469                 if (err)
1470                         pr_err("failed to read /chosen/board_info/major_revision\n");
1471                 else
1472                         bi->major_revision = prop_val;
1473
1474                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1475                 if (err)
1476                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1477                 else
1478                         bi->minor_revision = prop_val;
1479 #ifndef CONFIG_ARM64
1480                 system_serial_high = (bi->board_id << 16) | bi->sku;
1481                 system_serial_low = (bi->fab << 24) |
1482                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1483 #endif
1484         } else {
1485 #endif
1486 #ifdef CONFIG_ARM64
1487                 /* FIXME:
1488                  * use dummy values for now as system_serial_high/low
1489                  * are gone in arm64.
1490                  */
1491                 bi->board_id = 0xDEAD;
1492                 bi->sku = 0xDEAD;
1493                 bi->fab = 0xDD;
1494                 bi->major_revision = 0xDD;
1495                 bi->minor_revision = 0xDD;
1496 #else
1497                 if (system_serial_high || system_serial_low) {
1498                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1499                         bi->sku = (system_serial_high) & 0xFFFF;
1500                         bi->fab = (system_serial_low >> 24) & 0xFF;
1501                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1502                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1503                 } else {
1504                         memcpy(bi, &main_board_info, sizeof(struct board_info));
1505                 }
1506 #endif
1507 #ifdef CONFIG_OF
1508         }
1509 #endif
1510 }
1511
1512 #ifdef CONFIG_OF
1513 void find_dc_node(struct device_node **dc1_node,
1514                 struct device_node **dc2_node) {
1515         *dc1_node =
1516                 of_find_node_by_path("/host1x/dc@54200000");
1517         *dc2_node =
1518                 of_find_node_by_path("/host1x/dc@54240000");
1519 }
1520 #else
1521 void find_dc_node(struct device_node *dc1_node,
1522                 struct device_node *dc2_node) {
1523         return;
1524 }
1525 #endif
1526
1527 static int __init tegra_main_board_info(char *info)
1528 {
1529         char *p = info;
1530         main_board_info.board_id = memparse(p, &p);
1531         main_board_info.sku = memparse(p+1, &p);
1532         main_board_info.fab = memparse(p+1, &p);
1533         main_board_info.major_revision = memparse(p+1, &p);
1534         main_board_info.minor_revision = memparse(p+1, &p);
1535         return 1;
1536 }
1537
1538 __setup("board_info=", tegra_main_board_info);
1539
1540 static int __init tegra_pmu_board_info(char *info)
1541 {
1542         char *p = info;
1543         pmu_board_info.board_id = memparse(p, &p);
1544         pmu_board_info.sku = memparse(p+1, &p);
1545         pmu_board_info.fab = memparse(p+1, &p);
1546         pmu_board_info.major_revision = memparse(p+1, &p);
1547         pmu_board_info.minor_revision = memparse(p+1, &p);
1548         return 0;
1549 }
1550
1551 void tegra_get_pmu_board_info(struct board_info *bi)
1552 {
1553         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1554 }
1555
1556 early_param("pmuboard", tegra_pmu_board_info);
1557
1558 static int __init tegra_display_board_info(char *info)
1559 {
1560         char *p = info;
1561         display_board_info.board_id = memparse(p, &p);
1562         display_board_info.sku = memparse(p+1, &p);
1563         display_board_info.fab = memparse(p+1, &p);
1564         display_board_info.major_revision = memparse(p+1, &p);
1565         display_board_info.minor_revision = memparse(p+1, &p);
1566         return 1;
1567 }
1568
1569 void tegra_get_display_board_info(struct board_info *bi)
1570 {
1571         memcpy(bi, &display_board_info, sizeof(struct board_info));
1572 }
1573
1574 __setup("displayboard=", tegra_display_board_info);
1575
1576 static int __init tegra_camera_board_info(char *info)
1577 {
1578         char *p = info;
1579         camera_board_info.board_id = memparse(p, &p);
1580         camera_board_info.sku = memparse(p+1, &p);
1581         camera_board_info.fab = memparse(p+1, &p);
1582         camera_board_info.major_revision = memparse(p+1, &p);
1583         camera_board_info.minor_revision = memparse(p+1, &p);
1584         return 1;
1585 }
1586
1587 void tegra_get_camera_board_info(struct board_info *bi)
1588 {
1589         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1590 }
1591
1592 __setup("cameraboard=", tegra_camera_board_info);
1593
1594 static int __init tegra_leftspeaker_board_info(char *info)
1595 {
1596         char *p = info;
1597         leftspeaker_board_info.board_id = memparse(p, &p);
1598         leftspeaker_board_info.sku = memparse(p+1, &p);
1599         leftspeaker_board_info.fab = memparse(p+1, &p);
1600         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1601         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1602         return 1;
1603 }
1604
1605 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1606 {
1607         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1608 }
1609
1610 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1611
1612 static int __init tegra_rightspeaker_board_info(char *info)
1613 {
1614         char *p = info;
1615         rightspeaker_board_info.board_id = memparse(p, &p);
1616         rightspeaker_board_info.sku = memparse(p+1, &p);
1617         rightspeaker_board_info.fab = memparse(p+1, &p);
1618         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1619         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1620         return 1;
1621 }
1622
1623 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1624 {
1625         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1626 }
1627
1628 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1629
1630 static int __init tegra_joystick_board_info(char *info)
1631 {
1632         char *p = info;
1633         joystick_board_info.board_id = memparse(p, &p);
1634         joystick_board_info.sku = memparse(p+1, &p);
1635         joystick_board_info.fab = memparse(p+1, &p);
1636         joystick_board_info.major_revision = memparse(p+1, &p);
1637         joystick_board_info.minor_revision = memparse(p+1, &p);
1638         return 1;
1639 }
1640
1641 void tegra_get_joystick_board_info(struct board_info *bi)
1642 {
1643         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1644 }
1645
1646 __setup("joystickboard=", tegra_joystick_board_info);
1647
1648 static int __init tegra_button_board_info(char *info)
1649 {
1650         char *p = info;
1651         button_board_info.board_id = memparse(p, &p);
1652         button_board_info.sku = memparse(p+1, &p);
1653         button_board_info.fab = memparse(p+1, &p);
1654         button_board_info.major_revision = memparse(p+1, &p);
1655         button_board_info.minor_revision = memparse(p+1, &p);
1656         return 1;
1657 }
1658
1659 void tegra_get_button_board_info(struct board_info *bi)
1660 {
1661         memcpy(bi, &button_board_info, sizeof(struct board_info));
1662 }
1663
1664 __setup("buttonboard=", tegra_button_board_info);
1665
1666 static int __init tegra_io_board_info(char *info)
1667 {
1668         char *p = info;
1669         io_board_info.board_id = memparse(p, &p);
1670         io_board_info.sku = memparse(p+1, &p);
1671         io_board_info.fab = memparse(p+1, &p);
1672         io_board_info.major_revision = memparse(p+1, &p);
1673         io_board_info.minor_revision = memparse(p+1, &p);
1674         return 1;
1675 }
1676
1677 void tegra_get_io_board_info(struct board_info *bi)
1678 {
1679         memcpy(bi, &io_board_info, sizeof(struct board_info));
1680 }
1681
1682 __setup("ioboard=", tegra_io_board_info);
1683
1684 static int __init tegra_modem_id(char *id)
1685 {
1686         char *p = id;
1687
1688         modem_id = memparse(p, &p);
1689         return 1;
1690 }
1691
1692 int tegra_get_modem_id(void)
1693 {
1694         return modem_id;
1695 }
1696
1697 __setup("modem_id=", tegra_modem_id);
1698
1699 static int __init tegra_usb_port_owner_info(char *id)
1700 {
1701         char *p = id;
1702
1703         usb_port_owner_info = memparse(p, &p);
1704         return 1;
1705 }
1706
1707 int tegra_get_usb_port_owner_info(void)
1708 {
1709         return usb_port_owner_info;
1710 }
1711
1712 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1713
1714 static int __init tegra_lane_owner_info(char *id)
1715 {
1716         char *p = id;
1717
1718         lane_owner_info = memparse(p, &p);
1719         return 1;
1720 }
1721
1722 int tegra_get_lane_owner_info(void)
1723 {
1724         return lane_owner_info;
1725 }
1726
1727 __setup("lane_owner_info=", tegra_lane_owner_info);
1728
1729 static int __init tegra_commchip_id(char *id)
1730 {
1731         char *p = id;
1732
1733         if (get_option(&p, &commchip_id) != 1)
1734                 return 0;
1735         return 1;
1736 }
1737
1738 int tegra_get_commchip_id(void)
1739 {
1740         return commchip_id;
1741 }
1742
1743 __setup("commchip_id=", tegra_commchip_id);
1744
1745 /*
1746  * Tegra has a protected aperture that prevents access by most non-CPU
1747  * memory masters to addresses above the aperture value.  Enabling it
1748  * secures the CPU's memory from the GPU, except through the GART.
1749  */
1750 void __init tegra_protected_aperture_init(unsigned long aperture)
1751 {
1752         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1753         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1754         writel(aperture, mc_base + MC_SECURITY_CFG2);
1755 }
1756
1757 /*
1758  * Due to conflicting restrictions on the placement of the framebuffer,
1759  * the bootloader is likely to leave the framebuffer pointed at a location
1760  * in memory that is outside the grhost aperture.  This function will move
1761  * the framebuffer contents from a physical address that is anywhere (lowmem,
1762  * highmem, or outside the memory map) to a physical address that is outside
1763  * the memory map.
1764  */
1765 void __tegra_move_framebuffer(struct platform_device *pdev,
1766         phys_addr_t to, phys_addr_t from,
1767         size_t size)
1768 {
1769         struct page *page;
1770         void __iomem *to_io;
1771         void *from_virt;
1772         unsigned long i;
1773
1774         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1775         BUG_ON(PAGE_ALIGN(from) != from);
1776         BUG_ON(PAGE_ALIGN(size) != size);
1777
1778         to_io = ioremap(to, size);
1779         if (!to_io) {
1780                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1781                 return;
1782         }
1783
1784         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1785                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1786                         page = phys_to_page(from + i);
1787                         from_virt = kmap(page);
1788                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1789                         kunmap(page);
1790                 }
1791         } else if (from) {
1792                 void __iomem *from_io = ioremap(from, size);
1793                 if (!from_io) {
1794                         pr_err("%s: Failed to map source framebuffer\n",
1795                                 __func__);
1796                         goto out;
1797                 }
1798
1799                 for (i = 0; i < size; i += 4)
1800                         writel(readl(from_io + i), to_io + i);
1801
1802                 iounmap(from_io);
1803         }
1804
1805 out:
1806         iounmap(to_io);
1807 }
1808
1809 void __tegra_clear_framebuffer(struct platform_device *pdev,
1810                                unsigned long to, unsigned long size)
1811 {
1812         void __iomem *to_io;
1813         unsigned long i;
1814
1815         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1816         BUG_ON(PAGE_ALIGN(size) != size);
1817
1818         to_io = ioremap(to, size);
1819         if (!to_io) {
1820                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1821                 return;
1822         }
1823
1824         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1825                 for (i = 0 ; i < size; i += PAGE_SIZE)
1826                         memset(to_io + i, 0, PAGE_SIZE);
1827         } else {
1828                 for (i = 0; i < size; i += 4)
1829                         writel(0, to_io + i);
1830         }
1831
1832         iounmap(to_io);
1833 }
1834
1835 #ifdef CONFIG_PSTORE_RAM
1836 static struct ramoops_platform_data ramoops_data;
1837
1838 static struct platform_device ramoops_dev  = {
1839         .name = "ramoops",
1840         .dev = {
1841                 .platform_data = &ramoops_data,
1842         },
1843 };
1844
1845 static void __init tegra_reserve_ramoops_memory(unsigned long reserve_size)
1846 {
1847         ramoops_data.mem_size = reserve_size;
1848         ramoops_data.mem_address = memblock_end_of_4G() - reserve_size;
1849         ramoops_data.console_size = reserve_size;
1850         ramoops_data.dump_oops = 1;
1851         memblock_reserve(ramoops_data.mem_address, ramoops_data.mem_size);
1852 }
1853
1854 static int __init tegra_register_ramoops_device(void)
1855 {
1856         int ret = platform_device_register(&ramoops_dev);
1857         if (ret) {
1858                 pr_info("Unable to register ramoops platform device\n");
1859                 return ret;
1860         }
1861         return ret;
1862 }
1863 core_initcall(tegra_register_ramoops_device);
1864 #endif
1865
1866 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1867         unsigned long fb2_size)
1868 {
1869         struct iommu_linear_map map[4];
1870
1871 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1872         if (carveout_size) {
1873                 /*
1874                  * Place the carveout below the 4 GB physical address limit
1875                  * because IOVAs are only 32 bit wide.
1876                  */
1877                 BUG_ON(memblock_end_of_4G() == 0);
1878                 tegra_carveout_start = memblock_end_of_4G() - carveout_size;
1879                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1880                         pr_err("Failed to remove carveout %08lx@%08llx "
1881                                 "from memory map\n",
1882                                 carveout_size, (u64)tegra_carveout_start);
1883                         tegra_carveout_start = 0;
1884                         tegra_carveout_size = 0;
1885                 } else
1886                         tegra_carveout_size = carveout_size;
1887         }
1888 #endif
1889
1890         if (fb2_size) {
1891                 /*
1892                  * Place fb2 below the 4 GB physical address limit because
1893                  * IOVAs are only 32 bit wide.
1894                  */
1895                 BUG_ON(memblock_end_of_4G() == 0);
1896                 tegra_fb2_start = memblock_end_of_4G() - fb2_size;
1897                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1898                         pr_err("Failed to remove second framebuffer "
1899                                 "%08lx@%08llx from memory map\n",
1900                                 fb2_size, (u64)tegra_fb2_start);
1901                         tegra_fb2_start = 0;
1902                         tegra_fb2_size = 0;
1903                 } else
1904                         tegra_fb2_size = fb2_size;
1905         }
1906
1907         if (fb_size) {
1908                 /*
1909                  * Place fb below the 4 GB physical address limit because
1910                  * IOVAs are only 32 bit wide.
1911                  */
1912                 BUG_ON(memblock_end_of_4G() == 0);
1913                 tegra_fb_start = memblock_end_of_4G() - fb_size;
1914                 if (memblock_remove(tegra_fb_start, fb_size)) {
1915                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1916                                 "from memory map\n",
1917                                 fb_size, (u64)tegra_fb_start);
1918                         tegra_fb_start = 0;
1919                         tegra_fb_size = 0;
1920                 } else
1921                         tegra_fb_size = fb_size;
1922         }
1923
1924         if (tegra_cpu_is_asim()) {
1925                 if (tegra_split_mem_active()) {
1926                         tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1927                         tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1928
1929                         if (tegra_vpr_size == 0) {
1930                                 tegra_carveout_start =
1931                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1932                                 tegra_carveout_size =
1933                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1934                         } else if (
1935                                     (tegra_vpr_start <
1936                                      TEGRA_ASIM_QT_FB_START +
1937                                      TEGRA_ASIM_QT_FB_SIZE) ||
1938                                      (tegra_vpr_start + tegra_vpr_size - 1 >
1939                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1940                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1941                                 /*
1942                                  * On ASIM/ASIM + QT with
1943                                  * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1944                                  * the VPR region needs to be within the front
1945                                  * door memory region. Moreover, the VPR region
1946                                  * can't exist where the framebuffer resides.
1947                                  */
1948                                 BUG();
1949                         } else if (
1950                                         (tegra_vpr_start -
1951                                          (TEGRA_ASIM_QT_FB_START +
1952                                           TEGRA_ASIM_QT_FB_SIZE) <
1953                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1954                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1955                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1956                                          (tegra_vpr_start + tegra_vpr_size) <
1957                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1958                                 /*
1959                                  * The tegra ASIM/QT carveout has a min size:-
1960                                  * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1961                                  * regions in front door mem are smaller than
1962                                  * the min carveout size. Therefore, we can't
1963                                  * fit the carveout in front door mem.
1964                                  */
1965                                 BUG();
1966                         } else if (
1967                                         (tegra_vpr_start -
1968                                          (TEGRA_ASIM_QT_FB_START +
1969                                           TEGRA_ASIM_QT_FB_SIZE)) >=
1970                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1971                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1972                                          (tegra_vpr_start + tegra_vpr_size))) {
1973                                 /*
1974                                  * Place the tegra ASIM/QT carveout between the
1975                                  * framebuffer and VPR.
1976                                  */
1977                                 tegra_carveout_start =
1978                                   TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1979                                 tegra_carveout_size = tegra_vpr_start -
1980                                         (TEGRA_ASIM_QT_FB_START +
1981                                          TEGRA_ASIM_QT_FB_SIZE);
1982                         } else {
1983                                 /*
1984                                  * Place the tegra ASIM/QT carveout after VPR.
1985                                  */
1986                                 tegra_carveout_start = tegra_vpr_start +
1987                                                          tegra_vpr_size;
1988                                 tegra_carveout_size =
1989                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1990                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1991                                         (tegra_vpr_start + tegra_vpr_size);
1992                         }
1993                 } else if (tegra_vpr_size != 0) {
1994                         /*
1995                          * VPR cannot work on ASIM/ASIM + QT if split mem is not
1996                          * enabled.
1997                          */
1998                         BUG();
1999                 }
2000         }
2001
2002         if (tegra_fb_size)
2003                 tegra_grhost_aperture = tegra_fb_start;
2004
2005         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
2006                 tegra_grhost_aperture = tegra_fb2_start;
2007
2008         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
2009                 tegra_grhost_aperture = tegra_carveout_start;
2010
2011         if (tegra_lp0_vec_size &&
2012            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
2013                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
2014                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
2015                                 (u64)tegra_lp0_vec_size,
2016                                 (u64)tegra_lp0_vec_start);
2017                         tegra_lp0_vec_start = 0;
2018                         tegra_lp0_vec_size = 0;
2019                 }
2020                 tegra_lp0_vec_relocate = false;
2021         } else
2022                 tegra_lp0_vec_relocate = true;
2023
2024 #ifdef CONFIG_TEGRA_NVDUMPER
2025         if (nvdumper_reserved) {
2026                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
2027                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
2028                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
2029                         nvdumper_reserved = 0;
2030                 }
2031         }
2032 #endif
2033
2034 #ifdef CONFIG_TEGRA_USE_NCT
2035         if (tegra_nck_size &&
2036            (tegra_nck_start < memblock_end_of_DRAM())) {
2037                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
2038                         pr_err("Failed to reserve nck %08lx@%08lx\n",
2039                                 tegra_nck_size, tegra_nck_start);
2040                         tegra_nck_start = 0;
2041                         tegra_nck_size = 0;
2042                 }
2043         }
2044 #endif
2045
2046         /*
2047          * We copy the bootloader's framebuffer to the framebuffer allocated
2048          * above, and then free this one.
2049          * */
2050         if (tegra_bootloader_fb_size) {
2051                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
2052                 if (memblock_reserve(tegra_bootloader_fb_start,
2053                                 tegra_bootloader_fb_size)) {
2054                         pr_err("Failed to reserve bootloader frame buffer "
2055                                 "%08llx@%08llx\n",
2056                                 (u64)tegra_bootloader_fb_size,
2057                                 (u64)tegra_bootloader_fb_start);
2058                         tegra_bootloader_fb_start = 0;
2059                         tegra_bootloader_fb_size = 0;
2060                 }
2061         }
2062
2063         if (tegra_bootloader_fb2_size) {
2064                 tegra_bootloader_fb2_size =
2065                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2066                 if (memblock_reserve(tegra_bootloader_fb2_start,
2067                                 tegra_bootloader_fb2_size)) {
2068                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2069                                 (u64)tegra_bootloader_fb2_size,
2070                                 (u64)tegra_bootloader_fb2_start);
2071                         tegra_bootloader_fb2_start = 0;
2072                         tegra_bootloader_fb2_size = 0;
2073                 }
2074         }
2075
2076         pr_info("Tegra reserved memory:\n"
2077                 "LP0:                    %08llx - %08llx\n"
2078                 "Bootloader framebuffer: %08llx - %08llx\n"
2079                 "Bootloader framebuffer2: %08llx - %08llx\n"
2080                 "Framebuffer:            %08llx - %08llx\n"
2081                 "2nd Framebuffer:        %08llx - %08llx\n"
2082 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2083                 "Carveout:               %08llx - %08llx\n"
2084                 "Vpr:                    %08llx - %08llx\n"
2085 #endif
2086                 "Tsec:                   %08llx - %08llx\n",
2087                 (u64)tegra_lp0_vec_start,
2088                 (u64)(tegra_lp0_vec_size ?
2089                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2090                 (u64)tegra_bootloader_fb_start,
2091                 (u64)(tegra_bootloader_fb_size ?
2092                         tegra_bootloader_fb_start +
2093                         tegra_bootloader_fb_size - 1 : 0),
2094                 (u64)tegra_bootloader_fb2_start,
2095                 (u64)(tegra_bootloader_fb2_size ?
2096                         tegra_bootloader_fb2_start +
2097                         tegra_bootloader_fb2_size - 1 : 0),
2098                 (u64)tegra_fb_start,
2099                 (u64)(tegra_fb_size ?
2100                         tegra_fb_start + tegra_fb_size - 1 : 0),
2101                 (u64)tegra_fb2_start,
2102                 (u64)(tegra_fb2_size ?
2103                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2104 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2105                 (u64)tegra_carveout_start,
2106                 (u64)(tegra_carveout_size ?
2107                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2108                 (u64)tegra_vpr_start,
2109                 (u64)(tegra_vpr_size ?
2110                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2111 #endif
2112                 (u64)tegra_tsec_start,
2113                 (u64)(tegra_tsec_size ?
2114                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
2115
2116
2117 #ifdef CONFIG_TEGRA_NVDUMPER
2118         if (nvdumper_reserved) {
2119                 pr_info("Nvdumper:               %08lx - %08lx\n",
2120                         nvdumper_reserved,
2121                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2122         }
2123 #endif
2124
2125 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
2126         pr_info("Tzram:               %08lx - %08lx\n",
2127                 tegra_tzram_start,
2128                 tegra_tzram_size ?
2129                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2130 #endif
2131
2132 #ifdef CONFIG_TEGRA_USE_NCT
2133         if (tegra_nck_size) {
2134                 pr_info("Nck:                    %08lx - %08lx\n",
2135                         tegra_nck_start,
2136                         tegra_nck_size ?
2137                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2138         }
2139 #endif
2140
2141 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2142         /* Keep these at the end */
2143         if (carveout_size) {
2144                 if (dma_declare_contiguous(&tegra_generic_cma_dev,
2145                         carveout_size, 0, memblock_end_of_4G()))
2146                         pr_err("dma_declare_contiguous failed for generic\n");
2147                 tegra_carveout_size = carveout_size;
2148         }
2149
2150         if (tegra_vpr_size)
2151                 if (dma_declare_contiguous(&tegra_vpr_cma_dev,
2152                         tegra_vpr_size, 0, memblock_end_of_4G()))
2153                         pr_err("dma_declare_contiguous failed VPR carveout\n");
2154 #endif
2155
2156         tegra_fb_linear_set(map);
2157 #ifdef CONFIG_PSTORE_RAM
2158         tegra_reserve_ramoops_memory(SZ_1M);
2159 #endif
2160 }
2161
2162 void tegra_get_fb_resource(struct resource *fb_res)
2163 {
2164         fb_res->start = (resource_size_t) tegra_fb_start;
2165         fb_res->end = fb_res->start +
2166                         (resource_size_t) tegra_fb_size - 1;
2167 }
2168
2169 void tegra_get_fb2_resource(struct resource *fb2_res)
2170 {
2171         fb2_res->start = (resource_size_t) tegra_fb2_start;
2172         fb2_res->end = fb2_res->start +
2173                         (resource_size_t) tegra_fb2_size - 1;
2174 }
2175
2176 int __init tegra_register_fuse(void)
2177 {
2178         return platform_device_register(&tegra_fuse_device);
2179 }
2180
2181 int __init tegra_release_bootloader_fb(void)
2182 {
2183         /* Since bootloader fb is reserved in common.c, it is freed here. */
2184         if (tegra_bootloader_fb_size) {
2185                 if (memblock_free(tegra_bootloader_fb_start,
2186                                                 tegra_bootloader_fb_size))
2187                         pr_err("Failed to free bootloader fb.\n");
2188                 else
2189                         free_bootmem_late(tegra_bootloader_fb_start,
2190                                                 tegra_bootloader_fb_size);
2191         }
2192         if (tegra_bootloader_fb2_size) {
2193                 if (memblock_free(tegra_bootloader_fb2_start,
2194                                                 tegra_bootloader_fb2_size))
2195                         pr_err("Failed to free bootloader fb2.\n");
2196                 else
2197                         free_bootmem_late(tegra_bootloader_fb2_start,
2198                                                 tegra_bootloader_fb2_size);
2199         }
2200         return 0;
2201 }
2202 late_initcall(tegra_release_bootloader_fb);
2203
2204 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2205         [TEGRA_REVISION_UNKNOWN] = "unknown",
2206         [TEGRA_REVISION_A01]     = "A01",
2207         [TEGRA_REVISION_A02]     = "A02",
2208         [TEGRA_REVISION_A03]     = "A03",
2209         [TEGRA_REVISION_A03p]    = "A03 prime",
2210         [TEGRA_REVISION_A04]     = "A04",
2211         [TEGRA_REVISION_A04p]    = "A04 prime",
2212 };
2213
2214 static const char * __init tegra_get_revision(void)
2215 {
2216         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2217 }
2218
2219 static const char * __init tegra_get_family(void)
2220 {
2221         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2222         u32 cid = readl(chip_id);
2223         cid = (cid >> 8) & 0xFF;
2224
2225         switch (cid) {
2226         case TEGRA_CHIPID_TEGRA2:
2227                 cid = 2;
2228                 break;
2229         case TEGRA_CHIPID_TEGRA3:
2230                 cid = 3;
2231                 break;
2232         case TEGRA_CHIPID_TEGRA11:
2233                 cid = 11;
2234                 break;
2235         case TEGRA_CHIPID_TEGRA12:
2236                 cid = 12;
2237                 break;
2238         case TEGRA_CHIPID_TEGRA14:
2239                 cid = 14;
2240                 break;
2241
2242         case TEGRA_CHIPID_UNKNOWN:
2243         default:
2244                 cid = 0;
2245         }
2246         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2247 }
2248
2249 static const char * __init tegra_get_soc_id(void)
2250 {
2251         int package_id = tegra_package_id();
2252
2253         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2254                 tegra_revision_name[tegra_revision],
2255                 tegra_get_sku_id(), package_id);
2256 }
2257
2258 static void __init tegra_soc_info_populate(struct soc_device_attribute
2259         *soc_dev_attr, const char *machine)
2260 {
2261         soc_dev_attr->soc_id = tegra_get_soc_id();
2262         soc_dev_attr->machine  = machine;
2263         soc_dev_attr->family   = tegra_get_family();
2264         soc_dev_attr->revision = tegra_get_revision();
2265 }
2266
2267 int __init tegra_soc_device_init(const char *machine)
2268 {
2269         struct soc_device *soc_dev;
2270         struct soc_device_attribute *soc_dev_attr;
2271
2272         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2273         if (!soc_dev_attr)
2274                 return -ENOMEM;
2275
2276         tegra_soc_info_populate(soc_dev_attr, machine);
2277
2278         soc_dev = soc_device_register(soc_dev_attr);
2279         if (IS_ERR_OR_NULL(soc_dev)) {
2280                 kfree(soc_dev_attr);
2281                 return -1;
2282         }
2283
2284         return 0;
2285 }
2286
2287 void __init tegra_init_late(void)
2288 {
2289 #ifndef CONFIG_COMMON_CLK
2290         tegra_clk_debugfs_init();
2291 #endif
2292         tegra_powergate_debugfs_init();
2293 }
2294
2295 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2296 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2297
2298 static void asim_power_off(void)
2299 {
2300         pr_err("ASIM Powering off the device\n");
2301         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2302         while (1)
2303                 ;
2304 }
2305
2306 static int __init asim_power_off_init(void)
2307 {
2308         if (tegra_cpu_is_asim())
2309                 pm_power_off = asim_power_off;
2310         return 0;
2311 }
2312
2313 arch_initcall(asim_power_off_init);
2314
2315 #if defined(CONFIG_SMC91X)
2316 static struct resource tegra_asim_smc91x_resources[] = {
2317         [0] = {
2318                 .start          = TEGRA_SIM_ETH_BASE,
2319                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2320                 .flags          = IORESOURCE_MEM,
2321         },
2322         [1] = {
2323                 .start          = IRQ_ETH,
2324                 .end            = IRQ_ETH,
2325                 .flags          = IORESOURCE_IRQ,
2326         },
2327 };
2328
2329 static struct platform_device tegra_asim_smc91x_device = {
2330         .name           = "smc91x",
2331         .id             = 0,
2332         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2333         .resource       = tegra_asim_smc91x_resources,
2334 };
2335
2336 static int __init asim_enet_smc91x_init(void)
2337 {
2338         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2339                 platform_device_register(&tegra_asim_smc91x_device);
2340         return 0;
2341 }
2342
2343 rootfs_initcall(asim_enet_smc91x_init);
2344 #endif
2345 #endif
2346
2347 #if defined(CONFIG_SMSC911X)
2348 static struct resource tegra_smsc911x_resources[] = {
2349         [0] = {
2350                 .start          = 0x4E000000,
2351                 .end            = 0x4E000000 + SZ_64K - 1,
2352                 .flags          = IORESOURCE_MEM,
2353         },
2354         [1] = {
2355                 .start          = IRQ_ETH,
2356                 .end            = IRQ_ETH,
2357                 .flags          = IORESOURCE_IRQ,
2358         },
2359 };
2360
2361 static struct smsc911x_platform_config tegra_smsc911x_config = {
2362         .flags          = SMSC911X_USE_32BIT,
2363         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2364         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2365         .phy_interface  = PHY_INTERFACE_MODE_MII,
2366 };
2367
2368 static struct platform_device tegra_smsc911x_device = {
2369         .name              = "smsc911x",
2370         .id                = 0,
2371         .resource          = tegra_smsc911x_resources,
2372         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2373         .dev.platform_data = &tegra_smsc911x_config,
2374 };
2375
2376 static int __init enet_smsc911x_init(void)
2377 {
2378         if (!tegra_cpu_is_dsim())
2379                 platform_device_register(&tegra_smsc911x_device);
2380         return 0;
2381 }
2382
2383 rootfs_initcall(enet_smsc911x_init);
2384 #endif
2385
2386 int tegra_split_mem_active(void)
2387 {
2388         return tegra_split_mem_set;
2389 }
2390
2391 static int __init set_tegra_split_mem(char *options)
2392 {
2393         tegra_split_mem_set = 1;
2394         return 0;
2395 }
2396 early_param("tegra_split_mem", set_tegra_split_mem);
2397
2398 #define FUSE_SKU_INFO       0x110
2399 #define STRAP_OPT 0x008
2400 #define GMI_AD0 BIT(4)
2401 #define GMI_AD1 BIT(5)
2402 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
2403 #define RAM_CODE_SHIFT 4
2404
2405 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2406 static enum tegra_platform tegra_platform;
2407 static bool cpu_is_asim;
2408 static bool cpu_is_dsim;
2409 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
2410         [TEGRA_PLATFORM_SILICON] = "silicon",
2411         [TEGRA_PLATFORM_QT]      = "quickturn",
2412         [TEGRA_PLATFORM_LINSIM]  = "linsim",
2413         [TEGRA_PLATFORM_FPGA]    = "fpga",
2414 };
2415 #endif
2416
2417 static u32 tegra_chip_sku_id;
2418 static u32 tegra_chip_id;
2419 static u32 tegra_chip_bct_strapping;
2420 enum tegra_revision tegra_revision;
2421
2422 u32 tegra_read_pmc_reg(int offset)
2423 {
2424         return readl(IO_ADDRESS(TEGRA_PMC_BASE) + offset);
2425 }
2426
2427 u32 tegra_read_clk_ctrl_reg(int offset)
2428 {
2429         return readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + offset);
2430 }
2431
2432 u32 tegra_read_apb_misc_reg(int offset)
2433 {
2434         return readl(IO_ADDRESS(TEGRA_APB_MISC_BASE) + offset);
2435 }
2436
2437 u32 tegra_fuse_readl(unsigned long offset)
2438 {
2439         return readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2440 }
2441
2442 void tegra_fuse_writel(u32 val, unsigned long offset)
2443 {
2444         writel(val, IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2445 }
2446
2447 u32 tegra_read_chipid(void)
2448 {
2449         return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE)
2450                         + 0x804);
2451 }
2452
2453 static void tegra_set_sku_id(void)
2454 {
2455         u32 reg;
2456
2457         reg = tegra_fuse_readl(FUSE_SKU_INFO);
2458         tegra_chip_sku_id = reg & 0xFF;
2459 }
2460
2461 static void tegra_set_chip_id(void)
2462 {
2463         u32 id;
2464
2465         id = tegra_read_chipid();
2466         tegra_chip_id = (id >> 8) & 0xff;
2467 }
2468
2469 static void tegra_set_bct_strapping(void)
2470 {
2471         u32 reg;
2472
2473         reg = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + STRAP_OPT));
2474         tegra_chip_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
2475 }
2476
2477 u32 tegra_get_sku_id(void)
2478 {
2479         return tegra_chip_sku_id;
2480 }
2481
2482 u32 tegra_get_chip_id(void)
2483 {
2484         return tegra_chip_id;
2485 }
2486
2487 u32 tegra_get_bct_strapping(void)
2488 {
2489         return tegra_chip_bct_strapping;
2490 }
2491
2492 static void tegra_fuse_cfg_reg_visible(void)
2493 {
2494         /* Make all fuse registers visible */
2495         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2496         reg |= BIT(28);
2497         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2498 }
2499
2500 void tegra_init_fuse(void)
2501 {
2502         u32 sku_id;
2503
2504         tegra_fuse_cfg_reg_visible();
2505         tegra_set_sku_id();
2506         sku_id = tegra_get_sku_id();
2507         tegra_set_bct_strapping();
2508         tegra_set_chip_id();
2509         tegra_revision = tegra_chip_get_revision();
2510         tegra_init_speedo_data();
2511         pr_info("Tegra Revision: %s SKU: 0x%x CPU Process: %d Core Process: %d\n",
2512                 tegra_revision_name[tegra_revision],
2513                 sku_id, tegra_cpu_process_id(),
2514                 tegra_core_process_id());
2515 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2516         if (!tegra_platform_is_silicon()) {
2517                 pr_info("Tegra Platform: %s%s%s\n",
2518                         tegra_cpu_is_asim() ? "ASIM+" : "",
2519                         tegra_cpu_is_dsim() ? "DSIM+" : "",
2520                         tegra_platform_name[tegra_platform]);
2521         }
2522 #endif
2523 }
2524
2525 void __init display_tegra_dt_info(void)
2526 {
2527         unsigned long dt_root;
2528         const char *dts_fname;
2529
2530
2531         dt_root = of_get_flat_dt_root();
2532
2533         dts_fname = of_get_flat_dt_prop(dt_root, "nvidia,dtsfilename", NULL);
2534         if (dts_fname)
2535                 pr_info("DTS File Name: %s\n", dts_fname);
2536         else
2537                 pr_info("DTS File Name: <unknown>\n");
2538 }
2539
2540 static int __init tegra_get_last_reset_reason(void)
2541 {
2542 #define PMC_RST_STATUS 0x1b4
2543 #define RESET_STR(REASON) "last reset is due to "#REASON"\n"
2544         char *reset_reason[] = {
2545                 RESET_STR(power on reset),
2546                 RESET_STR(watchdog timeout),
2547                 RESET_STR(sensor),
2548                 RESET_STR(software reset),
2549                 RESET_STR(deep sleep reset),
2550         };
2551
2552         u32 val = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_RST_STATUS) & 0x7;
2553         if (val >= ARRAY_SIZE(reset_reason))
2554                 pr_info("last reset value is invalid 0x%x\n", val);
2555         else
2556                 pr_info("%s\n", reset_reason[val]);
2557         return 0;
2558 }
2559 late_initcall(tegra_get_last_reset_reason);