826752988d6788a15b73e6267a309665f4c5e6b5
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/irqchip.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32
33 #include <asm/hardware/cache-l2x0.h>
34 #include <asm/system_info.h>
35
36 #include <mach/powergate.h>
37 #include <mach/tegra_smmu.h>
38
39 #include "board.h"
40 #include "common.h"
41 #include "dvfs.h"
42 #include "fuse.h"
43 #include "iomap.h"
44 #include "pm.h"
45 #include "pmc.h"
46 #include "apbio.h"
47 #include "sleep.h"
48 #include "reset.h"
49 #include "devices.h"
50
51 #define MC_SECURITY_CFG2        0x7c
52
53 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
54 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
55 #define   PRIORITY_SELECT_USB   BIT(6)
56 #define   PRIORITY_SELECT_USB2  BIT(18)
57 #define   PRIORITY_SELECT_USB3  BIT(17)
58
59 #define AHB_GIZMO_AHB_MEM               0xc
60 #define   ENB_FAST_REARBITRATE  BIT(2)
61 #define   DONT_SPLIT_AHB_WR     BIT(7)
62
63 #define   RECOVERY_MODE BIT(31)
64 #define   BOOTLOADER_MODE       BIT(30)
65 #define   FORCED_RECOVERY_MODE  BIT(1)
66
67 #define AHB_GIZMO_USB           0x1c
68 #define AHB_GIZMO_USB2          0x78
69 #define AHB_GIZMO_USB3          0x7c
70 #define   IMMEDIATE     BIT(18)
71
72 #define AHB_MEM_PREFETCH_CFG3   0xe0
73 #define AHB_MEM_PREFETCH_CFG4   0xe4
74 #define AHB_MEM_PREFETCH_CFG1   0xec
75 #define AHB_MEM_PREFETCH_CFG2   0xf0
76 #define   PREFETCH_ENB  BIT(31)
77 #define   MST_ID(x)     (((x) & 0x1f) << 26)
78 #define   AHBDMA_MST_ID MST_ID(5)
79 #define   USB_MST_ID    MST_ID(6)
80 #define   USB2_MST_ID   MST_ID(18)
81 #define   USB3_MST_ID   MST_ID(17)
82 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
83 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
84
85 unsigned long tegra_bootloader_fb_start;
86 unsigned long tegra_bootloader_fb_size;
87 unsigned long tegra_fb_start;
88 unsigned long tegra_fb_size;
89 unsigned long tegra_fb2_start;
90 unsigned long tegra_fb2_size;
91 unsigned long tegra_carveout_start;
92 unsigned long tegra_carveout_size;
93 unsigned long tegra_vpr_start;
94 unsigned long tegra_vpr_size;
95 unsigned long tegra_lp0_vec_start;
96 unsigned long tegra_lp0_vec_size;
97 bool tegra_lp0_vec_relocate;
98 unsigned long tegra_grhost_aperture = ~0ul;
99 static   bool is_tegra_debug_uart_hsport;
100 static struct board_info pmu_board_info;
101 static struct board_info display_board_info;
102 static struct board_info camera_board_info;
103
104 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
105 static int board_panel_type;
106 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
107
108 /*
109  * Storage for debug-macro.S's state.
110  *
111  * This must be in .data not .bss so that it gets initialized each time the
112  * kernel is loaded. The data is declared here rather than debug-macro.S so
113  * that multiple inclusions of debug-macro.S point at the same data.
114  */
115 u32 tegra_uart_config[4] = {
116         /* Debug UART initialization required */
117         1,
118         /* Debug UART physical address */
119         0,
120         /* Debug UART virtual address */
121         0,
122         /* Scratch space for debug macro */
123         0,
124 };
125
126 #ifdef CONFIG_OF
127 void __init tegra_dt_init_irq(void)
128 {
129         tegra_clocks_init();
130         tegra_pmc_init();
131         tegra_init_irq();
132         irqchip_init();
133 }
134 #endif
135
136 #define NEVER_RESET 0
137
138 void tegra_assert_system_reset(char mode, const char *cmd)
139 {
140 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
141         printk("tegra_assert_system_reset() ignored.....");
142         do { } while (1);
143 #else
144         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
145         u32 reg;
146
147         reg = readl_relaxed(reset + PMC_SCRATCH0);
148         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
149         if (cmd) {
150                 if (!strcmp(cmd, "recovery"))
151                         reg |= RECOVERY_MODE;
152                 else if (!strcmp(cmd, "bootloader"))
153                         reg |= BOOTLOADER_MODE;
154                 else if (!strcmp(cmd, "forced-recovery"))
155                         reg |= FORCED_RECOVERY_MODE;
156                 else
157                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
158         }
159         else {
160                 /* Clearing SCRATCH0 31:30:1 on default reboot */
161                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
162         }
163         writel_relaxed(reg, reset + PMC_SCRATCH0);
164         reg = readl_relaxed(reset);
165         reg |= 0x10;
166         writel_relaxed(reg, reset);
167 #endif
168 }
169 static int modem_id;
170 int tegra_sku_override;
171 static int debug_uart_port_id;
172 static enum audio_codec_type audio_codec_name;
173 static enum image_type board_image_type = system_image;
174 static int max_cpu_current;
175
176 #ifdef CONFIG_CACHE_L2X0
177 #ifdef CONFIG_TRUSTED_FOUNDATIONS
178 static void tegra_cache_smc(bool enable, u32 arg)
179 {
180         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
181         bool need_affinity_switch;
182         bool can_switch_affinity;
183         bool l2x0_enabled;
184         cpumask_t local_cpu_mask;
185         cpumask_t saved_cpu_mask;
186         unsigned long flags;
187         long ret;
188
189         /*
190          * ISSUE : Some registers of PL310 controler must be written
191          *              from Secure context (and from CPU0)!
192          *
193          * When called form Normal we obtain an abort or do nothing.
194          * Instructions that must be called in Secure:
195          *      - Write to Control register (L2X0_CTRL==0x100)
196          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
197          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
198          *              mandatory at boot time.
199          *      - Tag and Data RAM Latency Control Registers
200          *              (0x108 & 0x10C) must be written in Secure.
201          */
202         need_affinity_switch = (smp_processor_id() != 0);
203         can_switch_affinity = !irqs_disabled();
204
205         WARN_ON(need_affinity_switch && !can_switch_affinity);
206         if (need_affinity_switch && can_switch_affinity) {
207                 cpu_set(0, local_cpu_mask);
208                 sched_getaffinity(0, &saved_cpu_mask);
209                 ret = sched_setaffinity(0, &local_cpu_mask);
210                 WARN_ON(ret != 0);
211         }
212
213         local_irq_save(flags);
214         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
215         if (enable && !l2x0_enabled)
216                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
217         else if (!enable && l2x0_enabled)
218                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
219         local_irq_restore(flags);
220
221         if (need_affinity_switch && can_switch_affinity) {
222                 ret = sched_setaffinity(0, &saved_cpu_mask);
223                 WARN_ON(ret != 0);
224         }
225 }
226
227 static void tegra_l2x0_disable(void)
228 {
229         unsigned long flags;
230         static u32 l2x0_way_mask;
231
232         if (!l2x0_way_mask) {
233                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
234                 u32 aux_ctrl;
235                 u32 ways;
236
237                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
238                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
239                 l2x0_way_mask = (1 << ways) - 1;
240         }
241
242         local_irq_save(flags);
243         tegra_cache_smc(false, l2x0_way_mask);
244         local_irq_restore(flags);
245 }
246 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
247
248 void tegra_init_cache(bool init)
249 {
250         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
251         u32 aux_ctrl, cache_type;
252         u32 tag_latency, data_latency;
253         u32 speedo;
254         u32 tmp;
255
256 #ifdef CONFIG_TRUSTED_FOUNDATIONS
257         /* issue the SMC to enable the L2 */
258         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
259         tegra_cache_smc(true, aux_ctrl);
260
261         /* after init, reread aux_ctrl and register handlers */
262         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
263         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
264
265         /* override outer_disable() with our disable */
266         outer_cache.disable = tegra_l2x0_disable;
267 #else
268 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
269         tag_latency = 0x331;
270         data_latency = 0x441;
271 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
272 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
273         if (is_lp_cluster()) {
274                 tag_latency = 0x221;
275                 data_latency = 0x221;
276         } else {
277                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
278                 speedo = tegra_cpu_speedo_id;
279                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
280                     speedo == 12 || speedo == 13) {
281                         tag_latency = 0x442;
282                         data_latency = 0x552;
283                 } else {
284                         tag_latency = 0x441;
285                         data_latency = 0x551;
286                 }
287         }
288 #else
289         tag_latency = 0x770;
290         data_latency = 0x770;
291 #endif
292 #endif
293         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
294         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
295
296 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
297 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
298         writel(7, p + L2X0_PREFETCH_CTRL);
299         writel(2, p + L2X0_POWER_CTRL);
300 #endif  
301 #endif
302
303         writel(0x3, p + L2X0_POWER_CTRL);
304         cache_type = readl(p + L2X0_CACHE_TYPE);
305         aux_ctrl = (cache_type & 0x700) << (17-8);
306         aux_ctrl |= 0x7C400001;
307         if (init) {
308                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
309         } else {
310                 tmp = aux_ctrl;
311                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
312                 aux_ctrl &= 0x8200c3fe;
313                 aux_ctrl |= tmp;
314                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
315         }
316         l2x0_enable();
317 #endif
318 }
319 #endif
320
321 static void __init tegra_init_power(void)
322 {
323 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
324         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
325 #endif
326 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
327         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
328 #endif
329 }
330
331 static inline unsigned long gizmo_readl(unsigned long offset)
332 {
333         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
334 }
335
336 static inline void gizmo_writel(unsigned long value, unsigned long offset)
337 {
338         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
339 }
340
341 static void __init tegra_init_ahb_gizmo_settings(void)
342 {
343         unsigned long val;
344
345         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
346         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
347         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
348
349         val = gizmo_readl(AHB_GIZMO_USB);
350         val |= IMMEDIATE;
351         gizmo_writel(val, AHB_GIZMO_USB);
352
353         val = gizmo_readl(AHB_GIZMO_USB2);
354         val |= IMMEDIATE;
355         gizmo_writel(val, AHB_GIZMO_USB2);
356
357         val = gizmo_readl(AHB_GIZMO_USB3);
358         val |= IMMEDIATE;
359         gizmo_writel(val, AHB_GIZMO_USB3);
360
361         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
362         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
363                                 | AHB_PRIORITY_WEIGHT(7);
364         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
365
366         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
367         val &= ~MST_ID(~0);
368         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
369         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
370
371         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
372         val &= ~MST_ID(~0);
373         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
374         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
375
376         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
377         val &= ~MST_ID(~0);
378         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
379         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
380
381         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
382         val &= ~MST_ID(~0);
383         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
384         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
385 }
386
387 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
388 void __init tegra20_init_early(void)
389 {
390 #ifndef CONFIG_SMP
391         /* For SMP system, initializing the reset handler here is too
392            late. For non-SMP systems, the function that calls the reset
393            handler initializer is not called, so do it here for non-SMP. */
394         tegra_cpu_reset_handler_init();
395 #endif
396         tegra_apb_io_init();
397         tegra_init_fuse();
398         tegra_init_cache(true);
399         tegra_powergate_init();
400         tegra20_hotplug_init();
401         tegra_init_power();
402         tegra_init_ahb_gizmo_settings();
403         tegra_init_debug_uart_rate();
404 }
405 #endif
406 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
407 void __init tegra30_init_early(void)
408 {
409 #ifndef CONFIG_SMP
410         /* For SMP system, initializing the reset handler here is too
411            late. For non-SMP systems, the function that calls the reset
412            handler initializer is not called, so do it here for non-SMP. */
413         tegra_cpu_reset_handler_init();
414 #endif
415         tegra_apb_io_init();
416         tegra_init_fuse();
417         tegra_init_cache(true);
418         tegra_pmc_init();
419         tegra_powergate_init();
420         tegra30_hotplug_init();
421         tegra_init_power();
422         tegra_init_ahb_gizmo_settings();
423         tegra_init_debug_uart_rate();
424 }
425 #endif
426
427 static int __init tegra_lp0_vec_arg(char *options)
428 {
429         char *p = options;
430
431         tegra_lp0_vec_size = memparse(p, &p);
432         if (*p == '@')
433                 tegra_lp0_vec_start = memparse(p+1, &p);
434         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
435                 tegra_lp0_vec_size = 0;
436                 tegra_lp0_vec_start = 0;
437         }
438
439         return 0;
440 }
441 early_param("lp0_vec", tegra_lp0_vec_arg);
442
443 static int __init tegra_bootloader_fb_arg(char *options)
444 {
445         char *p = options;
446
447         tegra_bootloader_fb_size = memparse(p, &p);
448         if (*p == '@')
449                 tegra_bootloader_fb_start = memparse(p+1, &p);
450
451         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
452                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
453
454         return 0;
455 }
456 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
457
458 static int __init tegra_init_sku_override(char *id)
459 {
460         char *p = id;
461
462         tegra_sku_override = memparse(p, &p);
463
464         return 0;
465 }
466 early_param("sku_override", tegra_init_sku_override);
467
468 static int __init tegra_vpr_arg(char *options)
469 {
470         char *p = options;
471
472         tegra_vpr_size = memparse(p, &p);
473         if (*p == '@')
474                 tegra_vpr_start = memparse(p+1, &p);
475         pr_info("Found vpr, start=0x%lx size=%lx",
476                 tegra_vpr_start, tegra_vpr_size);
477         return 0;
478 }
479 early_param("vpr", tegra_vpr_arg);
480
481 enum panel_type get_panel_type(void)
482 {
483         return board_panel_type;
484 }
485 static int __init tegra_board_panel_type(char *options)
486 {
487         if (!strcmp(options, "lvds"))
488                 board_panel_type = panel_type_lvds;
489         else if (!strcmp(options, "dsi"))
490                 board_panel_type = panel_type_dsi;
491         else
492                 return 0;
493         return 1;
494 }
495 __setup("panel=", tegra_board_panel_type);
496
497 enum power_supply_type get_power_supply_type(void)
498 {
499         return pow_supply_type;
500 }
501 static int __init tegra_board_power_supply_type(char *options)
502 {
503         if (!strcmp(options, "Adapter"))
504                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
505         if (!strcmp(options, "Mains"))
506                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
507         else if (!strcmp(options, "Battery"))
508                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
509         else
510                 return 0;
511         return 1;
512 }
513 __setup("power_supply=", tegra_board_power_supply_type);
514
515 int get_core_edp(void)
516 {
517         return pmu_core_edp;
518 }
519 static int __init tegra_pmu_core_edp(char *options)
520 {
521         char *p = options;
522         int core_edp = memparse(p, &p);
523         if (core_edp != 0)
524                 pmu_core_edp = core_edp;
525         return 0;
526 }
527 early_param("core_edp_mv", tegra_pmu_core_edp);
528
529 int get_maximum_cpu_current_supported(void)
530 {
531         return max_cpu_current;
532 }
533 static int __init tegra_max_cpu_current(char *options)
534 {
535         char *p = options;
536         max_cpu_current = memparse(p, &p);
537         return 1;
538 }
539 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
540
541 static int __init tegra_debug_uartport(char *info)
542 {
543         char *p = info;
544         unsigned long long port_id;
545         if (!strncmp(p, "hsport", 6))
546                 is_tegra_debug_uart_hsport = true;
547         else if (!strncmp(p, "lsport", 6))
548                 is_tegra_debug_uart_hsport = false;
549
550         if (p[6] == ',') {
551                 if (p[7] == '-') {
552                         debug_uart_port_id = -1;
553                 } else {
554                         port_id = memparse(p + 7, &p);
555                         debug_uart_port_id = (int) port_id;
556                 }
557         } else {
558                 debug_uart_port_id = -1;
559         }
560
561         return 1;
562 }
563
564 bool is_tegra_debug_uartport_hs(void)
565 {
566         return is_tegra_debug_uart_hsport;
567 }
568
569 int get_tegra_uart_debug_port_id(void)
570 {
571         return debug_uart_port_id;
572 }
573 __setup("debug_uartport=", tegra_debug_uartport);
574
575 static int __init tegra_image_type(char *options)
576 {
577         if (!strcmp(options, "RCK"))
578                 board_image_type = rck_image;
579
580         return 0;
581 }
582
583 enum image_type get_tegra_image_type(void)
584 {
585         return board_image_type;
586 }
587
588 __setup("image=", tegra_image_type);
589
590 static int __init tegra_audio_codec_type(char *info)
591 {
592         char *p = info;
593         if (!strncmp(p, "wm8903", 6))
594                 audio_codec_name = audio_codec_wm8903;
595         else
596                 audio_codec_name = audio_codec_none;
597
598         return 1;
599 }
600
601 enum audio_codec_type get_audio_codec_type(void)
602 {
603         return audio_codec_name;
604 }
605 __setup("audio_codec=", tegra_audio_codec_type);
606
607
608 void tegra_get_board_info(struct board_info *bi)
609 {
610         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
611         bi->sku = (system_serial_high) & 0xFFFF;
612         bi->fab = (system_serial_low >> 24) & 0xFF;
613         bi->major_revision = (system_serial_low >> 16) & 0xFF;
614         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
615 }
616
617 static int __init tegra_pmu_board_info(char *info)
618 {
619         char *p = info;
620         pmu_board_info.board_id = memparse(p, &p);
621         pmu_board_info.sku = memparse(p+1, &p);
622         pmu_board_info.fab = memparse(p+1, &p);
623         pmu_board_info.major_revision = memparse(p+1, &p);
624         pmu_board_info.minor_revision = memparse(p+1, &p);
625         return 1;
626 }
627
628 void tegra_get_pmu_board_info(struct board_info *bi)
629 {
630         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
631 }
632
633 __setup("pmuboard=", tegra_pmu_board_info);
634
635 static int __init tegra_display_board_info(char *info)
636 {
637         char *p = info;
638         display_board_info.board_id = memparse(p, &p);
639         display_board_info.sku = memparse(p+1, &p);
640         display_board_info.fab = memparse(p+1, &p);
641         display_board_info.major_revision = memparse(p+1, &p);
642         display_board_info.minor_revision = memparse(p+1, &p);
643         return 1;
644 }
645
646 void tegra_get_display_board_info(struct board_info *bi)
647 {
648         memcpy(bi, &display_board_info, sizeof(struct board_info));
649 }
650
651 __setup("displayboard=", tegra_display_board_info);
652
653 static int __init tegra_camera_board_info(char *info)
654 {
655         char *p = info;
656         camera_board_info.board_id = memparse(p, &p);
657         camera_board_info.sku = memparse(p+1, &p);
658         camera_board_info.fab = memparse(p+1, &p);
659         camera_board_info.major_revision = memparse(p+1, &p);
660         camera_board_info.minor_revision = memparse(p+1, &p);
661         return 1;
662 }
663
664 void tegra_get_camera_board_info(struct board_info *bi)
665 {
666         memcpy(bi, &camera_board_info, sizeof(struct board_info));
667 }
668
669 __setup("cameraboard=", tegra_camera_board_info);
670
671 static int __init tegra_modem_id(char *id)
672 {
673         char *p = id;
674
675         modem_id = memparse(p, &p);
676         return 1;
677 }
678
679 int tegra_get_modem_id(void)
680 {
681         return modem_id;
682 }
683
684 __setup("modem_id=", tegra_modem_id);
685
686 /*
687  * Tegra has a protected aperture that prevents access by most non-CPU
688  * memory masters to addresses above the aperture value.  Enabling it
689  * secures the CPU's memory from the GPU, except through the GART.
690  */
691 void __init tegra_protected_aperture_init(unsigned long aperture)
692 {
693 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
694         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
695         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
696         writel(aperture, mc_base + MC_SECURITY_CFG2);
697 #else
698         pr_err("Tegra protected aperture disabled because nvmap is using "
699                 "system memory\n");
700 #endif
701 }
702
703 /*
704  * Due to conflicting restrictions on the placement of the framebuffer,
705  * the bootloader is likely to leave the framebuffer pointed at a location
706  * in memory that is outside the grhost aperture.  This function will move
707  * the framebuffer contents from a physical address that is anywher (lowmem,
708  * highmem, or outside the memory map) to a physical address that is outside
709  * the memory map.
710  */
711 void tegra_move_framebuffer(unsigned long to, unsigned long from,
712         unsigned long size)
713 {
714         struct page *page;
715         void __iomem *to_io;
716         void *from_virt;
717         unsigned long i;
718
719         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
720         BUG_ON(PAGE_ALIGN(from) != from);
721         BUG_ON(PAGE_ALIGN(size) != size);
722
723         to_io = ioremap(to, size);
724         if (!to_io) {
725                 pr_err("%s: Failed to map target framebuffer\n", __func__);
726                 return;
727         }
728
729         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
730                 for (i = 0 ; i < size; i += PAGE_SIZE) {
731                         page = phys_to_page(from + i);
732                         from_virt = kmap(page);
733                         memcpy(to_io + i, from_virt, PAGE_SIZE);
734                         kunmap(page);
735                 }
736         } else {
737                 void __iomem *from_io = ioremap(from, size);
738                 if (!from_io) {
739                         pr_err("%s: Failed to map source framebuffer\n",
740                                 __func__);
741                         goto out;
742                 }
743
744                 for (i = 0; i < size; i += 4)
745                         writel(readl(from_io + i), to_io + i);
746
747                 iounmap(from_io);
748         }
749 out:
750         iounmap(to_io);
751 }
752
753 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
754         unsigned long fb2_size)
755 {
756         if (carveout_size) {
757                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
758                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
759                         pr_err("Failed to remove carveout %08lx@%08lx "
760                                 "from memory map\n",
761                                 carveout_size, tegra_carveout_start);
762                         tegra_carveout_start = 0;
763                         tegra_carveout_size = 0;
764                 } else
765                         tegra_carveout_size = carveout_size;
766         }
767
768         if (fb2_size) {
769                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
770                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
771                         pr_err("Failed to remove second framebuffer "
772                                 "%08lx@%08lx from memory map\n",
773                                 fb2_size, tegra_fb2_start);
774                         tegra_fb2_start = 0;
775                         tegra_fb2_size = 0;
776                 } else
777                         tegra_fb2_size = fb2_size;
778         }
779
780         if (fb_size) {
781                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
782                 if (memblock_remove(tegra_fb_start, fb_size)) {
783                         pr_err("Failed to remove framebuffer %08lx@%08lx "
784                                 "from memory map\n",
785                                 fb_size, tegra_fb_start);
786                         tegra_fb_start = 0;
787                         tegra_fb_size = 0;
788                 } else
789                         tegra_fb_size = fb_size;
790         }
791
792         if (tegra_fb_size)
793                 tegra_grhost_aperture = tegra_fb_start;
794
795         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
796                 tegra_grhost_aperture = tegra_fb2_start;
797
798         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
799                 tegra_grhost_aperture = tegra_carveout_start;
800
801         if (tegra_lp0_vec_size &&
802            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
803                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
804                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
805                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
806                         tegra_lp0_vec_start = 0;
807                         tegra_lp0_vec_size = 0;
808                 }
809                 tegra_lp0_vec_relocate = false;
810         } else
811                 tegra_lp0_vec_relocate = true;
812
813         /*
814          * We copy the bootloader's framebuffer to the framebuffer allocated
815          * above, and then free this one.
816          * */
817         if (tegra_bootloader_fb_size) {
818                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
819                 if (memblock_reserve(tegra_bootloader_fb_start,
820                                 tegra_bootloader_fb_size)) {
821                         pr_err("Failed to reserve bootloader frame buffer "
822                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
823                                 tegra_bootloader_fb_start);
824                         tegra_bootloader_fb_start = 0;
825                         tegra_bootloader_fb_size = 0;
826                 }
827         }
828
829         pr_info("Tegra reserved memory:\n"
830                 "LP0:                    %08lx - %08lx\n"
831                 "Bootloader framebuffer: %08lx - %08lx\n"
832                 "Framebuffer:            %08lx - %08lx\n"
833                 "2nd Framebuffer:        %08lx - %08lx\n"
834                 "Carveout:               %08lx - %08lx\n"
835                 "Vpr:                    %08lx - %08lx\n",
836                 tegra_lp0_vec_start,
837                 tegra_lp0_vec_size ?
838                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
839                 tegra_bootloader_fb_start,
840                 tegra_bootloader_fb_size ?
841                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
842                 tegra_fb_start,
843                 tegra_fb_size ?
844                         tegra_fb_start + tegra_fb_size - 1 : 0,
845                 tegra_fb2_start,
846                 tegra_fb2_size ?
847                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
848                 tegra_carveout_start,
849                 tegra_carveout_size ?
850                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
851                 tegra_vpr_start,
852                 tegra_vpr_size ?
853                         tegra_vpr_start + tegra_vpr_size - 1 : 0);
854 }
855
856 static struct resource ram_console_resources[] = {
857         {
858                 .flags = IORESOURCE_MEM,
859         },
860 };
861
862 static struct platform_device ram_console_device = {
863         .name           = "ram_console",
864         .id             = -1,
865         .num_resources  = ARRAY_SIZE(ram_console_resources),
866         .resource       = ram_console_resources,
867 };
868
869 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
870 {
871         struct resource *res;
872         long ret;
873
874         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
875         if (!res)
876                 goto fail;
877         res->start = memblock_end_of_DRAM() - ram_console_size;
878         res->end = res->start + ram_console_size - 1;
879         ret = memblock_remove(res->start, ram_console_size);
880         if (ret)
881                 goto fail;
882
883         return;
884
885 fail:
886         ram_console_device.resource = NULL;
887         ram_console_device.num_resources = 0;
888         pr_err("Failed to reserve memory block for ram console\n");
889 }
890
891 void __init tegra_ram_console_debug_init(void)
892 {
893         int err;
894
895         err = platform_device_register(&ram_console_device);
896         if (err) {
897                 pr_err("%s: ram console registration failed (%d)!\n", __func__, err);
898         }
899 }
900
901 void __init tegra_release_bootloader_fb(void)
902 {
903         /* Since bootloader fb is reserved in common.c, it is freed here. */
904         if (tegra_bootloader_fb_size)
905                 if (memblock_free(tegra_bootloader_fb_start,
906                                                 tegra_bootloader_fb_size))
907                         pr_err("Failed to free bootloader fb.\n");
908 }
909
910 static struct platform_device *pinmux_devices[] = {
911         &tegra_gpio_device,
912         &tegra_pinmux_device,
913 };
914
915 void tegra_enable_pinmux(void)
916 {
917         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
918 }
919
920 void __init tegra_init_late(void)
921 {
922 #ifndef CONFIG_COMMON_CLK
923         tegra_clk_debugfs_init();
924 #endif
925         tegra_powergate_debugfs_init();
926 }