video: tegra: support display board PM313
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2011 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/irqchip.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31
32 #include <asm/hardware/cache-l2x0.h>
33 #include <asm/system_info.h>
34
35 #include <mach/powergate.h>
36
37 #include "board.h"
38 #include "common.h"
39 #include "dvfs.h"
40 #include "fuse.h"
41 #include "iomap.h"
42 #include "pm.h"
43 #include "pmc.h"
44 #include "apbio.h"
45 #include "sleep.h"
46 #include "reset.h"
47
48 #define MC_SECURITY_CFG2        0x7c
49
50 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
51 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
52 #define   PRIORITY_SELECT_USB   BIT(6)
53 #define   PRIORITY_SELECT_USB2  BIT(18)
54 #define   PRIORITY_SELECT_USB3  BIT(17)
55
56 #define AHB_GIZMO_AHB_MEM               0xc
57 #define   ENB_FAST_REARBITRATE  BIT(2)
58 #define   DONT_SPLIT_AHB_WR     BIT(7)
59
60 #define AHB_GIZMO_USB           0x1c
61 #define AHB_GIZMO_USB2          0x78
62 #define AHB_GIZMO_USB3          0x7c
63 #define   IMMEDIATE     BIT(18)
64
65 #define AHB_MEM_PREFETCH_CFG3   0xe0
66 #define AHB_MEM_PREFETCH_CFG4   0xe4
67 #define AHB_MEM_PREFETCH_CFG1   0xec
68 #define AHB_MEM_PREFETCH_CFG2   0xf0
69 #define   PREFETCH_ENB  BIT(31)
70 #define   MST_ID(x)     (((x) & 0x1f) << 26)
71 #define   AHBDMA_MST_ID MST_ID(5)
72 #define   USB_MST_ID    MST_ID(6)
73 #define   USB2_MST_ID   MST_ID(18)
74 #define   USB3_MST_ID   MST_ID(17)
75 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
76 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
77
78 unsigned long tegra_bootloader_fb_start;
79 unsigned long tegra_bootloader_fb_size;
80 unsigned long tegra_fb_start;
81 unsigned long tegra_fb_size;
82 unsigned long tegra_fb2_start;
83 unsigned long tegra_fb2_size;
84 unsigned long tegra_carveout_start;
85 unsigned long tegra_carveout_size;
86 unsigned long tegra_lp0_vec_start;
87 unsigned long tegra_lp0_vec_size;
88 bool tegra_lp0_vec_relocate;
89 unsigned long tegra_grhost_aperture = ~0ul;
90 static   bool is_tegra_debug_uart_hsport;
91 static struct board_info pmu_board_info;
92 static struct board_info display_board_info;
93
94 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
95 static int board_panel_type;
96 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
97
98 /*
99  * Storage for debug-macro.S's state.
100  *
101  * This must be in .data not .bss so that it gets initialized each time the
102  * kernel is loaded. The data is declared here rather than debug-macro.S so
103  * that multiple inclusions of debug-macro.S point at the same data.
104  */
105 u32 tegra_uart_config[4] = {
106         /* Debug UART initialization required */
107         1,
108         /* Debug UART physical address */
109         0,
110         /* Debug UART virtual address */
111         0,
112         /* Scratch space for debug macro */
113         0,
114 };
115
116 #ifdef CONFIG_OF
117 void __init tegra_dt_init_irq(void)
118 {
119         tegra_clocks_init();
120         tegra_pmc_init();
121         tegra_init_irq();
122         irqchip_init();
123 }
124 #endif
125
126 void tegra_assert_system_reset(char mode, const char *cmd)
127 {
128         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
129         u32 reg;
130
131         reg = readl_relaxed(reset);
132         reg |= 0x10;
133         writel_relaxed(reg, reset);
134 }
135 static int modem_id;
136 static int debug_uart_port_id;
137 static enum audio_codec_type audio_codec_name;
138 static int max_cpu_current;
139
140 void tegra_init_cache(u32 tag_latency, u32 data_latency)
141 {
142 #ifdef CONFIG_CACHE_L2X0
143         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
144         u32 aux_ctrl, cache_type;
145         u32 tag_latency, data_latency;
146
147 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
148         tag_latency = 0x331;
149         data_latency = 0x441;
150 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
151 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
152         if (is_lp_cluster()) {
153                 tag_latency = 0x221;
154                 data_latency = 0x221;
155         } else {
156                 tag_latency = 0x441;
157                 data_latency = 0x551;
158         }
159 #else
160         tag_latency = 0x770;
161         data_latency = 0x770;
162 #endif
163 #endif
164         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
165         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
166
167 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
168 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
169         writel(7, p + L2X0_PREFETCH_CTRL);
170         writel(2, p + L2X0_POWER_CTRL);
171 #endif  
172 #endif
173
174         cache_type = readl(p + L2X0_CACHE_TYPE);
175         aux_ctrl = (cache_type & 0x700) << (17-8);
176         aux_ctrl |= 0x7C400001;
177
178         l2x0_init(p, aux_ctrl, 0x8200c3fe);
179 #endif
180 }
181
182 static void __init tegra_init_power(void)
183 {
184 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
185         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
186 #endif
187 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
188         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
189 #endif
190 }
191
192 static inline unsigned long gizmo_readl(unsigned long offset)
193 {
194         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
195 }
196
197 static inline void gizmo_writel(unsigned long value, unsigned long offset)
198 {
199         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
200 }
201
202 static void __init tegra_init_ahb_gizmo_settings(void)
203 {
204         unsigned long val;
205
206         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
207         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
208         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
209
210         val = gizmo_readl(AHB_GIZMO_USB);
211         val |= IMMEDIATE;
212         gizmo_writel(val, AHB_GIZMO_USB);
213
214         val = gizmo_readl(AHB_GIZMO_USB2);
215         val |= IMMEDIATE;
216         gizmo_writel(val, AHB_GIZMO_USB2);
217
218         val = gizmo_readl(AHB_GIZMO_USB3);
219         val |= IMMEDIATE;
220         gizmo_writel(val, AHB_GIZMO_USB3);
221
222         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
223         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
224                                 | AHB_PRIORITY_WEIGHT(7);
225         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
226
227         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
228         val &= ~MST_ID(~0);
229         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
230         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
231
232         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
233         val &= ~MST_ID(~0);
234         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
235         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
236
237         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
238         val &= ~MST_ID(~0);
239         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
240         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
241
242         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
243         val &= ~MST_ID(~0);
244         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
245         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
246 }
247
248 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
249 void __init tegra20_init_early(void)
250 {
251 #ifndef CONFIG_SMP
252         /* For SMP system, initializing the reset handler here is too
253            late. For non-SMP systems, the function that calls the reset
254            handler initializer is not called, so do it here for non-SMP. */
255         tegra_cpu_reset_handler_init();
256 #endif
257         tegra_apb_io_init();
258         tegra_init_fuse();
259         tegra_init_cache();
260         tegra_powergate_init();
261         tegra20_hotplug_init();
262         tegra_init_power();
263         tegra_init_ahb_gizmo_settings();
264 }
265 #endif
266 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
267 void __init tegra30_init_early(void)
268 {
269 #ifndef CONFIG_SMP
270         /* For SMP system, initializing the reset handler here is too
271            late. For non-SMP systems, the function that calls the reset
272            handler initializer is not called, so do it here for non-SMP. */
273         tegra_cpu_reset_handler_init();
274 #endif
275         tegra_apb_io_init();
276         tegra_init_fuse();
277         tegra_init_cache();
278         tegra_pmc_init();
279         tegra_powergate_init();
280         tegra30_hotplug_init();
281         tegra_init_power();
282         tegra_init_ahb_gizmo_settings();
283 }
284 #endif
285
286 static int __init tegra_lp0_vec_arg(char *options)
287 {
288         char *p = options;
289
290         tegra_lp0_vec_size = memparse(p, &p);
291         if (*p == '@')
292                 tegra_lp0_vec_start = memparse(p+1, &p);
293         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
294                 tegra_lp0_vec_size = 0;
295                 tegra_lp0_vec_start = 0;
296         }
297
298         return 0;
299 }
300 early_param("lp0_vec", tegra_lp0_vec_arg);
301
302 static int __init tegra_bootloader_fb_arg(char *options)
303 {
304         char *p = options;
305
306         tegra_bootloader_fb_size = memparse(p, &p);
307         if (*p == '@')
308                 tegra_bootloader_fb_start = memparse(p+1, &p);
309
310         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
311                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
312
313         return 0;
314 }
315 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
316
317 enum panel_type get_panel_type(void)
318 {
319         return board_panel_type;
320 }
321 static int __init tegra_board_panel_type(char *options)
322 {
323         if (!strcmp(options, "lvds"))
324                 board_panel_type = panel_type_lvds;
325         else if (!strcmp(options, "dsi"))
326                 board_panel_type = panel_type_dsi;
327         else
328                 return 0;
329         return 1;
330 }
331 __setup("panel=", tegra_board_panel_type);
332
333 enum power_supply_type get_power_supply_type(void)
334 {
335         return pow_supply_type;
336 }
337 static int __init tegra_board_power_supply_type(char *options)
338 {
339         if (!strcmp(options, "Adapter"))
340                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
341         if (!strcmp(options, "Mains"))
342                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
343         else if (!strcmp(options, "Battery"))
344                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
345         else
346                 return 0;
347         return 1;
348 }
349 __setup("power_supply=", tegra_board_power_supply_type);
350
351 int get_core_edp(void)
352 {
353         return pmu_core_edp;
354 }
355 static int __init tegra_pmu_core_edp(char *options)
356 {
357         char *p = options;
358         int core_edp = memparse(p, &p);
359         if (core_edp != 0)
360                 pmu_core_edp = core_edp;
361         return 0;
362 }
363 early_param("core_edp_mv", tegra_pmu_core_edp);
364
365 int get_maximum_cpu_current_supported(void)
366 {
367         return max_cpu_current;
368 }
369 static int __init tegra_max_cpu_current(char *options)
370 {
371         char *p = options;
372         max_cpu_current = memparse(p, &p);
373         return 1;
374 }
375 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
376
377 static int __init tegra_debug_uartport(char *info)
378 {
379         char *p = info;
380         unsigned long long port_id;
381         if (!strncmp(p, "hsport", 6))
382                 is_tegra_debug_uart_hsport = true;
383         else if (!strncmp(p, "lsport", 6))
384                 is_tegra_debug_uart_hsport = false;
385
386         if (p[6] == ',') {
387                 if (p[7] == '-') {
388                         debug_uart_port_id = -1;
389                 } else {
390                         port_id = memparse(p + 7, &p);
391                         debug_uart_port_id = (int) port_id;
392                 }
393         } else {
394                 debug_uart_port_id = -1;
395         }
396
397         return 1;
398 }
399
400 bool is_tegra_debug_uartport_hs(void)
401 {
402         return is_tegra_debug_uart_hsport;
403 }
404
405 int get_tegra_uart_debug_port_id(void)
406 {
407         return debug_uart_port_id;
408 }
409 __setup("debug_uartport=", tegra_debug_uartport);
410
411 static int __init tegra_audio_codec_type(char *info)
412 {
413         char *p = info;
414         if (!strncmp(p, "wm8903", 6))
415                 audio_codec_name = audio_codec_wm8903;
416         else
417                 audio_codec_name = audio_codec_none;
418
419         return 1;
420 }
421
422 enum audio_codec_type get_audio_codec_type(void)
423 {
424         return audio_codec_name;
425 }
426 __setup("audio_codec=", tegra_audio_codec_type);
427
428
429 void tegra_get_board_info(struct board_info *bi)
430 {
431         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
432         bi->sku = (system_serial_high) & 0xFFFF;
433         bi->fab = (system_serial_low >> 24) & 0xFF;
434         bi->major_revision = (system_serial_low >> 16) & 0xFF;
435         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
436 }
437
438 static int __init tegra_pmu_board_info(char *info)
439 {
440         char *p = info;
441         pmu_board_info.board_id = memparse(p, &p);
442         pmu_board_info.sku = memparse(p+1, &p);
443         pmu_board_info.fab = memparse(p+1, &p);
444         pmu_board_info.major_revision = memparse(p+1, &p);
445         pmu_board_info.minor_revision = memparse(p+1, &p);
446         return 1;
447 }
448
449 void tegra_get_pmu_board_info(struct board_info *bi)
450 {
451         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
452 }
453
454 __setup("pmuboard=", tegra_pmu_board_info);
455
456 static int __init tegra_display_board_info(char *info)
457 {
458         char *p = info;
459         display_board_info.board_id = memparse(p, &p);
460         display_board_info.sku = memparse(p+1, &p);
461         display_board_info.fab = memparse(p+1, &p);
462         display_board_info.major_revision = memparse(p+1, &p);
463         display_board_info.minor_revision = memparse(p+1, &p);
464         return 1;
465 }
466
467 void tegra_get_display_board_info(struct board_info *bi)
468 {
469         memcpy(bi, &display_board_info, sizeof(struct board_info));
470 }
471
472 __setup("displayboard=", tegra_display_board_info);
473
474 static int __init tegra_modem_id(char *id)
475 {
476         char *p = id;
477
478         modem_id = memparse(p, &p);
479         return 1;
480 }
481
482 int tegra_get_modem_id(void)
483 {
484         return modem_id;
485 }
486
487 __setup("modem_id=", tegra_modem_id);
488
489 /*
490  * Tegra has a protected aperture that prevents access by most non-CPU
491  * memory masters to addresses above the aperture value.  Enabling it
492  * secures the CPU's memory from the GPU, except through the GART.
493  */
494 void __init tegra_protected_aperture_init(unsigned long aperture)
495 {
496 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
497         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
498         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
499         writel(aperture, mc_base + MC_SECURITY_CFG2);
500 #else
501         pr_err("Tegra protected aperture disabled because nvmap is using "
502                 "system memory\n");
503 #endif
504 }
505
506 /*
507  * Due to conflicting restrictions on the placement of the framebuffer,
508  * the bootloader is likely to leave the framebuffer pointed at a location
509  * in memory that is outside the grhost aperture.  This function will move
510  * the framebuffer contents from a physical address that is anywher (lowmem,
511  * highmem, or outside the memory map) to a physical address that is outside
512  * the memory map.
513  */
514 void tegra_move_framebuffer(unsigned long to, unsigned long from,
515         unsigned long size)
516 {
517         struct page *page;
518         void __iomem *to_io;
519         void *from_virt;
520         unsigned long i;
521
522         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
523         BUG_ON(PAGE_ALIGN(from) != from);
524         BUG_ON(PAGE_ALIGN(size) != size);
525
526         to_io = ioremap(to, size);
527         if (!to_io) {
528                 pr_err("%s: Failed to map target framebuffer\n", __func__);
529                 return;
530         }
531
532         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
533                 for (i = 0 ; i < size; i += PAGE_SIZE) {
534                         page = phys_to_page(from + i);
535                         from_virt = kmap(page);
536                         memcpy(to_io + i, from_virt, PAGE_SIZE);
537                         kunmap(page);
538                 }
539         } else {
540                 void __iomem *from_io = ioremap(from, size);
541                 if (!from_io) {
542                         pr_err("%s: Failed to map source framebuffer\n",
543                                 __func__);
544                         goto out;
545                 }
546
547                 for (i = 0; i < size; i += 4)
548                         writel(readl(from_io + i), to_io + i);
549
550                 iounmap(from_io);
551         }
552 out:
553         iounmap(to_io);
554 }
555
556 #ifdef CONFIG_TEGRA_IOVMM_SMMU
557 /* Support for Tegra3 A01 chip mask that needs to have SMMU IOVA reside in
558  * the upper half of 4GB IOVA space. A02 and after use the bottom 1GB and
559  * do not need to reserve memory.
560  */
561 #define SUPPORT_TEGRA_3_IOVMM_SMMU_A01
562 #endif
563
564 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
565         unsigned long fb2_size)
566 {
567 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
568         int smmu_reserved = 0;
569         struct tegra_smmu_window *smmu_window = tegra_smmu_window(0);
570 #endif
571
572         if (carveout_size) {
573                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
574                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
575                         pr_err("Failed to remove carveout %08lx@%08lx "
576                                 "from memory map\n",
577                                 carveout_size, tegra_carveout_start);
578                         tegra_carveout_start = 0;
579                         tegra_carveout_size = 0;
580                 } else
581                         tegra_carveout_size = carveout_size;
582         }
583
584         if (fb2_size) {
585                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
586                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
587                         pr_err("Failed to remove second framebuffer "
588                                 "%08lx@%08lx from memory map\n",
589                                 fb2_size, tegra_fb2_start);
590                         tegra_fb2_start = 0;
591                         tegra_fb2_size = 0;
592                 } else
593                         tegra_fb2_size = fb2_size;
594         }
595
596         if (fb_size) {
597                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
598                 if (memblock_remove(tegra_fb_start, fb_size)) {
599                         pr_err("Failed to remove framebuffer %08lx@%08lx "
600                                 "from memory map\n",
601                                 fb_size, tegra_fb_start);
602                         tegra_fb_start = 0;
603                         tegra_fb_size = 0;
604                 } else
605                         tegra_fb_size = fb_size;
606         }
607
608         if (tegra_fb_size)
609                 tegra_grhost_aperture = tegra_fb_start;
610
611         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
612                 tegra_grhost_aperture = tegra_fb2_start;
613
614         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
615                 tegra_grhost_aperture = tegra_carveout_start;
616
617 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
618         if (!smmu_window) {
619                 pr_err("No SMMU resource\n");
620         } else {
621                 size_t smmu_window_size;
622
623                 if (tegra_revision == TEGRA_REVISION_A01) {
624                         smmu_window->start = TEGRA_SMMU_BASE_A01;
625                         smmu_window->end   = TEGRA_SMMU_BASE_A01 +
626                                                 TEGRA_SMMU_SIZE_A01 - 1;
627                 }
628                 smmu_window_size = smmu_window->end + 1 - smmu_window->start;
629                 if (smmu_window->start >= 0x80000000) {
630                         if (memblock_reserve(smmu_window->start,
631                                                 smmu_window_size))
632                                 pr_err(
633                         "Failed to reserve SMMU I/O VA window %08lx@%08lx\n",
634                                 (unsigned long)smmu_window_size,
635                                 (unsigned long)smmu_window->start);
636                         else
637                                 smmu_reserved = 1;
638                 }
639         }
640 #endif
641
642         if (tegra_lp0_vec_size &&
643            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
644                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
645                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
646                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
647                         tegra_lp0_vec_start = 0;
648                         tegra_lp0_vec_size = 0;
649                 }
650                 tegra_lp0_vec_relocate = false;
651         } else
652                 tegra_lp0_vec_relocate = true;
653
654         /*
655          * We copy the bootloader's framebuffer to the framebuffer allocated
656          * above, and then free this one.
657          * */
658         if (tegra_bootloader_fb_size) {
659                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
660                 if (memblock_reserve(tegra_bootloader_fb_start,
661                                 tegra_bootloader_fb_size)) {
662                         pr_err("Failed to reserve bootloader frame buffer "
663                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
664                                 tegra_bootloader_fb_start);
665                         tegra_bootloader_fb_start = 0;
666                         tegra_bootloader_fb_size = 0;
667                 }
668         }
669
670         pr_info("Tegra reserved memory:\n"
671                 "LP0:                    %08lx - %08lx\n"
672                 "Bootloader framebuffer: %08lx - %08lx\n"
673                 "Framebuffer:            %08lx - %08lx\n"
674                 "2nd Framebuffer:        %08lx - %08lx\n"
675                 "Carveout:               %08lx - %08lx\n",
676                 tegra_lp0_vec_start,
677                 tegra_lp0_vec_size ?
678                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
679                 tegra_bootloader_fb_start,
680                 tegra_bootloader_fb_size ?
681                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
682                 tegra_fb_start,
683                 tegra_fb_size ?
684                         tegra_fb_start + tegra_fb_size - 1 : 0,
685                 tegra_fb2_start,
686                 tegra_fb2_size ?
687                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
688                 tegra_carveout_start,
689                 tegra_carveout_size ?
690                         tegra_carveout_start + tegra_carveout_size - 1 : 0);
691
692 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
693         if (smmu_reserved)
694                 pr_info("SMMU:                   %08lx - %08lx\n",
695                         smmu_window->start, smmu_window->end);
696 #endif
697 }
698
699 void __init tegra_release_bootloader_fb(void)
700 {
701         /* Since bootloader fb is reserved in common.c, it is freed here. */
702         if (tegra_bootloader_fb_size)
703                 if (memblock_free(tegra_bootloader_fb_start,
704                                                 tegra_bootloader_fb_size))
705                         pr_err("Failed to free bootloader fb.\n");
706 }
707
708 void __init tegra_init_late(void)
709 {
710 #ifndef CONFIG_COMMON_CLK
711         tegra_clk_debugfs_init();
712 #endif
713         tegra_powergate_debugfs_init();
714 }