6c2458b7b5ff536c411169b452f3877c45902c5f
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36
37 #include <linux/export.h>
38 #include <linux/bootmem.h>
39 #include <trace/events/nvsecurity.h>
40
41 #include <asm/hardware/cache-l2x0.h>
42 #include <asm/system.h>
43 #include <asm/dma-mapping.h>
44
45 #include <mach/hardware.h>
46 #include <mach/powergate.h>
47 #include <mach/tegra_smmu.h>
48 #include <mach/nct.h>
49
50 #include "apbio.h"
51 #include "board.h"
52 #include "clock.h"
53 #include "common.h"
54 #include "dvfs.h"
55 #include "fuse.h"
56 #include "iomap.h"
57 #include "pm.h"
58 #include "sleep.h"
59 #include "reset.h"
60 #include "devices.h"
61 #include "pmc.h"
62
63 #define MC_SECURITY_CFG2        0x7c
64
65 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
66 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
67 #define   PRIORITY_SELECT_USB   BIT(6)
68 #define   PRIORITY_SELECT_USB2  BIT(18)
69 #define   PRIORITY_SELECT_USB3  BIT(17)
70 #define   PRIORITY_SELECT_SE BIT(14)
71
72 #define AHB_GIZMO_AHB_MEM               0xc
73 #define   ENB_FAST_REARBITRATE  BIT(2)
74 #define   DONT_SPLIT_AHB_WR     BIT(7)
75 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
76 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
77
78 #define   RECOVERY_MODE BIT(31)
79 #define   BOOTLOADER_MODE       BIT(30)
80 #define   FORCED_RECOVERY_MODE  BIT(1)
81
82 #define AHB_GIZMO_USB           0x1c
83 #define AHB_GIZMO_USB2          0x78
84 #define AHB_GIZMO_USB3          0x7c
85 #define AHB_GIZMO_SE            0x4c
86 #define   IMMEDIATE     BIT(18)
87
88 #define AHB_MEM_PREFETCH_CFG5   0xc8
89 #define AHB_MEM_PREFETCH_CFG3   0xe0
90 #define AHB_MEM_PREFETCH_CFG4   0xe4
91 #define AHB_MEM_PREFETCH_CFG1   0xec
92 #define AHB_MEM_PREFETCH_CFG2   0xf0
93 #define AHB_MEM_PREFETCH_CFG6   0xcc
94 #define   PREFETCH_ENB  BIT(31)
95 #define   MST_ID(x)     (((x) & 0x1f) << 26)
96 #define   AHBDMA_MST_ID MST_ID(5)
97 #define   USB_MST_ID    MST_ID(6)
98 #define SDMMC4_MST_ID   MST_ID(12)
99 #define   USB2_MST_ID   MST_ID(18)
100 #define   USB3_MST_ID   MST_ID(17)
101 #define   SE_MST_ID     MST_ID(14)
102 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
103 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
104
105 unsigned long tegra_avp_kernel_start;
106 unsigned long tegra_avp_kernel_size;
107 unsigned long tegra_bootloader_fb_start;
108 unsigned long tegra_bootloader_fb_size;
109 unsigned long tegra_bootloader_fb2_start;
110 unsigned long tegra_bootloader_fb2_size;
111 unsigned long tegra_fb_start;
112 unsigned long tegra_fb_size;
113 unsigned long tegra_fb2_start;
114 unsigned long tegra_fb2_size;
115 unsigned long tegra_carveout_start;
116 unsigned long tegra_carveout_size;
117 unsigned long tegra_vpr_start;
118 unsigned long tegra_vpr_size;
119 unsigned long tegra_tsec_start;
120 unsigned long tegra_tsec_size;
121 unsigned long tegra_lp0_vec_start;
122 unsigned long tegra_lp0_vec_size;
123 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
124 unsigned long tegra_wb0_params_address;
125 unsigned long tegra_wb0_params_instances;
126 unsigned long tegra_wb0_params_block_size;
127 #endif
128
129 #ifdef CONFIG_TEGRA_NVDUMPER
130 unsigned long nvdumper_reserved;
131 #endif
132 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
133 unsigned long tegra_tzram_start;
134 unsigned long tegra_tzram_size;
135 #endif
136 bool tegra_lp0_vec_relocate;
137 unsigned long tegra_grhost_aperture = ~0ul;
138 static   bool is_tegra_debug_uart_hsport;
139 static struct board_info pmu_board_info;
140 static struct board_info display_board_info;
141 static int panel_id;
142 static struct board_info camera_board_info;
143 static int touch_vendor_id;
144 static int touch_panel_id;
145 static struct board_info io_board_info;
146 static struct board_info button_board_info;
147 static struct board_info joystick_board_info;
148 static struct board_info rightspeaker_board_info;
149 static struct board_info leftspeaker_board_info;
150 #ifdef CONFIG_TEGRA_USE_NCT
151 unsigned long tegra_nck_start;
152 unsigned long tegra_nck_size;
153 #endif
154
155 static int pmu_core_edp;
156 static int board_panel_type;
157 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
158 static int pwr_i2c_clk = 400;
159 static u8 power_config;
160 static u8 display_config;
161 /*
162  * Storage for debug-macro.S's state.
163  *
164  * This must be in .data not .bss so that it gets initialized each time the
165  * kernel is loaded. The data is declared here rather than debug-macro.S so
166  * that multiple inclusions of debug-macro.S point at the same data.
167  */
168 u32 tegra_uart_config[4] = {
169         /* Debug UART initialization required */
170         1,
171         /* Debug UART physical address */
172         0,
173         /* Debug UART virtual address */
174         0,
175         /* Scratch space for debug macro */
176         0,
177 };
178
179
180 #define NEVER_RESET 0
181
182 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
183 {
184         unsigned long check;
185         int retry = 10;
186
187         /* Read and check if write is successful,
188          * if val doesn't match with read, retry write.
189          */
190         do {
191                 writel(val, reg);
192                 check = readl(reg);
193                 if (likely(check == val))
194                         break;
195                 else
196                         pr_err("AHB register access fail for reg\n");
197         } while (--retry);
198 }
199
200 void tegra_assert_system_reset(char mode, const char *cmd)
201 {
202 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
203         pr_info("tegra_assert_system_reset() ignored.....");
204         do { } while (1);
205 #else
206         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
207         u32 reg;
208
209         reg = readl_relaxed(reset + PMC_SCRATCH0);
210         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
211         if (cmd) {
212                 if (!strcmp(cmd, "recovery"))
213                         reg |= RECOVERY_MODE;
214                 else if (!strcmp(cmd, "bootloader"))
215                         reg |= BOOTLOADER_MODE;
216                 else if (!strcmp(cmd, "forced-recovery"))
217                         reg |= FORCED_RECOVERY_MODE;
218                 else
219                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
220         }
221         else {
222                 /* Clearing SCRATCH0 31:30:1 on default reboot */
223                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
224         }
225         writel_relaxed(reg, reset + PMC_SCRATCH0);
226         reg = readl_relaxed(reset);
227         reg |= 0x10;
228         writel_relaxed(reg, reset);
229 #endif
230 }
231 static int modem_id;
232 static int commchip_id;
233 static int sku_override;
234 static int debug_uart_port_id;
235 static enum audio_codec_type audio_codec_name;
236 static enum image_type board_image_type = system_image;
237 static int max_cpu_current;
238 static int max_core_current;
239 static int emc_max_dvfs;
240 static int usb_port_owner_info;
241
242 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
243 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
244         /* name         parent          rate            enabled */
245         { "clk_m",      NULL,           0,              true },
246         { "emc",        NULL,           0,              true },
247         { "cpu",        NULL,           0,              true },
248         { "kfuse",      NULL,           0,              true },
249         { "fuse",       NULL,           0,              true },
250         { "sclk",       NULL,           0,              true },
251         { "pll_p",      NULL,           0,              true },
252         { "pll_p_out1", "pll_p",        0,              false },
253         { "pll_p_out3", "pll_p",        0,              false },
254 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
255         { "pll_m_out1", "pll_m",        275000000,      false },
256         { "pll_p_out2",  "pll_p",       102000000,      false },
257         { "sclk",        "pll_p_out2",  102000000,      true },
258         { "pll_p_out4",  "pll_p",       204000000,      true },
259         { "hclk",       "sclk",         102000000,      true },
260         { "pclk",       "hclk",         51000000,       true },
261         { "mselect",    "pll_p",        102000000,      true },
262         { "host1x",     "pll_p",        102000000,      false },
263         { "cl_dvfs_ref", "pll_p",       51000000,       true },
264         { "cl_dvfs_soc", "pll_p",       51000000,       true },
265         { "dsialp", "pll_p",    70000000,       false },
266         { "dsiblp", "pll_p",    70000000,       false },
267 #else
268         { "pll_m_out1", "pll_m",        275000000,      true },
269         { "pll_p_out2", "pll_p",        108000000,      false },
270         { "sclk",       "pll_p_out2",   108000000,      true },
271         { "pll_p_out4", "pll_p",        216000000,      true },
272         { "hclk",       "sclk",         108000000,      true },
273         { "pclk",       "hclk",         54000000,       true },
274         { "mselect",    "pll_p",        108000000,      true },
275         { "host1x",     "pll_p",        108000000,      false },
276         { "cl_dvfs_ref", "clk_m",       13000000,       false },
277         { "cl_dvfs_soc", "clk_m",       13000000,       false },
278 #endif
279 #ifdef CONFIG_TEGRA_SLOW_CSITE
280         { "csite",      "clk_m",        1000000,        true },
281 #else
282         { "csite",      NULL,           0,              true },
283 #endif
284         { "pll_u",      NULL,           480000000,      true },
285         { "pll_re_vco", NULL,           612000000,      true },
286         { "xusb_falcon_src",    "pll_p",        204000000,      false},
287         { "xusb_host_src",      "pll_p",        102000000,      false},
288         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
289         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
290         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
291         { "sdmmc1",     "pll_p",        48000000,       false},
292         { "sdmmc3",     "pll_p",        48000000,       false},
293         { "sdmmc4",     "pll_p",        48000000,       false},
294         { "sbc1.sclk",  NULL,           40000000,       false},
295         { "sbc2.sclk",  NULL,           40000000,       false},
296         { "sbc3.sclk",  NULL,           40000000,       false},
297         { "sbc4.sclk",  NULL,           40000000,       false},
298         { "sbc5.sclk",  NULL,           40000000,       false},
299         { "sbc6.sclk",  NULL,           40000000,       false},
300 #ifdef CONFIG_TEGRA_PLLM_SCALED
301         { "vi",         "pll_p",        0,              false},
302 #endif
303 #ifdef CONFIG_TEGRA_SOCTHERM
304         { "soc_therm",  "pll_p",        51000000,       false },
305         { "tsensor",    "clk_m",        500000,         false },
306 #endif
307         { NULL,         NULL,           0,              0},
308 };
309 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
310 #ifdef CONFIG_TEGRA_DUAL_CBUS
311         { "c2bus",      "pll_c2",       250000000,      false },
312         { "c3bus",      "pll_c3",       250000000,      false },
313         { "pll_c",      NULL,           624000000,      false },
314 #else
315         { "cbus",       "pll_c",        250000000,      false },
316 #endif
317         { "pll_c_out1", "pll_c",        150000000,      false },
318         { NULL,         NULL,           0,              0},
319 };
320 #endif
321 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
322 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
323         /* name         parent          rate            enabled */
324         { "osc",        NULL,           0,              true },
325         { "clk_m",      "osc",          0,              true },
326         { "emc",        NULL,           0,              true },
327         { "cpu",        NULL,           0,              true },
328         { "kfuse",      NULL,           0,              true },
329         { "fuse",       NULL,           0,              true },
330         { "sclk",       NULL,           0,              true },
331 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
332         { "pll_p",      NULL,           0,              true },
333         { "pll_p_out1", "pll_p",        0,              false },
334         { "pll_p_out3", "pll_p",        0,              true },
335         { "pll_m_out1", "pll_m",        275000000,      false },
336         { "pll_p_out2",  "pll_p",       102000000,      false },
337         { "sclk",        "pll_p_out2",  102000000,      true },
338         { "pll_p_out4",  "pll_p",       204000000,      true },
339         { "hclk",       "sclk",         102000000,      true },
340         { "pclk",       "hclk",         51000000,       true },
341         { "mselect",    "pll_p",        102000000,      true },
342         { "host1x",     "pll_p",        102000000,      false },
343         { "cl_dvfs_ref", "pll_p",       51000000,       true },
344         { "cl_dvfs_soc", "pll_p",       51000000,       true },
345 #else
346         { "pll_p",      NULL,           0,              true },
347         { "pll_p_out1", "pll_p",        0,              false },
348         { "pll_p_out3", "pll_p",        0,              true },
349         { "pll_m_out1", "pll_m",        275000000,      true },
350         { "pll_p_out2", "pll_p",        108000000,      false },
351         { "sclk",       "pll_p_out2",   108000000,      true },
352         { "pll_p_out4", "pll_p",        216000000,      true },
353         { "host1x",     "pll_p",        108000000,      false },
354         { "cl_dvfs_ref", "clk_m",       13000000,       false },
355         { "cl_dvfs_soc", "clk_m",       13000000,       false },
356         { "hclk",       "sclk",         108000000,      true },
357         { "pclk",       "hclk",         54000000,       true },
358         { "wake.sclk",  NULL,           250000000,      true },
359         { "mselect",    "pll_p",        108000000,      true },
360 #endif
361 #ifdef CONFIG_TEGRA_SLOW_CSITE
362         { "csite",      "clk_m",        1000000,        true },
363 #else
364         { "csite",      NULL,           0,              true },
365 #endif
366         { "pll_u",      NULL,           480000000,      false },
367         { "sdmmc1",     "pll_p",        48000000,       false},
368         { "sdmmc3",     "pll_p",        48000000,       false},
369         { "sdmmc4",     "pll_p",        48000000,       false},
370         { "mon.avp",    NULL,           80000000,       true },
371         { "sbc1.sclk",  NULL,           20000000,       false},
372         { "sbc2.sclk",  NULL,           20000000,       false},
373         { "sbc3.sclk",  NULL,           20000000,       false},
374         { "msenc",      "pll_p",        108000000,      false },
375         { "tsec",       "pll_p",        108000000,      false },
376         { "mc_capa",    "emc",          0,              true },
377         { "mc_cbpa",    "emc",          0,              true },
378 #ifdef CONFIG_TEGRA_SOCTHERM
379         { "soc_therm",  "pll_p",        51000000,       false },
380         { "tsensor",    "clk_m",        400000,         false },
381 #endif
382         { NULL,         NULL,           0,              0},
383 };
384 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
385         /* Initialize c2bus, c3bus, or cbus at the end of the list
386          * after all the clocks are moved under the proper parents.
387          */
388 #ifdef CONFIG_TEGRA_DUAL_CBUS
389         { "c2bus",      "pll_c2",       200000000,      false },
390         { "c3bus",      "pll_c3",       200000000,      false },
391         { "pll_c",      NULL,           768000000,      false },
392 #else
393         { "cbus",       "pll_c",        200000000,      false },
394 #endif
395         { "pll_c_out1", "pll_c",        100000000,      false },
396         { NULL,         NULL,           0,              0},
397 };
398 #endif
399
400 #ifdef CONFIG_CACHE_L2X0
401 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
402 static void tegra_cache_smc(bool enable, u32 arg)
403 {
404         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
405         bool need_affinity_switch;
406         bool can_switch_affinity;
407         bool l2x0_enabled;
408         cpumask_t local_cpu_mask;
409         cpumask_t saved_cpu_mask;
410         unsigned long flags;
411         long ret;
412
413         /*
414          * ISSUE : Some registers of PL310 controler must be written
415          *              from Secure context (and from CPU0)!
416          *
417          * When called form Normal we obtain an abort or do nothing.
418          * Instructions that must be called in Secure:
419          *      - Write to Control register (L2X0_CTRL==0x100)
420          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
421          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
422          *              mandatory at boot time.
423          *      - Tag and Data RAM Latency Control Registers
424          *              (0x108 & 0x10C) must be written in Secure.
425          */
426         need_affinity_switch = (smp_processor_id() != 0);
427         can_switch_affinity = !irqs_disabled();
428
429         WARN_ON(need_affinity_switch && !can_switch_affinity);
430         if (need_affinity_switch && can_switch_affinity) {
431                 cpu_set(0, local_cpu_mask);
432                 sched_getaffinity(0, &saved_cpu_mask);
433                 ret = sched_setaffinity(0, &local_cpu_mask);
434                 WARN_ON(ret != 0);
435         }
436
437         local_irq_save(flags);
438         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
439         if (enable && !l2x0_enabled)
440                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
441         else if (!enable && l2x0_enabled)
442                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
443         local_irq_restore(flags);
444
445         if (need_affinity_switch && can_switch_affinity) {
446                 ret = sched_setaffinity(0, &saved_cpu_mask);
447                 WARN_ON(ret != 0);
448         }
449 }
450
451 static void tegra_l2x0_disable(void)
452 {
453         unsigned long flags;
454         static u32 l2x0_way_mask;
455
456         if (!l2x0_way_mask) {
457                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
458                 u32 aux_ctrl;
459                 u32 ways;
460
461                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
462                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
463                 l2x0_way_mask = (1 << ways) - 1;
464         }
465
466         local_irq_save(flags);
467         tegra_cache_smc(false, l2x0_way_mask);
468         local_irq_restore(flags);
469 }
470 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
471
472 void tegra_init_cache(bool init)
473 {
474         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
475         u32 aux_ctrl;
476 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
477         u32 cache_type;
478         u32 tag_latency, data_latency;
479 #endif
480
481 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
482         /* issue the SMC to enable the L2 */
483         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
484         trace_smc_init_cache(NVSEC_SMC_START);
485         tegra_cache_smc(true, aux_ctrl);
486         trace_smc_init_cache(NVSEC_SMC_DONE);
487
488         /* after init, reread aux_ctrl and register handlers */
489         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
490         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
491
492         /* override outer_disable() with our disable */
493         outer_cache.disable = tegra_l2x0_disable;
494 #else
495 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
496         tag_latency = 0x331;
497         data_latency = 0x441;
498 #else
499 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
500         if (is_lp_cluster()) {
501                 tag_latency = tegra_cpu_c1_l2_tag_latency;
502                 data_latency = tegra_cpu_c1_l2_data_latency;
503         } else {
504                 tag_latency = tegra_cpu_c0_l2_tag_latency;
505                 data_latency = tegra_cpu_c0_l2_data_latency;
506         }
507 #else
508         tag_latency = 0x770;
509         data_latency = 0x770;
510 #endif
511 #endif
512         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
513         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
514
515 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
516 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
517 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
518         /* Enable double line fill */
519         writel(0x40000007, p + L2X0_PREFETCH_CTRL);
520 #else
521         writel(0x7, p + L2X0_PREFETCH_CTRL);
522 #endif
523         writel(0x3, p + L2X0_POWER_CTRL);
524 #endif
525 #endif
526         cache_type = readl(p + L2X0_CACHE_TYPE);
527         aux_ctrl = (cache_type & 0x700) << (17-8);
528         aux_ctrl |= 0x7C400001;
529         if (init) {
530                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
531         } else {
532                 u32 tmp;
533
534                 tmp = aux_ctrl;
535                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
536                 aux_ctrl &= 0x8200c3fe;
537                 aux_ctrl |= tmp;
538                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
539         }
540         l2x0_enable();
541 #endif
542 }
543 #endif
544
545 static void __init tegra_perf_init(void)
546 {
547         u32 reg;
548
549         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
550         reg >>= 11;
551         reg = (1 << (reg & 0x1f))-1;
552         reg |= 0x80000000;
553         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
554         reg = 1;
555         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
556 }
557
558 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
559 static void __init tegra_ramrepair_init(void)
560 {
561         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
562                 u32 reg;
563                 reg = readl(FLOW_CTRL_RAM_REPAIR);
564                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
565                 writel(reg, FLOW_CTRL_RAM_REPAIR);
566         }
567 }
568 #endif
569
570 static void __init tegra_init_power(void)
571 {
572 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
573         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
574 #endif
575 #if defined(CONFIG_ARCH_TEGRA_HAS_PCIE) && \
576                         !defined(CONFIG_TEGRA_PCIE_SKIP_POWERGATING)
577         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
578 #endif
579 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
580         /* some partitions need to be powergated by default for t11x */
581         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
582         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
583         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
584 #endif
585 }
586
587 static inline unsigned long gizmo_readl(unsigned long offset)
588 {
589         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
590 }
591
592 static inline void gizmo_writel(unsigned long value, unsigned long offset)
593 {
594         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
595 }
596
597 static void __init tegra_init_ahb_gizmo_settings(void)
598 {
599         unsigned long val;
600
601         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
602         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
603
604         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11 &&
605                 tegra_revision == TEGRA_REVISION_A02)
606                 val |= WR_WAIT_COMMIT_ON_1K;
607 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
608         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
609 #endif
610         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
611
612         val = gizmo_readl(AHB_GIZMO_USB);
613         val |= IMMEDIATE;
614         gizmo_writel(val, AHB_GIZMO_USB);
615
616         val = gizmo_readl(AHB_GIZMO_USB2);
617         val |= IMMEDIATE;
618         gizmo_writel(val, AHB_GIZMO_USB2);
619
620         val = gizmo_readl(AHB_GIZMO_USB3);
621         val |= IMMEDIATE;
622         gizmo_writel(val, AHB_GIZMO_USB3);
623
624         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
625         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
626                                 | AHB_PRIORITY_WEIGHT(7);
627 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
628         val |= PRIORITY_SELECT_SE;
629 #endif
630
631         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
632
633         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
634         val &= ~MST_ID(~0);
635         val |= PREFETCH_ENB | AHBDMA_MST_ID |
636                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
637         ahb_gizmo_writel(val,
638                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
639
640         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
641         val &= ~MST_ID(~0);
642         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
643                 INACTIVITY_TIMEOUT(0x1000);
644 #if !defined(CONFIG_ANDROID)
645         val &= ~USB_MST_ID;
646 #endif
647         ahb_gizmo_writel(val,
648                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
649
650         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
651         val &= ~MST_ID(~0);
652         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
653                 INACTIVITY_TIMEOUT(0x1000);
654 #if !defined(CONFIG_ANDROID)
655         val &= ~USB3_MST_ID;
656 #endif
657         ahb_gizmo_writel(val,
658                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
659
660         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
661         val &= ~MST_ID(~0);
662         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
663                 INACTIVITY_TIMEOUT(0x1000);
664         ahb_gizmo_writel(val,
665                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
666
667         /*
668          * SDMMC controller is removed from AHB interface in T124 and
669          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
670          * in T11x and T14x SOCs.
671          */
672 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
673         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
674         val &= ~MST_ID(~0);
675         val |= PREFETCH_ENB | SDMMC4_MST_ID;
676         val &= ~SDMMC4_MST_ID;
677         ahb_gizmo_writel(val,
678                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
679 #endif
680
681 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
682         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
683         val &= ~MST_ID(~0);
684         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
685                 INACTIVITY_TIMEOUT(0x1000);
686         ahb_gizmo_writel(val,
687                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
688 #endif
689 }
690
691 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
692 void __init tegra20_init_early(void)
693 {
694 #ifndef CONFIG_SMP
695         /* For SMP system, initializing the reset handler here is too
696            late. For non-SMP systems, the function that calls the reset
697            handler initializer is not called, so do it here for non-SMP. */
698         tegra_cpu_reset_handler_init();
699 #endif
700         tegra_apb_io_init();
701         tegra_perf_init();
702         tegra_init_fuse();
703         tegra_init_cache(true);
704         tegra_pmc_init();
705         tegra_powergate_init();
706         tegra20_hotplug_init();
707         tegra_init_power();
708         tegra_init_ahb_gizmo_settings();
709         tegra_init_debug_uart_rate();
710         tegra_ram_console_debug_reserve(SZ_1M);
711 }
712 #endif
713 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
714 void __init tegra30_init_early(void)
715 {
716         u32 speedo;
717         u32 tag_latency, data_latency;
718
719 #ifndef CONFIG_SMP
720         /* For SMP system, initializing the reset handler here is too
721            late. For non-SMP systems, the function that calls the reset
722            handler initializer is not called, so do it here for non-SMP. */
723         tegra_cpu_reset_handler_init();
724 #endif
725         tegra_apb_io_init();
726         tegra_perf_init();
727         tegra_init_fuse();
728         /*
729          * Store G/LP cluster L2 latencies to IRAM and DRAM
730          */
731         tegra_cpu_c1_l2_tag_latency = 0x221;
732         tegra_cpu_c1_l2_data_latency = 0x221;
733         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
734         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
735         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
736         speedo = tegra_cpu_speedo_id();
737         if (speedo == 4 || speedo == 5 || speedo == 6 ||
738             speedo == 12 || speedo == 13) {
739                 tag_latency = 0x442;
740                 data_latency = 0x552;
741         } else {
742                 tag_latency = 0x441;
743                 data_latency = 0x551;
744         }
745         tegra_cpu_c0_l2_tag_latency = tag_latency;
746         tegra_cpu_c0_l2_data_latency = data_latency;
747         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
748         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
749         tegra_init_cache(true);
750         tegra_pmc_init();
751         tegra_powergate_init();
752         tegra30_hotplug_init();
753         tegra_init_power();
754         tegra_init_ahb_gizmo_settings();
755         tegra_init_debug_uart_rate();
756         tegra_ram_console_debug_reserve(SZ_1M);
757
758         init_dma_coherent_pool_size(SZ_1M);
759 }
760 #endif
761 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
762 void __init tegra11x_init_early(void)
763 {
764 #ifndef CONFIG_SMP
765         /* For SMP system, initializing the reset handler here is too
766            late. For non-SMP systems, the function that calls the reset
767            handler initializer is not called, so do it here for non-SMP. */
768         tegra_cpu_reset_handler_init();
769 #endif
770         tegra_apb_io_init();
771         tegra_perf_init();
772         tegra_init_fuse();
773         tegra_ramrepair_init();
774         tegra11x_init_clocks();
775         tegra11x_init_dvfs();
776         tegra_common_init_clock();
777         tegra_clk_init_from_table(tegra11x_clk_init_table);
778         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
779         tegra11x_clk_init_la();
780         tegra_pmc_init();
781         tegra_powergate_init();
782         tegra30_hotplug_init();
783         tegra_init_power();
784         tegra_init_ahb_gizmo_settings();
785         tegra_init_debug_uart_rate();
786
787         init_dma_coherent_pool_size(SZ_2M);
788 }
789 #endif
790 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
791 void __init tegra14x_init_early(void)
792 {
793 #ifndef CONFIG_SMP
794         /* For SMP system, initializing the reset handler here is too
795            late. For non-SMP systems, the function that calls the reset
796            handler initializer is not called, so do it here for non-SMP. */
797         tegra_cpu_reset_handler_init();
798 #endif
799         tegra_apb_io_init();
800         tegra_perf_init();
801         tegra_init_fuse();
802         tegra_ramrepair_init();
803         tegra14x_init_clocks();
804         tegra14x_init_dvfs();
805         tegra_common_init_clock();
806         tegra_clk_init_from_table(tegra14x_clk_init_table);
807         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
808         tegra_cpu_c1_l2_tag_latency = 0x110;
809         tegra_cpu_c1_l2_data_latency = 0x331;
810         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
811         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
812         tegra_cpu_c0_l2_tag_latency = 0x111;
813         tegra_cpu_c0_l2_data_latency = 0x441;
814         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
815         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
816         tegra_init_cache(true);
817         tegra_pmc_init();
818         tegra_powergate_init();
819         tegra30_hotplug_init();
820         tegra_init_power();
821         tegra_init_ahb_gizmo_settings();
822         tegra_init_debug_uart_rate();
823         tegra_ram_console_debug_reserve(SZ_1M);
824 }
825 #endif
826 static int __init tegra_lp0_vec_arg(char *options)
827 {
828         char *p = options;
829
830         tegra_lp0_vec_size = memparse(p, &p);
831         if (*p == '@')
832                 tegra_lp0_vec_start = memparse(p+1, &p);
833         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
834                 tegra_lp0_vec_size = 0;
835                 tegra_lp0_vec_start = 0;
836         }
837
838         return 0;
839 }
840 early_param("lp0_vec", tegra_lp0_vec_arg);
841
842 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
843 static int __init tegra_wb0_params_arg(char *options)
844 {
845         char *p = options;
846
847         tegra_wb0_params_address = memparse(p, &p);
848         if (*p == ',')
849                 tegra_wb0_params_instances = memparse(p+1, &p);
850         if (*p == ',')
851                 tegra_wb0_params_block_size = memparse(p+1, &p);
852
853         return 0;
854 }
855 early_param("wb0_params", tegra_wb0_params_arg);
856 #endif
857
858 #ifdef CONFIG_TEGRA_NVDUMPER
859 static int __init tegra_nvdumper_arg(char *options)
860 {
861         char *p = options;
862
863         nvdumper_reserved = memparse(p, &p);
864         return 0;
865 }
866 early_param("nvdumper_reserved", tegra_nvdumper_arg);
867 #endif
868
869 static int __init tegra_bootloader_fb_arg(char *options)
870 {
871         char *p = options;
872
873         tegra_bootloader_fb_size = memparse(p, &p);
874         if (*p == '@')
875                 tegra_bootloader_fb_start = memparse(p+1, &p);
876
877         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
878                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
879
880         return 0;
881 }
882 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
883
884 static int __init tegra_bootloader_fb2_arg(char *options)
885 {
886         char *p = options;
887
888         tegra_bootloader_fb2_size = memparse(p, &p);
889         if (*p == '@')
890                 tegra_bootloader_fb2_start = memparse(p+1, &p);
891
892         pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
893                 tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
894
895         return 0;
896 }
897 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
898
899 static int __init tegra_sku_override(char *id)
900 {
901         char *p = id;
902
903         sku_override = memparse(p, &p);
904
905         return 0;
906 }
907 early_param("sku_override", tegra_sku_override);
908
909 int tegra_get_sku_override(void)
910 {
911         return sku_override;
912 }
913
914 static int __init tegra_vpr_arg(char *options)
915 {
916         char *p = options;
917
918         tegra_vpr_size = memparse(p, &p);
919         if (*p == '@')
920                 tegra_vpr_start = memparse(p+1, &p);
921         pr_info("Found vpr, start=0x%lx size=%lx",
922                 tegra_vpr_start, tegra_vpr_size);
923         return 0;
924 }
925 early_param("vpr", tegra_vpr_arg);
926
927 static int __init tegra_tsec_arg(char *options)
928 {
929         char *p = options;
930
931         tegra_tsec_size = memparse(p, &p);
932         if (*p == '@')
933                 tegra_tsec_start = memparse(p+1, &p);
934         pr_info("Found tsec, start=0x%lx size=%lx",
935                 tegra_tsec_start, tegra_tsec_size);
936         return 0;
937 }
938 early_param("tsec", tegra_tsec_arg);
939
940 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
941 static int __init tegra_tzram_arg(char *options)
942 {
943         char *p = options;
944
945         tegra_tzram_size = memparse(p, &p);
946         if (*p == '@')
947                 tegra_tzram_start = memparse(p + 1, &p);
948         return 0;
949 }
950 early_param("tzram", tegra_tzram_arg);
951 #endif
952
953 #ifdef CONFIG_TEGRA_USE_NCT
954 static int __init tegra_nck_arg(char *options)
955 {
956         char *p = options;
957
958         tegra_nck_size = memparse(p, &p);
959         if (*p == '@')
960                 tegra_nck_start = memparse(p+1, &p);
961         if (!tegra_nck_size || !tegra_nck_start) {
962                 tegra_nck_size = 0;
963                 tegra_nck_start = 0;
964         }
965
966         return 0;
967 }
968 early_param("nck", tegra_nck_arg);
969 #endif  /* CONFIG_TEGRA_USE_NCT */
970
971 enum panel_type get_panel_type(void)
972 {
973         return board_panel_type;
974 }
975 static int __init tegra_board_panel_type(char *options)
976 {
977         if (!strcmp(options, "lvds"))
978                 board_panel_type = panel_type_lvds;
979         else if (!strcmp(options, "dsi"))
980                 board_panel_type = panel_type_dsi;
981         else
982                 return 0;
983         return 1;
984 }
985 __setup("panel=", tegra_board_panel_type);
986
987 int tegra_get_board_panel_id(void)
988 {
989         return panel_id;
990 }
991 static int __init tegra_board_panel_id(char *options)
992 {
993         char *p = options;
994         panel_id = memparse(p, &p);
995         return panel_id;
996 }
997 __setup("display_panel=", tegra_board_panel_id);
998
999 int tegra_get_touch_vendor_id(void)
1000 {
1001         return touch_vendor_id;
1002 }
1003 int tegra_get_touch_panel_id(void)
1004 {
1005         return touch_panel_id;
1006 }
1007 static int __init tegra_touch_id(char *options)
1008 {
1009         char *p = options;
1010         touch_vendor_id = memparse(p, &p);
1011         if (*p == '@')
1012                 touch_panel_id = memparse(p+1, &p);
1013         return 1;
1014 }
1015 __setup("touch_id=", tegra_touch_id);
1016
1017 u8 get_power_config(void)
1018 {
1019         return power_config;
1020 }
1021 static int __init tegra_board_power_config(char *options)
1022 {
1023         char *p = options;
1024         power_config = memparse(p, &p);
1025         return 1;
1026 }
1027 __setup("power-config=", tegra_board_power_config);
1028
1029 u8 get_display_config(void)
1030 {
1031         return display_config;
1032 }
1033 static int __init tegra_board_display_config(char *options)
1034 {
1035         char *p = options;
1036         display_config = memparse(p, &p);
1037         return 1;
1038 }
1039 __setup("display-config=", tegra_board_display_config);
1040
1041 enum power_supply_type get_power_supply_type(void)
1042 {
1043         return pow_supply_type;
1044 }
1045 static int __init tegra_board_power_supply_type(char *options)
1046 {
1047         if (!strcmp(options, "Adapter"))
1048                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1049         if (!strcmp(options, "Mains"))
1050                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1051         else if (!strcmp(options, "Battery"))
1052                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1053         else
1054                 return 0;
1055         return 1;
1056 }
1057 __setup("power_supply=", tegra_board_power_supply_type);
1058
1059 int get_core_edp(void)
1060 {
1061         return pmu_core_edp;
1062 }
1063 static int __init tegra_pmu_core_edp(char *options)
1064 {
1065         char *p = options;
1066         int core_edp = memparse(p, &p);
1067         if (core_edp != 0)
1068                 pmu_core_edp = core_edp;
1069         return 0;
1070 }
1071 early_param("core_edp_mv", tegra_pmu_core_edp);
1072
1073 int get_maximum_cpu_current_supported(void)
1074 {
1075         return max_cpu_current;
1076 }
1077 static int __init tegra_max_cpu_current(char *options)
1078 {
1079         char *p = options;
1080         max_cpu_current = memparse(p, &p);
1081         return 1;
1082 }
1083 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1084
1085 int get_maximum_core_current_supported(void)
1086 {
1087         return max_core_current;
1088 }
1089 static int __init tegra_max_core_current(char *options)
1090 {
1091         char *p = options;
1092         max_core_current = memparse(p, &p);
1093         return 1;
1094 }
1095 __setup("core_edp_ma=", tegra_max_core_current);
1096
1097 int get_emc_max_dvfs(void)
1098 {
1099         return emc_max_dvfs;
1100 }
1101 static int __init tegra_emc_max_dvfs(char *options)
1102 {
1103         char *p = options;
1104         emc_max_dvfs = memparse(p, &p);
1105         return 1;
1106 }
1107 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1108
1109 static int __init tegra_debug_uartport(char *info)
1110 {
1111         char *p = info;
1112         unsigned long long port_id;
1113         if (!strncmp(p, "hsport", 6))
1114                 is_tegra_debug_uart_hsport = true;
1115         else if (!strncmp(p, "lsport", 6))
1116                 is_tegra_debug_uart_hsport = false;
1117
1118         if (p[6] == ',') {
1119                 if (p[7] == '-') {
1120                         debug_uart_port_id = -1;
1121                 } else {
1122                         port_id = memparse(p + 7, &p);
1123                         debug_uart_port_id = (int) port_id;
1124                 }
1125         } else {
1126                 debug_uart_port_id = -1;
1127         }
1128
1129         return 1;
1130 }
1131
1132 bool is_tegra_debug_uartport_hs(void)
1133 {
1134         return is_tegra_debug_uart_hsport;
1135 }
1136
1137 int get_tegra_uart_debug_port_id(void)
1138 {
1139         return debug_uart_port_id;
1140 }
1141 __setup("debug_uartport=", tegra_debug_uartport);
1142
1143 static int __init tegra_image_type(char *options)
1144 {
1145         if (!strcmp(options, "RCK"))
1146                 board_image_type = rck_image;
1147
1148         return 0;
1149 }
1150
1151 enum image_type get_tegra_image_type(void)
1152 {
1153         return board_image_type;
1154 }
1155
1156 __setup("image=", tegra_image_type);
1157
1158 static int __init tegra_audio_codec_type(char *info)
1159 {
1160         char *p = info;
1161         if (!strncmp(p, "wm8903", 6))
1162                 audio_codec_name = audio_codec_wm8903;
1163         else
1164                 audio_codec_name = audio_codec_none;
1165
1166         return 1;
1167 }
1168
1169 enum audio_codec_type get_audio_codec_type(void)
1170 {
1171         return audio_codec_name;
1172 }
1173 __setup("audio_codec=", tegra_audio_codec_type);
1174
1175 static int tegra_get_pwr_i2c_clk_rate(char *options)
1176 {
1177         int clk = simple_strtol(options, NULL, 16);
1178         if (clk != 0)
1179                 pwr_i2c_clk = clk;
1180         return 0;
1181 }
1182
1183 int get_pwr_i2c_clk_rate(void)
1184 {
1185         return pwr_i2c_clk;
1186 }
1187 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1188
1189 static bool pmic_wdt_disable;
1190 bool is_pmic_wdt_disabled_at_boot(void)
1191 {
1192         return pmic_wdt_disable;
1193 }
1194
1195 static int parse_arg_pmic_wdt_disable(char *options)
1196 {
1197         /* no kernel command line argument "watchdog" interpreted as
1198          * watchdog enable
1199          */
1200         pmic_wdt_disable = false;
1201         if (!(strcmp(options, "enable")))
1202                 pmic_wdt_disable = false;
1203         else if (!(strcmp(options, "disable")))
1204                 pmic_wdt_disable = true;
1205         /* kernel command line from fastboot does not support
1206          * other values
1207          */
1208
1209         return 0;
1210 }
1211 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1212
1213 void tegra_get_board_info(struct board_info *bi)
1214 {
1215 #ifdef CONFIG_OF
1216         struct device_node *board_info;
1217         u32 prop_val;
1218         int err;
1219
1220         board_info = of_find_node_by_path("/chosen/board_info");
1221         if (!IS_ERR_OR_NULL(board_info)) {
1222                 memset(bi, 0, sizeof(*bi));
1223
1224                 err = of_property_read_u32(board_info, "id", &prop_val);
1225                 if (err)
1226                         pr_err("failed to read /chosen/board_info/id\n");
1227                 else
1228                         bi->board_id = prop_val;
1229
1230                 err = of_property_read_u32(board_info, "sku", &prop_val);
1231                 if (err)
1232                         pr_err("failed to read /chosen/board_info/sku\n");
1233                 else
1234                         bi->sku = prop_val;
1235
1236                 err = of_property_read_u32(board_info, "fab", &prop_val);
1237                 if (err)
1238                         pr_err("failed to read /chosen/board_info/fab\n");
1239                 else
1240                         bi->fab = prop_val;
1241
1242                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1243                 if (err)
1244                         pr_err("failed to read /chosen/board_info/major_revision\n");
1245                 else
1246                         bi->major_revision = prop_val;
1247
1248                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1249                 if (err)
1250                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1251                 else
1252                         bi->minor_revision = prop_val;
1253                 system_serial_high = (bi->board_id << 16) | bi->sku;
1254                 system_serial_low = (bi->fab << 24) |
1255                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1256         } else {
1257 #endif
1258                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1259                 bi->sku = (system_serial_high) & 0xFFFF;
1260                 bi->fab = (system_serial_low >> 24) & 0xFF;
1261                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1262                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1263 #ifdef CONFIG_OF
1264         }
1265 #endif
1266 }
1267
1268 static int __init tegra_pmu_board_info(char *info)
1269 {
1270         char *p = info;
1271         pmu_board_info.board_id = memparse(p, &p);
1272         pmu_board_info.sku = memparse(p+1, &p);
1273         pmu_board_info.fab = memparse(p+1, &p);
1274         pmu_board_info.major_revision = memparse(p+1, &p);
1275         pmu_board_info.minor_revision = memparse(p+1, &p);
1276         return 1;
1277 }
1278
1279 void tegra_get_pmu_board_info(struct board_info *bi)
1280 {
1281         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1282 }
1283
1284 __setup("pmuboard=", tegra_pmu_board_info);
1285
1286 static int __init tegra_display_board_info(char *info)
1287 {
1288         char *p = info;
1289         display_board_info.board_id = memparse(p, &p);
1290         display_board_info.sku = memparse(p+1, &p);
1291         display_board_info.fab = memparse(p+1, &p);
1292         display_board_info.major_revision = memparse(p+1, &p);
1293         display_board_info.minor_revision = memparse(p+1, &p);
1294         return 1;
1295 }
1296
1297 void tegra_get_display_board_info(struct board_info *bi)
1298 {
1299         memcpy(bi, &display_board_info, sizeof(struct board_info));
1300 }
1301
1302 __setup("displayboard=", tegra_display_board_info);
1303
1304 static int __init tegra_camera_board_info(char *info)
1305 {
1306         char *p = info;
1307         camera_board_info.board_id = memparse(p, &p);
1308         camera_board_info.sku = memparse(p+1, &p);
1309         camera_board_info.fab = memparse(p+1, &p);
1310         camera_board_info.major_revision = memparse(p+1, &p);
1311         camera_board_info.minor_revision = memparse(p+1, &p);
1312         return 1;
1313 }
1314
1315 void tegra_get_camera_board_info(struct board_info *bi)
1316 {
1317         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1318 }
1319
1320 __setup("cameraboard=", tegra_camera_board_info);
1321
1322 static int __init tegra_leftspeaker_board_info(char *info)
1323 {
1324         char *p = info;
1325         leftspeaker_board_info.board_id = memparse(p, &p);
1326         leftspeaker_board_info.sku = memparse(p+1, &p);
1327         leftspeaker_board_info.fab = memparse(p+1, &p);
1328         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1329         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1330         return 1;
1331 }
1332
1333 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1334 {
1335         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1336 }
1337
1338 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1339
1340 static int __init tegra_rightspeaker_board_info(char *info)
1341 {
1342         char *p = info;
1343         rightspeaker_board_info.board_id = memparse(p, &p);
1344         rightspeaker_board_info.sku = memparse(p+1, &p);
1345         rightspeaker_board_info.fab = memparse(p+1, &p);
1346         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1347         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1348         return 1;
1349 }
1350
1351 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1352 {
1353         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1354 }
1355
1356 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1357
1358 static int __init tegra_joystick_board_info(char *info)
1359 {
1360         char *p = info;
1361         joystick_board_info.board_id = memparse(p, &p);
1362         joystick_board_info.sku = memparse(p+1, &p);
1363         joystick_board_info.fab = memparse(p+1, &p);
1364         joystick_board_info.major_revision = memparse(p+1, &p);
1365         joystick_board_info.minor_revision = memparse(p+1, &p);
1366         return 1;
1367 }
1368
1369 void tegra_get_joystick_board_info(struct board_info *bi)
1370 {
1371         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1372 }
1373
1374 __setup("joystickboard=", tegra_joystick_board_info);
1375
1376 static int __init tegra_button_board_info(char *info)
1377 {
1378         char *p = info;
1379         button_board_info.board_id = memparse(p, &p);
1380         button_board_info.sku = memparse(p+1, &p);
1381         button_board_info.fab = memparse(p+1, &p);
1382         button_board_info.major_revision = memparse(p+1, &p);
1383         button_board_info.minor_revision = memparse(p+1, &p);
1384         return 1;
1385 }
1386
1387 void tegra_get_button_board_info(struct board_info *bi)
1388 {
1389         memcpy(bi, &button_board_info, sizeof(struct board_info));
1390 }
1391
1392 __setup("buttonboard=", tegra_button_board_info);
1393
1394 static int __init tegra_io_board_info(char *info)
1395 {
1396         char *p = info;
1397         io_board_info.board_id = memparse(p, &p);
1398         io_board_info.sku = memparse(p+1, &p);
1399         io_board_info.fab = memparse(p+1, &p);
1400         io_board_info.major_revision = memparse(p+1, &p);
1401         io_board_info.minor_revision = memparse(p+1, &p);
1402         return 1;
1403 }
1404
1405 void tegra_get_io_board_info(struct board_info *bi)
1406 {
1407         memcpy(bi, &io_board_info, sizeof(struct board_info));
1408 }
1409
1410 __setup("ioboard=", tegra_io_board_info);
1411
1412 static int __init tegra_modem_id(char *id)
1413 {
1414         char *p = id;
1415
1416         modem_id = memparse(p, &p);
1417         return 1;
1418 }
1419
1420 int tegra_get_modem_id(void)
1421 {
1422         return modem_id;
1423 }
1424
1425 __setup("modem_id=", tegra_modem_id);
1426
1427 static int __init tegra_usb_port_owner_info(char *id)
1428 {
1429         char *p = id;
1430
1431         usb_port_owner_info = memparse(p, &p);
1432         return 1;
1433 }
1434
1435 int tegra_get_usb_port_owner_info(void)
1436 {
1437         return usb_port_owner_info;
1438 }
1439
1440 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1441
1442 static int __init tegra_commchip_id(char *id)
1443 {
1444         char *p = id;
1445
1446         if (get_option(&p, &commchip_id) != 1)
1447                 return 0;
1448         return 1;
1449 }
1450
1451 int tegra_get_commchip_id(void)
1452 {
1453         return commchip_id;
1454 }
1455
1456 __setup("commchip_id=", tegra_commchip_id);
1457
1458 /*
1459  * Tegra has a protected aperture that prevents access by most non-CPU
1460  * memory masters to addresses above the aperture value.  Enabling it
1461  * secures the CPU's memory from the GPU, except through the GART.
1462  */
1463 void __init tegra_protected_aperture_init(unsigned long aperture)
1464 {
1465         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1466         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1467         writel(aperture, mc_base + MC_SECURITY_CFG2);
1468 }
1469
1470 /*
1471  * Due to conflicting restrictions on the placement of the framebuffer,
1472  * the bootloader is likely to leave the framebuffer pointed at a location
1473  * in memory that is outside the grhost aperture.  This function will move
1474  * the framebuffer contents from a physical address that is anywhere (lowmem,
1475  * highmem, or outside the memory map) to a physical address that is outside
1476  * the memory map.
1477  */
1478 void __tegra_move_framebuffer(struct platform_device *pdev,
1479         unsigned long to, unsigned long from,
1480         unsigned long size)
1481 {
1482         struct page *page;
1483         void __iomem *to_io;
1484         void *from_virt;
1485         unsigned long i, addr[] = { to, from, };
1486
1487         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1488         BUG_ON(PAGE_ALIGN(from) != from);
1489         BUG_ON(PAGE_ALIGN(size) != size);
1490
1491         to_io = ioremap(to, size);
1492         if (!to_io) {
1493                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1494                 return;
1495         }
1496
1497         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1498                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1499                         page = phys_to_page(from + i);
1500                         from_virt = kmap(page);
1501                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1502                         kunmap(page);
1503                 }
1504         } else {
1505                 void __iomem *from_io = ioremap(from, size);
1506                 if (!from_io) {
1507                         pr_err("%s: Failed to map source framebuffer\n",
1508                                 __func__);
1509                         goto out;
1510                 }
1511
1512                 for (i = 0; i < size; i += 4)
1513                         writel(readl(from_io + i), to_io + i);
1514
1515                 iounmap(from_io);
1516         }
1517
1518         if (!pdev)
1519                 goto out;
1520
1521         for (i = 0; i < ARRAY_SIZE(addr); i++)
1522                 dma_map_linear(&pdev->dev, addr[i], size, DMA_TO_DEVICE);
1523 out:
1524         iounmap(to_io);
1525 }
1526
1527 void __tegra_clear_framebuffer(struct platform_device *pdev,
1528                                unsigned long to, unsigned long size)
1529 {
1530         void __iomem *to_io;
1531         unsigned long i;
1532
1533         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1534         BUG_ON(PAGE_ALIGN(size) != size);
1535
1536         to_io = ioremap(to, size);
1537         if (!to_io) {
1538                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1539                 return;
1540         }
1541
1542         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1543                 for (i = 0 ; i < size; i += PAGE_SIZE)
1544                         memset(to_io + i, 0, PAGE_SIZE);
1545         } else {
1546                 for (i = 0; i < size; i += 4)
1547                         writel(0, to_io + i);
1548         }
1549
1550         if (!pdev)
1551                 goto out;
1552
1553         dma_map_linear(&pdev->dev, to, size, DMA_TO_DEVICE);
1554 out:
1555         iounmap(to_io);
1556 }
1557
1558 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1559         unsigned long fb2_size)
1560 {
1561         const size_t avp_kernel_reserve = SZ_32M;
1562 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1563         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1564         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1565         tegra_avp_kernel_size = SZ_1M;
1566         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1567         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1568                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1569                                 "from memory map\n",
1570                         (unsigned long)avp_kernel_reserve,
1571                         tegra_avp_kernel_start);
1572                 tegra_avp_kernel_size = 0;
1573         }
1574 #endif
1575
1576         if (carveout_size) {
1577                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1578                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1579                         pr_err("Failed to remove carveout %08lx@%08lx "
1580                                 "from memory map\n",
1581                                 carveout_size, tegra_carveout_start);
1582                         tegra_carveout_start = 0;
1583                         tegra_carveout_size = 0;
1584                 } else
1585                         tegra_carveout_size = carveout_size;
1586         }
1587
1588         if (fb2_size) {
1589                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1590                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1591                         pr_err("Failed to remove second framebuffer "
1592                                 "%08lx@%08lx from memory map\n",
1593                                 fb2_size, tegra_fb2_start);
1594                         tegra_fb2_start = 0;
1595                         tegra_fb2_size = 0;
1596                 } else
1597                         tegra_fb2_size = fb2_size;
1598         }
1599
1600         if (fb_size) {
1601                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1602                 if (memblock_remove(tegra_fb_start, fb_size)) {
1603                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1604                                 "from memory map\n",
1605                                 fb_size, tegra_fb_start);
1606                         tegra_fb_start = 0;
1607                         tegra_fb_size = 0;
1608                 } else
1609                         tegra_fb_size = fb_size;
1610         }
1611
1612         if (tegra_fb_size)
1613                 tegra_grhost_aperture = tegra_fb_start;
1614
1615         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1616                 tegra_grhost_aperture = tegra_fb2_start;
1617
1618         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1619                 tegra_grhost_aperture = tegra_carveout_start;
1620
1621         if (tegra_lp0_vec_size &&
1622            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1623                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1624                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1625                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1626                         tegra_lp0_vec_start = 0;
1627                         tegra_lp0_vec_size = 0;
1628                 }
1629                 tegra_lp0_vec_relocate = false;
1630         } else
1631                 tegra_lp0_vec_relocate = true;
1632
1633 #ifdef CONFIG_TEGRA_NVDUMPER
1634         if (nvdumper_reserved) {
1635                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1636                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1637                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1638                         nvdumper_reserved = 0;
1639                 }
1640         }
1641 #endif
1642
1643 #ifdef CONFIG_TEGRA_USE_NCT
1644         if (tegra_nck_size &&
1645            (tegra_nck_start < memblock_end_of_DRAM())) {
1646                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
1647                         pr_err("Failed to reserve nck %08lx@%08lx\n",
1648                                 tegra_nck_size, tegra_nck_start);
1649                         tegra_nck_start = 0;
1650                         tegra_nck_size = 0;
1651                 }
1652         }
1653 #endif
1654
1655         /*
1656          * We copy the bootloader's framebuffer to the framebuffer allocated
1657          * above, and then free this one.
1658          * */
1659         if (tegra_bootloader_fb_size) {
1660                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1661                 if (memblock_reserve(tegra_bootloader_fb_start,
1662                                 tegra_bootloader_fb_size)) {
1663                         pr_err("Failed to reserve bootloader frame buffer "
1664                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1665                                 tegra_bootloader_fb_start);
1666                         tegra_bootloader_fb_start = 0;
1667                         tegra_bootloader_fb_size = 0;
1668                 }
1669         }
1670
1671         if (tegra_bootloader_fb2_size) {
1672                 tegra_bootloader_fb2_size =
1673                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1674                 if (memblock_reserve(tegra_bootloader_fb2_start,
1675                                 tegra_bootloader_fb2_size)) {
1676                         pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
1677                                 tegra_bootloader_fb2_size,
1678                                 tegra_bootloader_fb2_start);
1679                         tegra_bootloader_fb2_start = 0;
1680                         tegra_bootloader_fb2_size = 0;
1681                 }
1682         }
1683
1684         pr_info("Tegra reserved memory:\n"
1685                 "LP0:                    %08lx - %08lx\n"
1686                 "Bootloader framebuffer: %08lx - %08lx\n"
1687                 "Bootloader framebuffer2: %08lx - %08lx\n"
1688                 "Framebuffer:            %08lx - %08lx\n"
1689                 "2nd Framebuffer:        %08lx - %08lx\n"
1690                 "Carveout:               %08lx - %08lx\n"
1691                 "Vpr:                    %08lx - %08lx\n"
1692                 "Tsec:                   %08lx - %08lx\n",
1693                 tegra_lp0_vec_start,
1694                 tegra_lp0_vec_size ?
1695                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1696                 tegra_bootloader_fb_start,
1697                 tegra_bootloader_fb_size ?
1698                  tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
1699                 tegra_bootloader_fb2_start,
1700                 tegra_bootloader_fb2_size ?
1701                  tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
1702                 tegra_fb_start,
1703                 tegra_fb_size ?
1704                         tegra_fb_start + tegra_fb_size - 1 : 0,
1705                 tegra_fb2_start,
1706                 tegra_fb2_size ?
1707                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1708                 tegra_carveout_start,
1709                 tegra_carveout_size ?
1710                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1711                 tegra_vpr_start,
1712                 tegra_vpr_size ?
1713                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1714                 tegra_tsec_start,
1715                 tegra_tsec_size ?
1716                 tegra_tsec_start + tegra_tsec_size - 1 : 0);
1717
1718         if (tegra_avp_kernel_size) {
1719                 /* Return excessive memory reserved for AVP kernel */
1720                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1721                         memblock_add(
1722                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1723                                 avp_kernel_reserve - tegra_avp_kernel_size);
1724                 pr_info(
1725                 "AVP kernel: %08lx - %08lx\n",
1726                         tegra_avp_kernel_start,
1727                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1728         }
1729
1730 #ifdef CONFIG_TEGRA_NVDUMPER
1731         if (nvdumper_reserved) {
1732                 pr_info("Nvdumper:               %08lx - %08lx\n",
1733                         nvdumper_reserved,
1734                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1735         }
1736 #endif
1737
1738 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1739         pr_info("Tzram:               %08lx - %08lx\n",
1740                 tegra_tzram_start,
1741                 tegra_tzram_size ?
1742                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
1743 #endif
1744
1745 #ifdef CONFIG_TEGRA_USE_NCT
1746         if (tegra_nck_size) {
1747                 pr_info("Nck:                    %08lx - %08lx\n",
1748                         tegra_nck_start,
1749                         tegra_nck_size ?
1750                                 tegra_nck_start + tegra_nck_size - 1 : 0);
1751         }
1752 #endif
1753 }
1754
1755 #ifdef CONFIG_PSTORE_RAM
1756 static struct persistent_ram_descriptor desc = {
1757         .name = "ramoops",
1758 };
1759
1760 static struct persistent_ram ram = {
1761         .descs = &desc,
1762         .num_descs = 1,
1763 };
1764
1765 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1766 {
1767         int ret;
1768
1769         ram.start = memblock_end_of_DRAM() - ram_console_size;
1770         ram.size = ram_console_size;
1771         ram.descs->size = ram_console_size;
1772
1773         INIT_LIST_HEAD(&ram.node);
1774
1775         ret = persistent_ram_early_init(&ram);
1776         if (ret)
1777                 goto fail;
1778
1779         return;
1780
1781 fail:
1782         pr_err("Failed to reserve memory block for ram console\n");
1783 }
1784 #endif
1785
1786 int __init tegra_register_fuse(void)
1787 {
1788         return platform_device_register(&tegra_fuse_device);
1789 }
1790
1791 void __init tegra_release_bootloader_fb(void)
1792 {
1793         /* Since bootloader fb is reserved in common.c, it is freed here. */
1794         if (tegra_bootloader_fb_size) {
1795                 if (memblock_free(tegra_bootloader_fb_start,
1796                                                 tegra_bootloader_fb_size))
1797                         pr_err("Failed to free bootloader fb.\n");
1798                 else
1799                         free_bootmem_late(tegra_bootloader_fb_start,
1800                                                 tegra_bootloader_fb_size);
1801         }
1802         if (tegra_bootloader_fb2_size) {
1803                 if (memblock_free(tegra_bootloader_fb2_start,
1804                                                 tegra_bootloader_fb2_size))
1805                         pr_err("Failed to free bootloader fb2.\n");
1806                 else
1807                         free_bootmem_late(tegra_bootloader_fb2_start,
1808                                                 tegra_bootloader_fb2_size);
1809         }
1810 }
1811
1812 static struct platform_device *pinmux_devices[] = {
1813         &tegra_gpio_device,
1814         &tegra_pinmux_device,
1815 };
1816
1817 void tegra_enable_pinmux(void)
1818 {
1819         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1820 }
1821
1822 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1823         [TEGRA_REVISION_UNKNOWN] = "unknown",
1824         [TEGRA_REVISION_A01]     = "A01",
1825         [TEGRA_REVISION_A02]     = "A02",
1826         [TEGRA_REVISION_A03]     = "A03",
1827         [TEGRA_REVISION_A03p]    = "A03 prime",
1828         [TEGRA_REVISION_A04]     = "A04",
1829         [TEGRA_REVISION_A04p]    = "A04 prime",
1830 };
1831
1832 static const char * __init tegra_get_revision(void)
1833 {
1834         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1835 }
1836
1837 static const char * __init tegra_get_family(void)
1838 {
1839         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1840         u32 cid = readl(chip_id);
1841         cid = (cid >> 8) & 0xFF;
1842
1843         switch (cid) {
1844         case TEGRA_CHIPID_TEGRA2:
1845                 cid = 2;
1846                 break;
1847         case TEGRA_CHIPID_TEGRA3:
1848                 cid = 3;
1849                 break;
1850         case TEGRA_CHIPID_TEGRA11:
1851                 cid = 11;
1852                 break;
1853         case TEGRA_CHIPID_TEGRA14:
1854                 cid = 14;
1855                 break;
1856
1857         case TEGRA_CHIPID_UNKNOWN:
1858         default:
1859                 cid = 0;
1860         }
1861         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1862 }
1863
1864 static const char * __init tegra_get_soc_id(void)
1865 {
1866         int package_id = tegra_package_id();
1867         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1868                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1869 }
1870
1871 static void __init tegra_soc_info_populate(struct soc_device_attribute
1872         *soc_dev_attr, const char *machine)
1873 {
1874         soc_dev_attr->soc_id = tegra_get_soc_id();
1875         soc_dev_attr->machine  = machine;
1876         soc_dev_attr->family   = tegra_get_family();
1877         soc_dev_attr->revision = tegra_get_revision();
1878 }
1879
1880 int __init tegra_soc_device_init(const char *machine)
1881 {
1882         struct soc_device *soc_dev;
1883         struct soc_device_attribute *soc_dev_attr;
1884
1885         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1886         if (!soc_dev_attr)
1887                 return -ENOMEM;
1888
1889         tegra_soc_info_populate(soc_dev_attr, machine);
1890
1891         soc_dev = soc_device_register(soc_dev_attr);
1892         if (IS_ERR_OR_NULL(soc_dev)) {
1893                 kfree(soc_dev_attr);
1894                 return -1;
1895         }
1896
1897         return 0;
1898 }
1899
1900 void __init tegra_init_late(void)
1901 {
1902 #ifndef CONFIG_COMMON_CLK
1903         tegra_clk_debugfs_init();
1904 #endif
1905         tegra_powergate_debugfs_init();
1906 }
1907
1908 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
1909 #define ASIM_SHUTDOWN_REG       0x538f0ffc
1910
1911 static void asim_power_off(void)
1912 {
1913         pr_err("ASIM Powering off the device\n");
1914         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
1915         while (1)
1916                 ;
1917 }
1918
1919 static int __init asim_power_off_init(void)
1920 {
1921         if (tegra_cpu_is_asim())
1922                 pm_power_off = asim_power_off;
1923         return 0;
1924 }
1925
1926 arch_initcall(asim_power_off_init);
1927
1928 #if defined(CONFIG_SMC91X)
1929 static struct resource tegra_asim_smc91x_resources[] = {
1930         [0] = {
1931                 .start          = TEGRA_SIM_ETH_BASE,
1932                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
1933                 .flags          = IORESOURCE_MEM,
1934         },
1935         [1] = {
1936                 .start          = IRQ_ETH,
1937                 .end            = IRQ_ETH,
1938                 .flags          = IORESOURCE_IRQ,
1939         },
1940 };
1941
1942 static struct platform_device tegra_asim_smc91x_device = {
1943         .name           = "smc91x",
1944         .id             = 0,
1945         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
1946         .resource       = tegra_asim_smc91x_resources,
1947 };
1948
1949 static int __init asim_enet_init(void)
1950 {
1951         if (tegra_cpu_is_asim())
1952                 platform_device_register(&tegra_asim_smc91x_device);
1953         return 0;
1954 }
1955
1956 rootfs_initcall(asim_enet_init);
1957 #endif
1958
1959 #endif