ARM: tegra11: clock: Change XUSB HS clock source
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36
37 #include <linux/export.h>
38 #include <linux/bootmem.h>
39 #include <trace/events/nvsecurity.h>
40
41 #include <asm/hardware/cache-l2x0.h>
42 #include <asm/system.h>
43 #include <asm/dma-mapping.h>
44
45 #include <mach/hardware.h>
46 #include <mach/powergate.h>
47 #include <mach/tegra_smmu.h>
48 #include <mach/gpio-tegra.h>
49
50 #include "apbio.h"
51 #include "board.h"
52 #include "clock.h"
53 #include "common.h"
54 #include "dvfs.h"
55 #include "fuse.h"
56 #include "iomap.h"
57 #include "pm.h"
58 #include "sleep.h"
59 #include "reset.h"
60 #include "devices.h"
61 #include "pmc.h"
62
63 #define MC_SECURITY_CFG2        0x7c
64
65 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
66 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
67 #define   PRIORITY_SELECT_USB   BIT(6)
68 #define PRIORITY_SELECT_SDMMC4  BIT(12)
69 #define   PRIORITY_SELECT_USB2  BIT(18)
70 #define   PRIORITY_SELECT_USB3  BIT(17)
71 #define   PRIORITY_SELECT_SE BIT(14)
72
73 #define AHB_GIZMO_AHB_MEM               0xc
74 #define   ENB_FAST_REARBITRATE  BIT(2)
75 #define   DONT_SPLIT_AHB_WR     BIT(7)
76
77 #define   RECOVERY_MODE BIT(31)
78 #define   BOOTLOADER_MODE       BIT(30)
79 #define   FORCED_RECOVERY_MODE  BIT(1)
80
81 #define AHB_GIZMO_USB           0x1c
82 #define AHB_GIZMO_SDMMC4        0x44
83 #define AHB_GIZMO_USB2          0x78
84 #define AHB_GIZMO_USB3          0x7c
85 #define AHB_GIZMO_SE            0x4c
86 #define   IMMEDIATE     BIT(18)
87
88 #define AHB_MEM_PREFETCH_CFG5   0xc8
89 #define AHB_MEM_PREFETCH_CFG3   0xe0
90 #define AHB_MEM_PREFETCH_CFG4   0xe4
91 #define AHB_MEM_PREFETCH_CFG1   0xec
92 #define AHB_MEM_PREFETCH_CFG2   0xf0
93 #define AHB_MEM_PREFETCH_CFG6   0xcc
94 #define   PREFETCH_ENB  BIT(31)
95 #define   MST_ID(x)     (((x) & 0x1f) << 26)
96 #define   AHBDMA_MST_ID MST_ID(5)
97 #define   USB_MST_ID    MST_ID(6)
98 #define SDMMC4_MST_ID   MST_ID(12)
99 #define   USB2_MST_ID   MST_ID(18)
100 #define   USB3_MST_ID   MST_ID(17)
101 #define   SE_MST_ID     MST_ID(14)
102 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
103 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
104
105 unsigned long tegra_avp_kernel_start;
106 unsigned long tegra_avp_kernel_size;
107 unsigned long tegra_bootloader_fb_start;
108 unsigned long tegra_bootloader_fb_size;
109 unsigned long tegra_bootloader_fb2_start;
110 unsigned long tegra_bootloader_fb2_size;
111 unsigned long tegra_fb_start;
112 unsigned long tegra_fb_size;
113 unsigned long tegra_fb2_start;
114 unsigned long tegra_fb2_size;
115 unsigned long tegra_carveout_start;
116 unsigned long tegra_carveout_size;
117 unsigned long tegra_vpr_start;
118 unsigned long tegra_vpr_size;
119 unsigned long tegra_tsec_start;
120 unsigned long tegra_tsec_size;
121 unsigned long tegra_lp0_vec_start;
122 unsigned long tegra_lp0_vec_size;
123 #ifdef CONFIG_TEGRA_NVDUMPER
124 unsigned long nvdumper_reserved;
125 #endif
126 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
127 unsigned long tegra_tzram_start;
128 unsigned long tegra_tzram_size;
129 #endif
130 bool tegra_lp0_vec_relocate;
131 unsigned long tegra_grhost_aperture = ~0ul;
132 static   bool is_tegra_debug_uart_hsport;
133 static struct board_info pmu_board_info;
134 static struct board_info display_board_info;
135 static int panel_id;
136 static struct board_info camera_board_info;
137 static int touch_id;
138
139 static int pmu_core_edp;
140 static int board_panel_type;
141 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
142 static int pwr_i2c_clk = 400;
143 static u8 power_config;
144 /*
145  * Storage for debug-macro.S's state.
146  *
147  * This must be in .data not .bss so that it gets initialized each time the
148  * kernel is loaded. The data is declared here rather than debug-macro.S so
149  * that multiple inclusions of debug-macro.S point at the same data.
150  */
151 u32 tegra_uart_config[4] = {
152         /* Debug UART initialization required */
153         1,
154         /* Debug UART physical address */
155         0,
156         /* Debug UART virtual address */
157         0,
158         /* Scratch space for debug macro */
159         0,
160 };
161
162
163 #define NEVER_RESET 0
164
165 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
166 {
167         unsigned long check;
168         int retry = 10;
169
170         /* Read and check if write is successful,
171          * if val doesn't match with read, retry write.
172          */
173         do {
174                 writel(val, reg);
175                 check = readl(reg);
176                 if (likely(check == val))
177                         break;
178                 else
179                         pr_err("AHB register access fail for reg\n");
180         } while (--retry);
181 }
182
183 void tegra_assert_system_reset(char mode, const char *cmd)
184 {
185 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
186         pr_info("tegra_assert_system_reset() ignored.....");
187         do { } while (1);
188 #else
189         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
190         u32 reg;
191
192         reg = readl_relaxed(reset + PMC_SCRATCH0);
193         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
194         if (cmd) {
195                 if (!strcmp(cmd, "recovery"))
196                         reg |= RECOVERY_MODE;
197                 else if (!strcmp(cmd, "bootloader"))
198                         reg |= BOOTLOADER_MODE;
199                 else if (!strcmp(cmd, "forced-recovery"))
200                         reg |= FORCED_RECOVERY_MODE;
201                 else
202                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
203         }
204         else {
205                 /* Clearing SCRATCH0 31:30:1 on default reboot */
206                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
207         }
208         writel_relaxed(reg, reset + PMC_SCRATCH0);
209         reg = readl_relaxed(reset);
210         reg |= 0x10;
211         writel_relaxed(reg, reset);
212 #endif
213 }
214 static int modem_id;
215 static int commchip_id;
216 static int sku_override;
217 static int debug_uart_port_id;
218 static enum audio_codec_type audio_codec_name;
219 static enum image_type board_image_type = system_image;
220 static int max_cpu_current;
221 static int max_core_current;
222 static int emc_max_dvfs;
223 static int usb_port_owner_info;
224
225 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
226 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
227         /* name         parent          rate            enabled */
228         { "clk_m",      NULL,           0,              true },
229         { "emc",        NULL,           0,              true },
230         { "cpu",        NULL,           0,              true },
231         { "kfuse",      NULL,           0,              true },
232         { "fuse",       NULL,           0,              true },
233         { "sclk",       NULL,           0,              true },
234         { "pll_p",      NULL,           0,              true },
235         { "pll_p_out1", "pll_p",        0,              false },
236         { "pll_p_out3", "pll_p",        0,              false },
237 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
238         { "pll_m_out1", "pll_m",        275000000,      false },
239         { "pll_p_out2",  "pll_p",       102000000,      false },
240         { "sclk",        "pll_p_out2",  102000000,      true },
241         { "pll_p_out4",  "pll_p",       204000000,      true },
242         { "hclk",       "sclk",         102000000,      true },
243         { "pclk",       "hclk",         51000000,       true },
244         { "mselect",    "pll_p",        102000000,      true },
245         { "host1x",     "pll_p",        102000000,      false },
246         { "cl_dvfs_ref", "pll_p",       51000000,       true },
247         { "cl_dvfs_soc", "pll_p",       51000000,       true },
248 #else
249         { "pll_m_out1", "pll_m",        275000000,      true },
250         { "pll_p_out2", "pll_p",        108000000,      false },
251         { "sclk",       "pll_p_out2",   108000000,      true },
252         { "pll_p_out4", "pll_p",        216000000,      true },
253         { "hclk",       "sclk",         108000000,      true },
254         { "pclk",       "hclk",         54000000,       true },
255         { "mselect",    "pll_p",        108000000,      true },
256         { "host1x",     "pll_p",        108000000,      false },
257         { "cl_dvfs_ref", "clk_m",       13000000,       false },
258         { "cl_dvfs_soc", "clk_m",       13000000,       false },
259 #endif
260 #ifdef CONFIG_TEGRA_SLOW_CSITE
261         { "csite",      "clk_m",        1000000,        true },
262 #else
263         { "csite",      NULL,           0,              true },
264 #endif
265         { "pll_u",      NULL,           480000000,      true },
266         { "pll_re_vco", NULL,           672000000,      false },
267         { "xusb_falcon_src",    "pll_re_vco",   224000000,      false},
268         { "xusb_host_src",      "pll_re_vco",   112000000,      false},
269         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
270         { "xusb_hs_src",        "xusb_ss_div2", 60000000,       false},
271         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
272         { "sdmmc1",     "pll_p",        48000000,       false},
273         { "sdmmc3",     "pll_p",        48000000,       false},
274         { "sdmmc4",     "pll_p",        48000000,       false},
275         { "sbc1.sclk",  NULL,           40000000,       false},
276         { "sbc2.sclk",  NULL,           40000000,       false},
277         { "sbc3.sclk",  NULL,           40000000,       false},
278         { "sbc4.sclk",  NULL,           40000000,       false},
279         { "sbc5.sclk",  NULL,           40000000,       false},
280         { "sbc6.sclk",  NULL,           40000000,       false},
281 #ifdef CONFIG_TEGRA_PLLM_SCALED
282         { "vi",         "pll_p",        0,              false},
283 #endif
284 #ifdef CONFIG_TEGRA_SOCTHERM
285         { "soc_therm",  "pll_p",        51000000,       false },
286         { "tsensor",    "clk_m",        500000,         false },
287 #endif
288         { NULL,         NULL,           0,              0},
289 };
290 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
291 #ifdef CONFIG_TEGRA_DUAL_CBUS
292         { "c2bus",      "pll_c2",       250000000,      false },
293         { "c3bus",      "pll_c3",       250000000,      false },
294         { "pll_c",      NULL,           624000000,      false },
295 #else
296         { "cbus",       "pll_c",        250000000,      false },
297 #endif
298         { "pll_c_out1", "pll_c",        150000000,      false },
299         { NULL,         NULL,           0,              0},
300 };
301 #endif
302 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
303 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
304         /* name         parent          rate            enabled */
305         { "osc",        NULL,           0,              true },
306         { "clk_m",      "osc",          0,              true },
307         { "emc",        NULL,           0,              true },
308         { "cpu",        NULL,           0,              true },
309         { "kfuse",      NULL,           0,              true },
310         { "fuse",       NULL,           0,              true },
311         { "sclk",       NULL,           0,              true },
312 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
313         { "pll_p",      NULL,           0,              true },
314         { "pll_p_out1", "pll_p",        0,              false },
315         { "pll_p_out3", "pll_p",        0,              true },
316         { "pll_m_out1", "pll_m",        275000000,      false },
317         { "pll_p_out2",  "pll_p",       102000000,      false },
318         { "sclk",        "pll_p_out2",  102000000,      true },
319         { "pll_p_out4",  "pll_p",       204000000,      true },
320         { "hclk",       "sclk",         102000000,      true },
321         { "pclk",       "hclk",         51000000,       true },
322         { "mselect",    "pll_p",        102000000,      true },
323         { "host1x",     "pll_p",        102000000,      false },
324         { "cl_dvfs_ref", "pll_p",       51000000,       true },
325         { "cl_dvfs_soc", "pll_p",       51000000,       true },
326 #else
327         { "pll_p",      NULL,           0,              true },
328         { "pll_p_out1", "pll_p",        0,              false },
329         { "pll_p_out3", "pll_p",        0,              true },
330         { "pll_m_out1", "pll_m",        275000000,      true },
331         { "pll_p_out2", "pll_p",        108000000,      false },
332         { "sclk",       "pll_p_out2",   108000000,      true },
333         { "pll_p_out4", "pll_p",        216000000,      true },
334         { "host1x",     "pll_p",        108000000,      false },
335         { "cl_dvfs_ref", "clk_m",       13000000,       false },
336         { "cl_dvfs_soc", "clk_m",       13000000,       false },
337         { "hclk",       "sclk",         108000000,      true },
338         { "pclk",       "hclk",         54000000,       true },
339         { "wake.sclk",  NULL,           250000000,      true },
340         { "mselect",    "pll_p",        108000000,      true },
341 #endif
342 #ifdef CONFIG_TEGRA_SLOW_CSITE
343         { "csite",      "clk_m",        1000000,        true },
344 #else
345         { "csite",      NULL,           0,              true },
346 #endif
347         { "pll_u",      NULL,           480000000,      false },
348         { "sdmmc1",     "pll_p",        48000000,       false},
349         { "sdmmc3",     "pll_p",        48000000,       false},
350         { "sdmmc4",     "pll_p",        48000000,       false},
351         { "sbc1.sclk",  NULL,           40000000,       false},
352         { "sbc2.sclk",  NULL,           40000000,       false},
353         { "sbc3.sclk",  NULL,           40000000,       false},
354         { "msenc",      "pll_p",        108000000,      false },
355         { "tsec",       "pll_p",        108000000,      false },
356         { "mc_capa",    "emc",          0,              true },
357         { "mc_cbpa",    "emc",          0,              true },
358 #ifdef CONFIG_TEGRA_SOCTHERM
359         { "soc_therm",  "pll_p",        51000000,       false },
360         { "tsensor",    "clk_m",        400000,         false },
361 #endif
362         { NULL,         NULL,           0,              0},
363 };
364 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
365         /* Initialize c2bus, c3bus, or cbus at the end of the list
366          * after all the clocks are moved under the proper parents.
367          */
368 #ifdef CONFIG_TEGRA_DUAL_CBUS
369         { "c2bus",      "pll_c2",       200000000,      false },
370         { "c3bus",      "pll_c3",       200000000,      false },
371         { "pll_c",      NULL,           768000000,      false },
372 #else
373         { "cbus",       "pll_c",        200000000,      false },
374 #endif
375         { "pll_c_out1", "pll_c",        100000000,      false },
376         { NULL,         NULL,           0,              0},
377 };
378 #endif
379
380 #ifdef CONFIG_CACHE_L2X0
381 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
382 static void tegra_cache_smc(bool enable, u32 arg)
383 {
384         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
385         bool need_affinity_switch;
386         bool can_switch_affinity;
387         bool l2x0_enabled;
388         cpumask_t local_cpu_mask;
389         cpumask_t saved_cpu_mask;
390         unsigned long flags;
391         long ret;
392
393         /*
394          * ISSUE : Some registers of PL310 controler must be written
395          *              from Secure context (and from CPU0)!
396          *
397          * When called form Normal we obtain an abort or do nothing.
398          * Instructions that must be called in Secure:
399          *      - Write to Control register (L2X0_CTRL==0x100)
400          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
401          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
402          *              mandatory at boot time.
403          *      - Tag and Data RAM Latency Control Registers
404          *              (0x108 & 0x10C) must be written in Secure.
405          */
406         need_affinity_switch = (smp_processor_id() != 0);
407         can_switch_affinity = !irqs_disabled();
408
409         WARN_ON(need_affinity_switch && !can_switch_affinity);
410         if (need_affinity_switch && can_switch_affinity) {
411                 cpu_set(0, local_cpu_mask);
412                 sched_getaffinity(0, &saved_cpu_mask);
413                 ret = sched_setaffinity(0, &local_cpu_mask);
414                 WARN_ON(ret != 0);
415         }
416
417         local_irq_save(flags);
418         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
419         if (enable && !l2x0_enabled)
420                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
421         else if (!enable && l2x0_enabled)
422                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
423         local_irq_restore(flags);
424
425         if (need_affinity_switch && can_switch_affinity) {
426                 ret = sched_setaffinity(0, &saved_cpu_mask);
427                 WARN_ON(ret != 0);
428         }
429 }
430
431 static void tegra_l2x0_disable(void)
432 {
433         unsigned long flags;
434         static u32 l2x0_way_mask;
435
436         if (!l2x0_way_mask) {
437                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
438                 u32 aux_ctrl;
439                 u32 ways;
440
441                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
442                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
443                 l2x0_way_mask = (1 << ways) - 1;
444         }
445
446         local_irq_save(flags);
447         tegra_cache_smc(false, l2x0_way_mask);
448         local_irq_restore(flags);
449 }
450 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
451
452 void tegra_init_cache(bool init)
453 {
454         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
455         u32 aux_ctrl;
456 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
457         u32 cache_type;
458         u32 tag_latency, data_latency;
459 #endif
460
461 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
462         /* issue the SMC to enable the L2 */
463         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
464         trace_smc_init_cache(NVSEC_SMC_START);
465         tegra_cache_smc(true, aux_ctrl);
466         trace_smc_init_cache(NVSEC_SMC_DONE);
467
468         /* after init, reread aux_ctrl and register handlers */
469         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
470         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
471
472         /* override outer_disable() with our disable */
473         outer_cache.disable = tegra_l2x0_disable;
474 #else
475 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
476         tag_latency = 0x331;
477         data_latency = 0x441;
478 #else
479 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
480         if (is_lp_cluster()) {
481                 tag_latency = tegra_cpu_c1_l2_tag_latency;
482                 data_latency = tegra_cpu_c1_l2_data_latency;
483         } else {
484                 tag_latency = tegra_cpu_c0_l2_tag_latency;
485                 data_latency = tegra_cpu_c0_l2_data_latency;
486         }
487 #else
488         tag_latency = 0x770;
489         data_latency = 0x770;
490 #endif
491 #endif
492         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
493         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
494
495 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
496 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
497 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
498         /* Enable double line fill */
499         writel(0x40000007, p + L2X0_PREFETCH_CTRL);
500 #else
501         writel(0x7, p + L2X0_PREFETCH_CTRL);
502 #endif
503         writel(0x3, p + L2X0_POWER_CTRL);
504 #endif
505 #endif
506         cache_type = readl(p + L2X0_CACHE_TYPE);
507         aux_ctrl = (cache_type & 0x700) << (17-8);
508         aux_ctrl |= 0x7C400001;
509         if (init) {
510                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
511         } else {
512                 u32 tmp;
513
514                 tmp = aux_ctrl;
515                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
516                 aux_ctrl &= 0x8200c3fe;
517                 aux_ctrl |= tmp;
518                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
519         }
520         l2x0_enable();
521 #endif
522 }
523 #endif
524
525 static void __init tegra_perf_init(void)
526 {
527         u32 reg;
528
529         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
530         reg >>= 11;
531         reg = (1 << (reg & 0x1f))-1;
532         reg |= 0x80000000;
533         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
534         reg = 1;
535         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
536 }
537
538 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
539 static void __init tegra_ramrepair_init(void)
540 {
541         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
542                 u32 reg;
543                 reg = readl(FLOW_CTRL_RAM_REPAIR);
544                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
545                 writel(reg, FLOW_CTRL_RAM_REPAIR);
546         }
547 }
548 #endif
549
550 static void __init tegra_init_power(void)
551 {
552 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
553         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
554 #endif
555 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
556         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
557 #endif
558 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
559         /* some partitions need to be powergated by default for t11x */
560         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
561         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
562         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
563 #endif
564 }
565
566 static inline unsigned long gizmo_readl(unsigned long offset)
567 {
568         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
569 }
570
571 static inline void gizmo_writel(unsigned long value, unsigned long offset)
572 {
573         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
574 }
575
576 static void __init tegra_init_ahb_gizmo_settings(void)
577 {
578         unsigned long val;
579
580         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
581         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
582         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
583
584         val = gizmo_readl(AHB_GIZMO_USB);
585         val |= IMMEDIATE;
586         gizmo_writel(val, AHB_GIZMO_USB);
587
588         val = gizmo_readl(AHB_GIZMO_USB2);
589         val |= IMMEDIATE;
590         gizmo_writel(val, AHB_GIZMO_USB2);
591
592         val = gizmo_readl(AHB_GIZMO_USB3);
593         val |= IMMEDIATE;
594         gizmo_writel(val, AHB_GIZMO_USB3);
595
596 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
597         val = gizmo_readl(AHB_GIZMO_SE);
598         val |= IMMEDIATE;
599         gizmo_writel(val, AHB_GIZMO_SE);
600 #endif
601
602         /*
603          * SDMMC controller is removed from AHB interface in T124 and
604          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
605          * in T11x and T14x SOCs.
606          */
607 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
608         val = gizmo_readl(AHB_GIZMO_SDMMC4);
609         val |= IMMEDIATE;
610         gizmo_writel(val, AHB_GIZMO_SDMMC4);
611 #endif
612
613         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
614         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
615                                 | AHB_PRIORITY_WEIGHT(7);
616 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
617         val |= PRIORITY_SELECT_SE;
618 #endif
619
620 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
621         val |= PRIORITY_SELECT_SDMMC4;
622 #endif
623         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
624
625         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
626         val &= ~MST_ID(~0);
627         val |= PREFETCH_ENB | AHBDMA_MST_ID |
628                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
629         ahb_gizmo_writel(val,
630                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
631
632         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
633         val &= ~MST_ID(~0);
634         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
635                 INACTIVITY_TIMEOUT(0x1000);
636 #if !defined(CONFIG_ANDROID)
637         val &= ~USB_MST_ID;
638 #endif
639         ahb_gizmo_writel(val,
640                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
641
642         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
643         val &= ~MST_ID(~0);
644         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
645                 INACTIVITY_TIMEOUT(0x1000);
646 #if !defined(CONFIG_ANDROID)
647         val &= ~USB3_MST_ID;
648 #endif
649         ahb_gizmo_writel(val,
650                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
651
652         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
653         val &= ~MST_ID(~0);
654         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
655                 INACTIVITY_TIMEOUT(0x1000);
656         ahb_gizmo_writel(val,
657                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
658
659         /*
660          * SDMMC controller is removed from AHB interface in T124 and
661          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
662          * in T11x and T14x SOCs.
663          */
664 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
665         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
666         val &= ~MST_ID(~0);
667         val |= PREFETCH_ENB | SDMMC4_MST_ID | ADDR_BNDRY(0xc) |
668                 INACTIVITY_TIMEOUT(0x1000);
669         val &= ~SDMMC4_MST_ID;
670         ahb_gizmo_writel(val,
671                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
672 #endif
673
674 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
675         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
676         val &= ~MST_ID(~0);
677         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
678                 INACTIVITY_TIMEOUT(0x1000);
679         ahb_gizmo_writel(val,
680                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
681 #endif
682 }
683
684 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
685 void __init tegra20_init_early(void)
686 {
687 #ifndef CONFIG_SMP
688         /* For SMP system, initializing the reset handler here is too
689            late. For non-SMP systems, the function that calls the reset
690            handler initializer is not called, so do it here for non-SMP. */
691         tegra_cpu_reset_handler_init();
692 #endif
693         tegra_apb_io_init();
694         tegra_perf_init();
695         tegra_init_fuse();
696         tegra_init_cache(true);
697         tegra_pmc_init();
698         tegra_powergate_init();
699         tegra20_hotplug_init();
700         tegra_init_power();
701         tegra_init_ahb_gizmo_settings();
702         tegra_init_debug_uart_rate();
703         tegra_gpio_resume_init();
704         tegra_ram_console_debug_reserve(SZ_1M);
705 }
706 #endif
707 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
708 void __init tegra30_init_early(void)
709 {
710         u32 speedo;
711         u32 tag_latency, data_latency;
712
713 #ifndef CONFIG_SMP
714         /* For SMP system, initializing the reset handler here is too
715            late. For non-SMP systems, the function that calls the reset
716            handler initializer is not called, so do it here for non-SMP. */
717         tegra_cpu_reset_handler_init();
718 #endif
719         tegra_apb_io_init();
720         tegra_perf_init();
721         tegra_init_fuse();
722         /*
723          * Store G/LP cluster L2 latencies to IRAM and DRAM
724          */
725         tegra_cpu_c1_l2_tag_latency = 0x221;
726         tegra_cpu_c1_l2_data_latency = 0x221;
727         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
728         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
729         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
730         speedo = tegra_cpu_speedo_id();
731         if (speedo == 4 || speedo == 5 || speedo == 6 ||
732             speedo == 12 || speedo == 13) {
733                 tag_latency = 0x442;
734                 data_latency = 0x552;
735         } else {
736                 tag_latency = 0x441;
737                 data_latency = 0x551;
738         }
739         tegra_cpu_c0_l2_tag_latency = tag_latency;
740         tegra_cpu_c0_l2_data_latency = data_latency;
741         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
742         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
743         tegra_init_cache(true);
744         tegra_pmc_init();
745         tegra_powergate_init();
746         tegra30_hotplug_init();
747         tegra_init_power();
748         tegra_init_ahb_gizmo_settings();
749         tegra_init_debug_uart_rate();
750         tegra_gpio_resume_init();
751         tegra_ram_console_debug_reserve(SZ_1M);
752
753         init_dma_coherent_pool_size(SZ_1M);
754 }
755 #endif
756 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
757 void __init tegra11x_init_early(void)
758 {
759 #ifndef CONFIG_SMP
760         /* For SMP system, initializing the reset handler here is too
761            late. For non-SMP systems, the function that calls the reset
762            handler initializer is not called, so do it here for non-SMP. */
763         tegra_cpu_reset_handler_init();
764 #endif
765         tegra_apb_io_init();
766         tegra_perf_init();
767         tegra_init_fuse();
768         tegra_ramrepair_init();
769         tegra11x_init_clocks();
770         tegra11x_init_dvfs();
771         tegra_common_init_clock();
772         tegra_clk_init_from_table(tegra11x_clk_init_table);
773         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
774         tegra11x_clk_init_la();
775         tegra_pmc_init();
776         tegra_powergate_init();
777         tegra30_hotplug_init();
778         tegra_init_power();
779         tegra_init_ahb_gizmo_settings();
780         tegra_init_debug_uart_rate();
781         tegra_gpio_resume_init();
782
783         init_dma_coherent_pool_size(SZ_2M);
784 }
785 #endif
786 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
787 void __init tegra14x_init_early(void)
788 {
789 #ifndef CONFIG_SMP
790         /* For SMP system, initializing the reset handler here is too
791            late. For non-SMP systems, the function that calls the reset
792            handler initializer is not called, so do it here for non-SMP. */
793         tegra_cpu_reset_handler_init();
794 #endif
795         tegra_apb_io_init();
796         tegra_perf_init();
797         tegra_init_fuse();
798         tegra_ramrepair_init();
799         tegra14x_init_clocks();
800         tegra14x_init_dvfs();
801         tegra_common_init_clock();
802         tegra_clk_init_from_table(tegra14x_clk_init_table);
803         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
804         tegra_cpu_c1_l2_tag_latency = 0x110;
805         tegra_cpu_c1_l2_data_latency = 0x331;
806         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
807         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
808         tegra_cpu_c0_l2_tag_latency = 0x111;
809         tegra_cpu_c0_l2_data_latency = 0x441;
810         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
811         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
812         tegra_init_cache(true);
813         tegra_pmc_init();
814         tegra_powergate_init();
815         tegra30_hotplug_init();
816         tegra_init_power();
817         tegra_init_ahb_gizmo_settings();
818         tegra_init_debug_uart_rate();
819         tegra_gpio_resume_init();
820         tegra_ram_console_debug_reserve(SZ_1M);
821 }
822 #endif
823 static int __init tegra_lp0_vec_arg(char *options)
824 {
825         char *p = options;
826
827         tegra_lp0_vec_size = memparse(p, &p);
828         if (*p == '@')
829                 tegra_lp0_vec_start = memparse(p+1, &p);
830         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
831                 tegra_lp0_vec_size = 0;
832                 tegra_lp0_vec_start = 0;
833         }
834
835         return 0;
836 }
837 early_param("lp0_vec", tegra_lp0_vec_arg);
838
839 #ifdef CONFIG_TEGRA_NVDUMPER
840 static int __init tegra_nvdumper_arg(char *options)
841 {
842         char *p = options;
843
844         nvdumper_reserved = memparse(p, &p);
845         return 0;
846 }
847 early_param("nvdumper_reserved", tegra_nvdumper_arg);
848 #endif
849
850 static int __init tegra_bootloader_fb_arg(char *options)
851 {
852         char *p = options;
853
854         tegra_bootloader_fb_size = memparse(p, &p);
855         if (*p == '@')
856                 tegra_bootloader_fb_start = memparse(p+1, &p);
857
858         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
859                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
860
861         return 0;
862 }
863 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
864
865 static int __init tegra_bootloader_fb2_arg(char *options)
866 {
867         char *p = options;
868
869         tegra_bootloader_fb2_size = memparse(p, &p);
870         if (*p == '@')
871                 tegra_bootloader_fb2_start = memparse(p+1, &p);
872
873         pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
874                 tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
875
876         return 0;
877 }
878 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
879
880 static int __init tegra_sku_override(char *id)
881 {
882         char *p = id;
883
884         sku_override = memparse(p, &p);
885
886         return 0;
887 }
888 early_param("sku_override", tegra_sku_override);
889
890 int tegra_get_sku_override(void)
891 {
892         return sku_override;
893 }
894
895 static int __init tegra_vpr_arg(char *options)
896 {
897         char *p = options;
898
899         tegra_vpr_size = memparse(p, &p);
900         if (*p == '@')
901                 tegra_vpr_start = memparse(p+1, &p);
902         pr_info("Found vpr, start=0x%lx size=%lx",
903                 tegra_vpr_start, tegra_vpr_size);
904         return 0;
905 }
906 early_param("vpr", tegra_vpr_arg);
907
908 static int __init tegra_tsec_arg(char *options)
909 {
910         char *p = options;
911
912         tegra_tsec_size = memparse(p, &p);
913         if (*p == '@')
914                 tegra_tsec_start = memparse(p+1, &p);
915         pr_info("Found tsec, start=0x%lx size=%lx",
916                 tegra_tsec_start, tegra_tsec_size);
917         return 0;
918 }
919 early_param("tsec", tegra_tsec_arg);
920
921 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
922 static int __init tegra_tzram_arg(char *options)
923 {
924         char *p = options;
925
926         tegra_tzram_size = memparse(p, &p);
927         if (*p == '@')
928                 tegra_tzram_start = memparse(p + 1, &p);
929         return 0;
930 }
931 early_param("tzram", tegra_tzram_arg);
932 #endif
933
934 enum panel_type get_panel_type(void)
935 {
936         return board_panel_type;
937 }
938 static int __init tegra_board_panel_type(char *options)
939 {
940         if (!strcmp(options, "lvds"))
941                 board_panel_type = panel_type_lvds;
942         else if (!strcmp(options, "dsi"))
943                 board_panel_type = panel_type_dsi;
944         else
945                 return 0;
946         return 1;
947 }
948 __setup("panel=", tegra_board_panel_type);
949
950 int tegra_get_board_panel_id(void)
951 {
952         return panel_id;
953 }
954 static int __init tegra_board_panel_id(char *options)
955 {
956         char *p = options;
957         panel_id = memparse(p, &p);
958         return panel_id;
959 }
960 __setup("display_panel=", tegra_board_panel_id);
961
962 int tegra_get_touch_id(void)
963 {
964         return touch_id;
965 }
966 static int __init tegra_touch_id(char *options)
967 {
968         char *p = options;
969         touch_id = memparse(p, &p);
970         return touch_id;
971 }
972 __setup("touch_type=", tegra_touch_id);
973
974
975 u8 get_power_config(void)
976 {
977         return power_config;
978 }
979 static int __init tegra_board_power_config(char *options)
980 {
981         char *p = options;
982         power_config = memparse(p, &p);
983         return 1;
984 }
985 __setup("power-config=", tegra_board_power_config);
986
987 enum power_supply_type get_power_supply_type(void)
988 {
989         return pow_supply_type;
990 }
991 static int __init tegra_board_power_supply_type(char *options)
992 {
993         if (!strcmp(options, "Adapter"))
994                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
995         if (!strcmp(options, "Mains"))
996                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
997         else if (!strcmp(options, "Battery"))
998                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
999         else
1000                 return 0;
1001         return 1;
1002 }
1003 __setup("power_supply=", tegra_board_power_supply_type);
1004
1005 int get_core_edp(void)
1006 {
1007         return pmu_core_edp;
1008 }
1009 static int __init tegra_pmu_core_edp(char *options)
1010 {
1011         char *p = options;
1012         int core_edp = memparse(p, &p);
1013         if (core_edp != 0)
1014                 pmu_core_edp = core_edp;
1015         return 0;
1016 }
1017 early_param("core_edp_mv", tegra_pmu_core_edp);
1018
1019 int get_maximum_cpu_current_supported(void)
1020 {
1021         return max_cpu_current;
1022 }
1023 static int __init tegra_max_cpu_current(char *options)
1024 {
1025         char *p = options;
1026         max_cpu_current = memparse(p, &p);
1027         return 1;
1028 }
1029 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1030
1031 int get_maximum_core_current_supported(void)
1032 {
1033         return max_core_current;
1034 }
1035 static int __init tegra_max_core_current(char *options)
1036 {
1037         char *p = options;
1038         max_core_current = memparse(p, &p);
1039         return 1;
1040 }
1041 __setup("core_edp_ma=", tegra_max_core_current);
1042
1043 int get_emc_max_dvfs(void)
1044 {
1045         return emc_max_dvfs;
1046 }
1047 static int __init tegra_emc_max_dvfs(char *options)
1048 {
1049         char *p = options;
1050         emc_max_dvfs = memparse(p, &p);
1051         return 1;
1052 }
1053 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1054
1055 static int __init tegra_debug_uartport(char *info)
1056 {
1057         char *p = info;
1058         unsigned long long port_id;
1059         if (!strncmp(p, "hsport", 6))
1060                 is_tegra_debug_uart_hsport = true;
1061         else if (!strncmp(p, "lsport", 6))
1062                 is_tegra_debug_uart_hsport = false;
1063
1064         if (p[6] == ',') {
1065                 if (p[7] == '-') {
1066                         debug_uart_port_id = -1;
1067                 } else {
1068                         port_id = memparse(p + 7, &p);
1069                         debug_uart_port_id = (int) port_id;
1070                 }
1071         } else {
1072                 debug_uart_port_id = -1;
1073         }
1074
1075         return 1;
1076 }
1077
1078 bool is_tegra_debug_uartport_hs(void)
1079 {
1080         return is_tegra_debug_uart_hsport;
1081 }
1082
1083 int get_tegra_uart_debug_port_id(void)
1084 {
1085         return debug_uart_port_id;
1086 }
1087 __setup("debug_uartport=", tegra_debug_uartport);
1088
1089 static int __init tegra_image_type(char *options)
1090 {
1091         if (!strcmp(options, "RCK"))
1092                 board_image_type = rck_image;
1093
1094         return 0;
1095 }
1096
1097 enum image_type get_tegra_image_type(void)
1098 {
1099         return board_image_type;
1100 }
1101
1102 __setup("image=", tegra_image_type);
1103
1104 static int __init tegra_audio_codec_type(char *info)
1105 {
1106         char *p = info;
1107         if (!strncmp(p, "wm8903", 6))
1108                 audio_codec_name = audio_codec_wm8903;
1109         else
1110                 audio_codec_name = audio_codec_none;
1111
1112         return 1;
1113 }
1114
1115 enum audio_codec_type get_audio_codec_type(void)
1116 {
1117         return audio_codec_name;
1118 }
1119 __setup("audio_codec=", tegra_audio_codec_type);
1120
1121 static int tegra_get_pwr_i2c_clk_rate(char *options)
1122 {
1123         int clk = simple_strtol(options, NULL, 16);
1124         if (clk != 0)
1125                 pwr_i2c_clk = clk;
1126         return 0;
1127 }
1128
1129 int get_pwr_i2c_clk_rate(void)
1130 {
1131         return pwr_i2c_clk;
1132 }
1133 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1134
1135 void tegra_get_board_info(struct board_info *bi)
1136 {
1137 #ifdef CONFIG_OF
1138         struct device_node *board_info;
1139         u32 prop_val;
1140         int err;
1141
1142         board_info = of_find_node_by_path("/chosen/board_info");
1143         if (!IS_ERR_OR_NULL(board_info)) {
1144                 memset(bi, 0, sizeof(*bi));
1145
1146                 err = of_property_read_u32(board_info, "id", &prop_val);
1147                 if (err)
1148                         pr_err("failed to read /chosen/board_info/id\n");
1149                 else
1150                         bi->board_id = prop_val;
1151
1152                 err = of_property_read_u32(board_info, "sku", &prop_val);
1153                 if (err)
1154                         pr_err("failed to read /chosen/board_info/sku\n");
1155                 else
1156                         bi->sku = prop_val;
1157
1158                 err = of_property_read_u32(board_info, "fab", &prop_val);
1159                 if (err)
1160                         pr_err("failed to read /chosen/board_info/fab\n");
1161                 else
1162                         bi->fab = prop_val;
1163
1164                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1165                 if (err)
1166                         pr_err("failed to read /chosen/board_info/major_revision\n");
1167                 else
1168                         bi->major_revision = prop_val;
1169
1170                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1171                 if (err)
1172                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1173                 else
1174                         bi->minor_revision = prop_val;
1175                 system_serial_high = (bi->board_id << 16) | bi->sku;
1176                 system_serial_low = (bi->fab << 24) |
1177                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1178         } else {
1179 #endif
1180                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1181                 bi->sku = (system_serial_high) & 0xFFFF;
1182                 bi->fab = (system_serial_low >> 24) & 0xFF;
1183                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1184                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1185 #ifdef CONFIG_OF
1186         }
1187 #endif
1188 }
1189
1190 static int __init tegra_pmu_board_info(char *info)
1191 {
1192         char *p = info;
1193         pmu_board_info.board_id = memparse(p, &p);
1194         pmu_board_info.sku = memparse(p+1, &p);
1195         pmu_board_info.fab = memparse(p+1, &p);
1196         pmu_board_info.major_revision = memparse(p+1, &p);
1197         pmu_board_info.minor_revision = memparse(p+1, &p);
1198         return 1;
1199 }
1200
1201 void tegra_get_pmu_board_info(struct board_info *bi)
1202 {
1203         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1204 }
1205
1206 __setup("pmuboard=", tegra_pmu_board_info);
1207
1208 static int __init tegra_display_board_info(char *info)
1209 {
1210         char *p = info;
1211         display_board_info.board_id = memparse(p, &p);
1212         display_board_info.sku = memparse(p+1, &p);
1213         display_board_info.fab = memparse(p+1, &p);
1214         display_board_info.major_revision = memparse(p+1, &p);
1215         display_board_info.minor_revision = memparse(p+1, &p);
1216         return 1;
1217 }
1218
1219 void tegra_get_display_board_info(struct board_info *bi)
1220 {
1221         memcpy(bi, &display_board_info, sizeof(struct board_info));
1222 }
1223
1224 __setup("displayboard=", tegra_display_board_info);
1225
1226 static int __init tegra_camera_board_info(char *info)
1227 {
1228         char *p = info;
1229         camera_board_info.board_id = memparse(p, &p);
1230         camera_board_info.sku = memparse(p+1, &p);
1231         camera_board_info.fab = memparse(p+1, &p);
1232         camera_board_info.major_revision = memparse(p+1, &p);
1233         camera_board_info.minor_revision = memparse(p+1, &p);
1234         return 1;
1235 }
1236
1237 void tegra_get_camera_board_info(struct board_info *bi)
1238 {
1239         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1240 }
1241
1242 __setup("cameraboard=", tegra_camera_board_info);
1243
1244 static int __init tegra_modem_id(char *id)
1245 {
1246         char *p = id;
1247
1248         modem_id = memparse(p, &p);
1249         return 1;
1250 }
1251
1252 int tegra_get_modem_id(void)
1253 {
1254         return modem_id;
1255 }
1256
1257 __setup("modem_id=", tegra_modem_id);
1258
1259 static int __init tegra_usb_port_owner_info(char *id)
1260 {
1261         char *p = id;
1262
1263         usb_port_owner_info = memparse(p, &p);
1264         return 1;
1265 }
1266
1267 int tegra_get_usb_port_owner_info(void)
1268 {
1269         return usb_port_owner_info;
1270 }
1271
1272 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1273
1274 static int __init tegra_commchip_id(char *id)
1275 {
1276         char *p = id;
1277
1278         if (get_option(&p, &commchip_id) != 1)
1279                 return 0;
1280         return 1;
1281 }
1282
1283 int tegra_get_commchip_id(void)
1284 {
1285         return commchip_id;
1286 }
1287
1288 __setup("commchip_id=", tegra_commchip_id);
1289
1290 /*
1291  * Tegra has a protected aperture that prevents access by most non-CPU
1292  * memory masters to addresses above the aperture value.  Enabling it
1293  * secures the CPU's memory from the GPU, except through the GART.
1294  */
1295 void __init tegra_protected_aperture_init(unsigned long aperture)
1296 {
1297 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
1298         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1299         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1300         writel(aperture, mc_base + MC_SECURITY_CFG2);
1301 #else
1302         pr_err("Tegra protected aperture disabled because nvmap is using "
1303                 "system memory\n");
1304 #endif
1305 }
1306
1307 /*
1308  * Due to conflicting restrictions on the placement of the framebuffer,
1309  * the bootloader is likely to leave the framebuffer pointed at a location
1310  * in memory that is outside the grhost aperture.  This function will move
1311  * the framebuffer contents from a physical address that is anywhere (lowmem,
1312  * highmem, or outside the memory map) to a physical address that is outside
1313  * the memory map.
1314  */
1315 void __tegra_move_framebuffer(struct platform_device *pdev,
1316         unsigned long to, unsigned long from,
1317         unsigned long size)
1318 {
1319         struct page *page;
1320         void __iomem *to_io;
1321         void *from_virt;
1322         unsigned long i, addr[] = { to, from, };
1323
1324         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1325         BUG_ON(PAGE_ALIGN(from) != from);
1326         BUG_ON(PAGE_ALIGN(size) != size);
1327
1328         to_io = ioremap(to, size);
1329         if (!to_io) {
1330                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1331                 return;
1332         }
1333
1334         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1335                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1336                         page = phys_to_page(from + i);
1337                         from_virt = kmap(page);
1338                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1339                         kunmap(page);
1340                 }
1341         } else {
1342                 void __iomem *from_io = ioremap(from, size);
1343                 if (!from_io) {
1344                         pr_err("%s: Failed to map source framebuffer\n",
1345                                 __func__);
1346                         goto out;
1347                 }
1348
1349                 for (i = 0; i < size; i += 4)
1350                         writel(readl(from_io + i), to_io + i);
1351
1352                 iounmap(from_io);
1353         }
1354
1355         if (!pdev)
1356                 goto out;
1357
1358         for (i = 0; i < ARRAY_SIZE(addr); i++)
1359                 dma_map_linear(&pdev->dev, addr[i], size, DMA_TO_DEVICE);
1360 out:
1361         iounmap(to_io);
1362 }
1363
1364 void __tegra_clear_framebuffer(struct platform_device *pdev,
1365                                unsigned long to, unsigned long size)
1366 {
1367         void __iomem *to_io;
1368         unsigned long i;
1369
1370         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1371         BUG_ON(PAGE_ALIGN(size) != size);
1372
1373         to_io = ioremap(to, size);
1374         if (!to_io) {
1375                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1376                 return;
1377         }
1378
1379         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1380                 for (i = 0 ; i < size; i += PAGE_SIZE)
1381                         memset(to_io + i, 0, PAGE_SIZE);
1382         } else {
1383                 for (i = 0; i < size; i += 4)
1384                         writel(0, to_io + i);
1385         }
1386
1387         if (!pdev)
1388                 goto out;
1389
1390         dma_map_linear(&pdev->dev, to, size, DMA_TO_DEVICE);
1391 out:
1392         iounmap(to_io);
1393 }
1394
1395 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1396         unsigned long fb2_size)
1397 {
1398         const size_t avp_kernel_reserve = SZ_32M;
1399 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1400         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1401         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1402         tegra_avp_kernel_size = SZ_1M;
1403         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1404         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1405                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1406                                 "from memory map\n",
1407                         (unsigned long)avp_kernel_reserve,
1408                         tegra_avp_kernel_start);
1409                 tegra_avp_kernel_size = 0;
1410         }
1411 #endif
1412
1413         if (carveout_size) {
1414                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1415                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1416                         pr_err("Failed to remove carveout %08lx@%08lx "
1417                                 "from memory map\n",
1418                                 carveout_size, tegra_carveout_start);
1419                         tegra_carveout_start = 0;
1420                         tegra_carveout_size = 0;
1421                 } else
1422                         tegra_carveout_size = carveout_size;
1423         }
1424
1425         if (fb2_size) {
1426                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1427                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1428                         pr_err("Failed to remove second framebuffer "
1429                                 "%08lx@%08lx from memory map\n",
1430                                 fb2_size, tegra_fb2_start);
1431                         tegra_fb2_start = 0;
1432                         tegra_fb2_size = 0;
1433                 } else
1434                         tegra_fb2_size = fb2_size;
1435         }
1436
1437         if (fb_size) {
1438                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1439                 if (memblock_remove(tegra_fb_start, fb_size)) {
1440                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1441                                 "from memory map\n",
1442                                 fb_size, tegra_fb_start);
1443                         tegra_fb_start = 0;
1444                         tegra_fb_size = 0;
1445                 } else
1446                         tegra_fb_size = fb_size;
1447         }
1448
1449         if (tegra_fb_size)
1450                 tegra_grhost_aperture = tegra_fb_start;
1451
1452         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1453                 tegra_grhost_aperture = tegra_fb2_start;
1454
1455         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1456                 tegra_grhost_aperture = tegra_carveout_start;
1457
1458         if (tegra_lp0_vec_size &&
1459            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1460                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1461                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1462                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1463                         tegra_lp0_vec_start = 0;
1464                         tegra_lp0_vec_size = 0;
1465                 }
1466                 tegra_lp0_vec_relocate = false;
1467         } else
1468                 tegra_lp0_vec_relocate = true;
1469
1470 #ifdef CONFIG_TEGRA_NVDUMPER
1471         if (nvdumper_reserved) {
1472                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1473                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1474                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1475                         nvdumper_reserved = 0;
1476                 }
1477         }
1478 #endif
1479
1480         /*
1481          * We copy the bootloader's framebuffer to the framebuffer allocated
1482          * above, and then free this one.
1483          * */
1484         if (tegra_bootloader_fb_size) {
1485                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1486                 if (memblock_reserve(tegra_bootloader_fb_start,
1487                                 tegra_bootloader_fb_size)) {
1488                         pr_err("Failed to reserve bootloader frame buffer "
1489                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1490                                 tegra_bootloader_fb_start);
1491                         tegra_bootloader_fb_start = 0;
1492                         tegra_bootloader_fb_size = 0;
1493                 }
1494         }
1495
1496         if (tegra_bootloader_fb2_size) {
1497                 tegra_bootloader_fb2_size =
1498                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1499                 if (memblock_reserve(tegra_bootloader_fb2_start,
1500                                 tegra_bootloader_fb2_size)) {
1501                         pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
1502                                 tegra_bootloader_fb2_size,
1503                                 tegra_bootloader_fb2_start);
1504                         tegra_bootloader_fb2_start = 0;
1505                         tegra_bootloader_fb2_size = 0;
1506                 }
1507         }
1508
1509         pr_info("Tegra reserved memory:\n"
1510                 "LP0:                    %08lx - %08lx\n"
1511                 "Bootloader framebuffer: %08lx - %08lx\n"
1512                 "Bootloader framebuffer2: %08lx - %08lx\n"
1513                 "Framebuffer:            %08lx - %08lx\n"
1514                 "2nd Framebuffer:        %08lx - %08lx\n"
1515                 "Carveout:               %08lx - %08lx\n"
1516                 "Vpr:                    %08lx - %08lx\n"
1517                 "Tsec:                   %08lx - %08lx\n",
1518                 tegra_lp0_vec_start,
1519                 tegra_lp0_vec_size ?
1520                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1521                 tegra_bootloader_fb_start,
1522                 tegra_bootloader_fb_size ?
1523                  tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
1524                 tegra_bootloader_fb2_start,
1525                 tegra_bootloader_fb2_size ?
1526                  tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
1527                 tegra_fb_start,
1528                 tegra_fb_size ?
1529                         tegra_fb_start + tegra_fb_size - 1 : 0,
1530                 tegra_fb2_start,
1531                 tegra_fb2_size ?
1532                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1533                 tegra_carveout_start,
1534                 tegra_carveout_size ?
1535                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1536                 tegra_vpr_start,
1537                 tegra_vpr_size ?
1538                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1539                 tegra_tsec_start,
1540                 tegra_tsec_size ?
1541                 tegra_tsec_start + tegra_tsec_size - 1 : 0);
1542
1543         if (tegra_avp_kernel_size) {
1544                 /* Return excessive memory reserved for AVP kernel */
1545                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1546                         memblock_add(
1547                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1548                                 avp_kernel_reserve - tegra_avp_kernel_size);
1549                 pr_info(
1550                 "AVP kernel: %08lx - %08lx\n",
1551                         tegra_avp_kernel_start,
1552                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1553         }
1554
1555 #ifdef CONFIG_TEGRA_NVDUMPER
1556         if (nvdumper_reserved) {
1557                 pr_info("Nvdumper:               %08lx - %08lx\n",
1558                         nvdumper_reserved,
1559                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1560         }
1561 #endif
1562
1563 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1564         pr_info("Tzram:               %08lx - %08lx\n",
1565                 tegra_tzram_start,
1566                 tegra_tzram_size ?
1567                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
1568 #endif
1569 }
1570
1571 #ifdef CONFIG_PSTORE_RAM
1572 static struct persistent_ram_descriptor desc = {
1573         .name = "ramoops",
1574 };
1575
1576 static struct persistent_ram ram = {
1577         .descs = &desc,
1578         .num_descs = 1,
1579 };
1580
1581 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1582 {
1583         int ret;
1584
1585         ram.start = memblock_end_of_DRAM() - ram_console_size;
1586         ram.size = ram_console_size;
1587         ram.descs->size = ram_console_size;
1588
1589         INIT_LIST_HEAD(&ram.node);
1590
1591         ret = persistent_ram_early_init(&ram);
1592         if (ret)
1593                 goto fail;
1594
1595         return;
1596
1597 fail:
1598         pr_err("Failed to reserve memory block for ram console\n");
1599 }
1600 #endif
1601
1602 int __init tegra_register_fuse(void)
1603 {
1604         return platform_device_register(&tegra_fuse_device);
1605 }
1606
1607 void __init tegra_release_bootloader_fb(void)
1608 {
1609         /* Since bootloader fb is reserved in common.c, it is freed here. */
1610         if (tegra_bootloader_fb_size) {
1611                 if (memblock_free(tegra_bootloader_fb_start,
1612                                                 tegra_bootloader_fb_size))
1613                         pr_err("Failed to free bootloader fb.\n");
1614                 else
1615                         free_bootmem_late(tegra_bootloader_fb_start,
1616                                                 tegra_bootloader_fb_size);
1617         }
1618         if (tegra_bootloader_fb2_size) {
1619                 if (memblock_free(tegra_bootloader_fb2_start,
1620                                                 tegra_bootloader_fb2_size))
1621                         pr_err("Failed to free bootloader fb2.\n");
1622                 else
1623                         free_bootmem_late(tegra_bootloader_fb2_start,
1624                                                 tegra_bootloader_fb2_size);
1625         }
1626 }
1627
1628 static struct platform_device *pinmux_devices[] = {
1629         &tegra_gpio_device,
1630         &tegra_pinmux_device,
1631 };
1632
1633 void tegra_enable_pinmux(void)
1634 {
1635         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1636 }
1637
1638 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1639         [TEGRA_REVISION_UNKNOWN] = "unknown",
1640         [TEGRA_REVISION_A01]     = "A01",
1641         [TEGRA_REVISION_A02]     = "A02",
1642         [TEGRA_REVISION_A03]     = "A03",
1643         [TEGRA_REVISION_A03p]    = "A03 prime",
1644         [TEGRA_REVISION_A04]     = "A04",
1645         [TEGRA_REVISION_A04p]    = "A04 prime",
1646 };
1647
1648 static const char * __init tegra_get_revision(void)
1649 {
1650         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1651 }
1652
1653 static const char * __init tegra_get_family(void)
1654 {
1655         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1656         u32 cid = readl(chip_id);
1657         cid = (cid >> 8) & 0xFF;
1658
1659         switch (cid) {
1660         case TEGRA_CHIPID_TEGRA2:
1661                 cid = 2;
1662                 break;
1663         case TEGRA_CHIPID_TEGRA3:
1664                 cid = 3;
1665                 break;
1666         case TEGRA_CHIPID_TEGRA11:
1667                 cid = 11;
1668                 break;
1669         case TEGRA_CHIPID_TEGRA14:
1670                 cid = 14;
1671                 break;
1672
1673         case TEGRA_CHIPID_UNKNOWN:
1674         default:
1675                 cid = 0;
1676         }
1677         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1678 }
1679
1680 static const char * __init tegra_get_soc_id(void)
1681 {
1682         int package_id = tegra_package_id();
1683         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1684                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1685 }
1686
1687 static void __init tegra_soc_info_populate(struct soc_device_attribute
1688         *soc_dev_attr, const char *machine)
1689 {
1690         soc_dev_attr->soc_id = tegra_get_soc_id();
1691         soc_dev_attr->machine  = machine;
1692         soc_dev_attr->family   = tegra_get_family();
1693         soc_dev_attr->revision = tegra_get_revision();
1694 }
1695
1696 int __init tegra_soc_device_init(const char *machine)
1697 {
1698         struct soc_device *soc_dev;
1699         struct soc_device_attribute *soc_dev_attr;
1700
1701         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1702         if (!soc_dev_attr)
1703                 return -ENOMEM;
1704
1705         tegra_soc_info_populate(soc_dev_attr, machine);
1706
1707         soc_dev = soc_device_register(soc_dev_attr);
1708         if (IS_ERR_OR_NULL(soc_dev)) {
1709                 kfree(soc_dev_attr);
1710                 return -1;
1711         }
1712
1713         return 0;
1714 }
1715
1716 void __init tegra_init_late(void)
1717 {
1718 #ifndef CONFIG_COMMON_CLK
1719         tegra_clk_debugfs_init();
1720 #endif
1721         tegra_powergate_debugfs_init();
1722 }
1723
1724 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
1725 #define ASIM_SHUTDOWN_REG       0x538f0ffc
1726
1727 static void asim_power_off(void)
1728 {
1729         pr_err("ASIM Powering off the device\n");
1730         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
1731         while (1)
1732                 ;
1733 }
1734
1735 static int __init asim_power_off_init(void)
1736 {
1737         if (tegra_cpu_is_asim())
1738                 pm_power_off = asim_power_off;
1739         return 0;
1740 }
1741
1742 arch_initcall(asim_power_off_init);
1743
1744 #if defined(CONFIG_SMC91X)
1745 static struct resource tegra_asim_smc91x_resources[] = {
1746         [0] = {
1747                 .start          = TEGRA_SIM_ETH_BASE,
1748                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
1749                 .flags          = IORESOURCE_MEM,
1750         },
1751         [1] = {
1752                 .start          = IRQ_ETH,
1753                 .end            = IRQ_ETH,
1754                 .flags          = IORESOURCE_IRQ,
1755         },
1756 };
1757
1758 static struct platform_device tegra_asim_smc91x_device = {
1759         .name           = "smc91x",
1760         .id             = 0,
1761         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
1762         .resource       = tegra_asim_smc91x_resources,
1763 };
1764
1765 static int __init asim_enet_init(void)
1766 {
1767         if (tegra_cpu_is_asim())
1768                 platform_device_register(&tegra_asim_smc91x_device);
1769         return 0;
1770 }
1771
1772 rootfs_initcall(asim_enet_init);
1773 #endif
1774
1775 #endif