ARM: tegra14: clock: Fix order in clk_init_table
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36
37 #include <trace/events/nvsecurity.h>
38
39 #include <asm/hardware/cache-l2x0.h>
40 #include <asm/system.h>
41 #include <asm/dma-mapping.h>
42
43 #include <mach/hardware.h>
44 #include <mach/powergate.h>
45 #include <mach/tegra_smmu.h>
46 #include <mach/gpio-tegra.h>
47
48 #include "apbio.h"
49 #include "board.h"
50 #include "clock.h"
51 #include "common.h"
52 #include "dvfs.h"
53 #include "fuse.h"
54 #include "iomap.h"
55 #include "pm.h"
56 #include "sleep.h"
57 #include "reset.h"
58 #include "devices.h"
59 #include "pmc.h"
60
61 #define MC_SECURITY_CFG2        0x7c
62
63 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
64 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
65 #define   PRIORITY_SELECT_USB   BIT(6)
66 #define PRIORITY_SELECT_SDMMC4  BIT(12)
67 #define   PRIORITY_SELECT_USB2  BIT(18)
68 #define   PRIORITY_SELECT_USB3  BIT(17)
69 #define   PRIORITY_SELECT_SE BIT(14)
70
71 #define AHB_GIZMO_AHB_MEM               0xc
72 #define   ENB_FAST_REARBITRATE  BIT(2)
73 #define   DONT_SPLIT_AHB_WR     BIT(7)
74
75 #define   RECOVERY_MODE BIT(31)
76 #define   BOOTLOADER_MODE       BIT(30)
77 #define   FORCED_RECOVERY_MODE  BIT(1)
78
79 #define AHB_GIZMO_USB           0x1c
80 #define AHB_GIZMO_SDMMC4        0x44
81 #define AHB_GIZMO_USB2          0x78
82 #define AHB_GIZMO_USB3          0x7c
83 #define AHB_GIZMO_SE            0x4c
84 #define   IMMEDIATE     BIT(18)
85
86 #define AHB_MEM_PREFETCH_CFG5   0xc8
87 #define AHB_MEM_PREFETCH_CFG3   0xe0
88 #define AHB_MEM_PREFETCH_CFG4   0xe4
89 #define AHB_MEM_PREFETCH_CFG1   0xec
90 #define AHB_MEM_PREFETCH_CFG2   0xf0
91 #define AHB_MEM_PREFETCH_CFG6   0xcc
92 #define   PREFETCH_ENB  BIT(31)
93 #define   MST_ID(x)     (((x) & 0x1f) << 26)
94 #define   AHBDMA_MST_ID MST_ID(5)
95 #define   USB_MST_ID    MST_ID(6)
96 #define SDMMC4_MST_ID   MST_ID(12)
97 #define   USB2_MST_ID   MST_ID(18)
98 #define   USB3_MST_ID   MST_ID(17)
99 #define   SE_MST_ID     MST_ID(14)
100 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
101 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
102
103 unsigned long tegra_avp_kernel_start;
104 unsigned long tegra_avp_kernel_size;
105 unsigned long tegra_bootloader_fb_start;
106 unsigned long tegra_bootloader_fb_size;
107 unsigned long tegra_bootloader_fb2_start;
108 unsigned long tegra_bootloader_fb2_size;
109 unsigned long tegra_fb_start;
110 unsigned long tegra_fb_size;
111 unsigned long tegra_fb2_start;
112 unsigned long tegra_fb2_size;
113 unsigned long tegra_carveout_start;
114 unsigned long tegra_carveout_size;
115 unsigned long tegra_vpr_start;
116 unsigned long tegra_vpr_size;
117 unsigned long tegra_tsec_start;
118 unsigned long tegra_tsec_size;
119 unsigned long tegra_lp0_vec_start;
120 unsigned long tegra_lp0_vec_size;
121 #ifdef CONFIG_TEGRA_NVDUMPER
122 unsigned long nvdumper_reserved;
123 #endif
124 #ifdef CONFIG_TRUSTED_FOUNDATIONS
125 unsigned long tegra_tzram_start;
126 unsigned long tegra_tzram_size;
127 #endif
128 bool tegra_lp0_vec_relocate;
129 unsigned long tegra_grhost_aperture = ~0ul;
130 static   bool is_tegra_debug_uart_hsport;
131 static struct board_info pmu_board_info;
132 static struct board_info display_board_info;
133 static int panel_id;
134 static struct board_info camera_board_info;
135
136 static int pmu_core_edp;
137 static int board_panel_type;
138 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
139 static int pwr_i2c_clk = 400;
140 /*
141  * Storage for debug-macro.S's state.
142  *
143  * This must be in .data not .bss so that it gets initialized each time the
144  * kernel is loaded. The data is declared here rather than debug-macro.S so
145  * that multiple inclusions of debug-macro.S point at the same data.
146  */
147 u32 tegra_uart_config[4] = {
148         /* Debug UART initialization required */
149         1,
150         /* Debug UART physical address */
151         0,
152         /* Debug UART virtual address */
153         0,
154         /* Scratch space for debug macro */
155         0,
156 };
157
158
159 #define NEVER_RESET 0
160
161 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
162 {
163         unsigned long check;
164         int retry = 10;
165
166         /* Read and check if write is successful,
167          * if val doesn't match with read, retry write.
168          */
169         do {
170                 writel(val, reg);
171                 check = readl(reg);
172                 if (likely(check == val))
173                         break;
174                 else
175                         pr_err("AHB register access fail for reg\n");
176         } while (--retry);
177 }
178
179 void tegra_assert_system_reset(char mode, const char *cmd)
180 {
181 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
182         pr_info("tegra_assert_system_reset() ignored.....");
183         do { } while (1);
184 #else
185         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
186         u32 reg;
187
188         reg = readl_relaxed(reset + PMC_SCRATCH0);
189         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
190         if (cmd) {
191                 if (!strcmp(cmd, "recovery"))
192                         reg |= RECOVERY_MODE;
193                 else if (!strcmp(cmd, "bootloader"))
194                         reg |= BOOTLOADER_MODE;
195                 else if (!strcmp(cmd, "forced-recovery"))
196                         reg |= FORCED_RECOVERY_MODE;
197                 else
198                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
199         }
200         else {
201                 /* Clearing SCRATCH0 31:30:1 on default reboot */
202                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
203         }
204         writel_relaxed(reg, reset + PMC_SCRATCH0);
205         reg = readl_relaxed(reset);
206         reg |= 0x10;
207         writel_relaxed(reg, reset);
208 #endif
209 }
210 static int modem_id;
211 static int commchip_id;
212 static int sku_override;
213 static int debug_uart_port_id;
214 static enum audio_codec_type audio_codec_name;
215 static enum image_type board_image_type = system_image;
216 static int max_cpu_current;
217 static int max_core_current;
218 static int emc_max_dvfs;
219 static int usb_port_owner_info;
220
221 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
222 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
223         /* name         parent          rate            enabled */
224         { "clk_m",      NULL,           0,              true },
225         { "emc",        NULL,           0,              true },
226         { "cpu",        NULL,           0,              true },
227         { "kfuse",      NULL,           0,              true },
228         { "fuse",       NULL,           0,              true },
229         { "sclk",       NULL,           0,              true },
230         { "pll_p",      NULL,           0,              true },
231         { "pll_p_out1", "pll_p",        0,              false },
232         { "pll_p_out3", "pll_p",        0,              false },
233 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
234         { "pll_m_out1", "pll_m",        275000000,      false },
235         { "pll_p_out2",  "pll_p",       102000000,      false },
236         { "sclk",        "pll_p_out2",  102000000,      true },
237         { "pll_p_out4",  "pll_p",       204000000,      true },
238         { "hclk",       "sclk",         102000000,      true },
239         { "pclk",       "hclk",         51000000,       true },
240         { "mselect",    "pll_p",        102000000,      true },
241         { "host1x",     "pll_p",        102000000,      false },
242         { "cl_dvfs_ref", "pll_p",       51000000,       true },
243         { "cl_dvfs_soc", "pll_p",       51000000,       true },
244 #else
245         { "pll_m_out1", "pll_m",        275000000,      true },
246         { "pll_p_out2", "pll_p",        108000000,      false },
247         { "sclk",       "pll_p_out2",   108000000,      true },
248         { "pll_p_out4", "pll_p",        216000000,      true },
249         { "hclk",       "sclk",         108000000,      true },
250         { "pclk",       "hclk",         54000000,       true },
251         { "mselect",    "pll_p",        108000000,      true },
252         { "host1x",     "pll_p",        108000000,      false },
253         { "cl_dvfs_ref", "clk_m",       13000000,       false },
254         { "cl_dvfs_soc", "clk_m",       13000000,       false },
255 #endif
256 #ifdef CONFIG_TEGRA_SLOW_CSITE
257         { "csite",      "clk_m",        1000000,        true },
258 #else
259         { "csite",      NULL,           0,              true },
260 #endif
261         { "pll_u",      NULL,           480000000,      true },
262         { "pll_re_vco", NULL,           672000000,      false },
263         { "xusb_falcon_src",    "pll_re_vco",   224000000,      false},
264         { "xusb_host_src",      "pll_re_vco",   112000000,      false},
265         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
266         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
267         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
268         { "sdmmc1",     "pll_p",        48000000,       false},
269         { "sdmmc3",     "pll_p",        48000000,       false},
270         { "sdmmc4",     "pll_p",        48000000,       false},
271         { "sbc1.sclk",  NULL,           40000000,       false},
272         { "sbc2.sclk",  NULL,           40000000,       false},
273         { "sbc3.sclk",  NULL,           40000000,       false},
274         { "sbc4.sclk",  NULL,           40000000,       false},
275         { "sbc5.sclk",  NULL,           40000000,       false},
276         { "sbc6.sclk",  NULL,           40000000,       false},
277 #ifdef CONFIG_TEGRA_DUAL_CBUS
278         { "c2bus",      "pll_c2",       250000000,      false },
279         { "c3bus",      "pll_c3",       250000000,      false },
280         { "pll_c",      NULL,           624000000,      false },
281 #else
282         { "cbus",       "pll_c",        250000000,      false },
283 #endif
284         { "pll_c_out1", "pll_c",        150000000,      false },
285 #ifdef CONFIG_TEGRA_PLLM_SCALED
286         { "vi",         "pll_p",        0,              false},
287 #endif
288 #ifdef CONFIG_TEGRA_SOCTHERM
289         { "soc_therm",  "pll_p",        136000000,      false },
290         { "tsensor",    "clk_m",        500000,         false },
291 #endif
292         { NULL,         NULL,           0,              0},
293 };
294 #endif
295 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
296 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
297         /* name         parent          rate            enabled */
298         { "osc",        NULL,           0,              true },
299         { "clk_m",      "osc",          0,              true },
300         { "emc",        NULL,           0,              true },
301         { "cpu",        NULL,           0,              true },
302         { "kfuse",      NULL,           0,              true },
303         { "fuse",       NULL,           0,              true },
304         { "sclk",       NULL,           0,              true },
305 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
306         { "pll_p",      NULL,           0,              true },
307         { "pll_p_out1", "pll_p",        0,              false },
308         { "pll_p_out3", "pll_p",        0,              true },
309         { "pll_m_out1", "pll_m",        275000000,      false },
310         { "pll_p_out2",  "pll_p",       102000000,      false },
311         { "sclk",        "pll_p_out2",  102000000,      true },
312         { "pll_p_out4",  "pll_p",       204000000,      true },
313         { "hclk",       "sclk",         102000000,      true },
314         { "pclk",       "hclk",         51000000,       true },
315         { "mselect",    "pll_p",        102000000,      true },
316         { "host1x",     "pll_p",        102000000,      false },
317         { "cl_dvfs_ref", "pll_p",       51000000,       false },
318         { "cl_dvfs_soc", "pll_p",       51000000,       false },
319 #else
320         { "pll_p",      NULL,           0,              true },
321         { "pll_p_out1", "pll_p",        0,              false },
322         { "pll_p_out3", "pll_p",        0,              true },
323         { "pll_m_out1", "pll_m",        275000000,      true },
324         { "pll_p_out2", "pll_p",        108000000,      false },
325         { "sclk",       "pll_p_out2",   108000000,      true },
326         { "pll_p_out4", "pll_p",        216000000,      true },
327         { "host1x",     "pll_p",        108000000,      false },
328         { "cl_dvfs_ref", "clk_m",       13000000,       false },
329         { "cl_dvfs_soc", "clk_m",       13000000,       false },
330         { "hclk",       "sclk",         108000000,      true },
331         { "pclk",       "hclk",         54000000,       true },
332         { "wake.sclk",  NULL,           250000000,      true },
333         { "mselect",    "pll_p",        108000000,      true },
334 #endif
335 #ifdef CONFIG_TEGRA_SLOW_CSITE
336         { "csite",      "clk_m",        1000000,        true },
337 #else
338         { "csite",      NULL,           0,              true },
339 #endif
340         { "pll_u",      NULL,           480000000,      false },
341         { "sdmmc1",     "pll_p",        48000000,       false},
342         { "sdmmc3",     "pll_p",        48000000,       false},
343         { "sdmmc4",     "pll_p",        48000000,       false},
344         { "sbc1.sclk",  NULL,           40000000,       false},
345         { "sbc2.sclk",  NULL,           40000000,       false},
346         { "sbc3.sclk",  NULL,           40000000,       false},
347         { "sbc4.sclk",  NULL,           40000000,       false},
348         { "sbc5.sclk",  NULL,           40000000,       false},
349         { "sbc6.sclk",  NULL,           40000000,       false},
350         { "msenc",      "pll_p",        108000000,      false },
351         { "tsec",       "pll_p",        108000000,      false },
352         /* FIXME: pllp_bbc and mc_bbc has to be turned on by drivers */
353         { "pll_p_bbc",  "pll_p",        0,              true },
354         { "mc_bbc",     "emc",          0,              true },
355         { "mc_capa",    "emc",          0,              true },
356         { "mc_cbpa",    "emc",          0,              true },
357         /* Initialize c2bus, c3bus, or cbus at the end of the list
358          * after all the clocks are moved under the proper parents.
359          */
360 #ifdef CONFIG_TEGRA_DUAL_CBUS
361         { "c2bus",      "pll_c2",       200000000,      false },
362         { "c3bus",      "pll_c3",       200000000,      false },
363 #else
364         { "cbus",       "pll_c",        200000000,      false },
365         { "pll_c_out1", "pll_c",        100000000,      false },
366 #endif
367         { NULL,         NULL,           0,              0},
368 };
369 #endif
370
371 #ifdef CONFIG_CACHE_L2X0
372 #ifdef CONFIG_TRUSTED_FOUNDATIONS
373 static void tegra_cache_smc(bool enable, u32 arg)
374 {
375         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
376         bool need_affinity_switch;
377         bool can_switch_affinity;
378         bool l2x0_enabled;
379         cpumask_t local_cpu_mask;
380         cpumask_t saved_cpu_mask;
381         unsigned long flags;
382         long ret;
383
384         /*
385          * ISSUE : Some registers of PL310 controler must be written
386          *              from Secure context (and from CPU0)!
387          *
388          * When called form Normal we obtain an abort or do nothing.
389          * Instructions that must be called in Secure:
390          *      - Write to Control register (L2X0_CTRL==0x100)
391          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
392          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
393          *              mandatory at boot time.
394          *      - Tag and Data RAM Latency Control Registers
395          *              (0x108 & 0x10C) must be written in Secure.
396          */
397         need_affinity_switch = (smp_processor_id() != 0);
398         can_switch_affinity = !irqs_disabled();
399
400         WARN_ON(need_affinity_switch && !can_switch_affinity);
401         if (need_affinity_switch && can_switch_affinity) {
402                 cpu_set(0, local_cpu_mask);
403                 sched_getaffinity(0, &saved_cpu_mask);
404                 ret = sched_setaffinity(0, &local_cpu_mask);
405                 WARN_ON(ret != 0);
406         }
407
408         local_irq_save(flags);
409         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
410         if (enable && !l2x0_enabled)
411                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
412         else if (!enable && l2x0_enabled)
413                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
414         local_irq_restore(flags);
415
416         if (need_affinity_switch && can_switch_affinity) {
417                 ret = sched_setaffinity(0, &saved_cpu_mask);
418                 WARN_ON(ret != 0);
419         }
420 }
421
422 static void tegra_l2x0_disable(void)
423 {
424         unsigned long flags;
425         static u32 l2x0_way_mask;
426
427         if (!l2x0_way_mask) {
428                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
429                 u32 aux_ctrl;
430                 u32 ways;
431
432                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
433                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
434                 l2x0_way_mask = (1 << ways) - 1;
435         }
436
437         local_irq_save(flags);
438         tegra_cache_smc(false, l2x0_way_mask);
439         local_irq_restore(flags);
440 }
441 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
442
443 void tegra_init_cache(bool init)
444 {
445         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
446         u32 aux_ctrl;
447 #ifndef CONFIG_TRUSTED_FOUNDATIONS
448         u32 cache_type;
449         u32 tag_latency, data_latency;
450 #endif
451
452 #ifdef CONFIG_TRUSTED_FOUNDATIONS
453         /* issue the SMC to enable the L2 */
454         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
455         trace_smc_init_cache(NVSEC_SMC_START);
456         tegra_cache_smc(true, aux_ctrl);
457         trace_smc_init_cache(NVSEC_SMC_DONE);
458
459         /* after init, reread aux_ctrl and register handlers */
460         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
461         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
462
463         /* override outer_disable() with our disable */
464         outer_cache.disable = tegra_l2x0_disable;
465 #else
466 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
467         tag_latency = 0x331;
468         data_latency = 0x441;
469 #else
470 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
471         if (is_lp_cluster()) {
472 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
473                 tag_latency = 0x110;
474                 data_latency = 0x331;
475 #else
476                 tag_latency = 0x221;
477                 data_latency = 0x221;
478 #endif
479         } else {
480 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
481                 tag_latency = 0x111;
482                 data_latency = 0x441;
483 #else
484                 u32 speedo;
485                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
486                 speedo = tegra_cpu_speedo_id();
487                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
488                     speedo == 12 || speedo == 13) {
489                         tag_latency = 0x442;
490                         data_latency = 0x552;
491                 } else {
492                         tag_latency = 0x441;
493                         data_latency = 0x551;
494                 }
495 #endif
496         }
497 #else
498         tag_latency = 0x770;
499         data_latency = 0x770;
500 #endif
501 #endif
502         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
503         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
504
505 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
506 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
507         writel(7, p + L2X0_PREFETCH_CTRL);
508         writel(0x3, p + L2X0_POWER_CTRL);
509 #endif
510 #endif
511         cache_type = readl(p + L2X0_CACHE_TYPE);
512         aux_ctrl = (cache_type & 0x700) << (17-8);
513         aux_ctrl |= 0x7C400001;
514         if (init) {
515                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
516         } else {
517                 u32 tmp;
518
519                 tmp = aux_ctrl;
520                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
521                 aux_ctrl &= 0x8200c3fe;
522                 aux_ctrl |= tmp;
523                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
524         }
525         l2x0_enable();
526 #endif
527 }
528 #endif
529
530 static void __init tegra_perf_init(void)
531 {
532         u32 reg;
533
534         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
535         reg >>= 11;
536         reg = (1 << (reg & 0x1f))-1;
537         reg |= 0x80000000;
538         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
539         reg = 1;
540         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
541 }
542
543 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
544 static void __init tegra_ramrepair_init(void)
545 {
546         if (tegra_spare_fuse(10) & tegra_spare_fuse(11) & 1) {
547                 u32 reg;
548                 reg = readl(FLOW_CTRL_RAM_REPAIR);
549                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
550                 writel(reg, FLOW_CTRL_RAM_REPAIR);
551         }
552 }
553 #endif
554
555 static void __init tegra_init_power(void)
556 {
557 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
558         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
559 #endif
560 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
561         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
562 #endif
563 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
564         /* some partitions need to be powergated by default for t11x */
565         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
566         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
567         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
568 #endif
569 }
570
571 static inline unsigned long gizmo_readl(unsigned long offset)
572 {
573         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
574 }
575
576 static inline void gizmo_writel(unsigned long value, unsigned long offset)
577 {
578         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
579 }
580
581 static void __init tegra_init_ahb_gizmo_settings(void)
582 {
583         unsigned long val;
584
585         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
586         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
587         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
588
589         val = gizmo_readl(AHB_GIZMO_USB);
590         val |= IMMEDIATE;
591         gizmo_writel(val, AHB_GIZMO_USB);
592
593         val = gizmo_readl(AHB_GIZMO_USB2);
594         val |= IMMEDIATE;
595         gizmo_writel(val, AHB_GIZMO_USB2);
596
597         val = gizmo_readl(AHB_GIZMO_USB3);
598         val |= IMMEDIATE;
599         gizmo_writel(val, AHB_GIZMO_USB3);
600
601 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
602         val = gizmo_readl(AHB_GIZMO_SE);
603         val |= IMMEDIATE;
604         gizmo_writel(val, AHB_GIZMO_SE);
605 #endif
606
607         /*
608          * SDMMC controller is removed from AHB interface in T124 and
609          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
610          * in T11x and T14x SOCs.
611          */
612 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
613         val = gizmo_readl(AHB_GIZMO_SDMMC4);
614         val |= IMMEDIATE;
615         gizmo_writel(val, AHB_GIZMO_SDMMC4);
616 #endif
617
618         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
619         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
620                                 | AHB_PRIORITY_WEIGHT(7);
621 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
622         val |= PRIORITY_SELECT_SE;
623 #endif
624
625 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
626         val |= PRIORITY_SELECT_SDMMC4;
627 #endif
628         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
629
630         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
631         val &= ~MST_ID(~0);
632         val |= PREFETCH_ENB | AHBDMA_MST_ID |
633                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
634         ahb_gizmo_writel(val,
635                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
636
637         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
638         val &= ~MST_ID(~0);
639         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
640                 INACTIVITY_TIMEOUT(0x1000);
641         ahb_gizmo_writel(val,
642                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
643
644         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
645         val &= ~MST_ID(~0);
646         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
647                 INACTIVITY_TIMEOUT(0x1000);
648         ahb_gizmo_writel(val,
649                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
650
651         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
652         val &= ~MST_ID(~0);
653         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
654                 INACTIVITY_TIMEOUT(0x1000);
655         ahb_gizmo_writel(val,
656                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
657
658         /*
659          * SDMMC controller is removed from AHB interface in T124 and
660          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
661          * in T11x and T14x SOCs.
662          */
663 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
664         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
665         val &= ~MST_ID(~0);
666         val |= PREFETCH_ENB | SDMMC4_MST_ID | ADDR_BNDRY(0xc) |
667                 INACTIVITY_TIMEOUT(0x1000);
668         val &= ~SDMMC4_MST_ID;
669         ahb_gizmo_writel(val,
670                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
671 #endif
672
673 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
674         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
675         val &= ~MST_ID(~0);
676         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
677                 INACTIVITY_TIMEOUT(0x1000);
678         ahb_gizmo_writel(val,
679                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
680 #endif
681 }
682
683 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
684 void __init tegra20_init_early(void)
685 {
686 #ifndef CONFIG_SMP
687         /* For SMP system, initializing the reset handler here is too
688            late. For non-SMP systems, the function that calls the reset
689            handler initializer is not called, so do it here for non-SMP. */
690         tegra_cpu_reset_handler_init();
691 #endif
692         tegra_apb_io_init();
693         tegra_perf_init();
694         tegra_init_fuse();
695         tegra_init_cache(true);
696         tegra_pmc_init();
697         tegra_powergate_init();
698         tegra20_hotplug_init();
699         tegra_init_power();
700         tegra_init_ahb_gizmo_settings();
701         tegra_init_debug_uart_rate();
702         tegra_gpio_resume_init();
703         tegra_ram_console_debug_reserve(SZ_1M);
704 }
705 #endif
706 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
707 void __init tegra30_init_early(void)
708 {
709 #ifndef CONFIG_SMP
710         /* For SMP system, initializing the reset handler here is too
711            late. For non-SMP systems, the function that calls the reset
712            handler initializer is not called, so do it here for non-SMP. */
713         tegra_cpu_reset_handler_init();
714 #endif
715         tegra_apb_io_init();
716         tegra_perf_init();
717         tegra_init_fuse();
718         tegra_init_cache(true);
719         tegra_pmc_init();
720         tegra_powergate_init();
721         tegra30_hotplug_init();
722         tegra_init_power();
723         tegra_init_ahb_gizmo_settings();
724         tegra_init_debug_uart_rate();
725         tegra_gpio_resume_init();
726         tegra_ram_console_debug_reserve(SZ_1M);
727
728         init_dma_coherent_pool_size(SZ_1M);
729 }
730 #endif
731 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
732 void __init tegra11x_init_early(void)
733 {
734 #ifndef CONFIG_SMP
735         /* For SMP system, initializing the reset handler here is too
736            late. For non-SMP systems, the function that calls the reset
737            handler initializer is not called, so do it here for non-SMP. */
738         tegra_cpu_reset_handler_init();
739 #endif
740         tegra_apb_io_init();
741         tegra_perf_init();
742         tegra_init_fuse();
743         tegra_ramrepair_init();
744         tegra11x_init_clocks();
745         tegra11x_init_dvfs();
746         tegra_common_init_clock();
747         tegra_clk_init_from_table(tegra11x_clk_init_table);
748         tegra11x_clk_init_la();
749         tegra_pmc_init();
750         tegra_powergate_init();
751         tegra30_hotplug_init();
752         tegra_init_power();
753         tegra_init_ahb_gizmo_settings();
754         tegra_init_debug_uart_rate();
755         tegra_gpio_resume_init();
756
757         init_dma_coherent_pool_size(SZ_2M);
758 }
759 #endif
760 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
761 void __init tegra14x_init_early(void)
762 {
763 #ifndef CONFIG_SMP
764         /* For SMP system, initializing the reset handler here is too
765            late. For non-SMP systems, the function that calls the reset
766            handler initializer is not called, so do it here for non-SMP. */
767         tegra_cpu_reset_handler_init();
768 #endif
769         tegra_apb_io_init();
770         tegra_perf_init();
771         tegra_init_fuse();
772         tegra_ramrepair_init();
773         tegra14x_init_clocks();
774         tegra14x_init_dvfs();
775         tegra_common_init_clock();
776         tegra_clk_init_from_table(tegra14x_clk_init_table);
777         tegra_init_cache(true);
778         tegra_pmc_init();
779         tegra_powergate_init();
780         tegra30_hotplug_init();
781         tegra_init_power();
782         tegra_init_ahb_gizmo_settings();
783         tegra_init_debug_uart_rate();
784         tegra_gpio_resume_init();
785 }
786 #endif
787 static int __init tegra_lp0_vec_arg(char *options)
788 {
789         char *p = options;
790
791         tegra_lp0_vec_size = memparse(p, &p);
792         if (*p == '@')
793                 tegra_lp0_vec_start = memparse(p+1, &p);
794         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
795                 tegra_lp0_vec_size = 0;
796                 tegra_lp0_vec_start = 0;
797         }
798
799         return 0;
800 }
801 early_param("lp0_vec", tegra_lp0_vec_arg);
802
803 #ifdef CONFIG_TEGRA_NVDUMPER
804 static int __init tegra_nvdumper_arg(char *options)
805 {
806         char *p = options;
807
808         nvdumper_reserved = memparse(p, &p);
809         return 0;
810 }
811 early_param("nvdumper_reserved", tegra_nvdumper_arg);
812 #endif
813
814 static int __init tegra_bootloader_fb_arg(char *options)
815 {
816         char *p = options;
817
818         tegra_bootloader_fb_size = memparse(p, &p);
819         if (*p == '@')
820                 tegra_bootloader_fb_start = memparse(p+1, &p);
821
822         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
823                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
824
825         return 0;
826 }
827 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
828
829 static int __init tegra_bootloader_fb2_arg(char *options)
830 {
831         char *p = options;
832
833         tegra_bootloader_fb2_size = memparse(p, &p);
834         if (*p == '@')
835                 tegra_bootloader_fb2_start = memparse(p+1, &p);
836
837         pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
838                 tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
839
840         return 0;
841 }
842 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
843
844 static int __init tegra_sku_override(char *id)
845 {
846         char *p = id;
847
848         sku_override = memparse(p, &p);
849
850         return 0;
851 }
852 early_param("sku_override", tegra_sku_override);
853
854 int tegra_get_sku_override(void)
855 {
856         return sku_override;
857 }
858
859 static int __init tegra_vpr_arg(char *options)
860 {
861         char *p = options;
862
863         tegra_vpr_size = memparse(p, &p);
864         if (*p == '@')
865                 tegra_vpr_start = memparse(p+1, &p);
866         pr_info("Found vpr, start=0x%lx size=%lx",
867                 tegra_vpr_start, tegra_vpr_size);
868         return 0;
869 }
870 early_param("vpr", tegra_vpr_arg);
871
872 static int __init tegra_tsec_arg(char *options)
873 {
874         char *p = options;
875
876         tegra_tsec_size = memparse(p, &p);
877         if (*p == '@')
878                 tegra_tsec_start = memparse(p+1, &p);
879         pr_info("Found tsec, start=0x%lx size=%lx",
880                 tegra_tsec_start, tegra_tsec_size);
881         return 0;
882 }
883 early_param("tsec", tegra_tsec_arg);
884
885 #ifdef CONFIG_TRUSTED_FOUNDATIONS
886 static int __init tegra_tzram_arg(char *options)
887 {
888         char *p = options;
889
890         tegra_tzram_size = memparse(p, &p);
891         if (*p == '@')
892                 tegra_tzram_start = memparse(p + 1, &p);
893         return 0;
894 }
895 early_param("tzram", tegra_tzram_arg);
896 #endif
897
898 enum panel_type get_panel_type(void)
899 {
900         return board_panel_type;
901 }
902 static int __init tegra_board_panel_type(char *options)
903 {
904         if (!strcmp(options, "lvds"))
905                 board_panel_type = panel_type_lvds;
906         else if (!strcmp(options, "dsi"))
907                 board_panel_type = panel_type_dsi;
908         else
909                 return 0;
910         return 1;
911 }
912 __setup("panel=", tegra_board_panel_type);
913
914 int tegra_get_board_panel_id(void)
915 {
916         return panel_id;
917 }
918 static int __init tegra_board_panel_id(char *options)
919 {
920         char *p = options;
921         panel_id = memparse(p, &p);
922         return panel_id;
923 }
924 __setup("display_panel=", tegra_board_panel_id);
925
926 enum power_supply_type get_power_supply_type(void)
927 {
928         return pow_supply_type;
929 }
930 static int __init tegra_board_power_supply_type(char *options)
931 {
932         if (!strcmp(options, "Adapter"))
933                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
934         if (!strcmp(options, "Mains"))
935                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
936         else if (!strcmp(options, "Battery"))
937                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
938         else
939                 return 0;
940         return 1;
941 }
942 __setup("power_supply=", tegra_board_power_supply_type);
943
944 int get_core_edp(void)
945 {
946         return pmu_core_edp;
947 }
948 static int __init tegra_pmu_core_edp(char *options)
949 {
950         char *p = options;
951         int core_edp = memparse(p, &p);
952         if (core_edp != 0)
953                 pmu_core_edp = core_edp;
954         return 0;
955 }
956 early_param("core_edp_mv", tegra_pmu_core_edp);
957
958 int get_maximum_cpu_current_supported(void)
959 {
960         return max_cpu_current;
961 }
962 static int __init tegra_max_cpu_current(char *options)
963 {
964         char *p = options;
965         max_cpu_current = memparse(p, &p);
966         return 1;
967 }
968 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
969
970 int get_maximum_core_current_supported(void)
971 {
972         return max_core_current;
973 }
974 static int __init tegra_max_core_current(char *options)
975 {
976         char *p = options;
977         max_core_current = memparse(p, &p);
978         return 1;
979 }
980 __setup("core_edp_ma=", tegra_max_core_current);
981
982 int get_emc_max_dvfs(void)
983 {
984         return emc_max_dvfs;
985 }
986 static int __init tegra_emc_max_dvfs(char *options)
987 {
988         char *p = options;
989         emc_max_dvfs = memparse(p, &p);
990         return 1;
991 }
992 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
993
994 static int __init tegra_debug_uartport(char *info)
995 {
996         char *p = info;
997         unsigned long long port_id;
998         if (!strncmp(p, "hsport", 6))
999                 is_tegra_debug_uart_hsport = true;
1000         else if (!strncmp(p, "lsport", 6))
1001                 is_tegra_debug_uart_hsport = false;
1002
1003         if (p[6] == ',') {
1004                 if (p[7] == '-') {
1005                         debug_uart_port_id = -1;
1006                 } else {
1007                         port_id = memparse(p + 7, &p);
1008                         debug_uart_port_id = (int) port_id;
1009                 }
1010         } else {
1011                 debug_uart_port_id = -1;
1012         }
1013
1014         return 1;
1015 }
1016
1017 bool is_tegra_debug_uartport_hs(void)
1018 {
1019         return is_tegra_debug_uart_hsport;
1020 }
1021
1022 int get_tegra_uart_debug_port_id(void)
1023 {
1024         return debug_uart_port_id;
1025 }
1026 __setup("debug_uartport=", tegra_debug_uartport);
1027
1028 static int __init tegra_image_type(char *options)
1029 {
1030         if (!strcmp(options, "RCK"))
1031                 board_image_type = rck_image;
1032
1033         return 0;
1034 }
1035
1036 enum image_type get_tegra_image_type(void)
1037 {
1038         return board_image_type;
1039 }
1040
1041 __setup("image=", tegra_image_type);
1042
1043 static int __init tegra_audio_codec_type(char *info)
1044 {
1045         char *p = info;
1046         if (!strncmp(p, "wm8903", 6))
1047                 audio_codec_name = audio_codec_wm8903;
1048         else
1049                 audio_codec_name = audio_codec_none;
1050
1051         return 1;
1052 }
1053
1054 enum audio_codec_type get_audio_codec_type(void)
1055 {
1056         return audio_codec_name;
1057 }
1058 __setup("audio_codec=", tegra_audio_codec_type);
1059
1060 static int tegra_get_pwr_i2c_clk_rate(char *options)
1061 {
1062         int clk = simple_strtol(options, NULL, 16);
1063         if (clk != 0)
1064                 pwr_i2c_clk = clk;
1065         return 0;
1066 }
1067
1068 int get_pwr_i2c_clk_rate(void)
1069 {
1070         return pwr_i2c_clk;
1071 }
1072 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1073
1074 void tegra_get_board_info(struct board_info *bi)
1075 {
1076 #ifdef CONFIG_OF
1077         struct device_node *board_info;
1078         u32 prop_val;
1079         int err;
1080
1081         board_info = of_find_node_by_path("/chosen/board_info");
1082         if (!IS_ERR_OR_NULL(board_info)) {
1083                 memset(bi, 0, sizeof(*bi));
1084
1085                 err = of_property_read_u32(board_info, "id", &prop_val);
1086                 if (err)
1087                         pr_err("failed to read /chosen/board_info/id\n");
1088                 else
1089                         bi->board_id = prop_val;
1090
1091                 err = of_property_read_u32(board_info, "sku", &prop_val);
1092                 if (err)
1093                         pr_err("failed to read /chosen/board_info/sku\n");
1094                 else
1095                         bi->sku = prop_val;
1096
1097                 err = of_property_read_u32(board_info, "fab", &prop_val);
1098                 if (err)
1099                         pr_err("failed to read /chosen/board_info/fab\n");
1100                 else
1101                         bi->fab = prop_val;
1102
1103                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1104                 if (err)
1105                         pr_err("failed to read /chosen/board_info/major_revision\n");
1106                 else
1107                         bi->major_revision = prop_val;
1108
1109                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1110                 if (err)
1111                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1112                 else
1113                         bi->minor_revision = prop_val;
1114                 system_serial_high = (bi->board_id << 16) | bi->sku;
1115                 system_serial_low = (bi->fab << 24) |
1116                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1117         } else {
1118 #endif
1119                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1120                 bi->sku = (system_serial_high) & 0xFFFF;
1121                 bi->fab = (system_serial_low >> 24) & 0xFF;
1122                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1123                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1124 #ifdef CONFIG_OF
1125         }
1126 #endif
1127 }
1128
1129 static int __init tegra_pmu_board_info(char *info)
1130 {
1131         char *p = info;
1132         pmu_board_info.board_id = memparse(p, &p);
1133         pmu_board_info.sku = memparse(p+1, &p);
1134         pmu_board_info.fab = memparse(p+1, &p);
1135         pmu_board_info.major_revision = memparse(p+1, &p);
1136         pmu_board_info.minor_revision = memparse(p+1, &p);
1137         return 1;
1138 }
1139
1140 void tegra_get_pmu_board_info(struct board_info *bi)
1141 {
1142         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1143 }
1144
1145 __setup("pmuboard=", tegra_pmu_board_info);
1146
1147 static int __init tegra_display_board_info(char *info)
1148 {
1149         char *p = info;
1150         display_board_info.board_id = memparse(p, &p);
1151         display_board_info.sku = memparse(p+1, &p);
1152         display_board_info.fab = memparse(p+1, &p);
1153         display_board_info.major_revision = memparse(p+1, &p);
1154         display_board_info.minor_revision = memparse(p+1, &p);
1155         return 1;
1156 }
1157
1158 void tegra_get_display_board_info(struct board_info *bi)
1159 {
1160         memcpy(bi, &display_board_info, sizeof(struct board_info));
1161 }
1162
1163 __setup("displayboard=", tegra_display_board_info);
1164
1165 static int __init tegra_camera_board_info(char *info)
1166 {
1167         char *p = info;
1168         camera_board_info.board_id = memparse(p, &p);
1169         camera_board_info.sku = memparse(p+1, &p);
1170         camera_board_info.fab = memparse(p+1, &p);
1171         camera_board_info.major_revision = memparse(p+1, &p);
1172         camera_board_info.minor_revision = memparse(p+1, &p);
1173         return 1;
1174 }
1175
1176 void tegra_get_camera_board_info(struct board_info *bi)
1177 {
1178         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1179 }
1180
1181 __setup("cameraboard=", tegra_camera_board_info);
1182
1183 static int __init tegra_modem_id(char *id)
1184 {
1185         char *p = id;
1186
1187         modem_id = memparse(p, &p);
1188         return 1;
1189 }
1190
1191 int tegra_get_modem_id(void)
1192 {
1193         return modem_id;
1194 }
1195
1196 __setup("modem_id=", tegra_modem_id);
1197
1198 static int __init tegra_usb_port_owner_info(char *id)
1199 {
1200         char *p = id;
1201
1202         usb_port_owner_info = memparse(p, &p);
1203         return 1;
1204 }
1205
1206 int tegra_get_usb_port_owner_info(void)
1207 {
1208         return usb_port_owner_info;
1209 }
1210
1211 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1212
1213 static int __init tegra_commchip_id(char *id)
1214 {
1215         char *p = id;
1216
1217         if (get_option(&p, &commchip_id) != 1)
1218                 return 0;
1219         return 1;
1220 }
1221
1222 int tegra_get_commchip_id(void)
1223 {
1224         return commchip_id;
1225 }
1226
1227 __setup("commchip_id=", tegra_commchip_id);
1228
1229 /*
1230  * Tegra has a protected aperture that prevents access by most non-CPU
1231  * memory masters to addresses above the aperture value.  Enabling it
1232  * secures the CPU's memory from the GPU, except through the GART.
1233  */
1234 void __init tegra_protected_aperture_init(unsigned long aperture)
1235 {
1236 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
1237         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1238         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1239         writel(aperture, mc_base + MC_SECURITY_CFG2);
1240 #else
1241         pr_err("Tegra protected aperture disabled because nvmap is using "
1242                 "system memory\n");
1243 #endif
1244 }
1245
1246 /*
1247  * Due to conflicting restrictions on the placement of the framebuffer,
1248  * the bootloader is likely to leave the framebuffer pointed at a location
1249  * in memory that is outside the grhost aperture.  This function will move
1250  * the framebuffer contents from a physical address that is anywhere (lowmem,
1251  * highmem, or outside the memory map) to a physical address that is outside
1252  * the memory map.
1253  */
1254 void __tegra_move_framebuffer(struct platform_device *pdev,
1255         unsigned long to, unsigned long from,
1256         unsigned long size)
1257 {
1258         struct page *page;
1259         void __iomem *to_io;
1260         void *from_virt;
1261         unsigned long i, addr[] = { to, from, };
1262
1263         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1264         BUG_ON(PAGE_ALIGN(from) != from);
1265         BUG_ON(PAGE_ALIGN(size) != size);
1266
1267         to_io = ioremap(to, size);
1268         if (!to_io) {
1269                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1270                 return;
1271         }
1272
1273         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1274                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1275                         page = phys_to_page(from + i);
1276                         from_virt = kmap(page);
1277                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1278                         kunmap(page);
1279                 }
1280         } else {
1281                 void __iomem *from_io = ioremap(from, size);
1282                 if (!from_io) {
1283                         pr_err("%s: Failed to map source framebuffer\n",
1284                                 __func__);
1285                         goto out;
1286                 }
1287
1288                 for (i = 0; i < size; i += 4)
1289                         writel(readl(from_io + i), to_io + i);
1290
1291                 iounmap(from_io);
1292         }
1293
1294         if (!pdev)
1295                 goto out;
1296
1297         for (i = 0; i < ARRAY_SIZE(addr); i++)
1298                 dma_map_linear(&pdev->dev, addr[i], size, DMA_TO_DEVICE);
1299 out:
1300         iounmap(to_io);
1301 }
1302
1303 void __tegra_clear_framebuffer(struct platform_device *pdev,
1304                                unsigned long to, unsigned long size)
1305 {
1306         void __iomem *to_io;
1307         unsigned long i;
1308
1309         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1310         BUG_ON(PAGE_ALIGN(size) != size);
1311
1312         to_io = ioremap(to, size);
1313         if (!to_io) {
1314                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1315                 return;
1316         }
1317
1318         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1319                 for (i = 0 ; i < size; i += PAGE_SIZE)
1320                         memset(to_io + i, 0, PAGE_SIZE);
1321         } else {
1322                 for (i = 0; i < size; i += 4)
1323                         writel(0, to_io + i);
1324         }
1325         iounmap(to_io);
1326 }
1327
1328 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1329         unsigned long fb2_size)
1330 {
1331         const size_t avp_kernel_reserve = SZ_32M;
1332 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1333         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1334         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1335         tegra_avp_kernel_size = SZ_1M;
1336         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1337         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1338                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1339                                 "from memory map\n",
1340                         (unsigned long)avp_kernel_reserve,
1341                         tegra_avp_kernel_start);
1342                 tegra_avp_kernel_size = 0;
1343         }
1344 #endif
1345
1346         if (carveout_size) {
1347                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1348                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1349                         pr_err("Failed to remove carveout %08lx@%08lx "
1350                                 "from memory map\n",
1351                                 carveout_size, tegra_carveout_start);
1352                         tegra_carveout_start = 0;
1353                         tegra_carveout_size = 0;
1354                 } else
1355                         tegra_carveout_size = carveout_size;
1356         }
1357
1358         if (fb2_size) {
1359                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1360                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1361                         pr_err("Failed to remove second framebuffer "
1362                                 "%08lx@%08lx from memory map\n",
1363                                 fb2_size, tegra_fb2_start);
1364                         tegra_fb2_start = 0;
1365                         tegra_fb2_size = 0;
1366                 } else
1367                         tegra_fb2_size = fb2_size;
1368         }
1369
1370         if (fb_size) {
1371                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1372                 if (memblock_remove(tegra_fb_start, fb_size)) {
1373                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1374                                 "from memory map\n",
1375                                 fb_size, tegra_fb_start);
1376                         tegra_fb_start = 0;
1377                         tegra_fb_size = 0;
1378                 } else
1379                         tegra_fb_size = fb_size;
1380         }
1381
1382         if (tegra_fb_size)
1383                 tegra_grhost_aperture = tegra_fb_start;
1384
1385         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1386                 tegra_grhost_aperture = tegra_fb2_start;
1387
1388         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1389                 tegra_grhost_aperture = tegra_carveout_start;
1390
1391         if (tegra_lp0_vec_size &&
1392            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1393                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1394                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1395                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1396                         tegra_lp0_vec_start = 0;
1397                         tegra_lp0_vec_size = 0;
1398                 }
1399                 tegra_lp0_vec_relocate = false;
1400         } else
1401                 tegra_lp0_vec_relocate = true;
1402
1403 #ifdef CONFIG_TEGRA_NVDUMPER
1404         if (nvdumper_reserved) {
1405                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1406                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1407                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1408                         nvdumper_reserved = 0;
1409                 }
1410         }
1411 #endif
1412
1413         /*
1414          * We copy the bootloader's framebuffer to the framebuffer allocated
1415          * above, and then free this one.
1416          * */
1417         if (tegra_bootloader_fb_size) {
1418                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1419                 if (memblock_reserve(tegra_bootloader_fb_start,
1420                                 tegra_bootloader_fb_size)) {
1421                         pr_err("Failed to reserve bootloader frame buffer "
1422                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1423                                 tegra_bootloader_fb_start);
1424                         tegra_bootloader_fb_start = 0;
1425                         tegra_bootloader_fb_size = 0;
1426                 }
1427         }
1428
1429         if (tegra_bootloader_fb2_size) {
1430                 tegra_bootloader_fb2_size =
1431                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1432                 if (memblock_reserve(tegra_bootloader_fb2_start,
1433                                 tegra_bootloader_fb2_size)) {
1434                         pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
1435                                 tegra_bootloader_fb2_size,
1436                                 tegra_bootloader_fb2_start);
1437                         tegra_bootloader_fb2_start = 0;
1438                         tegra_bootloader_fb2_size = 0;
1439                 }
1440         }
1441
1442         pr_info("Tegra reserved memory:\n"
1443                 "LP0:                    %08lx - %08lx\n"
1444                 "Bootloader framebuffer: %08lx - %08lx\n"
1445                 "Bootloader framebuffer2: %08lx - %08lx\n"
1446                 "Framebuffer:            %08lx - %08lx\n"
1447                 "2nd Framebuffer:        %08lx - %08lx\n"
1448                 "Carveout:               %08lx - %08lx\n"
1449                 "Vpr:                    %08lx - %08lx\n"
1450                 "Tsec:                   %08lx - %08lx\n",
1451                 tegra_lp0_vec_start,
1452                 tegra_lp0_vec_size ?
1453                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1454                 tegra_bootloader_fb_start,
1455                 tegra_bootloader_fb_size ?
1456                  tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
1457                 tegra_bootloader_fb2_start,
1458                 tegra_bootloader_fb2_size ?
1459                  tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
1460                 tegra_fb_start,
1461                 tegra_fb_size ?
1462                         tegra_fb_start + tegra_fb_size - 1 : 0,
1463                 tegra_fb2_start,
1464                 tegra_fb2_size ?
1465                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1466                 tegra_carveout_start,
1467                 tegra_carveout_size ?
1468                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1469                 tegra_vpr_start,
1470                 tegra_vpr_size ?
1471                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1472                 tegra_tsec_start,
1473                 tegra_tsec_size ?
1474                 tegra_tsec_start + tegra_tsec_size - 1 : 0);
1475
1476         if (tegra_avp_kernel_size) {
1477                 /* Return excessive memory reserved for AVP kernel */
1478                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1479                         memblock_add(
1480                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1481                                 avp_kernel_reserve - tegra_avp_kernel_size);
1482                 pr_info(
1483                 "AVP kernel: %08lx - %08lx\n",
1484                         tegra_avp_kernel_start,
1485                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1486         }
1487
1488 #ifdef CONFIG_TEGRA_NVDUMPER
1489         if (nvdumper_reserved) {
1490                 pr_info("Nvdumper:               %08lx - %08lx\n",
1491                         nvdumper_reserved,
1492                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1493         }
1494 #endif
1495
1496 #ifdef CONFIG_TRUSTED_FOUNDATIONS
1497         pr_info("Tzram:               %08lx - %08lx\n",
1498                 tegra_tzram_start,
1499                 tegra_tzram_size ?
1500                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
1501 #endif
1502 }
1503
1504 #ifdef CONFIG_PSTORE_RAM
1505 static struct persistent_ram_descriptor desc = {
1506         .name = "ramoops",
1507 };
1508
1509 static struct persistent_ram ram = {
1510         .descs = &desc,
1511         .num_descs = 1,
1512 };
1513
1514 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1515 {
1516         int ret;
1517
1518         ram.start = memblock_end_of_DRAM() - ram_console_size;
1519         ram.size = ram_console_size;
1520         ram.descs->size = ram_console_size;
1521
1522         INIT_LIST_HEAD(&ram.node);
1523
1524         ret = persistent_ram_early_init(&ram);
1525         if (ret)
1526                 goto fail;
1527
1528         return;
1529
1530 fail:
1531         pr_err("Failed to reserve memory block for ram console\n");
1532 }
1533 #endif
1534
1535 int __init tegra_register_fuse(void)
1536 {
1537         return platform_device_register(&tegra_fuse_device);
1538 }
1539
1540 void __init tegra_release_bootloader_fb(void)
1541 {
1542         /* Since bootloader fb is reserved in common.c, it is freed here. */
1543         if (tegra_bootloader_fb_size)
1544                 if (memblock_free(tegra_bootloader_fb_start,
1545                                                 tegra_bootloader_fb_size))
1546                         pr_err("Failed to free bootloader fb.\n");
1547         if (tegra_bootloader_fb2_size)
1548                 if (memblock_free(tegra_bootloader_fb2_start,
1549                                                 tegra_bootloader_fb2_size))
1550                         pr_err("Failed to free bootloader fb2.\n");
1551 }
1552
1553 static struct platform_device *pinmux_devices[] = {
1554         &tegra_gpio_device,
1555         &tegra_pinmux_device,
1556 };
1557
1558 void tegra_enable_pinmux(void)
1559 {
1560         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1561 }
1562
1563 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1564         [TEGRA_REVISION_UNKNOWN] = "unknown",
1565         [TEGRA_REVISION_A01]     = "A01",
1566         [TEGRA_REVISION_A02]     = "A02",
1567         [TEGRA_REVISION_A03]     = "A03",
1568         [TEGRA_REVISION_A03p]    = "A03 prime",
1569         [TEGRA_REVISION_A04]     = "A04",
1570         [TEGRA_REVISION_A04p]    = "A04 prime",
1571 };
1572
1573 static const char * __init tegra_get_revision(void)
1574 {
1575         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1576 }
1577
1578 static const char * __init tegra_get_family(void)
1579 {
1580         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1581         u32 cid = readl(chip_id);
1582         cid = (cid >> 8) & 0xFF;
1583
1584         switch (cid) {
1585         case TEGRA_CHIPID_TEGRA2:
1586                 cid = 2;
1587                 break;
1588         case TEGRA_CHIPID_TEGRA3:
1589                 cid = 3;
1590                 break;
1591         case TEGRA_CHIPID_TEGRA11:
1592                 cid = 11;
1593                 break;
1594         case TEGRA_CHIPID_TEGRA14:
1595                 cid = 14;
1596                 break;
1597
1598         case TEGRA_CHIPID_UNKNOWN:
1599         default:
1600                 cid = 0;
1601         }
1602         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1603 }
1604
1605 static const char * __init tegra_get_soc_id(void)
1606 {
1607         int package_id = tegra_package_id();
1608         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1609                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1610 }
1611
1612 static void __init tegra_soc_info_populate(struct soc_device_attribute
1613         *soc_dev_attr, const char *machine)
1614 {
1615         soc_dev_attr->soc_id = tegra_get_soc_id();
1616         soc_dev_attr->machine  = machine;
1617         soc_dev_attr->family   = tegra_get_family();
1618         soc_dev_attr->revision = tegra_get_revision();
1619 }
1620
1621 int __init tegra_soc_device_init(const char *machine)
1622 {
1623         struct soc_device *soc_dev;
1624         struct soc_device_attribute *soc_dev_attr;
1625
1626         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1627         if (!soc_dev_attr)
1628                 return -ENOMEM;
1629
1630         tegra_soc_info_populate(soc_dev_attr, machine);
1631
1632         soc_dev = soc_device_register(soc_dev_attr);
1633         if (IS_ERR_OR_NULL(soc_dev)) {
1634                 kfree(soc_dev_attr);
1635                 return -1;
1636         }
1637
1638         return 0;
1639 }
1640
1641 void __init tegra_init_late(void)
1642 {
1643 #ifndef CONFIG_COMMON_CLK
1644         tegra_clk_debugfs_init();
1645 #endif
1646         tegra_powergate_debugfs_init();
1647 }
1648
1649 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
1650 #define ASIM_SHUTDOWN_REG       0x538f0ffc
1651
1652 static void asim_power_off(void)
1653 {
1654         pr_err("ASIM Powering off the device\n");
1655         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
1656         while (1)
1657                 ;
1658 }
1659
1660 static int __init asim_power_off_init(void)
1661 {
1662         if (tegra_cpu_is_asim())
1663                 pm_power_off = asim_power_off;
1664         return 0;
1665 }
1666
1667 arch_initcall(asim_power_off_init);
1668
1669 #if defined(CONFIG_SMC91X)
1670 static struct resource tegra_asim_smc91x_resources[] = {
1671         [0] = {
1672                 .start          = TEGRA_SIM_ETH_BASE,
1673                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
1674                 .flags          = IORESOURCE_MEM,
1675         },
1676         [1] = {
1677                 .start          = IRQ_ETH,
1678                 .end            = IRQ_ETH,
1679                 .flags          = IORESOURCE_IRQ,
1680         },
1681 };
1682
1683 static struct platform_device tegra_asim_smc91x_device = {
1684         .name           = "smc91x",
1685         .id             = 0,
1686         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
1687         .resource       = tegra_asim_smc91x_resources,
1688 };
1689
1690 static int __init asim_enet_init(void)
1691 {
1692         if (tegra_cpu_is_asim())
1693                 platform_device_register(&tegra_asim_smc91x_device);
1694         return 0;
1695 }
1696
1697 rootfs_initcall(asim_enet_init);
1698 #endif
1699
1700 #endif