48b76f4e78d12d7f99e1ce5db52fe7807e3b842c
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36 #if defined(CONFIG_SMSC911X)
37 #include <linux/smsc911x.h>
38 #endif
39
40 #include <linux/export.h>
41 #include <linux/bootmem.h>
42 #include <trace/events/nvsecurity.h>
43
44 #ifdef CONFIG_ARM64
45 #include <linux/irqchip/gic.h>
46 #else
47 #include <asm/system.h>
48 #include <asm/hardware/cache-l2x0.h>
49 #endif
50 #include <asm/dma-mapping.h>
51
52 #include <mach/hardware.h>
53 #include <mach/powergate.h>
54 #include <mach/tegra_smmu.h>
55 #include <mach/nct.h>
56
57 #include "apbio.h"
58 #include "board.h"
59 #include "clock.h"
60 #include "common.h"
61 #include "dvfs.h"
62 #include "fuse.h"
63 #include "iomap.h"
64 #include "pm.h"
65 #include "sleep.h"
66 #include "reset.h"
67 #include "devices.h"
68 #include "pmc.h"
69
70 #define MC_SECURITY_CFG2        0x7c
71
72 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
73 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
74 #define   PRIORITY_SELECT_USB   BIT(6)
75 #define   PRIORITY_SELECT_USB2  BIT(18)
76 #define   PRIORITY_SELECT_USB3  BIT(17)
77 #define   PRIORITY_SELECT_SE BIT(14)
78
79 #define AHB_GIZMO_AHB_MEM               0xc
80 #define   ENB_FAST_REARBITRATE  BIT(2)
81 #define   DONT_SPLIT_AHB_WR     BIT(7)
82 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
83 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
84
85 #define   RECOVERY_MODE BIT(31)
86 #define   BOOTLOADER_MODE       BIT(30)
87 #define   FORCED_RECOVERY_MODE  BIT(1)
88
89 #define AHB_GIZMO_USB           0x1c
90 #define AHB_GIZMO_USB2          0x78
91 #define AHB_GIZMO_USB3          0x7c
92 #define AHB_GIZMO_SE            0x4c
93 #define   IMMEDIATE     BIT(18)
94
95 #define AHB_MEM_PREFETCH_CFG5   0xc8
96 #define AHB_MEM_PREFETCH_CFG3   0xe0
97 #define AHB_MEM_PREFETCH_CFG4   0xe4
98 #define AHB_MEM_PREFETCH_CFG1   0xec
99 #define AHB_MEM_PREFETCH_CFG2   0xf0
100 #define AHB_MEM_PREFETCH_CFG6   0xcc
101 #define   PREFETCH_ENB  BIT(31)
102 #define   MST_ID(x)     (((x) & 0x1f) << 26)
103 #define   AHBDMA_MST_ID MST_ID(5)
104 #define   USB_MST_ID    MST_ID(6)
105 #define SDMMC4_MST_ID   MST_ID(12)
106 #define   USB2_MST_ID   MST_ID(18)
107 #define   USB3_MST_ID   MST_ID(17)
108 #define   SE_MST_ID     MST_ID(14)
109 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
110 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
111
112 phys_addr_t tegra_avp_kernel_start;
113 phys_addr_t tegra_avp_kernel_size;
114 phys_addr_t tegra_bootloader_fb_start;
115 phys_addr_t tegra_bootloader_fb_size;
116 phys_addr_t tegra_bootloader_fb2_start;
117 phys_addr_t tegra_bootloader_fb2_size;
118 phys_addr_t tegra_fb_start;
119 phys_addr_t tegra_fb_size;
120 phys_addr_t tegra_fb2_start;
121 phys_addr_t tegra_fb2_size;
122 phys_addr_t tegra_carveout_start;
123 phys_addr_t tegra_carveout_size;
124 phys_addr_t tegra_vpr_start;
125 phys_addr_t tegra_vpr_size;
126 phys_addr_t tegra_tsec_start;
127 phys_addr_t tegra_tsec_size;
128 phys_addr_t tegra_lp0_vec_start;
129 phys_addr_t tegra_lp0_vec_size;
130 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
131 phys_addr_t tegra_wb0_params_address;
132 phys_addr_t tegra_wb0_params_instances;
133 phys_addr_t tegra_wb0_params_block_size;
134 #endif
135
136 #ifdef CONFIG_TEGRA_NVDUMPER
137 unsigned long nvdumper_reserved;
138 #endif
139 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
140 unsigned long tegra_tzram_start;
141 unsigned long tegra_tzram_size;
142 #endif
143 bool tegra_lp0_vec_relocate;
144 unsigned long tegra_grhost_aperture = ~0ul;
145 static   bool is_tegra_debug_uart_hsport;
146 static struct board_info pmu_board_info;
147 static struct board_info display_board_info;
148 static int panel_id;
149 static struct board_info camera_board_info;
150 static int touch_vendor_id;
151 static int touch_panel_id;
152 static struct board_info io_board_info;
153 static struct board_info button_board_info;
154 static struct board_info joystick_board_info;
155 static struct board_info rightspeaker_board_info;
156 static struct board_info leftspeaker_board_info;
157 #ifdef CONFIG_TEGRA_USE_NCT
158 unsigned long tegra_nck_start;
159 unsigned long tegra_nck_size;
160 #endif
161
162 static int pmu_core_edp;
163 static int board_panel_type;
164 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
165 static int pwr_i2c_clk = 400;
166 static u8 power_config;
167 static u8 display_config;
168
169 #ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
170 static int tegra_split_mem_set;
171 #endif
172
173 /*
174  * Storage for debug-macro.S's state.
175  *
176  * This must be in .data not .bss so that it gets initialized each time the
177  * kernel is loaded. The data is declared here rather than debug-macro.S so
178  * that multiple inclusions of debug-macro.S point at the same data.
179  */
180 u32 tegra_uart_config[4] = {
181         /* Debug UART initialization required */
182         1,
183         /* Debug UART physical address */
184         0,
185         /* Debug UART virtual address */
186         0,
187         /* Scratch space for debug macro */
188         0,
189 };
190
191
192 #define NEVER_RESET 0
193 static DEFINE_SPINLOCK(ahb_lock);
194
195 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
196 {
197         unsigned long check;
198         int retry = 10;
199
200         /* Read and check if write is successful,
201          * if val doesn't match with read, retry write.
202          */
203         spin_lock(&ahb_lock);
204         do {
205                 writel(val, reg);
206                 check = readl(reg);
207                 if (likely(check == val))
208                         break;
209                 else
210                         pr_err("AHB register access fail for reg\n");
211         } while (--retry);
212         spin_unlock(&ahb_lock);
213 }
214
215 void tegra_assert_system_reset(char mode, const char *cmd)
216 {
217 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
218         pr_info("tegra_assert_system_reset() ignored.....");
219         do { } while (1);
220 #else
221         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
222         u32 reg;
223
224         reg = readl_relaxed(reset + PMC_SCRATCH0);
225         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
226         if (cmd) {
227                 if (!strcmp(cmd, "recovery"))
228                         reg |= RECOVERY_MODE;
229                 else if (!strcmp(cmd, "bootloader"))
230                         reg |= BOOTLOADER_MODE;
231                 else if (!strcmp(cmd, "forced-recovery"))
232                         reg |= FORCED_RECOVERY_MODE;
233                 else
234                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
235         }
236         else {
237                 /* Clearing SCRATCH0 31:30:1 on default reboot */
238                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
239         }
240         writel_relaxed(reg, reset + PMC_SCRATCH0);
241         reg = readl_relaxed(reset);
242         reg |= 0x10;
243         writel_relaxed(reg, reset);
244 #endif
245 }
246 static int modem_id;
247 static int commchip_id;
248 static int sku_override;
249 static int debug_uart_port_id;
250 static enum audio_codec_type audio_codec_name;
251 static enum image_type board_image_type = system_image;
252 static int max_cpu_current;
253 static int max_core_current;
254 static int emc_max_dvfs;
255 static int usb_port_owner_info;
256
257 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
258 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
259         /* name         parent          rate            enabled */
260         { "clk_m",      NULL,           0,              true },
261         { "emc",        NULL,           0,              true },
262         { "cpu",        NULL,           0,              true },
263         { "kfuse",      NULL,           0,              true },
264         { "fuse",       NULL,           0,              true },
265         { "sclk",       NULL,           0,              true },
266         { "pll_p",      NULL,           0,              true },
267         { "pll_p_out1", "pll_p",        0,              false },
268         { "pll_p_out3", "pll_p",        0,              false },
269 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
270         { "pll_m_out1", "pll_m",        275000000,      false },
271         { "pll_p_out2",  "pll_p",       102000000,      false },
272         { "sclk",        "pll_p_out2",  102000000,      true },
273         { "pll_p_out4",  "pll_p",       204000000,      true },
274         { "hclk",       "sclk",         102000000,      true },
275         { "pclk",       "hclk",         51000000,       true },
276         { "mselect",    "pll_p",        102000000,      true },
277         { "host1x",     "pll_p",        102000000,      false },
278         { "cl_dvfs_ref", "pll_p",       51000000,       true },
279         { "cl_dvfs_soc", "pll_p",       51000000,       true },
280         { "dsialp", "pll_p",    70000000,       false },
281         { "dsiblp", "pll_p",    70000000,       false },
282 #else
283         { "pll_m_out1", "pll_m",        275000000,      true },
284         { "pll_p_out2", "pll_p",        108000000,      false },
285         { "sclk",       "pll_p_out2",   108000000,      true },
286         { "pll_p_out4", "pll_p",        216000000,      true },
287         { "hclk",       "sclk",         108000000,      true },
288         { "pclk",       "hclk",         54000000,       true },
289         { "mselect",    "pll_p",        108000000,      true },
290         { "host1x",     "pll_p",        108000000,      false },
291         { "cl_dvfs_ref", "clk_m",       13000000,       false },
292         { "cl_dvfs_soc", "clk_m",       13000000,       false },
293 #endif
294 #ifdef CONFIG_TEGRA_SLOW_CSITE
295         { "csite",      "clk_m",        1000000,        true },
296 #else
297         { "csite",      NULL,           0,              true },
298 #endif
299         { "pll_u",      NULL,           480000000,      true },
300         { "pll_re_vco", NULL,           612000000,      false },
301         { "xusb_falcon_src",    "pll_p",        204000000,      false},
302         { "xusb_host_src",      "pll_p",        102000000,      false},
303         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
304         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
305         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
306         { "sdmmc1",     "pll_p",        48000000,       false},
307         { "sdmmc3",     "pll_p",        48000000,       false},
308         { "sdmmc4",     "pll_p",        48000000,       false},
309         { "sbc1.sclk",  NULL,           40000000,       false},
310         { "sbc2.sclk",  NULL,           40000000,       false},
311         { "sbc3.sclk",  NULL,           40000000,       false},
312         { "sbc4.sclk",  NULL,           40000000,       false},
313         { "sbc5.sclk",  NULL,           40000000,       false},
314         { "sbc6.sclk",  NULL,           40000000,       false},
315 #ifdef CONFIG_TEGRA_DUAL_CBUS
316         { "c2bus",      "pll_c2",       250000000,      false },
317         { "c3bus",      "pll_c3",       250000000,      false },
318         { "pll_c",      NULL,           624000000,      false },
319 #else
320         { "cbus",       "pll_c",        250000000,      false },
321 #endif
322         { "pll_c_out1", "pll_c",        150000000,      false },
323 #ifdef CONFIG_TEGRA_PLLM_SCALED
324         { "vi",         "pll_p",        0,              false},
325 #endif
326 #ifdef CONFIG_TEGRA_SOCTHERM
327         { "soc_therm",  "pll_p",        136000000,      false },
328         { "tsensor",    "clk_m",        500000,         false },
329 #endif
330         { "csite",      NULL,           0,              true },
331         { NULL,         NULL,           0,              0},
332 };
333 #endif
334 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
335 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
336         /* name         parent          rate            enabled */
337         { "clk_m",      NULL,           0,              true },
338         { "emc",        NULL,           0,              true },
339         { "cpu",        NULL,           0,              true },
340         { "kfuse",      NULL,           0,              true },
341         { "fuse",       NULL,           0,              true },
342         { "sclk",       NULL,           0,              true },
343 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
344         { "pll_p",      NULL,           0,              true },
345         { "pll_p_out1", "pll_p",        0,              false },
346         { "pll_p_out3", "pll_p",        0,              true },
347         { "pll_m_out1", "pll_m",        275000000,      false },
348         { "pll_p_out2", "pll_p",        102000000,      false },
349         { "sclk",       "pll_p_out2",   102000000,      true },
350         { "pll_p_out4", "pll_p",        204000000,      true },
351         { "host1x",     "pll_p",        102000000,      false },
352         { "cl_dvfs_ref", "pll_p",       54000000,       true },
353         { "cl_dvfs_soc", "pll_p",       54000000,       true },
354         { "hclk",       "sclk",         102000000,      true },
355         { "pclk",       "hclk",         51000000,       true },
356         { "wake.sclk",  NULL,           40000000,       true },
357         { "mselect",    "pll_p",        102000000,      true },
358 #else
359         { "pll_m_out1", "pll_m",        275000000,      true },
360         { "pll_p_out2", "pll_p",        108000000,      false },
361         { "sclk",       "pll_p_out2",   108000000,      true },
362         { "pll_p_out4", "pll_p",        216000000,      true },
363         { "hclk",       "sclk",         108000000,      true },
364         { "pclk",       "hclk",         54000000,       true },
365         { "mselect",    "pll_p",        108000000,      true },
366         { "host1x",     "pll_p",        108000000,      false },
367         { "cl_dvfs_ref", "clk_m",       13000000,       false },
368         { "cl_dvfs_soc", "clk_m",       13000000,       false },
369 #endif
370 #ifdef CONFIG_TEGRA_SLOW_CSITE
371         { "csite",      "clk_m",        1000000,        true },
372 #else
373         { "csite",      NULL,           0,              true },
374 #endif
375         { "pll_u",      NULL,           480000000,      true },
376         { "pll_re_vco", NULL,           612000000,      true },
377         { "xusb_falcon_src",    "pll_p",        204000000,      false},
378         { "xusb_host_src",      "pll_p",        102000000,      false},
379         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
380         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
381         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
382         { "sdmmc1",     "pll_p",        48000000,       false},
383         { "sdmmc3",     "pll_p",        48000000,       false},
384         { "sdmmc4",     "pll_p",        48000000,       false},
385         { "sbc1.sclk",  NULL,           40000000,       false},
386         { "sbc2.sclk",  NULL,           40000000,       false},
387         { "sbc3.sclk",  NULL,           40000000,       false},
388         { "sbc4.sclk",  NULL,           40000000,       false},
389         { "sbc5.sclk",  NULL,           40000000,       false},
390         { "sbc6.sclk",  NULL,           40000000,       false},
391 #ifdef CONFIG_TEGRA_PLLM_SCALED
392         { "vi",         "pll_p",        0,              false},
393 #endif
394 #ifdef CONFIG_TEGRA_SOCTHERM
395         { "soc_therm",  "pll_p",        51000000,       false },
396         { "tsensor",    "clk_m",        500000,         false },
397 #endif
398 #if defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
399         { "vde",        "pll_c3",       48400000,       true},
400 #endif
401         { NULL,         NULL,           0,              0},
402 };
403 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
404 #ifdef CONFIG_TEGRA_DUAL_CBUS
405         { "c2bus",      "pll_c2",       250000000,      false },
406         { "c3bus",      "pll_c3",       250000000,      false },
407         { "pll_c",      NULL,           624000000,      false },
408 #else
409         { "cbus",       "pll_c",        250000000,      false },
410 #endif
411         { "pll_c_out1", "pll_c",        150000000,      false },
412         { NULL,         NULL,           0,              0},
413 };
414 #endif
415 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
416 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
417         /* name         parent          rate            enabled */
418         { "osc",        NULL,           0,              true },
419         { "clk_m",      "osc",          0,              true },
420         { "emc",        NULL,           0,              true },
421         { "cpu",        NULL,           0,              true },
422         { "kfuse",      NULL,           0,              true },
423         { "fuse",       NULL,           0,              true },
424         { "sclk",       NULL,           0,              true },
425 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
426         { "pll_p",      NULL,           0,              true },
427         { "pll_p_out1", "pll_p",        0,              false },
428         { "pll_p_out3", "pll_p",        0,              true },
429         { "pll_m_out1", "pll_m",        275000000,      false },
430         { "pll_p_out2",  "pll_p",       102000000,      false },
431         { "sclk",        "pll_p_out2",  102000000,      true },
432         { "pll_p_out4",  "pll_p",       204000000,      true },
433         { "hclk",       "sclk",         102000000,      true },
434         { "pclk",       "hclk",         51000000,       true },
435         { "mselect",    "pll_p",        102000000,      true },
436         { "host1x",     "pll_p",        102000000,      false },
437         { "cl_dvfs_ref", "pll_p",       51000000,       true },
438         { "cl_dvfs_soc", "pll_p",       51000000,       true },
439 #else
440         { "pll_p",      NULL,           0,              true },
441         { "pll_p_out1", "pll_p",        0,              false },
442         { "pll_p_out3", "pll_p",        0,              true },
443         { "pll_m_out1", "pll_m",        275000000,      true },
444         { "pll_p_out2", "pll_p",        108000000,      false },
445         { "sclk",       "pll_p_out2",   108000000,      true },
446         { "pll_p_out4", "pll_p",        216000000,      true },
447         { "host1x",     "pll_p",        108000000,      false },
448         { "cl_dvfs_ref", "clk_m",       13000000,       false },
449         { "cl_dvfs_soc", "clk_m",       13000000,       false },
450         { "hclk",       "sclk",         108000000,      true },
451         { "pclk",       "hclk",         54000000,       true },
452         { "wake.sclk",  NULL,           250000000,      true },
453         { "mselect",    "pll_p",        108000000,      true },
454 #endif
455 #ifdef CONFIG_TEGRA_SLOW_CSITE
456         { "csite",      "clk_m",        1000000,        true },
457 #else
458         { "csite",      NULL,           0,              true },
459 #endif
460         { "pll_u",      NULL,           480000000,      false },
461         { "sdmmc1",     "pll_p",        48000000,       false},
462         { "sdmmc3",     "pll_p",        48000000,       false},
463         { "sdmmc4",     "pll_p",        48000000,       false},
464         { "mon.avp",    NULL,           80000000,       true },
465         { "sbc1.sclk",  NULL,           20000000,       false},
466         { "sbc2.sclk",  NULL,           20000000,       false},
467         { "sbc3.sclk",  NULL,           20000000,       false},
468         { "msenc",      "pll_p",        108000000,      false },
469         { "tsec",       "pll_p",        108000000,      false },
470         { "mc_capa",    "emc",          0,              true },
471         { "mc_cbpa",    "emc",          0,              true },
472 #ifdef CONFIG_TEGRA_SOCTHERM
473         { "soc_therm",  "pll_p",        51000000,       false },
474         { "tsensor",    "clk_m",        400000,         false },
475 #endif
476         { NULL,         NULL,           0,              0},
477 };
478 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
479         /* Initialize c2bus, c3bus, or cbus at the end of the list
480          * after all the clocks are moved under the proper parents.
481          */
482 #ifdef CONFIG_TEGRA_DUAL_CBUS
483         { "c2bus",      "pll_c2",       200000000,      false },
484         { "c3bus",      "pll_c3",       200000000,      false },
485         { "pll_c",      NULL,           768000000,      false },
486 #else
487         { "cbus",       "pll_c",        200000000,      false },
488 #endif
489         { "pll_c_out1", "pll_c",        100000000,      false },
490         { NULL,         NULL,           0,              0},
491 };
492 #endif
493
494 #ifdef CONFIG_CACHE_L2X0
495 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
496 static void tegra_cache_smc(bool enable, u32 arg)
497 {
498         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
499         bool need_affinity_switch;
500         bool can_switch_affinity;
501         bool l2x0_enabled;
502         cpumask_t local_cpu_mask;
503         cpumask_t saved_cpu_mask;
504         unsigned long flags;
505         long ret;
506
507         /*
508          * ISSUE : Some registers of PL310 controler must be written
509          *              from Secure context (and from CPU0)!
510          *
511          * When called form Normal we obtain an abort or do nothing.
512          * Instructions that must be called in Secure:
513          *      - Write to Control register (L2X0_CTRL==0x100)
514          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
515          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
516          *              mandatory at boot time.
517          *      - Tag and Data RAM Latency Control Registers
518          *              (0x108 & 0x10C) must be written in Secure.
519          */
520         need_affinity_switch = (smp_processor_id() != 0);
521         can_switch_affinity = !irqs_disabled();
522
523         WARN_ON(need_affinity_switch && !can_switch_affinity);
524         if (need_affinity_switch && can_switch_affinity) {
525                 cpu_set(0, local_cpu_mask);
526                 sched_getaffinity(0, &saved_cpu_mask);
527                 ret = sched_setaffinity(0, &local_cpu_mask);
528                 WARN_ON(ret != 0);
529         }
530
531         local_irq_save(flags);
532         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
533         if (enable && !l2x0_enabled)
534                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
535         else if (!enable && l2x0_enabled)
536                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
537         local_irq_restore(flags);
538
539         if (need_affinity_switch && can_switch_affinity) {
540                 ret = sched_setaffinity(0, &saved_cpu_mask);
541                 WARN_ON(ret != 0);
542         }
543 }
544
545 static void tegra_l2x0_disable(void)
546 {
547         unsigned long flags;
548         static u32 l2x0_way_mask;
549
550         if (!l2x0_way_mask) {
551                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
552                 u32 aux_ctrl;
553                 u32 ways;
554
555                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
556                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
557                 l2x0_way_mask = (1 << ways) - 1;
558         }
559
560         local_irq_save(flags);
561         tegra_cache_smc(false, l2x0_way_mask);
562         local_irq_restore(flags);
563 }
564 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
565
566 void tegra_init_cache(bool init)
567 {
568         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
569         u32 aux_ctrl;
570 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
571         u32 cache_type;
572         u32 tag_latency, data_latency;
573 #endif
574
575 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
576         /* issue the SMC to enable the L2 */
577         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
578         trace_smc_init_cache(NVSEC_SMC_START);
579         tegra_cache_smc(true, aux_ctrl);
580         trace_smc_init_cache(NVSEC_SMC_DONE);
581
582         /* after init, reread aux_ctrl and register handlers */
583         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
584         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
585
586         /* override outer_disable() with our disable */
587         outer_cache.disable = tegra_l2x0_disable;
588 #else
589 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
590         tag_latency = 0x331;
591         data_latency = 0x441;
592 #else
593 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
594         if (is_lp_cluster()) {
595                 tag_latency = tegra_cpu_c1_l2_tag_latency;
596                 data_latency = tegra_cpu_c1_l2_data_latency;
597         } else {
598                 tag_latency = tegra_cpu_c0_l2_tag_latency;
599                 data_latency = tegra_cpu_c0_l2_data_latency;
600         }
601 #else
602         tag_latency = 0x770;
603         data_latency = 0x770;
604 #endif
605 #endif
606         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
607         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
608
609 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
610 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
611 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
612         /* Enable double line fill */
613         writel(0x40000007, p + L2X0_PREFETCH_CTRL);
614 #else
615         writel(0x7, p + L2X0_PREFETCH_CTRL);
616 #endif
617         writel(0x3, p + L2X0_POWER_CTRL);
618 #endif
619 #endif
620         cache_type = readl(p + L2X0_CACHE_TYPE);
621         aux_ctrl = (cache_type & 0x700) << (17-8);
622         aux_ctrl |= 0x7C400001;
623         if (init) {
624                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
625         } else {
626                 u32 tmp;
627
628                 tmp = aux_ctrl;
629                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
630                 aux_ctrl &= 0x8200c3fe;
631                 aux_ctrl |= tmp;
632                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
633         }
634         l2x0_enable();
635 #endif
636 }
637 #endif
638
639 static void __init tegra_perf_init(void)
640 {
641         u32 reg;
642
643 #ifdef CONFIG_ARM64
644         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
645         reg >>= 11;
646         reg = (1 << (reg & 0x1f))-1;
647         reg |= 0x80000000;
648         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
649         reg = 1;
650         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
651 #else
652         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
653         reg >>= 11;
654         reg = (1 << (reg & 0x1f))-1;
655         reg |= 0x80000000;
656         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
657         reg = 1;
658         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
659 #endif
660 }
661
662 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
663 static void __init tegra_ramrepair_init(void)
664 {
665         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
666                 u32 reg;
667                 reg = readl(FLOW_CTRL_RAM_REPAIR);
668                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
669                 writel(reg, FLOW_CTRL_RAM_REPAIR);
670         }
671 }
672 #endif
673
674 static void __init tegra_init_power(void)
675 {
676 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
677         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
678 #endif
679 #if defined(CONFIG_ARCH_TEGRA_HAS_PCIE) && \
680                         !defined(CONFIG_TEGRA_PCIE_SKIP_POWERGATING)
681         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
682 #endif
683 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
684         /* some partitions need to be powergated by default for t11x */
685         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
686         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
687         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
688 #endif
689 }
690
691 static inline unsigned long gizmo_readl(unsigned long offset)
692 {
693         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
694 }
695
696 static inline void gizmo_writel(unsigned long value, unsigned long offset)
697 {
698         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
699 }
700
701 static void __init tegra_init_ahb_gizmo_settings(void)
702 {
703         unsigned long val;
704
705         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
706         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
707
708         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11 &&
709                 tegra_revision == TEGRA_REVISION_A02)
710                 val |= WR_WAIT_COMMIT_ON_1K;
711 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
712         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
713 #endif
714         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
715
716         val = gizmo_readl(AHB_GIZMO_USB);
717         val |= IMMEDIATE;
718         gizmo_writel(val, AHB_GIZMO_USB);
719
720         val = gizmo_readl(AHB_GIZMO_USB2);
721         val |= IMMEDIATE;
722         gizmo_writel(val, AHB_GIZMO_USB2);
723
724         val = gizmo_readl(AHB_GIZMO_USB3);
725         val |= IMMEDIATE;
726         gizmo_writel(val, AHB_GIZMO_USB3);
727
728         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
729         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
730                                 | AHB_PRIORITY_WEIGHT(7);
731 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
732         val |= PRIORITY_SELECT_SE;
733 #endif
734
735         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
736
737         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
738         val &= ~MST_ID(~0);
739         val |= PREFETCH_ENB | AHBDMA_MST_ID |
740                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
741         ahb_gizmo_writel(val,
742                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
743
744         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
745         val &= ~MST_ID(~0);
746         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
747                 INACTIVITY_TIMEOUT(0x1000);
748 #if !defined(CONFIG_ANDROID)
749         val &= ~USB_MST_ID;
750 #endif
751         ahb_gizmo_writel(val,
752                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
753
754         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
755         val &= ~MST_ID(~0);
756         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
757                 INACTIVITY_TIMEOUT(0x1000);
758 #if !defined(CONFIG_ANDROID)
759         val &= ~USB3_MST_ID;
760 #endif
761         ahb_gizmo_writel(val,
762                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
763
764         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
765         val &= ~MST_ID(~0);
766         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
767                 INACTIVITY_TIMEOUT(0x1000);
768         ahb_gizmo_writel(val,
769                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
770
771         /*
772          * SDMMC controller is removed from AHB interface in T124 and
773          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
774          * in T11x and T14x SOCs.
775          */
776 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
777         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
778         val &= ~MST_ID(~0);
779         val |= PREFETCH_ENB | SDMMC4_MST_ID;
780         val &= ~SDMMC4_MST_ID;
781         ahb_gizmo_writel(val,
782                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
783 #endif
784
785 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
786         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
787         val &= ~MST_ID(~0);
788         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
789                 INACTIVITY_TIMEOUT(0x1000);
790         ahb_gizmo_writel(val,
791                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
792 #endif
793 }
794
795 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
796 void __init tegra20_init_early(void)
797 {
798 #ifndef CONFIG_SMP
799         /* For SMP system, initializing the reset handler here is too
800            late. For non-SMP systems, the function that calls the reset
801            handler initializer is not called, so do it here for non-SMP. */
802         tegra_cpu_reset_handler_init();
803 #endif
804         tegra_apb_io_init();
805         tegra_perf_init();
806         tegra_init_fuse();
807         tegra_init_cache(true);
808         tegra_pmc_init();
809         tegra_powergate_init();
810         tegra20_hotplug_init();
811         tegra_init_power();
812         tegra_init_ahb_gizmo_settings();
813         tegra_init_debug_uart_rate();
814         tegra_ram_console_debug_reserve(SZ_1M);
815 }
816 #endif
817 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
818 void __init tegra30_init_early(void)
819 {
820         u32 speedo;
821         u32 tag_latency, data_latency;
822
823 #ifndef CONFIG_SMP
824         /* For SMP system, initializing the reset handler here is too
825            late. For non-SMP systems, the function that calls the reset
826            handler initializer is not called, so do it here for non-SMP. */
827         tegra_cpu_reset_handler_init();
828 #endif
829         tegra_apb_io_init();
830         tegra_perf_init();
831         tegra_init_fuse();
832         /*
833          * Store G/LP cluster L2 latencies to IRAM and DRAM
834          */
835         tegra_cpu_c1_l2_tag_latency = 0x221;
836         tegra_cpu_c1_l2_data_latency = 0x221;
837         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
838         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
839         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
840         speedo = tegra_cpu_speedo_id();
841         if (speedo == 4 || speedo == 5 || speedo == 6 ||
842             speedo == 12 || speedo == 13) {
843                 tag_latency = 0x442;
844                 data_latency = 0x552;
845         } else {
846                 tag_latency = 0x441;
847                 data_latency = 0x551;
848         }
849         tegra_cpu_c0_l2_tag_latency = tag_latency;
850         tegra_cpu_c0_l2_data_latency = data_latency;
851         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
852         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
853         tegra_init_cache(true);
854         tegra_pmc_init();
855         tegra_powergate_init();
856         tegra30_hotplug_init();
857         tegra_init_power();
858         tegra_init_ahb_gizmo_settings();
859         tegra_init_debug_uart_rate();
860         tegra_ram_console_debug_reserve(SZ_1M);
861
862         init_dma_coherent_pool_size(SZ_1M);
863 }
864 #endif
865 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
866 void __init tegra11x_init_early(void)
867 {
868 #ifndef CONFIG_SMP
869         /* For SMP system, initializing the reset handler here is too
870            late. For non-SMP systems, the function that calls the reset
871            handler initializer is not called, so do it here for non-SMP. */
872         tegra_cpu_reset_handler_init();
873 #endif
874         tegra_apb_io_init();
875         tegra_perf_init();
876         tegra_init_fuse();
877         tegra_ramrepair_init();
878         tegra11x_init_clocks();
879         tegra11x_init_dvfs();
880         tegra_common_init_clock();
881         tegra_clk_init_from_table(tegra11x_clk_init_table);
882         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
883         tegra11x_clk_init_la();
884         tegra_pmc_init();
885         tegra_powergate_init();
886         tegra30_hotplug_init();
887         tegra_init_power();
888         tegra_init_ahb_gizmo_settings();
889         tegra_init_debug_uart_rate();
890
891         init_dma_coherent_pool_size(SZ_2M);
892 }
893 #endif
894 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
895 void __init tegra12x_init_early(void)
896 {
897 #ifndef CONFIG_SMP
898         /* For SMP system, initializing the reset handler here is too
899            late. For non-SMP systems, the function that calls the reset
900            handler initializer is not called, so do it here for non-SMP. */
901         tegra_cpu_reset_handler_init();
902 #endif
903         tegra_apb_io_init();
904         tegra_init_fuse();
905         tegra_ramrepair_init();
906         tegra12x_init_clocks();
907         tegra12x_init_dvfs();
908         tegra_common_init_clock();
909         tegra_clk_init_from_table(tegra12x_clk_init_table);
910         tegra_init_cache(true);
911         tegra_pmc_init();
912         tegra_powergate_init();
913         tegra_init_power();
914         tegra_init_ahb_gizmo_settings();
915         tegra_init_debug_uart_rate();
916 }
917 #endif
918 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
919 void __init tegra14x_init_early(void)
920 {
921 #ifndef CONFIG_SMP
922         /* For SMP system, initializing the reset handler here is too
923            late. For non-SMP systems, the function that calls the reset
924            handler initializer is not called, so do it here for non-SMP. */
925         tegra_cpu_reset_handler_init();
926 #endif
927         tegra_apb_io_init();
928         tegra_perf_init();
929         tegra_init_fuse();
930         tegra_ramrepair_init();
931         tegra14x_init_clocks();
932         tegra14x_init_dvfs();
933         tegra_common_init_clock();
934         tegra_clk_init_from_table(tegra14x_clk_init_table);
935         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
936         tegra_cpu_c1_l2_tag_latency = 0x110;
937         tegra_cpu_c1_l2_data_latency = 0x331;
938         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
939         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
940         tegra_cpu_c0_l2_tag_latency = 0x111;
941         tegra_cpu_c0_l2_data_latency = 0x441;
942         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
943         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
944         tegra_init_cache(true);
945         tegra_pmc_init();
946         tegra_powergate_init();
947         tegra30_hotplug_init();
948         tegra_init_power();
949         tegra_init_ahb_gizmo_settings();
950         tegra_init_debug_uart_rate();
951         tegra_ram_console_debug_reserve(SZ_1M);
952 }
953 #endif
954 static int __init tegra_lp0_vec_arg(char *options)
955 {
956         char *p = options;
957
958         tegra_lp0_vec_size = memparse(p, &p);
959         if (*p == '@')
960                 tegra_lp0_vec_start = memparse(p+1, &p);
961         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
962                 tegra_lp0_vec_size = 0;
963                 tegra_lp0_vec_start = 0;
964         }
965
966         return 0;
967 }
968 early_param("lp0_vec", tegra_lp0_vec_arg);
969
970 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
971 static int __init tegra_wb0_params_arg(char *options)
972 {
973         char *p = options;
974
975         tegra_wb0_params_address = memparse(p, &p);
976         if (*p == ',')
977                 tegra_wb0_params_instances = memparse(p+1, &p);
978         if (*p == ',')
979                 tegra_wb0_params_block_size = memparse(p+1, &p);
980
981         return 0;
982 }
983 early_param("wb0_params", tegra_wb0_params_arg);
984 #endif
985
986 #ifdef CONFIG_TEGRA_NVDUMPER
987 static int __init tegra_nvdumper_arg(char *options)
988 {
989         char *p = options;
990
991         nvdumper_reserved = memparse(p, &p);
992         return 0;
993 }
994 early_param("nvdumper_reserved", tegra_nvdumper_arg);
995 #endif
996
997 static int __init tegra_bootloader_fb_arg(char *options)
998 {
999         char *p = options;
1000
1001         tegra_bootloader_fb_size = memparse(p, &p);
1002         if (*p == '@')
1003                 tegra_bootloader_fb_start = memparse(p+1, &p);
1004
1005         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1006                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1007
1008         return 0;
1009 }
1010 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1011
1012 static int __init tegra_bootloader_fb2_arg(char *options)
1013 {
1014         char *p = options;
1015
1016         tegra_bootloader_fb2_size = memparse(p, &p);
1017         if (*p == '@')
1018                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1019
1020         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1021                 (u64)tegra_bootloader_fb2_size,
1022                 (u64)tegra_bootloader_fb2_start);
1023
1024         return 0;
1025 }
1026 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1027
1028 static int __init tegra_sku_override(char *id)
1029 {
1030         char *p = id;
1031
1032         sku_override = memparse(p, &p);
1033
1034         return 0;
1035 }
1036 early_param("sku_override", tegra_sku_override);
1037
1038 int tegra_get_sku_override(void)
1039 {
1040         return sku_override;
1041 }
1042
1043 static int __init tegra_vpr_arg(char *options)
1044 {
1045         char *p = options;
1046
1047         tegra_vpr_size = memparse(p, &p);
1048         if (*p == '@')
1049                 tegra_vpr_start = memparse(p+1, &p);
1050         pr_info("Found vpr, start=0x%llx size=%llx",
1051                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1052         return 0;
1053 }
1054 early_param("vpr", tegra_vpr_arg);
1055
1056 static int __init tegra_tsec_arg(char *options)
1057 {
1058         char *p = options;
1059
1060         tegra_tsec_size = memparse(p, &p);
1061         if (*p == '@')
1062                 tegra_tsec_start = memparse(p+1, &p);
1063         pr_info("Found tsec, start=0x%llx size=%llx",
1064                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1065         return 0;
1066 }
1067 early_param("tsec", tegra_tsec_arg);
1068
1069 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1070 static int __init tegra_tzram_arg(char *options)
1071 {
1072         char *p = options;
1073
1074         tegra_tzram_size = memparse(p, &p);
1075         if (*p == '@')
1076                 tegra_tzram_start = memparse(p + 1, &p);
1077         return 0;
1078 }
1079 early_param("tzram", tegra_tzram_arg);
1080 #endif
1081
1082 #ifdef CONFIG_TEGRA_USE_NCT
1083 static int __init tegra_nck_arg(char *options)
1084 {
1085         char *p = options;
1086
1087         tegra_nck_size = memparse(p, &p);
1088         if (*p == '@')
1089                 tegra_nck_start = memparse(p+1, &p);
1090         if (!tegra_nck_size || !tegra_nck_start) {
1091                 tegra_nck_size = 0;
1092                 tegra_nck_start = 0;
1093         }
1094
1095         return 0;
1096 }
1097 early_param("nck", tegra_nck_arg);
1098 #endif  /* CONFIG_TEGRA_USE_NCT */
1099
1100 enum panel_type get_panel_type(void)
1101 {
1102         return board_panel_type;
1103 }
1104 static int __init tegra_board_panel_type(char *options)
1105 {
1106         if (!strcmp(options, "lvds"))
1107                 board_panel_type = panel_type_lvds;
1108         else if (!strcmp(options, "dsi"))
1109                 board_panel_type = panel_type_dsi;
1110         else
1111                 return 0;
1112         return 1;
1113 }
1114 __setup("panel=", tegra_board_panel_type);
1115
1116 int tegra_get_board_panel_id(void)
1117 {
1118         return panel_id;
1119 }
1120 static int __init tegra_board_panel_id(char *options)
1121 {
1122         char *p = options;
1123         panel_id = memparse(p, &p);
1124         return panel_id;
1125 }
1126 __setup("display_panel=", tegra_board_panel_id);
1127
1128 int tegra_get_touch_vendor_id(void)
1129 {
1130         return touch_vendor_id;
1131 }
1132 int tegra_get_touch_panel_id(void)
1133 {
1134         return touch_panel_id;
1135 }
1136 static int __init tegra_touch_id(char *options)
1137 {
1138         char *p = options;
1139         touch_vendor_id = memparse(p, &p);
1140         if (*p == '@')
1141                 touch_panel_id = memparse(p+1, &p);
1142         return 1;
1143 }
1144 __setup("touch_id=", tegra_touch_id);
1145
1146 u8 get_power_config(void)
1147 {
1148         return power_config;
1149 }
1150 static int __init tegra_board_power_config(char *options)
1151 {
1152         char *p = options;
1153         power_config = memparse(p, &p);
1154         return 1;
1155 }
1156 __setup("power-config=", tegra_board_power_config);
1157
1158 u8 get_display_config(void)
1159 {
1160         return display_config;
1161 }
1162 static int __init tegra_board_display_config(char *options)
1163 {
1164         char *p = options;
1165         display_config = memparse(p, &p);
1166         return 1;
1167 }
1168 __setup("display-config=", tegra_board_display_config);
1169
1170 enum power_supply_type get_power_supply_type(void)
1171 {
1172         return pow_supply_type;
1173 }
1174 static int __init tegra_board_power_supply_type(char *options)
1175 {
1176         if (!strcmp(options, "Adapter"))
1177                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1178         if (!strcmp(options, "Mains"))
1179                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1180         else if (!strcmp(options, "Battery"))
1181                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1182         else
1183                 return 0;
1184         return 1;
1185 }
1186 __setup("power_supply=", tegra_board_power_supply_type);
1187
1188 int get_core_edp(void)
1189 {
1190         return pmu_core_edp;
1191 }
1192 static int __init tegra_pmu_core_edp(char *options)
1193 {
1194         char *p = options;
1195         int core_edp = memparse(p, &p);
1196         if (core_edp != 0)
1197                 pmu_core_edp = core_edp;
1198         return 0;
1199 }
1200 early_param("core_edp_mv", tegra_pmu_core_edp);
1201
1202 int get_maximum_cpu_current_supported(void)
1203 {
1204         return max_cpu_current;
1205 }
1206 static int __init tegra_max_cpu_current(char *options)
1207 {
1208         char *p = options;
1209         max_cpu_current = memparse(p, &p);
1210         return 1;
1211 }
1212 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1213
1214 int get_maximum_core_current_supported(void)
1215 {
1216         return max_core_current;
1217 }
1218 static int __init tegra_max_core_current(char *options)
1219 {
1220         char *p = options;
1221         max_core_current = memparse(p, &p);
1222         return 1;
1223 }
1224 __setup("core_edp_ma=", tegra_max_core_current);
1225
1226 int get_emc_max_dvfs(void)
1227 {
1228         return emc_max_dvfs;
1229 }
1230 static int __init tegra_emc_max_dvfs(char *options)
1231 {
1232         char *p = options;
1233         emc_max_dvfs = memparse(p, &p);
1234         return 1;
1235 }
1236 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1237
1238 static int __init tegra_debug_uartport(char *info)
1239 {
1240         char *p = info;
1241         unsigned long long port_id;
1242         if (!strncmp(p, "hsport", 6))
1243                 is_tegra_debug_uart_hsport = true;
1244         else if (!strncmp(p, "lsport", 6))
1245                 is_tegra_debug_uart_hsport = false;
1246
1247         if (p[6] == ',') {
1248                 if (p[7] == '-') {
1249                         debug_uart_port_id = -1;
1250                 } else {
1251                         port_id = memparse(p + 7, &p);
1252                         debug_uart_port_id = (int) port_id;
1253                 }
1254         } else {
1255                 debug_uart_port_id = -1;
1256         }
1257
1258         return 1;
1259 }
1260
1261 bool is_tegra_debug_uartport_hs(void)
1262 {
1263         return is_tegra_debug_uart_hsport;
1264 }
1265
1266 int get_tegra_uart_debug_port_id(void)
1267 {
1268         return debug_uart_port_id;
1269 }
1270 __setup("debug_uartport=", tegra_debug_uartport);
1271
1272 static int __init tegra_image_type(char *options)
1273 {
1274         if (!strcmp(options, "RCK"))
1275                 board_image_type = rck_image;
1276
1277         return 0;
1278 }
1279
1280 enum image_type get_tegra_image_type(void)
1281 {
1282         return board_image_type;
1283 }
1284
1285 __setup("image=", tegra_image_type);
1286
1287 static int __init tegra_audio_codec_type(char *info)
1288 {
1289         char *p = info;
1290         if (!strncmp(p, "wm8903", 6))
1291                 audio_codec_name = audio_codec_wm8903;
1292         else
1293                 audio_codec_name = audio_codec_none;
1294
1295         return 1;
1296 }
1297
1298 enum audio_codec_type get_audio_codec_type(void)
1299 {
1300         return audio_codec_name;
1301 }
1302 __setup("audio_codec=", tegra_audio_codec_type);
1303
1304 static int tegra_get_pwr_i2c_clk_rate(char *options)
1305 {
1306         int clk = simple_strtol(options, NULL, 16);
1307         if (clk != 0)
1308                 pwr_i2c_clk = clk;
1309         return 0;
1310 }
1311
1312 int get_pwr_i2c_clk_rate(void)
1313 {
1314         return pwr_i2c_clk;
1315 }
1316 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1317
1318 static bool pmic_wdt_disable;
1319 bool is_pmic_wdt_disabled_at_boot(void)
1320 {
1321         return pmic_wdt_disable;
1322 }
1323
1324 static int parse_arg_pmic_wdt_disable(char *options)
1325 {
1326         /* no kernel command line argument "watchdog" interpreted as
1327          * watchdog enable
1328          */
1329         pmic_wdt_disable = false;
1330         if (!(strcmp(options, "enable")))
1331                 pmic_wdt_disable = false;
1332         else if (!(strcmp(options, "disable")))
1333                 pmic_wdt_disable = true;
1334         /* kernel command line from fastboot does not support
1335          * other values
1336          */
1337
1338         return 0;
1339 }
1340 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1341
1342 void tegra_get_board_info(struct board_info *bi)
1343 {
1344 #ifdef CONFIG_OF
1345         struct device_node *board_info;
1346         u32 prop_val;
1347         int err;
1348
1349         board_info = of_find_node_by_path("/chosen/board_info");
1350         if (!IS_ERR_OR_NULL(board_info)) {
1351                 memset(bi, 0, sizeof(*bi));
1352
1353                 err = of_property_read_u32(board_info, "id", &prop_val);
1354                 if (err)
1355                         pr_err("failed to read /chosen/board_info/id\n");
1356                 else
1357                         bi->board_id = prop_val;
1358
1359                 err = of_property_read_u32(board_info, "sku", &prop_val);
1360                 if (err)
1361                         pr_err("failed to read /chosen/board_info/sku\n");
1362                 else
1363                         bi->sku = prop_val;
1364
1365                 err = of_property_read_u32(board_info, "fab", &prop_val);
1366                 if (err)
1367                         pr_err("failed to read /chosen/board_info/fab\n");
1368                 else
1369                         bi->fab = prop_val;
1370
1371                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1372                 if (err)
1373                         pr_err("failed to read /chosen/board_info/major_revision\n");
1374                 else
1375                         bi->major_revision = prop_val;
1376
1377                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1378                 if (err)
1379                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1380                 else
1381                         bi->minor_revision = prop_val;
1382 #ifndef CONFIG_ARM64
1383                 system_serial_high = (bi->board_id << 16) | bi->sku;
1384                 system_serial_low = (bi->fab << 24) |
1385                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1386 #endif
1387         } else {
1388 #endif
1389 #ifdef CONFIG_ARM64
1390                 /* FIXME:
1391                  * use dummy values for now as system_serial_high/low
1392                  * are gone in arm64.
1393                  */
1394                 bi->board_id = 0xDEAD;
1395                 bi->sku = 0xDEAD;
1396                 bi->fab = 0xDD;
1397                 bi->major_revision = 0xDD;
1398                 bi->minor_revision = 0xDD;
1399 #else
1400                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1401                 bi->sku = (system_serial_high) & 0xFFFF;
1402                 bi->fab = (system_serial_low >> 24) & 0xFF;
1403                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1404                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1405 #endif
1406 #ifdef CONFIG_OF
1407         }
1408 #endif
1409 }
1410
1411 static int __init tegra_pmu_board_info(char *info)
1412 {
1413         char *p = info;
1414         pmu_board_info.board_id = memparse(p, &p);
1415         pmu_board_info.sku = memparse(p+1, &p);
1416         pmu_board_info.fab = memparse(p+1, &p);
1417         pmu_board_info.major_revision = memparse(p+1, &p);
1418         pmu_board_info.minor_revision = memparse(p+1, &p);
1419         return 1;
1420 }
1421
1422 void tegra_get_pmu_board_info(struct board_info *bi)
1423 {
1424         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1425 }
1426
1427 __setup("pmuboard=", tegra_pmu_board_info);
1428
1429 static int __init tegra_display_board_info(char *info)
1430 {
1431         char *p = info;
1432         display_board_info.board_id = memparse(p, &p);
1433         display_board_info.sku = memparse(p+1, &p);
1434         display_board_info.fab = memparse(p+1, &p);
1435         display_board_info.major_revision = memparse(p+1, &p);
1436         display_board_info.minor_revision = memparse(p+1, &p);
1437         return 1;
1438 }
1439
1440 void tegra_get_display_board_info(struct board_info *bi)
1441 {
1442         memcpy(bi, &display_board_info, sizeof(struct board_info));
1443 }
1444
1445 __setup("displayboard=", tegra_display_board_info);
1446
1447 static int __init tegra_camera_board_info(char *info)
1448 {
1449         char *p = info;
1450         camera_board_info.board_id = memparse(p, &p);
1451         camera_board_info.sku = memparse(p+1, &p);
1452         camera_board_info.fab = memparse(p+1, &p);
1453         camera_board_info.major_revision = memparse(p+1, &p);
1454         camera_board_info.minor_revision = memparse(p+1, &p);
1455         return 1;
1456 }
1457
1458 void tegra_get_camera_board_info(struct board_info *bi)
1459 {
1460         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1461 }
1462
1463 __setup("cameraboard=", tegra_camera_board_info);
1464
1465 static int __init tegra_leftspeaker_board_info(char *info)
1466 {
1467         char *p = info;
1468         leftspeaker_board_info.board_id = memparse(p, &p);
1469         leftspeaker_board_info.sku = memparse(p+1, &p);
1470         leftspeaker_board_info.fab = memparse(p+1, &p);
1471         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1472         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1473         return 1;
1474 }
1475
1476 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1477 {
1478         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1479 }
1480
1481 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1482
1483 static int __init tegra_rightspeaker_board_info(char *info)
1484 {
1485         char *p = info;
1486         rightspeaker_board_info.board_id = memparse(p, &p);
1487         rightspeaker_board_info.sku = memparse(p+1, &p);
1488         rightspeaker_board_info.fab = memparse(p+1, &p);
1489         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1490         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1491         return 1;
1492 }
1493
1494 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1495 {
1496         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1497 }
1498
1499 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1500
1501 static int __init tegra_joystick_board_info(char *info)
1502 {
1503         char *p = info;
1504         joystick_board_info.board_id = memparse(p, &p);
1505         joystick_board_info.sku = memparse(p+1, &p);
1506         joystick_board_info.fab = memparse(p+1, &p);
1507         joystick_board_info.major_revision = memparse(p+1, &p);
1508         joystick_board_info.minor_revision = memparse(p+1, &p);
1509         return 1;
1510 }
1511
1512 void tegra_get_joystick_board_info(struct board_info *bi)
1513 {
1514         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1515 }
1516
1517 __setup("joystickboard=", tegra_joystick_board_info);
1518
1519 static int __init tegra_button_board_info(char *info)
1520 {
1521         char *p = info;
1522         button_board_info.board_id = memparse(p, &p);
1523         button_board_info.sku = memparse(p+1, &p);
1524         button_board_info.fab = memparse(p+1, &p);
1525         button_board_info.major_revision = memparse(p+1, &p);
1526         button_board_info.minor_revision = memparse(p+1, &p);
1527         return 1;
1528 }
1529
1530 void tegra_get_button_board_info(struct board_info *bi)
1531 {
1532         memcpy(bi, &button_board_info, sizeof(struct board_info));
1533 }
1534
1535 __setup("buttonboard=", tegra_button_board_info);
1536
1537 static int __init tegra_io_board_info(char *info)
1538 {
1539         char *p = info;
1540         io_board_info.board_id = memparse(p, &p);
1541         io_board_info.sku = memparse(p+1, &p);
1542         io_board_info.fab = memparse(p+1, &p);
1543         io_board_info.major_revision = memparse(p+1, &p);
1544         io_board_info.minor_revision = memparse(p+1, &p);
1545         return 1;
1546 }
1547
1548 void tegra_get_io_board_info(struct board_info *bi)
1549 {
1550         memcpy(bi, &io_board_info, sizeof(struct board_info));
1551 }
1552
1553 __setup("ioboard=", tegra_io_board_info);
1554
1555 static int __init tegra_modem_id(char *id)
1556 {
1557         char *p = id;
1558
1559         modem_id = memparse(p, &p);
1560         return 1;
1561 }
1562
1563 int tegra_get_modem_id(void)
1564 {
1565         return modem_id;
1566 }
1567
1568 __setup("modem_id=", tegra_modem_id);
1569
1570 static int __init tegra_usb_port_owner_info(char *id)
1571 {
1572         char *p = id;
1573
1574         usb_port_owner_info = memparse(p, &p);
1575         return 1;
1576 }
1577
1578 int tegra_get_usb_port_owner_info(void)
1579 {
1580         return usb_port_owner_info;
1581 }
1582
1583 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1584
1585 static int __init tegra_commchip_id(char *id)
1586 {
1587         char *p = id;
1588
1589         if (get_option(&p, &commchip_id) != 1)
1590                 return 0;
1591         return 1;
1592 }
1593
1594 int tegra_get_commchip_id(void)
1595 {
1596         return commchip_id;
1597 }
1598
1599 __setup("commchip_id=", tegra_commchip_id);
1600
1601 /*
1602  * Tegra has a protected aperture that prevents access by most non-CPU
1603  * memory masters to addresses above the aperture value.  Enabling it
1604  * secures the CPU's memory from the GPU, except through the GART.
1605  */
1606 void __init tegra_protected_aperture_init(unsigned long aperture)
1607 {
1608         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1609         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1610         writel(aperture, mc_base + MC_SECURITY_CFG2);
1611 }
1612
1613 /*
1614  * Due to conflicting restrictions on the placement of the framebuffer,
1615  * the bootloader is likely to leave the framebuffer pointed at a location
1616  * in memory that is outside the grhost aperture.  This function will move
1617  * the framebuffer contents from a physical address that is anywhere (lowmem,
1618  * highmem, or outside the memory map) to a physical address that is outside
1619  * the memory map.
1620  */
1621 void __tegra_move_framebuffer(struct platform_device *pdev,
1622         phys_addr_t to, phys_addr_t from,
1623         size_t size)
1624 {
1625         struct page *page;
1626         void __iomem *to_io;
1627         void *from_virt;
1628         unsigned long i;
1629         phys_addr_t addr[] = { to, from, };
1630
1631         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1632         BUG_ON(PAGE_ALIGN(from) != from);
1633         BUG_ON(PAGE_ALIGN(size) != size);
1634
1635         to_io = ioremap(to, size);
1636         if (!to_io) {
1637                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1638                 return;
1639         }
1640
1641         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1642                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1643                         page = phys_to_page(from + i);
1644                         from_virt = kmap(page);
1645                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1646                         kunmap(page);
1647                 }
1648         } else if (from) {
1649                 void __iomem *from_io = ioremap(from, size);
1650                 if (!from_io) {
1651                         pr_err("%s: Failed to map source framebuffer\n",
1652                                 __func__);
1653                         goto out;
1654                 }
1655
1656                 for (i = 0; i < size; i += 4)
1657                         writel(readl(from_io + i), to_io + i);
1658
1659                 iounmap(from_io);
1660         }
1661
1662         if (!pdev)
1663                 goto out;
1664
1665 #ifdef CONFIG_ARM64
1666         BUG(); /* ARM64 doesn't support dma_map_linear yet!!! */
1667 #else
1668         for (i = 0; i < ARRAY_SIZE(addr); i++)
1669                 dma_map_linear(&pdev->dev, addr[i], size, DMA_TO_DEVICE);
1670 #endif
1671 out:
1672         iounmap(to_io);
1673 }
1674
1675 void __tegra_clear_framebuffer(struct platform_device *pdev,
1676                                unsigned long to, unsigned long size)
1677 {
1678         void __iomem *to_io;
1679         unsigned long i;
1680
1681         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1682         BUG_ON(PAGE_ALIGN(size) != size);
1683
1684         to_io = ioremap(to, size);
1685         if (!to_io) {
1686                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1687                 return;
1688         }
1689
1690         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1691                 for (i = 0 ; i < size; i += PAGE_SIZE)
1692                         memset(to_io + i, 0, PAGE_SIZE);
1693         } else {
1694                 for (i = 0; i < size; i += 4)
1695                         writel(0, to_io + i);
1696         }
1697
1698         if (!pdev)
1699                 goto out;
1700
1701 #ifndef CONFIG_ARM64 /* FIXME */
1702         dma_map_linear(&pdev->dev, to, size, DMA_TO_DEVICE);
1703 #endif
1704 out:
1705         iounmap(to_io);
1706 }
1707
1708 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1709         unsigned long fb2_size)
1710 {
1711         const size_t avp_kernel_reserve = SZ_32M;
1712         int i = 0;
1713 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1714         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1715         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1716         tegra_avp_kernel_size = SECTION_SIZE;
1717
1718         /*
1719          * Choose a DRAM region in which to allocate the AVP kernel, using the
1720          * following guidelines:
1721          *     - Choose a DRAM region which exists below the 4 GB physical
1722          *       address limit. This is necessary because AVP is a 32 bit
1723          *       processor and it cannot access physical addresses above 4 GB.
1724          *     - Out of the applicable DRAM regions (i.e. those which exist
1725          *       below 4 GB), choose the region with the highest starting
1726          *       physical address.
1727          */
1728         for (i = memblock.memory.cnt - 1; i >= 0; i--) {
1729                 if ((u64)(memblock.memory.regions[i].base) +
1730                         (u64)(memblock.memory.regions[i].size) <
1731                         (u64)(SZ_2G)*(u64)(2)) {
1732                         tegra_avp_kernel_start =
1733                                 memblock.memory.regions[i].base +
1734                                 memblock.memory.regions[i].size -
1735                                 avp_kernel_reserve;
1736                         break;
1737                 }
1738         }
1739         /*
1740          * If tegra_avp_kernel_start is still 0, that means we didn't find any
1741          * DRAM region below the 4 GB physical address limit. This is a problem
1742          * because the AVP kernel must reside below 4 GB.
1743          */
1744         BUG_ON(tegra_avp_kernel_start == 0);
1745
1746         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1747                 pr_err("Failed to remove AVP kernel load area %08lx@%08llx "
1748                                 "from memory map\n",
1749                         (unsigned long)avp_kernel_reserve,
1750                         (u64)tegra_avp_kernel_start);
1751                 tegra_avp_kernel_size = 0;
1752         }
1753 #endif
1754
1755         if (carveout_size) {
1756                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1757                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1758                         pr_err("Failed to remove carveout %08lx@%08llx "
1759                                 "from memory map\n",
1760                                 carveout_size, (u64)tegra_carveout_start);
1761                         tegra_carveout_start = 0;
1762                         tegra_carveout_size = 0;
1763                 } else
1764                         tegra_carveout_size = carveout_size;
1765         }
1766
1767         if (fb2_size) {
1768                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1769                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1770                         pr_err("Failed to remove second framebuffer "
1771                                 "%08lx@%08llx from memory map\n",
1772                                 fb2_size, (u64)tegra_fb2_start);
1773                         tegra_fb2_start = 0;
1774                         tegra_fb2_size = 0;
1775                 } else
1776                         tegra_fb2_size = fb2_size;
1777         }
1778
1779         if (fb_size) {
1780                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1781                 if (memblock_remove(tegra_fb_start, fb_size)) {
1782                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1783                                 "from memory map\n",
1784                                 fb_size, (u64)tegra_fb_start);
1785                         tegra_fb_start = 0;
1786                         tegra_fb_size = 0;
1787                 } else
1788                         tegra_fb_size = fb_size;
1789         }
1790
1791 #ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
1792         if (tegra_split_mem_active()) {
1793                 tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1794                 tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1795
1796                 if (tegra_vpr_size == 0) {
1797                         tegra_carveout_start =
1798                                 TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1799                         tegra_carveout_size =
1800                                 TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1801                 } else if (
1802                         (tegra_vpr_start <
1803                                 TEGRA_ASIM_QT_FB_START +
1804                                 TEGRA_ASIM_QT_FB_SIZE) ||
1805                         (tegra_vpr_start + tegra_vpr_size - 1 >
1806                                 TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1807                                 TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1808                         /*
1809                          * On ASIM/ASIM + QT with
1810                          * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled, the VPR
1811                          * region needs to be within the front door memory
1812                          * region. Moreover, the VPR region can't exist where
1813                          * the framebuffer resides.
1814                          */
1815                         BUG();
1816                 } else if (
1817                         (tegra_vpr_start -
1818                         (TEGRA_ASIM_QT_FB_START +
1819                         TEGRA_ASIM_QT_FB_SIZE) <
1820                                 TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1821                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1822                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1823                         (tegra_vpr_start + tegra_vpr_size) <
1824                                 TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1825                         /*
1826                          * The tegra ASIM/QT carveout has a min size:-
1827                          * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free regions in
1828                          * front door mem are smaller than the min carveout
1829                          * size. Therefore, we can't fit the carveout in front
1830                          * door mem.
1831                          */
1832                         BUG();
1833                 } else if (
1834                         (tegra_vpr_start -
1835                         (TEGRA_ASIM_QT_FB_START + TEGRA_ASIM_QT_FB_SIZE)) >=
1836                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1837                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1838                         (tegra_vpr_start + tegra_vpr_size))) {
1839                         /*
1840                          * Place the tegra ASIM/QT carveout between the
1841                          * framebuffer and VPR.
1842                          */
1843                         tegra_carveout_start =
1844                                 TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1845                         tegra_carveout_size = tegra_vpr_start -
1846                                                 (TEGRA_ASIM_QT_FB_START +
1847                                                 TEGRA_ASIM_QT_FB_SIZE);
1848                 } else {
1849                         /*
1850                          * Place the tegra ASIM/QT carveout after VPR.
1851                          */
1852                         tegra_carveout_start = tegra_vpr_start + tegra_vpr_size;
1853                         tegra_carveout_size =
1854                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1855                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1856                                         (tegra_vpr_start + tegra_vpr_size);
1857                 }
1858         } else if (tegra_vpr_size != 0) {
1859                 /*
1860                  * VPR cannot work on ASIM/ASIM + QT if split mem is not
1861                  * enabled.
1862                  */
1863                 BUG();
1864         }
1865 #endif
1866
1867         if (tegra_fb_size)
1868                 tegra_grhost_aperture = tegra_fb_start;
1869
1870         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1871                 tegra_grhost_aperture = tegra_fb2_start;
1872
1873         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1874                 tegra_grhost_aperture = tegra_carveout_start;
1875
1876         if (tegra_lp0_vec_size &&
1877            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1878                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1879                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
1880                                 (u64)tegra_lp0_vec_size,
1881                                 (u64)tegra_lp0_vec_start);
1882                         tegra_lp0_vec_start = 0;
1883                         tegra_lp0_vec_size = 0;
1884                 }
1885                 tegra_lp0_vec_relocate = false;
1886         } else
1887                 tegra_lp0_vec_relocate = true;
1888
1889 #ifdef CONFIG_TEGRA_NVDUMPER
1890         if (nvdumper_reserved) {
1891                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1892                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1893                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1894                         nvdumper_reserved = 0;
1895                 }
1896         }
1897 #endif
1898
1899 #ifdef CONFIG_TEGRA_USE_NCT
1900         if (tegra_nck_size &&
1901            (tegra_nck_start < memblock_end_of_DRAM())) {
1902                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
1903                         pr_err("Failed to reserve nck %08lx@%08lx\n",
1904                                 tegra_nck_size, tegra_nck_start);
1905                         tegra_nck_start = 0;
1906                         tegra_nck_size = 0;
1907                 }
1908         }
1909 #endif
1910
1911         /*
1912          * We copy the bootloader's framebuffer to the framebuffer allocated
1913          * above, and then free this one.
1914          * */
1915         if (tegra_bootloader_fb_size) {
1916                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1917                 if (memblock_reserve(tegra_bootloader_fb_start,
1918                                 tegra_bootloader_fb_size)) {
1919                         pr_err("Failed to reserve bootloader frame buffer "
1920                                 "%08llx@%08llx\n",
1921                                 (u64)tegra_bootloader_fb_size,
1922                                 (u64)tegra_bootloader_fb_start);
1923                         tegra_bootloader_fb_start = 0;
1924                         tegra_bootloader_fb_size = 0;
1925                 }
1926         }
1927
1928         if (tegra_bootloader_fb2_size) {
1929                 tegra_bootloader_fb2_size =
1930                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1931                 if (memblock_reserve(tegra_bootloader_fb2_start,
1932                                 tegra_bootloader_fb2_size)) {
1933                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
1934                                 (u64)tegra_bootloader_fb2_size,
1935                                 (u64)tegra_bootloader_fb2_start);
1936                         tegra_bootloader_fb2_start = 0;
1937                         tegra_bootloader_fb2_size = 0;
1938                 }
1939         }
1940
1941         pr_info("Tegra reserved memory:\n"
1942                 "LP0:                    %08llx - %08llx\n"
1943                 "Bootloader framebuffer: %08llx - %08llx\n"
1944                 "Bootloader framebuffer2: %08llx - %08llx\n"
1945                 "Framebuffer:            %08llx - %08llx\n"
1946                 "2nd Framebuffer:        %08llx - %08llx\n"
1947                 "Carveout:               %08llx - %08llx\n"
1948                 "Vpr:                    %08llx - %08llx\n"
1949                 "Tsec:                   %08llx - %08llx\n",
1950                 (u64)tegra_lp0_vec_start,
1951                 (u64)(tegra_lp0_vec_size ?
1952                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
1953                 (u64)tegra_bootloader_fb_start,
1954                 (u64)(tegra_bootloader_fb_size ?
1955                         tegra_bootloader_fb_start +
1956                         tegra_bootloader_fb_size - 1 : 0),
1957                 (u64)tegra_bootloader_fb2_start,
1958                 (u64)(tegra_bootloader_fb2_size ?
1959                         tegra_bootloader_fb2_start +
1960                         tegra_bootloader_fb2_size - 1 : 0),
1961                 (u64)tegra_fb_start,
1962                 (u64)(tegra_fb_size ?
1963                         tegra_fb_start + tegra_fb_size - 1 : 0),
1964                 (u64)tegra_fb2_start,
1965                 (u64)(tegra_fb2_size ?
1966                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
1967                 (u64)tegra_carveout_start,
1968                 (u64)(tegra_carveout_size ?
1969                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
1970                 (u64)tegra_vpr_start,
1971                 (u64)(tegra_vpr_size ?
1972                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
1973                 (u64)tegra_tsec_start,
1974                 (u64)(tegra_tsec_size ?
1975                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
1976
1977         if (tegra_avp_kernel_size) {
1978                 /* Return excessive memory reserved for AVP kernel */
1979                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1980                         memblock_add(
1981                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1982                                 avp_kernel_reserve - tegra_avp_kernel_size);
1983                 /* The AVP kernel should be loaded below the 4 GB physical
1984                    address limit. */
1985                 BUG_ON((u64)(tegra_avp_kernel_start) +
1986                         (u64)(tegra_avp_kernel_size) - (u64)(1) >=
1987                         (u64)(SZ_2G)*(u64)(2));
1988                 pr_info(
1989                 "AVP kernel: %08llx - %08llx\n",
1990                         (u64)tegra_avp_kernel_start,
1991                         (u64)(tegra_avp_kernel_start +
1992                                 tegra_avp_kernel_size - 1));
1993         }
1994
1995 #ifdef CONFIG_TEGRA_NVDUMPER
1996         if (nvdumper_reserved) {
1997                 pr_info("Nvdumper:               %08lx - %08lx\n",
1998                         nvdumper_reserved,
1999                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2000         }
2001 #endif
2002
2003 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
2004         pr_info("Tzram:               %08lx - %08lx\n",
2005                 tegra_tzram_start,
2006                 tegra_tzram_size ?
2007                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2008 #endif
2009
2010 #ifdef CONFIG_TEGRA_USE_NCT
2011         if (tegra_nck_size) {
2012                 pr_info("Nck:                    %08lx - %08lx\n",
2013                         tegra_nck_start,
2014                         tegra_nck_size ?
2015                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2016         }
2017 #endif
2018 }
2019
2020 #ifdef CONFIG_PSTORE_RAM
2021 static struct persistent_ram_descriptor desc = {
2022         .name = "ramoops",
2023 };
2024
2025 static struct persistent_ram ram = {
2026         .descs = &desc,
2027         .num_descs = 1,
2028 };
2029
2030 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
2031 {
2032         int ret;
2033
2034         ram.start = memblock_end_of_DRAM() - ram_console_size;
2035         ram.size = ram_console_size;
2036         ram.descs->size = ram_console_size;
2037
2038         INIT_LIST_HEAD(&ram.node);
2039
2040         ret = persistent_ram_early_init(&ram);
2041         if (ret)
2042                 goto fail;
2043
2044         return;
2045
2046 fail:
2047         pr_err("Failed to reserve memory block for ram console\n");
2048 }
2049 #endif
2050
2051 int __init tegra_register_fuse(void)
2052 {
2053         return platform_device_register(&tegra_fuse_device);
2054 }
2055
2056 void __init tegra_release_bootloader_fb(void)
2057 {
2058         /* Since bootloader fb is reserved in common.c, it is freed here. */
2059         if (tegra_bootloader_fb_size) {
2060                 if (memblock_free(tegra_bootloader_fb_start,
2061                                                 tegra_bootloader_fb_size))
2062                         pr_err("Failed to free bootloader fb.\n");
2063                 else
2064                         free_bootmem_late(tegra_bootloader_fb_start,
2065                                                 tegra_bootloader_fb_size);
2066         }
2067         if (tegra_bootloader_fb2_size) {
2068                 if (memblock_free(tegra_bootloader_fb2_start,
2069                                                 tegra_bootloader_fb2_size))
2070                         pr_err("Failed to free bootloader fb2.\n");
2071                 else
2072                         free_bootmem_late(tegra_bootloader_fb2_start,
2073                                                 tegra_bootloader_fb2_size);
2074         }
2075 }
2076
2077 static struct platform_device *pinmux_devices[] = {
2078         &tegra_gpio_device,
2079         &tegra_pinmux_device,
2080 };
2081
2082 void tegra_enable_pinmux(void)
2083 {
2084         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
2085 }
2086
2087 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2088         [TEGRA_REVISION_UNKNOWN] = "unknown",
2089         [TEGRA_REVISION_A01]     = "A01",
2090         [TEGRA_REVISION_A02]     = "A02",
2091         [TEGRA_REVISION_A03]     = "A03",
2092         [TEGRA_REVISION_A03p]    = "A03 prime",
2093         [TEGRA_REVISION_A04]     = "A04",
2094         [TEGRA_REVISION_A04p]    = "A04 prime",
2095 };
2096
2097 static const char * __init tegra_get_revision(void)
2098 {
2099         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2100 }
2101
2102 static const char * __init tegra_get_family(void)
2103 {
2104         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2105         u32 cid = readl(chip_id);
2106         cid = (cid >> 8) & 0xFF;
2107
2108         switch (cid) {
2109         case TEGRA_CHIPID_TEGRA2:
2110                 cid = 2;
2111                 break;
2112         case TEGRA_CHIPID_TEGRA3:
2113                 cid = 3;
2114                 break;
2115         case TEGRA_CHIPID_TEGRA11:
2116                 cid = 11;
2117                 break;
2118         case TEGRA_CHIPID_TEGRA14:
2119                 cid = 14;
2120                 break;
2121
2122         case TEGRA_CHIPID_UNKNOWN:
2123         default:
2124                 cid = 0;
2125         }
2126         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2127 }
2128
2129 static const char * __init tegra_get_soc_id(void)
2130 {
2131         int package_id = tegra_package_id();
2132         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2133                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
2134 }
2135
2136 static void __init tegra_soc_info_populate(struct soc_device_attribute
2137         *soc_dev_attr, const char *machine)
2138 {
2139         soc_dev_attr->soc_id = tegra_get_soc_id();
2140         soc_dev_attr->machine  = machine;
2141         soc_dev_attr->family   = tegra_get_family();
2142         soc_dev_attr->revision = tegra_get_revision();
2143 }
2144
2145 int __init tegra_soc_device_init(const char *machine)
2146 {
2147         struct soc_device *soc_dev;
2148         struct soc_device_attribute *soc_dev_attr;
2149
2150         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2151         if (!soc_dev_attr)
2152                 return -ENOMEM;
2153
2154         tegra_soc_info_populate(soc_dev_attr, machine);
2155
2156         soc_dev = soc_device_register(soc_dev_attr);
2157         if (IS_ERR_OR_NULL(soc_dev)) {
2158                 kfree(soc_dev_attr);
2159                 return -1;
2160         }
2161
2162         return 0;
2163 }
2164
2165 void __init tegra_init_late(void)
2166 {
2167 #ifndef CONFIG_COMMON_CLK
2168         tegra_clk_debugfs_init();
2169 #endif
2170         tegra_powergate_debugfs_init();
2171 }
2172
2173 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2174 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2175
2176 static void asim_power_off(void)
2177 {
2178         pr_err("ASIM Powering off the device\n");
2179         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2180         while (1)
2181                 ;
2182 }
2183
2184 static int __init asim_power_off_init(void)
2185 {
2186         if (tegra_cpu_is_asim())
2187                 pm_power_off = asim_power_off;
2188         return 0;
2189 }
2190
2191 arch_initcall(asim_power_off_init);
2192
2193 #if defined(CONFIG_SMC91X)
2194 static struct resource tegra_asim_smc91x_resources[] = {
2195         [0] = {
2196                 .start          = TEGRA_SIM_ETH_BASE,
2197                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2198                 .flags          = IORESOURCE_MEM,
2199         },
2200         [1] = {
2201                 .start          = IRQ_ETH,
2202                 .end            = IRQ_ETH,
2203                 .flags          = IORESOURCE_IRQ,
2204         },
2205 };
2206
2207 static struct platform_device tegra_asim_smc91x_device = {
2208         .name           = "smc91x",
2209         .id             = 0,
2210         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2211         .resource       = tegra_asim_smc91x_resources,
2212 };
2213
2214 static int __init asim_enet_smc91x_init(void)
2215 {
2216         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2217                 platform_device_register(&tegra_asim_smc91x_device);
2218         return 0;
2219 }
2220
2221 rootfs_initcall(asim_enet_smc91x_init);
2222 #endif
2223
2224 #if defined(CONFIG_SMSC911X)
2225 static struct resource tegra_smsc911x_resources[] = {
2226         [0] = {
2227                 .start          = 0x4E000000,
2228                 .end            = 0x4E000000 + SZ_64K - 1,
2229                 .flags          = IORESOURCE_MEM,
2230         },
2231         [1] = {
2232                 .start          = IRQ_ETH,
2233                 .end            = IRQ_ETH,
2234                 .flags          = IORESOURCE_IRQ,
2235         },
2236 };
2237
2238 static struct smsc911x_platform_config tegra_smsc911x_config = {
2239         .flags          = SMSC911X_USE_32BIT,
2240         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2241         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2242         .phy_interface  = PHY_INTERFACE_MODE_MII,
2243 };
2244
2245 static struct platform_device tegra_smsc911x_device = {
2246         .name              = "smsc911x",
2247         .id                = 0,
2248         .resource          = tegra_smsc911x_resources,
2249         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2250         .dev.platform_data = &tegra_smsc911x_config,
2251 };
2252
2253 static int __init enet_smsc911x_init(void)
2254 {
2255         if (!tegra_cpu_is_dsim())
2256                 platform_device_register(&tegra_smsc911x_device);
2257         return 0;
2258 }
2259
2260 rootfs_initcall(enet_smsc911x_init);
2261 #endif
2262
2263 #ifdef CONFIG_TEGRA_SIMULATION_SPLIT_MEM
2264 int tegra_split_mem_active(void)
2265 {
2266         return tegra_split_mem_set;
2267 }
2268
2269 static int __init set_tegra_split_mem(char *options)
2270 {
2271         tegra_split_mem_set = 1;
2272         return 0;
2273 }
2274 early_param("tegra_split_mem", set_tegra_split_mem);
2275 #endif
2276 #endif