ARM: Build fix after Tegra14 K3.4 merge
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36
37 #include <trace/events/nvsecurity.h>
38
39 #include <asm/hardware/cache-l2x0.h>
40 #include <asm/system.h>
41 #include <asm/dma-mapping.h>
42
43 #include <mach/hardware.h>
44 #include <mach/powergate.h>
45 #include <mach/tegra_smmu.h>
46 #include <mach/gpio-tegra.h>
47
48 #include "apbio.h"
49 #include "board.h"
50 #include "clock.h"
51 #include "common.h"
52 #include "dvfs.h"
53 #include "fuse.h"
54 #include "iomap.h"
55 #include "pm.h"
56 #include "sleep.h"
57 #include "reset.h"
58 #include "devices.h"
59 #include "pmc.h"
60
61 #define MC_SECURITY_CFG2        0x7c
62
63 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
64 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
65 #define   PRIORITY_SELECT_USB   BIT(6)
66 #define PRIORITY_SELECT_SDMMC4  BIT(12)
67 #define   PRIORITY_SELECT_USB2  BIT(18)
68 #define   PRIORITY_SELECT_USB3  BIT(17)
69 #define   PRIORITY_SELECT_SE BIT(14)
70
71 #define AHB_GIZMO_AHB_MEM               0xc
72 #define   ENB_FAST_REARBITRATE  BIT(2)
73 #define   DONT_SPLIT_AHB_WR     BIT(7)
74
75 #define   RECOVERY_MODE BIT(31)
76 #define   BOOTLOADER_MODE       BIT(30)
77 #define   FORCED_RECOVERY_MODE  BIT(1)
78
79 #define AHB_GIZMO_USB           0x1c
80 #define AHB_GIZMO_SDMMC4        0x44
81 #define AHB_GIZMO_USB2          0x78
82 #define AHB_GIZMO_USB3          0x7c
83 #define AHB_GIZMO_SE            0x4c
84 #define   IMMEDIATE     BIT(18)
85
86 #define AHB_MEM_PREFETCH_CFG5   0xc8
87 #define AHB_MEM_PREFETCH_CFG3   0xe0
88 #define AHB_MEM_PREFETCH_CFG4   0xe4
89 #define AHB_MEM_PREFETCH_CFG1   0xec
90 #define AHB_MEM_PREFETCH_CFG2   0xf0
91 #define AHB_MEM_PREFETCH_CFG6   0xcc
92 #define   PREFETCH_ENB  BIT(31)
93 #define   MST_ID(x)     (((x) & 0x1f) << 26)
94 #define   AHBDMA_MST_ID MST_ID(5)
95 #define   USB_MST_ID    MST_ID(6)
96 #define SDMMC4_MST_ID   MST_ID(12)
97 #define   USB2_MST_ID   MST_ID(18)
98 #define   USB3_MST_ID   MST_ID(17)
99 #define   SE_MST_ID     MST_ID(14)
100 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
101 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
102
103 unsigned long tegra_avp_kernel_start;
104 unsigned long tegra_avp_kernel_size;
105 unsigned long tegra_bootloader_fb_start;
106 unsigned long tegra_bootloader_fb_size;
107 unsigned long tegra_fb_start;
108 unsigned long tegra_fb_size;
109 unsigned long tegra_fb2_start;
110 unsigned long tegra_fb2_size;
111 unsigned long tegra_carveout_start;
112 unsigned long tegra_carveout_size;
113 unsigned long tegra_vpr_start;
114 unsigned long tegra_vpr_size;
115 unsigned long tegra_tsec_start;
116 unsigned long tegra_tsec_size;
117 unsigned long tegra_lp0_vec_start;
118 unsigned long tegra_lp0_vec_size;
119 #ifdef CONFIG_TEGRA_NVDUMPER
120 unsigned long nvdumper_reserved;
121 #endif
122 bool tegra_lp0_vec_relocate;
123 unsigned long tegra_grhost_aperture = ~0ul;
124 static   bool is_tegra_debug_uart_hsport;
125 static struct board_info pmu_board_info;
126 static struct board_info display_board_info;
127 static int panel_id;
128 static struct board_info camera_board_info;
129
130 static int pmu_core_edp;
131 static int board_panel_type;
132 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
133 static int pwr_i2c_clk = 400;
134 /*
135  * Storage for debug-macro.S's state.
136  *
137  * This must be in .data not .bss so that it gets initialized each time the
138  * kernel is loaded. The data is declared here rather than debug-macro.S so
139  * that multiple inclusions of debug-macro.S point at the same data.
140  */
141 u32 tegra_uart_config[4] = {
142         /* Debug UART initialization required */
143         1,
144         /* Debug UART physical address */
145         0,
146         /* Debug UART virtual address */
147         0,
148         /* Scratch space for debug macro */
149         0,
150 };
151
152 #define NEVER_RESET 0
153
154 inline void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
155 {
156         unsigned long check;
157         int retry = 10;
158
159         /* Read and check if write is successful,
160          * if val doesn't match with read, retry write.
161          */
162         do {
163                 writel(val, reg);
164                 check = readl(reg);
165                 if (likely(check == val))
166                         break;
167                 else
168                         pr_err("AHB register access fail for reg\n");
169         } while (--retry);
170 }
171
172 void tegra_assert_system_reset(char mode, const char *cmd)
173 {
174 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
175         pr_info("tegra_assert_system_reset() ignored.....");
176         do { } while (1);
177 #else
178         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
179         u32 reg;
180
181         reg = readl_relaxed(reset + PMC_SCRATCH0);
182         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
183         if (cmd) {
184                 if (!strcmp(cmd, "recovery"))
185                         reg |= RECOVERY_MODE;
186                 else if (!strcmp(cmd, "bootloader"))
187                         reg |= BOOTLOADER_MODE;
188                 else if (!strcmp(cmd, "forced-recovery"))
189                         reg |= FORCED_RECOVERY_MODE;
190                 else
191                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
192         }
193         else {
194                 /* Clearing SCRATCH0 31:30:1 on default reboot */
195                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
196         }
197         writel_relaxed(reg, reset + PMC_SCRATCH0);
198         reg = readl_relaxed(reset);
199         reg |= 0x10;
200         writel_relaxed(reg, reset);
201 #endif
202 }
203 static int modem_id;
204 static int commchip_id;
205 static int sku_override;
206 static int debug_uart_port_id;
207 static enum audio_codec_type audio_codec_name;
208 static enum image_type board_image_type = system_image;
209 static int max_cpu_current;
210 static int max_core_current;
211 static int emc_max_dvfs;
212 static int usb_port_owner_info;
213
214 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
215 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
216         /* name         parent          rate            enabled */
217         { "clk_m",      NULL,           0,              true },
218         { "emc",        NULL,           0,              true },
219         { "cpu",        NULL,           0,              true },
220         { "kfuse",      NULL,           0,              true },
221         { "fuse",       NULL,           0,              true },
222         { "sclk",       NULL,           0,              true },
223         { "pll_p",      NULL,           0,              true },
224         { "pll_p_out1", "pll_p",        0,              false },
225         { "pll_p_out3", "pll_p",        0,              false },
226 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
227         { "pll_m_out1", "pll_m",        275000000,      false },
228         { "pll_p_out2",  "pll_p",       102000000,      false },
229         { "sclk",        "pll_p_out2",  102000000,      true },
230         { "pll_p_out4",  "pll_p",       204000000,      true },
231         { "hclk",       "sclk",         102000000,      true },
232         { "pclk",       "hclk",         51000000,       true },
233         { "mselect",    "pll_p",        102000000,      true },
234         { "host1x",     "pll_p",        102000000,      false },
235         { "cl_dvfs_ref", "pll_p",       51000000,       true },
236         { "cl_dvfs_soc", "pll_p",       51000000,       true },
237 #else
238         { "pll_m_out1", "pll_m",        275000000,      true },
239         { "pll_p_out2", "pll_p",        108000000,      false },
240         { "sclk",       "pll_p_out2",   108000000,      true },
241         { "pll_p_out4", "pll_p",        216000000,      true },
242         { "hclk",       "sclk",         108000000,      true },
243         { "pclk",       "hclk",         54000000,       true },
244         { "mselect",    "pll_p",        108000000,      true },
245         { "host1x",     "pll_p",        108000000,      false },
246         { "cl_dvfs_ref", "clk_m",       13000000,       false },
247         { "cl_dvfs_soc", "clk_m",       13000000,       false },
248 #endif
249 #ifdef CONFIG_TEGRA_SLOW_CSITE
250         { "csite",      "clk_m",        1000000,        true },
251 #else
252         { "csite",      NULL,           0,              true },
253 #endif
254         { "pll_u",      NULL,           480000000,      true },
255         { "pll_re_vco", NULL,           312000000,      false },
256         { "sdmmc1",     "pll_p",        48000000,       false},
257         { "sdmmc3",     "pll_p",        48000000,       false},
258         { "sdmmc4",     "pll_p",        48000000,       false},
259         { "sbc1.sclk",  NULL,           40000000,       false},
260         { "sbc2.sclk",  NULL,           40000000,       false},
261         { "sbc3.sclk",  NULL,           40000000,       false},
262         { "sbc4.sclk",  NULL,           40000000,       false},
263         { "sbc5.sclk",  NULL,           40000000,       false},
264         { "sbc6.sclk",  NULL,           40000000,       false},
265 #ifdef CONFIG_TEGRA_DUAL_CBUS
266         { "c2bus",      "pll_c2",       250000000,      false },
267         { "c3bus",      "pll_c3",       250000000,      false },
268         { "pll_c",      NULL,           624000000,      false },
269 #else
270         { "cbus",       "pll_c",        250000000,      false },
271 #endif
272         { "pll_c_out1", "pll_c",        150000000,      false },
273 #ifdef CONFIG_TEGRA_PLLM_SCALED
274         { "vi",         "pll_p",        0,              false},
275 #endif
276         { NULL,         NULL,           0,              0},
277 };
278 #endif
279 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
280 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
281         /* name         parent          rate            enabled */
282         { "clk_m",      NULL,           0,              true },
283         { "emc",        NULL,           0,              true },
284         { "cpu",        NULL,           0,              true },
285         { "kfuse",      NULL,           0,              true },
286         { "fuse",       NULL,           0,              true },
287         { "sclk",       NULL,           0,              true },
288 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
289         { "pll_p",      NULL,           0,              true },
290         { "pll_p_out1", "pll_p",        0,              false },
291         { "pll_p_out3", "pll_p",        0,              true },
292         { "pll_m_out1", "pll_m",        275000000,      false },
293         { "pll_p_out2",  "pll_p",       102000000,      false },
294         { "sclk",        "pll_p_out2",  102000000,      true },
295         { "pll_p_out4",  "pll_p",       204000000,      true },
296         { "host1x",     "pll_p",        102000000,      false },
297         { "cl_dvfs_ref", "pll_p",       54000000,       false },
298         { "cl_dvfs_soc", "pll_p",       54000000,       false },
299 #else
300         { "pll_p",      NULL,           0,              true },
301         { "pll_p_out1", "pll_p",        0,              false },
302         { "pll_p_out3", "pll_p",        0,              true },
303         { "pll_m_out1", "pll_m",        275000000,      true },
304         { "pll_p_out2", "pll_p",        108000000,      false },
305         { "sclk",       "pll_p_out2",   108000000,      true },
306         { "pll_p_out4", "pll_p",        216000000,      true },
307         { "host1x",     "pll_p",        108000000,      false },
308         { "cl_dvfs_ref", "clk_m",       13000000,       false },
309         { "cl_dvfs_soc", "clk_m",       13000000,       false },
310         { "hclk",       "sclk",         108000000,      true },
311         { "pclk",       "hclk",         54000000,       true },
312         { "wake.sclk",  NULL,           250000000,      true },
313         { "mselect",    "pll_p",        108000000,      true },
314 #endif
315 #ifdef CONFIG_TEGRA_SLOW_CSITE
316         { "csite",      "clk_m",        1000000,        true },
317 #else
318         { "csite",      NULL,           0,              true },
319 #endif
320         { "pll_u",      NULL,           480000000,      false },
321         { "sdmmc1",     "pll_p",        48000000,       false},
322         { "sdmmc3",     "pll_p",        48000000,       false},
323         { "sdmmc4",     "pll_p",        48000000,       false},
324         { "sbc1.sclk",  NULL,           40000000,       false},
325         { "sbc2.sclk",  NULL,           40000000,       false},
326         { "sbc3.sclk",  NULL,           40000000,       false},
327         { "sbc4.sclk",  NULL,           40000000,       false},
328         { "sbc5.sclk",  NULL,           40000000,       false},
329         { "sbc6.sclk",  NULL,           40000000,       false},
330 #ifdef CONFIG_TEGRA_DUAL_CBUS
331         { "c2bus",      "pll_c2",       300000000,      false },
332         { "c3bus",      "pll_c3",       300000000,      false },
333 #else
334         { "cbus",       "pll_c",        416000000,      false },
335         { "pll_c_out1", "pll_c",        208000000,      false },
336 #endif
337         { NULL,         NULL,           0,              0},
338 };
339 #endif
340
341 #ifdef CONFIG_CACHE_L2X0
342 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
343 #ifdef CONFIG_TRUSTED_FOUNDATIONS
344 static void tegra_cache_smc(bool enable, u32 arg)
345 {
346         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
347         bool need_affinity_switch;
348         bool can_switch_affinity;
349         bool l2x0_enabled;
350         cpumask_t local_cpu_mask;
351         cpumask_t saved_cpu_mask;
352         unsigned long flags;
353         long ret;
354
355         /*
356          * ISSUE : Some registers of PL310 controler must be written
357          *              from Secure context (and from CPU0)!
358          *
359          * When called form Normal we obtain an abort or do nothing.
360          * Instructions that must be called in Secure:
361          *      - Write to Control register (L2X0_CTRL==0x100)
362          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
363          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
364          *              mandatory at boot time.
365          *      - Tag and Data RAM Latency Control Registers
366          *              (0x108 & 0x10C) must be written in Secure.
367          */
368         need_affinity_switch = (smp_processor_id() != 0);
369         can_switch_affinity = !irqs_disabled();
370
371         WARN_ON(need_affinity_switch && !can_switch_affinity);
372         if (need_affinity_switch && can_switch_affinity) {
373                 cpu_set(0, local_cpu_mask);
374                 sched_getaffinity(0, &saved_cpu_mask);
375                 ret = sched_setaffinity(0, &local_cpu_mask);
376                 WARN_ON(ret != 0);
377         }
378
379         local_irq_save(flags);
380         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
381         if (enable && !l2x0_enabled)
382                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
383         else if (!enable && l2x0_enabled)
384                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
385         local_irq_restore(flags);
386
387         if (need_affinity_switch && can_switch_affinity) {
388                 ret = sched_setaffinity(0, &saved_cpu_mask);
389                 WARN_ON(ret != 0);
390         }
391 }
392
393 static void tegra_l2x0_disable(void)
394 {
395         unsigned long flags;
396         static u32 l2x0_way_mask;
397
398         if (!l2x0_way_mask) {
399                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
400                 u32 aux_ctrl;
401                 u32 ways;
402
403                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
404                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
405                 l2x0_way_mask = (1 << ways) - 1;
406         }
407
408         local_irq_save(flags);
409         tegra_cache_smc(false, l2x0_way_mask);
410         local_irq_restore(flags);
411 }
412 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
413
414 void tegra_init_cache(bool init)
415 {
416         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
417         u32 aux_ctrl;
418 #ifndef CONFIG_TRUSTED_FOUNDATIONS
419         u32 cache_type;
420         u32 tag_latency, data_latency;
421 #endif
422
423 #ifdef CONFIG_TRUSTED_FOUNDATIONS
424         /* issue the SMC to enable the L2 */
425         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
426         trace_smc_init_cache(NVSEC_SMC_START);
427         tegra_cache_smc(true, aux_ctrl);
428         trace_smc_init_cache(NVSEC_SMC_DONE);
429
430         /* after init, reread aux_ctrl and register handlers */
431         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
432         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
433
434         /* override outer_disable() with our disable */
435         outer_cache.disable = tegra_l2x0_disable;
436 #else
437 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
438         tag_latency = 0x331;
439         data_latency = 0x441;
440 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
441 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
442         if (is_lp_cluster()) {
443                 tag_latency = 0x221;
444                 data_latency = 0x221;
445         } else {
446                 u32 speedo;
447
448                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
449                 speedo = tegra_cpu_speedo_id();
450                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
451                     speedo == 12 || speedo == 13) {
452                         tag_latency = 0x442;
453                         data_latency = 0x552;
454                 } else {
455                         tag_latency = 0x441;
456                         data_latency = 0x551;
457                 }
458         }
459 #else
460         tag_latency = 0x770;
461         data_latency = 0x770;
462 #endif
463 #endif
464         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
465         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
466
467 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
468 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
469         writel(7, p + L2X0_PREFETCH_CTRL);
470         writel(2, p + L2X0_POWER_CTRL);
471 #endif
472 #endif
473
474         writel(0x3, p + L2X0_POWER_CTRL);
475         cache_type = readl(p + L2X0_CACHE_TYPE);
476         aux_ctrl = (cache_type & 0x700) << (17-8);
477         aux_ctrl |= 0x7C400001;
478         if (init) {
479                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
480         } else {
481                 u32 tmp;
482
483                 tmp = aux_ctrl;
484                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
485                 aux_ctrl &= 0x8200c3fe;
486                 aux_ctrl |= tmp;
487                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
488         }
489         l2x0_enable();
490 #endif
491 }
492 #else
493 void tegra_init_cache(bool init)
494 {
495 }
496 #endif
497 #endif
498
499 static void __init tegra_perf_init(void)
500 {
501         u32 reg;
502
503         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
504         reg >>= 11;
505         reg = (1 << (reg & 0x1f))-1;
506         reg |= 0x80000000;
507         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
508         reg = 1;
509         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
510 }
511
512 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
513 static void __init tegra_ramrepair_init(void)
514 {
515         if (tegra_spare_fuse(10) & tegra_spare_fuse(11) & 1) {
516                 u32 reg;
517                 reg = readl(FLOW_CTRL_RAM_REPAIR);
518                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
519                 writel(reg, FLOW_CTRL_RAM_REPAIR);
520         }
521 }
522 #endif
523
524 static void __init tegra_init_power(void)
525 {
526 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
527         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
528 #endif
529 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
530         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
531 #endif
532 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
533         /* some partitions need to be powergated by default for t11x */
534         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
535         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
536         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
537 #endif
538 }
539
540 static inline unsigned long gizmo_readl(unsigned long offset)
541 {
542         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
543 }
544
545 static inline void gizmo_writel(unsigned long value, unsigned long offset)
546 {
547         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
548 }
549
550 static void __init tegra_init_ahb_gizmo_settings(void)
551 {
552         unsigned long val;
553
554         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
555         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
556         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
557
558         val = gizmo_readl(AHB_GIZMO_USB);
559         val |= IMMEDIATE;
560         gizmo_writel(val, AHB_GIZMO_USB);
561
562         val = gizmo_readl(AHB_GIZMO_USB2);
563         val |= IMMEDIATE;
564         gizmo_writel(val, AHB_GIZMO_USB2);
565
566         val = gizmo_readl(AHB_GIZMO_USB3);
567         val |= IMMEDIATE;
568         gizmo_writel(val, AHB_GIZMO_USB3);
569
570 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
571         val = gizmo_readl(AHB_GIZMO_SE);
572         val |= IMMEDIATE;
573         gizmo_writel(val, AHB_GIZMO_SE);
574 #endif
575
576         /*
577          * SDMMC controller is removed from AHB interface in T124 and
578          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
579          * in T11x and T14x SOCs.
580          */
581 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
582         val = gizmo_readl(AHB_GIZMO_SDMMC4);
583         val |= IMMEDIATE;
584         gizmo_writel(val, AHB_GIZMO_SDMMC4);
585 #endif
586
587         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
588         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
589                                 | AHB_PRIORITY_WEIGHT(7);
590 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
591         val |= PRIORITY_SELECT_SE;
592 #endif
593
594 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
595         val |= PRIORITY_SELECT_SDMMC4;
596 #endif
597         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
598
599         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
600         val &= ~MST_ID(~0);
601         val |= PREFETCH_ENB | AHBDMA_MST_ID |
602                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
603         ahb_gizmo_writel(val,
604                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
605
606         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
607         val &= ~MST_ID(~0);
608         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
609                 INACTIVITY_TIMEOUT(0x1000);
610         ahb_gizmo_writel(val,
611                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
612
613         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
614         val &= ~MST_ID(~0);
615         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
616                 INACTIVITY_TIMEOUT(0x1000);
617         ahb_gizmo_writel(val,
618                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
619
620         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
621         val &= ~MST_ID(~0);
622         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
623                 INACTIVITY_TIMEOUT(0x1000);
624         ahb_gizmo_writel(val,
625                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
626
627         /*
628          * SDMMC controller is removed from AHB interface in T124 and
629          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
630          * in T11x and T14x SOCs.
631          */
632 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
633         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
634         val &= ~MST_ID(~0);
635         val |= PREFETCH_ENB | SDMMC4_MST_ID | ADDR_BNDRY(0xc) |
636                 INACTIVITY_TIMEOUT(0x1000);
637         ahb_gizmo_writel(val,
638                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
639 #endif
640
641 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
642         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
643         val &= ~MST_ID(~0);
644         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
645                 INACTIVITY_TIMEOUT(0x1000);
646         ahb_gizmo_writel(val,
647                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
648 #endif
649 }
650
651 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
652 void __init tegra20_init_early(void)
653 {
654 #ifndef CONFIG_SMP
655         /* For SMP system, initializing the reset handler here is too
656            late. For non-SMP systems, the function that calls the reset
657            handler initializer is not called, so do it here for non-SMP. */
658         tegra_cpu_reset_handler_init();
659 #endif
660         tegra_apb_io_init();
661         tegra_perf_init();
662         tegra_init_fuse();
663         tegra_init_cache(true);
664         tegra_pmc_init();
665         tegra_powergate_init();
666         tegra20_hotplug_init();
667         tegra_init_power();
668         tegra_init_ahb_gizmo_settings();
669         tegra_init_debug_uart_rate();
670         tegra_gpio_resume_init();
671         tegra_ram_console_debug_reserve(SZ_1M);
672 }
673 #endif
674 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
675 void __init tegra30_init_early(void)
676 {
677 #ifndef CONFIG_SMP
678         /* For SMP system, initializing the reset handler here is too
679            late. For non-SMP systems, the function that calls the reset
680            handler initializer is not called, so do it here for non-SMP. */
681         tegra_cpu_reset_handler_init();
682 #endif
683         tegra_apb_io_init();
684         tegra_perf_init();
685         tegra_init_fuse();
686         tegra_init_cache(true);
687         tegra_pmc_init();
688         tegra_powergate_init();
689         tegra30_hotplug_init();
690         tegra_init_power();
691         tegra_init_ahb_gizmo_settings();
692         tegra_init_debug_uart_rate();
693         tegra_gpio_resume_init();
694         tegra_ram_console_debug_reserve(SZ_1M);
695
696         init_dma_coherent_pool_size(SZ_1M);
697 }
698 #endif
699 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
700 void __init tegra11x_init_early(void)
701 {
702 #ifndef CONFIG_SMP
703         /* For SMP system, initializing the reset handler here is too
704            late. For non-SMP systems, the function that calls the reset
705            handler initializer is not called, so do it here for non-SMP. */
706         tegra_cpu_reset_handler_init();
707 #endif
708         tegra_apb_io_init();
709         tegra_perf_init();
710         tegra_init_fuse();
711         tegra_ramrepair_init();
712         tegra11x_init_clocks();
713         tegra11x_init_dvfs();
714         tegra_common_init_clock();
715         tegra_clk_init_from_table(tegra11x_clk_init_table);
716         tegra11x_clk_init_la();
717         tegra_pmc_init();
718         tegra_powergate_init();
719         tegra_init_power();
720         tegra_init_ahb_gizmo_settings();
721         tegra_init_debug_uart_rate();
722         tegra_gpio_resume_init();
723
724         init_dma_coherent_pool_size(SZ_1M);
725 }
726 #endif
727 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
728 void __init tegra14x_init_early(void)
729 {
730 #ifndef CONFIG_SMP
731         /* For SMP system, initializing the reset handler here is too
732            late. For non-SMP systems, the function that calls the reset
733            handler initializer is not called, so do it here for non-SMP. */
734         tegra_cpu_reset_handler_init();
735 #endif
736         tegra_init_fuse();
737         tegra11x_init_clocks(); /* using Tegra11x for now */
738         tegra11x_init_dvfs(); /* using Tegra11x for now */
739         tegra_common_init_clock();
740         tegra_clk_init_from_table(tegra14x_clk_init_table);
741         tegra_init_cache(true);
742         tegra_pmc_init();
743         tegra_powergate_init();
744         tegra_init_power();
745         tegra_init_ahb_gizmo_settings();
746         tegra_init_debug_uart_rate();
747         tegra_gpio_resume_init();
748 }
749 #endif
750 static int __init tegra_lp0_vec_arg(char *options)
751 {
752         char *p = options;
753
754         tegra_lp0_vec_size = memparse(p, &p);
755         if (*p == '@')
756                 tegra_lp0_vec_start = memparse(p+1, &p);
757         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
758                 tegra_lp0_vec_size = 0;
759                 tegra_lp0_vec_start = 0;
760         }
761
762         return 0;
763 }
764 early_param("lp0_vec", tegra_lp0_vec_arg);
765
766 #ifdef CONFIG_TEGRA_NVDUMPER
767 static int __init tegra_nvdumper_arg(char *options)
768 {
769         char *p = options;
770
771         nvdumper_reserved = memparse(p, &p);
772         return 0;
773 }
774 early_param("nvdumper_reserved", tegra_nvdumper_arg);
775 #endif
776
777 static int __init tegra_bootloader_fb_arg(char *options)
778 {
779         char *p = options;
780
781         tegra_bootloader_fb_size = memparse(p, &p);
782         if (*p == '@')
783                 tegra_bootloader_fb_start = memparse(p+1, &p);
784
785         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
786                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
787
788         return 0;
789 }
790 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
791
792 static int __init tegra_sku_override(char *id)
793 {
794         char *p = id;
795
796         sku_override = memparse(p, &p);
797
798         return 0;
799 }
800 early_param("sku_override", tegra_sku_override);
801
802 int tegra_get_sku_override(void)
803 {
804         return sku_override;
805 }
806
807 static int __init tegra_vpr_arg(char *options)
808 {
809         char *p = options;
810
811         tegra_vpr_size = memparse(p, &p);
812         if (*p == '@')
813                 tegra_vpr_start = memparse(p+1, &p);
814         pr_info("Found vpr, start=0x%lx size=%lx",
815                 tegra_vpr_start, tegra_vpr_size);
816         return 0;
817 }
818 early_param("vpr", tegra_vpr_arg);
819
820 static int __init tegra_tsec_arg(char *options)
821 {
822         char *p = options;
823
824         tegra_tsec_size = memparse(p, &p);
825         if (*p == '@')
826                 tegra_tsec_start = memparse(p+1, &p);
827         pr_info("Found tsec, start=0x%lx size=%lx",
828                 tegra_tsec_start, tegra_tsec_size);
829         return 0;
830 }
831 early_param("tsec", tegra_tsec_arg);
832
833 enum panel_type get_panel_type(void)
834 {
835         return board_panel_type;
836 }
837 static int __init tegra_board_panel_type(char *options)
838 {
839         if (!strcmp(options, "lvds"))
840                 board_panel_type = panel_type_lvds;
841         else if (!strcmp(options, "dsi"))
842                 board_panel_type = panel_type_dsi;
843         else
844                 return 0;
845         return 1;
846 }
847 __setup("panel=", tegra_board_panel_type);
848
849 int tegra_get_board_panel_id(void)
850 {
851         return panel_id;
852 }
853 static int __init tegra_board_panel_id(char *options)
854 {
855         char *p = options;
856         panel_id = memparse(p, &p);
857         return panel_id;
858 }
859 __setup("display_panel=", tegra_board_panel_id);
860
861 enum power_supply_type get_power_supply_type(void)
862 {
863         return pow_supply_type;
864 }
865 static int __init tegra_board_power_supply_type(char *options)
866 {
867         if (!strcmp(options, "Adapter"))
868                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
869         if (!strcmp(options, "Mains"))
870                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
871         else if (!strcmp(options, "Battery"))
872                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
873         else
874                 return 0;
875         return 1;
876 }
877 __setup("power_supply=", tegra_board_power_supply_type);
878
879 int get_core_edp(void)
880 {
881         return pmu_core_edp;
882 }
883 static int __init tegra_pmu_core_edp(char *options)
884 {
885         char *p = options;
886         int core_edp = memparse(p, &p);
887         if (core_edp != 0)
888                 pmu_core_edp = core_edp;
889         return 0;
890 }
891 early_param("core_edp_mv", tegra_pmu_core_edp);
892
893 int get_maximum_cpu_current_supported(void)
894 {
895         return max_cpu_current;
896 }
897 static int __init tegra_max_cpu_current(char *options)
898 {
899         char *p = options;
900         max_cpu_current = memparse(p, &p);
901         return 1;
902 }
903 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
904
905 int get_maximum_core_current_supported(void)
906 {
907         return max_core_current;
908 }
909 static int __init tegra_max_core_current(char *options)
910 {
911         char *p = options;
912         max_core_current = memparse(p, &p);
913         return 1;
914 }
915 __setup("core_edp_ma=", tegra_max_core_current);
916
917 int get_emc_max_dvfs(void)
918 {
919         return emc_max_dvfs;
920 }
921 static int __init tegra_emc_max_dvfs(char *options)
922 {
923         char *p = options;
924         emc_max_dvfs = memparse(p, &p);
925         return 1;
926 }
927 __setup("emc_max_dvfs", tegra_emc_max_dvfs);
928
929 static int __init tegra_debug_uartport(char *info)
930 {
931         char *p = info;
932         unsigned long long port_id;
933         if (!strncmp(p, "hsport", 6))
934                 is_tegra_debug_uart_hsport = true;
935         else if (!strncmp(p, "lsport", 6))
936                 is_tegra_debug_uart_hsport = false;
937
938         if (p[6] == ',') {
939                 if (p[7] == '-') {
940                         debug_uart_port_id = -1;
941                 } else {
942                         port_id = memparse(p + 7, &p);
943                         debug_uart_port_id = (int) port_id;
944                 }
945         } else {
946                 debug_uart_port_id = -1;
947         }
948
949         return 1;
950 }
951
952 bool is_tegra_debug_uartport_hs(void)
953 {
954         return is_tegra_debug_uart_hsport;
955 }
956
957 int get_tegra_uart_debug_port_id(void)
958 {
959         return debug_uart_port_id;
960 }
961 __setup("debug_uartport=", tegra_debug_uartport);
962
963 static int __init tegra_image_type(char *options)
964 {
965         if (!strcmp(options, "RCK"))
966                 board_image_type = rck_image;
967
968         return 0;
969 }
970
971 enum image_type get_tegra_image_type(void)
972 {
973         return board_image_type;
974 }
975
976 __setup("image=", tegra_image_type);
977
978 static int __init tegra_audio_codec_type(char *info)
979 {
980         char *p = info;
981         if (!strncmp(p, "wm8903", 6))
982                 audio_codec_name = audio_codec_wm8903;
983         else
984                 audio_codec_name = audio_codec_none;
985
986         return 1;
987 }
988
989 enum audio_codec_type get_audio_codec_type(void)
990 {
991         return audio_codec_name;
992 }
993 __setup("audio_codec=", tegra_audio_codec_type);
994
995 static int tegra_get_pwr_i2c_clk_rate(char *options)
996 {
997         int clk = simple_strtol(options, NULL, 16);
998         if (clk != 0)
999                 pwr_i2c_clk = clk;
1000         return 0;
1001 }
1002
1003 int get_pwr_i2c_clk_rate(void)
1004 {
1005         return pwr_i2c_clk;
1006 }
1007 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1008
1009 void tegra_get_board_info(struct board_info *bi)
1010 {
1011 #ifdef CONFIG_OF
1012         struct device_node *board_info;
1013         u32 prop_val;
1014         int err;
1015
1016         board_info = of_find_node_by_path("/chosen/board_info");
1017         if (!IS_ERR_OR_NULL(board_info)) {
1018                 memset(bi, 0, sizeof(*bi));
1019
1020                 err = of_property_read_u32(board_info, "id", &prop_val);
1021                 if (err)
1022                         pr_err("failed to read /chosen/board_info/id\n");
1023                 else
1024                         bi->board_id = prop_val;
1025
1026                 err = of_property_read_u32(board_info, "sku", &prop_val);
1027                 if (err)
1028                         pr_err("failed to read /chosen/board_info/sku\n");
1029                 else
1030                         bi->sku = prop_val;
1031
1032                 err = of_property_read_u32(board_info, "fab", &prop_val);
1033                 if (err)
1034                         pr_err("failed to read /chosen/board_info/fab\n");
1035                 else
1036                         bi->fab = prop_val;
1037
1038                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1039                 if (err)
1040                         pr_err("failed to read /chosen/board_info/major_revision\n");
1041                 else
1042                         bi->major_revision = prop_val;
1043
1044                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1045                 if (err)
1046                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1047                 else
1048                         bi->minor_revision = prop_val;
1049         } else {
1050 #endif
1051                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1052                 bi->sku = (system_serial_high) & 0xFFFF;
1053                 bi->fab = (system_serial_low >> 24) & 0xFF;
1054                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1055                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1056 #ifdef CONFIG_OF
1057         }
1058 #endif
1059 }
1060
1061 static int __init tegra_pmu_board_info(char *info)
1062 {
1063         char *p = info;
1064         pmu_board_info.board_id = memparse(p, &p);
1065         pmu_board_info.sku = memparse(p+1, &p);
1066         pmu_board_info.fab = memparse(p+1, &p);
1067         pmu_board_info.major_revision = memparse(p+1, &p);
1068         pmu_board_info.minor_revision = memparse(p+1, &p);
1069         return 1;
1070 }
1071
1072 void tegra_get_pmu_board_info(struct board_info *bi)
1073 {
1074         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1075 }
1076
1077 __setup("pmuboard=", tegra_pmu_board_info);
1078
1079 static int __init tegra_display_board_info(char *info)
1080 {
1081         char *p = info;
1082         display_board_info.board_id = memparse(p, &p);
1083         display_board_info.sku = memparse(p+1, &p);
1084         display_board_info.fab = memparse(p+1, &p);
1085         display_board_info.major_revision = memparse(p+1, &p);
1086         display_board_info.minor_revision = memparse(p+1, &p);
1087         return 1;
1088 }
1089
1090 void tegra_get_display_board_info(struct board_info *bi)
1091 {
1092         memcpy(bi, &display_board_info, sizeof(struct board_info));
1093 }
1094
1095 __setup("displayboard=", tegra_display_board_info);
1096
1097 static int __init tegra_camera_board_info(char *info)
1098 {
1099         char *p = info;
1100         camera_board_info.board_id = memparse(p, &p);
1101         camera_board_info.sku = memparse(p+1, &p);
1102         camera_board_info.fab = memparse(p+1, &p);
1103         camera_board_info.major_revision = memparse(p+1, &p);
1104         camera_board_info.minor_revision = memparse(p+1, &p);
1105         return 1;
1106 }
1107
1108 void tegra_get_camera_board_info(struct board_info *bi)
1109 {
1110         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1111 }
1112
1113 __setup("cameraboard=", tegra_camera_board_info);
1114
1115 static int __init tegra_modem_id(char *id)
1116 {
1117         char *p = id;
1118
1119         modem_id = memparse(p, &p);
1120         return 1;
1121 }
1122
1123 int tegra_get_modem_id(void)
1124 {
1125         return modem_id;
1126 }
1127
1128 __setup("modem_id=", tegra_modem_id);
1129
1130 static int __init tegra_usb_port_owner_info(char *id)
1131 {
1132         char *p = id;
1133
1134         usb_port_owner_info = memparse(p, &p);
1135         return 1;
1136 }
1137
1138 int tegra_get_usb_port_owner_info(void)
1139 {
1140         return usb_port_owner_info;
1141 }
1142
1143 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1144
1145 static int __init tegra_commchip_id(char *id)
1146 {
1147         char *p = id;
1148
1149         if (get_option(&p, &commchip_id) != 1)
1150                 return 0;
1151         return 1;
1152 }
1153
1154 int tegra_get_commchip_id(void)
1155 {
1156         return commchip_id;
1157 }
1158
1159 __setup("commchip_id=", tegra_commchip_id);
1160
1161 /*
1162  * Tegra has a protected aperture that prevents access by most non-CPU
1163  * memory masters to addresses above the aperture value.  Enabling it
1164  * secures the CPU's memory from the GPU, except through the GART.
1165  */
1166 void __init tegra_protected_aperture_init(unsigned long aperture)
1167 {
1168 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
1169         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1170         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1171         writel(aperture, mc_base + MC_SECURITY_CFG2);
1172 #else
1173         pr_err("Tegra protected aperture disabled because nvmap is using "
1174                 "system memory\n");
1175 #endif
1176 }
1177
1178 /*
1179  * Due to conflicting restrictions on the placement of the framebuffer,
1180  * the bootloader is likely to leave the framebuffer pointed at a location
1181  * in memory that is outside the grhost aperture.  This function will move
1182  * the framebuffer contents from a physical address that is anywhere (lowmem,
1183  * highmem, or outside the memory map) to a physical address that is outside
1184  * the memory map.
1185  */
1186 void __tegra_move_framebuffer(struct platform_device *pdev,
1187         unsigned long to, unsigned long from,
1188         unsigned long size)
1189 {
1190         struct page *page;
1191         void __iomem *to_io;
1192         void *from_virt;
1193         unsigned long i, addr[] = { to, from, };
1194
1195         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1196         BUG_ON(PAGE_ALIGN(from) != from);
1197         BUG_ON(PAGE_ALIGN(size) != size);
1198
1199         to_io = ioremap(to, size);
1200         if (!to_io) {
1201                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1202                 return;
1203         }
1204
1205         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1206                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1207                         page = phys_to_page(from + i);
1208                         from_virt = kmap(page);
1209                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1210                         kunmap(page);
1211                 }
1212         } else {
1213                 void __iomem *from_io = ioremap(from, size);
1214                 if (!from_io) {
1215                         pr_err("%s: Failed to map source framebuffer\n",
1216                                 __func__);
1217                         goto out;
1218                 }
1219
1220                 for (i = 0; i < size; i += 4)
1221                         writel(readl(from_io + i), to_io + i);
1222
1223                 iounmap(from_io);
1224         }
1225
1226         for (i = 0; i < ARRAY_SIZE(addr); i++)
1227                 dma_map_linear_at(NULL, addr[i], size, DMA_TO_DEVICE);
1228 out:
1229         iounmap(to_io);
1230 }
1231
1232 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1233         unsigned long fb2_size)
1234 {
1235         const size_t avp_kernel_reserve = SZ_32M;
1236 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1237         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1238         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1239         tegra_avp_kernel_size = SZ_1M;
1240         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1241         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1242                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1243                                 "from memory map\n",
1244                         (unsigned long)avp_kernel_reserve,
1245                         tegra_avp_kernel_start);
1246                 tegra_avp_kernel_size = 0;
1247         }
1248 #endif
1249
1250         if (carveout_size) {
1251                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1252                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1253                         pr_err("Failed to remove carveout %08lx@%08lx "
1254                                 "from memory map\n",
1255                                 carveout_size, tegra_carveout_start);
1256                         tegra_carveout_start = 0;
1257                         tegra_carveout_size = 0;
1258                 } else
1259                         tegra_carveout_size = carveout_size;
1260         }
1261
1262         if (fb2_size) {
1263                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1264                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1265                         pr_err("Failed to remove second framebuffer "
1266                                 "%08lx@%08lx from memory map\n",
1267                                 fb2_size, tegra_fb2_start);
1268                         tegra_fb2_start = 0;
1269                         tegra_fb2_size = 0;
1270                 } else
1271                         tegra_fb2_size = fb2_size;
1272         }
1273
1274         if (fb_size) {
1275                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1276                 if (memblock_remove(tegra_fb_start, fb_size)) {
1277                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1278                                 "from memory map\n",
1279                                 fb_size, tegra_fb_start);
1280                         tegra_fb_start = 0;
1281                         tegra_fb_size = 0;
1282                 } else
1283                         tegra_fb_size = fb_size;
1284         }
1285
1286         if (tegra_fb_size)
1287                 tegra_grhost_aperture = tegra_fb_start;
1288
1289         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1290                 tegra_grhost_aperture = tegra_fb2_start;
1291
1292         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1293                 tegra_grhost_aperture = tegra_carveout_start;
1294
1295         if (tegra_lp0_vec_size &&
1296            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1297                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1298                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1299                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1300                         tegra_lp0_vec_start = 0;
1301                         tegra_lp0_vec_size = 0;
1302                 }
1303                 tegra_lp0_vec_relocate = false;
1304         } else
1305                 tegra_lp0_vec_relocate = true;
1306
1307 #ifdef CONFIG_TEGRA_NVDUMPER
1308         if (nvdumper_reserved) {
1309                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1310                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1311                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1312                         nvdumper_reserved = 0;
1313                 }
1314         }
1315 #endif
1316
1317         /*
1318          * We copy the bootloader's framebuffer to the framebuffer allocated
1319          * above, and then free this one.
1320          * */
1321         if (tegra_bootloader_fb_size) {
1322                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1323                 if (memblock_reserve(tegra_bootloader_fb_start,
1324                                 tegra_bootloader_fb_size)) {
1325                         pr_err("Failed to reserve bootloader frame buffer "
1326                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1327                                 tegra_bootloader_fb_start);
1328                         tegra_bootloader_fb_start = 0;
1329                         tegra_bootloader_fb_size = 0;
1330                 }
1331         }
1332
1333         pr_info("Tegra reserved memory:\n"
1334                 "LP0:                    %08lx - %08lx\n"
1335                 "Bootloader framebuffer: %08lx - %08lx\n"
1336                 "Framebuffer:            %08lx - %08lx\n"
1337                 "2nd Framebuffer:        %08lx - %08lx\n"
1338                 "Carveout:               %08lx - %08lx\n"
1339                 "Vpr:                    %08lx - %08lx\n"
1340                 "Tsec:                   %08lx - %08lx\n",
1341                 tegra_lp0_vec_start,
1342                 tegra_lp0_vec_size ?
1343                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1344                 tegra_bootloader_fb_start,
1345                 tegra_bootloader_fb_size ?
1346                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1
1347                         : 0,
1348                 tegra_fb_start,
1349                 tegra_fb_size ?
1350                         tegra_fb_start + tegra_fb_size - 1 : 0,
1351                 tegra_fb2_start,
1352                 tegra_fb2_size ?
1353                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1354                 tegra_carveout_start,
1355                 tegra_carveout_size ?
1356                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1357                 tegra_vpr_start,
1358                 tegra_vpr_size ?
1359                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1360                 tegra_tsec_start,
1361                 tegra_tsec_size ?
1362                         tegra_tsec_start + tegra_tsec_size - 1 : 0);
1363
1364         if (tegra_avp_kernel_size) {
1365                 /* Return excessive memory reserved for AVP kernel */
1366                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1367                         memblock_add(
1368                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1369                                 avp_kernel_reserve - tegra_avp_kernel_size);
1370                 pr_info(
1371                 "AVP kernel: %08lx - %08lx\n",
1372                         tegra_avp_kernel_start,
1373                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1374         }
1375
1376 #ifdef CONFIG_TEGRA_NVDUMPER
1377         if (nvdumper_reserved) {
1378                 pr_info("Nvdumper:               %08lx - %08lx\n",
1379                         nvdumper_reserved,
1380                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1381         }
1382 #endif
1383 }
1384
1385 #ifdef CONFIG_PSTORE_RAM
1386 static struct persistent_ram_descriptor desc = {
1387         .name = "ramoops",
1388 };
1389
1390 static struct persistent_ram ram = {
1391         .descs = &desc,
1392         .num_descs = 1,
1393 };
1394
1395 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1396 {
1397         int ret;
1398
1399         ram.start = memblock_end_of_DRAM() - ram_console_size;
1400         ram.size = ram_console_size;
1401         ram.descs->size = ram_console_size;
1402
1403         INIT_LIST_HEAD(&ram.node);
1404
1405         ret = persistent_ram_early_init(&ram);
1406         if (ret)
1407                 goto fail;
1408
1409         return;
1410
1411 fail:
1412         pr_err("Failed to reserve memory block for ram console\n");
1413 }
1414 #endif
1415
1416 void __init tegra_release_bootloader_fb(void)
1417 {
1418         /* Since bootloader fb is reserved in common.c, it is freed here. */
1419         if (tegra_bootloader_fb_size)
1420                 if (memblock_free(tegra_bootloader_fb_start,
1421                                                 tegra_bootloader_fb_size))
1422                         pr_err("Failed to free bootloader fb.\n");
1423 }
1424
1425 static struct platform_device *pinmux_devices[] = {
1426         &tegra_gpio_device,
1427         &tegra_pinmux_device,
1428 };
1429
1430 void tegra_enable_pinmux(void)
1431 {
1432         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1433 }
1434
1435 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1436         [TEGRA_REVISION_UNKNOWN] = "unknown",
1437         [TEGRA_REVISION_A01]     = "A01",
1438         [TEGRA_REVISION_A02]     = "A02",
1439         [TEGRA_REVISION_A03]     = "A03",
1440         [TEGRA_REVISION_A03p]    = "A03 prime",
1441         [TEGRA_REVISION_A04]     = "A04",
1442         [TEGRA_REVISION_A04p]    = "A04 prime",
1443 };
1444
1445 static const char * __init tegra_get_revision(void)
1446 {
1447         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1448 }
1449
1450 static const char * __init tegra_get_family(void)
1451 {
1452         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1453         u32 cid = readl(chip_id);
1454         cid = (cid >> 8) & 0xFF;
1455
1456         switch (cid) {
1457         case TEGRA_CHIPID_TEGRA2:
1458                 cid = 2;
1459                 break;
1460         case TEGRA_CHIPID_TEGRA3:
1461                 cid = 3;
1462                 break;
1463         case TEGRA_CHIPID_TEGRA11:
1464                 cid = 11;
1465                 break;
1466
1467         case TEGRA_CHIPID_UNKNOWN:
1468         default:
1469                 cid = 0;
1470         }
1471         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1472 }
1473
1474 static const char * __init tegra_get_soc_id(void)
1475 {
1476         int package_id = tegra_package_id();
1477         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1478                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1479 }
1480
1481 static void __init tegra_soc_info_populate(struct soc_device_attribute
1482         *soc_dev_attr, const char *machine)
1483 {
1484         soc_dev_attr->soc_id = tegra_get_soc_id();
1485         soc_dev_attr->machine  = machine;
1486         soc_dev_attr->family   = tegra_get_family();
1487         soc_dev_attr->revision = tegra_get_revision();
1488 }
1489
1490 int __init tegra_soc_device_init(const char *machine)
1491 {
1492         struct soc_device *soc_dev;
1493         struct soc_device_attribute *soc_dev_attr;
1494
1495         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1496         if (!soc_dev_attr)
1497                 return -ENOMEM;
1498
1499         tegra_soc_info_populate(soc_dev_attr, machine);
1500
1501         soc_dev = soc_device_register(soc_dev_attr);
1502         if (IS_ERR_OR_NULL(soc_dev)) {
1503                 kfree(soc_dev_attr);
1504                 return -1;
1505         }
1506
1507         return 0;
1508 }
1509
1510 void __init tegra_init_late(void)
1511 {
1512 #ifndef CONFIG_COMMON_CLK
1513         tegra_clk_debugfs_init();
1514 #endif
1515         tegra_powergate_debugfs_init();
1516 }