ARM: tegra: loki: fix build error due to warning
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36 #if defined(CONFIG_SMSC911X)
37 #include <linux/smsc911x.h>
38 #endif
39 #include <linux/pm.h>
40 #include <linux/tegra-powergate.h>
41
42 #include <linux/export.h>
43 #include <linux/bootmem.h>
44 #include <linux/tegra-soc.h>
45 #include <trace/events/nvsecurity.h>
46
47 #ifdef CONFIG_ARM64
48 #include <linux/irqchip/gic.h>
49 #else
50 #include <asm/system.h>
51 #include <asm/hardware/cache-l2x0.h>
52 #endif
53 #include <asm/dma-mapping.h>
54
55 #include <mach/tegra_smmu.h>
56 #include <mach/nct.h>
57
58 #include "apbio.h"
59 #include "board.h"
60 #include "clock.h"
61 #include "common.h"
62 #include "dvfs.h"
63 #include "fuse.h"
64 #include "iomap.h"
65 #include "pm.h"
66 #include "sleep.h"
67 #include "reset.h"
68 #include "devices.h"
69 #include "pmc.h"
70
71 #define MC_SECURITY_CFG2        0x7c
72
73 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
74 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
75 #define   PRIORITY_SELECT_USB   BIT(6)
76 #define   PRIORITY_SELECT_USB2  BIT(18)
77 #define   PRIORITY_SELECT_USB3  BIT(17)
78 #define   PRIORITY_SELECT_SE BIT(14)
79
80 #define AHB_GIZMO_AHB_MEM               0xc
81 #define   ENB_FAST_REARBITRATE  BIT(2)
82 #define   DONT_SPLIT_AHB_WR     BIT(7)
83 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
84 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
85
86 #define   RECOVERY_MODE BIT(31)
87 #define   BOOTLOADER_MODE       BIT(30)
88 #define   FORCED_RECOVERY_MODE  BIT(1)
89
90 #define AHB_GIZMO_USB           0x1c
91 #define AHB_GIZMO_USB2          0x78
92 #define AHB_GIZMO_USB3          0x7c
93 #define AHB_GIZMO_SE            0x4c
94 #define   IMMEDIATE     BIT(18)
95
96 #define AHB_MEM_PREFETCH_CFG5   0xc8
97 #define AHB_MEM_PREFETCH_CFG3   0xe0
98 #define AHB_MEM_PREFETCH_CFG4   0xe4
99 #define AHB_MEM_PREFETCH_CFG1   0xec
100 #define AHB_MEM_PREFETCH_CFG2   0xf0
101 #define AHB_MEM_PREFETCH_CFG6   0xcc
102 #define   PREFETCH_ENB  BIT(31)
103 #define   MST_ID(x)     (((x) & 0x1f) << 26)
104 #define   AHBDMA_MST_ID MST_ID(5)
105 #define   USB_MST_ID    MST_ID(6)
106 #define SDMMC4_MST_ID   MST_ID(12)
107 #define   USB2_MST_ID   MST_ID(18)
108 #define   USB3_MST_ID   MST_ID(17)
109 #define   SE_MST_ID     MST_ID(14)
110 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
111 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
112
113 phys_addr_t tegra_avp_kernel_start;
114 phys_addr_t tegra_avp_kernel_size;
115 phys_addr_t tegra_bootloader_fb_start;
116 phys_addr_t tegra_bootloader_fb_size;
117 phys_addr_t tegra_bootloader_fb2_start;
118 phys_addr_t tegra_bootloader_fb2_size;
119 phys_addr_t tegra_fb_start;
120 phys_addr_t tegra_fb_size;
121 phys_addr_t tegra_fb2_start;
122 phys_addr_t tegra_fb2_size;
123 phys_addr_t tegra_carveout_start;
124 phys_addr_t tegra_carveout_size;
125 phys_addr_t tegra_vpr_start;
126 phys_addr_t tegra_vpr_size;
127 phys_addr_t tegra_tsec_start;
128 phys_addr_t tegra_tsec_size;
129 phys_addr_t tegra_lp0_vec_start;
130 phys_addr_t tegra_lp0_vec_size;
131 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
132 phys_addr_t tegra_wb0_params_address;
133 phys_addr_t tegra_wb0_params_instances;
134 phys_addr_t tegra_wb0_params_block_size;
135 #endif
136
137 #ifdef CONFIG_TEGRA_NVDUMPER
138 unsigned long nvdumper_reserved;
139 #endif
140 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
141 unsigned long tegra_tzram_start;
142 unsigned long tegra_tzram_size;
143 #endif
144 bool tegra_lp0_vec_relocate;
145 unsigned long tegra_grhost_aperture = ~0ul;
146 static   bool is_tegra_debug_uart_hsport;
147 static struct board_info main_board_info;
148 static struct board_info pmu_board_info;
149 static struct board_info display_board_info;
150 static int panel_id;
151 static struct board_info camera_board_info;
152 static int touch_vendor_id;
153 static int touch_panel_id;
154 static struct board_info io_board_info;
155 static struct board_info button_board_info;
156 static struct board_info joystick_board_info;
157 static struct board_info rightspeaker_board_info;
158 static struct board_info leftspeaker_board_info;
159 #ifdef CONFIG_TEGRA_USE_NCT
160 unsigned long tegra_nck_start;
161 unsigned long tegra_nck_size;
162 #endif
163
164 static int pmu_core_edp;
165 static int board_panel_type;
166 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
167 static int pwr_i2c_clk = 400;
168 static u8 power_config;
169 static u8 display_config;
170
171 static int tegra_split_mem_set;
172
173 /*
174  * Storage for debug-macro.S's state.
175  *
176  * This must be in .data not .bss so that it gets initialized each time the
177  * kernel is loaded. The data is declared here rather than debug-macro.S so
178  * that multiple inclusions of debug-macro.S point at the same data.
179  */
180 u32 tegra_uart_config[4] = {
181         /* Debug UART initialization required */
182         1,
183         /* Debug UART physical address */
184         0,
185         /* Debug UART virtual address */
186         0,
187         /* Scratch space for debug macro */
188         0,
189 };
190
191
192 #define NEVER_RESET 0
193 static DEFINE_SPINLOCK(ahb_lock);
194
195 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
196 {
197         unsigned long check;
198         int retry = 10;
199         unsigned long flags;
200
201         /* Read and check if write is successful,
202          * if val doesn't match with read, retry write.
203          */
204         spin_lock_irqsave(&ahb_lock, flags);
205         do {
206                 writel(val, reg);
207                 check = readl(reg);
208                 if (likely(check == val))
209                         break;
210                 else
211                         pr_err("AHB register access fail for reg\n");
212         } while (--retry);
213         spin_unlock_irqrestore(&ahb_lock, flags);
214 }
215
216 void tegra_assert_system_reset(char mode, const char *cmd)
217 {
218         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
219         u32 reg;
220         bool empty_command = false;
221
222         if (tegra_platform_is_fpga() || NEVER_RESET) {
223                 pr_info("tegra_assert_system_reset() ignored.....");
224                 do { } while (1);
225         }
226
227         reg = readl_relaxed(reset + PMC_SCRATCH0);
228         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
229         if (cmd) {
230                 if (!strcmp(cmd, "recovery"))
231                         reg |= RECOVERY_MODE;
232                 else if (!strcmp(cmd, "bootloader"))
233                         reg |= BOOTLOADER_MODE;
234                 else if (!strcmp(cmd, "forced-recovery"))
235                         reg |= FORCED_RECOVERY_MODE;
236                 else {
237                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
238                         empty_command = true;
239                 }
240         }
241         else {
242                 /* Clearing SCRATCH0 31:30:1 on default reboot */
243                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
244         }
245         writel_relaxed(reg, reset + PMC_SCRATCH0);
246         if ((!cmd || empty_command) && pm_power_reset) {
247                 pm_power_reset();
248         } else {
249                 reg = readl_relaxed(reset);
250                 reg |= 0x10;
251                 writel_relaxed(reg, reset);
252         }
253 }
254 static int modem_id;
255 static int commchip_id;
256 static int sku_override;
257 static int debug_uart_port_id;
258 static enum audio_codec_type audio_codec_name;
259 static enum image_type board_image_type = system_image;
260 static int max_cpu_current;
261 static int max_core_current;
262 static int emc_max_dvfs;
263 static unsigned int memory_type;
264 static int usb_port_owner_info;
265 static int lane_owner_info;
266
267 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
268 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
269         /* name         parent          rate            enabled */
270         { "clk_m",      NULL,           0,              true },
271         { "emc",        NULL,           0,              true },
272         { "cpu",        NULL,           0,              true },
273         { "kfuse",      NULL,           0,              true },
274         { "fuse",       NULL,           0,              true },
275         { "sclk",       NULL,           0,              true },
276         { "pll_p",      NULL,           0,              true },
277         { "pll_p_out1", "pll_p",        0,              false },
278         { "pll_p_out3", "pll_p",        0,              false },
279 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
280         { "pll_m_out1", "pll_m",        275000000,      false },
281         { "pll_p_out2",  "pll_p",       102000000,      false },
282         { "sclk",        "pll_p_out2",  102000000,      true },
283         { "pll_p_out4",  "pll_p",       204000000,      true },
284         { "hclk",       "sclk",         102000000,      true },
285         { "pclk",       "hclk",         51000000,       true },
286         { "mselect",    "pll_p",        102000000,      true },
287         { "host1x",     "pll_p",        102000000,      false },
288         { "cl_dvfs_ref", "pll_p",       51000000,       true },
289         { "cl_dvfs_soc", "pll_p",       51000000,       true },
290         { "dsialp", "pll_p",    70000000,       false },
291         { "dsiblp", "pll_p",    70000000,       false },
292 #else
293         { "pll_m_out1", "pll_m",        275000000,      true },
294         { "pll_p_out2", "pll_p",        108000000,      false },
295         { "sclk",       "pll_p_out2",   108000000,      true },
296         { "pll_p_out4", "pll_p",        216000000,      true },
297         { "hclk",       "sclk",         108000000,      true },
298         { "pclk",       "hclk",         54000000,       true },
299         { "mselect",    "pll_p",        108000000,      true },
300         { "host1x",     "pll_p",        108000000,      false },
301         { "cl_dvfs_ref", "clk_m",       13000000,       false },
302         { "cl_dvfs_soc", "clk_m",       13000000,       false },
303 #endif
304 #ifdef CONFIG_TEGRA_SLOW_CSITE
305         { "csite",      "clk_m",        1000000,        true },
306 #else
307         { "csite",      NULL,           0,              true },
308 #endif
309         { "pll_u",      NULL,           480000000,      true },
310         { "pll_re_vco", NULL,           612000000,      true },
311         { "xusb_falcon_src",    "pll_p",        204000000,      false},
312         { "xusb_host_src",      "pll_p",        102000000,      false},
313         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
314         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
315         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
316         { "sdmmc1",     "pll_p",        48000000,       false},
317         { "sdmmc3",     "pll_p",        48000000,       false},
318         { "sdmmc4",     "pll_p",        48000000,       false},
319         { "sbc1.sclk",  NULL,           40000000,       false},
320         { "sbc2.sclk",  NULL,           40000000,       false},
321         { "sbc3.sclk",  NULL,           40000000,       false},
322         { "sbc4.sclk",  NULL,           40000000,       false},
323         { "sbc5.sclk",  NULL,           40000000,       false},
324         { "sbc6.sclk",  NULL,           40000000,       false},
325 #ifdef CONFIG_TEGRA_DUAL_CBUS
326         { "c2bus",      "pll_c2",       250000000,      false },
327         { "c3bus",      "pll_c3",       250000000,      false },
328         { "pll_c",      NULL,           624000000,      false },
329 #else
330         { "cbus",       "pll_c",        250000000,      false },
331 #endif
332         { "pll_c_out1", "pll_c",        150000000,      false },
333 #ifdef CONFIG_TEGRA_PLLM_SCALED
334         { "vi",         "pll_p",        0,              false},
335 #endif
336 #ifdef CONFIG_TEGRA_SOCTHERM
337         { "soc_therm",  "pll_p",        136000000,      false },
338         { "tsensor",    "clk_m",        500000,         false },
339 #endif
340         { "csite",      NULL,           0,              true },
341         { NULL,         NULL,           0,              0},
342 };
343 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
344 #ifdef CONFIG_TEGRA_DUAL_CBUS
345         { "c2bus",      "pll_c2",       250000000,      false },
346         { "c3bus",      "pll_c3",       250000000,      false },
347         { "pll_c",      NULL,           624000000,      false },
348 #else
349         { "cbus",       "pll_c",        250000000,      false },
350 #endif
351         { "pll_c_out1", "pll_c",        150000000,      false },
352         { NULL,         NULL,           0,              0},
353 };
354 #endif
355 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
356 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
357         /* name         parent          rate            enabled */
358         { "clk_m",      NULL,           0,              true },
359         { "emc",        NULL,           0,              true },
360         { "cpu",        NULL,           0,              true },
361         { "kfuse",      NULL,           0,              true },
362         { "fuse",       NULL,           0,              true },
363         { "sclk",       NULL,           0,              true },
364         { "pll_p",      NULL,           0,              true,
365                 TEGRA_CLK_INIT_PLATFORM_SI },
366         { "pll_p_out1", "pll_p",        0,              false,
367                 TEGRA_CLK_INIT_PLATFORM_SI },
368         { "pll_p_out3", "pll_p",        0,              true,
369                 TEGRA_CLK_INIT_PLATFORM_SI },
370         { "pll_m_out1", "pll_m",        275000000,      false,
371                 TEGRA_CLK_INIT_PLATFORM_SI },
372         { "pll_p_out2", "pll_p",        102000000,      false,
373                 TEGRA_CLK_INIT_PLATFORM_SI },
374         { "sclk",       "pll_p_out2",   102000000,      true,
375                 TEGRA_CLK_INIT_PLATFORM_SI },
376         { "pll_p_out4", "pll_p",        204000000,      true,
377                 TEGRA_CLK_INIT_PLATFORM_SI },
378         { "host1x",     "pll_p",        102000000,      false,
379                 TEGRA_CLK_INIT_PLATFORM_SI },
380         { "cl_dvfs_ref", "pll_p",       54000000,       true,
381                 TEGRA_CLK_INIT_PLATFORM_SI },
382         { "cl_dvfs_soc", "pll_p",       54000000,       true,
383                 TEGRA_CLK_INIT_PLATFORM_SI },
384         { "hclk",       "sclk",         102000000,      true,
385                 TEGRA_CLK_INIT_PLATFORM_SI },
386         { "pclk",       "hclk",         51000000,       true,
387                 TEGRA_CLK_INIT_PLATFORM_SI },
388         { "wake.sclk",  NULL,           40000000,       true,
389                 TEGRA_CLK_INIT_PLATFORM_SI },
390         { "mselect",    "pll_p",        102000000,      true,
391                 TEGRA_CLK_INIT_PLATFORM_SI },
392         { "pll_p_out5", "pll_p",        102000000,      true,
393                 TEGRA_CLK_INIT_PLATFORM_SI },
394 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
395         { "pll_m_out1", "pll_m",        275000000,      true,
396                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
397         { "pll_p_out2", "pll_p",        108000000,      false,
398                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
399         { "sclk",       "pll_p_out2",   108000000,      true,
400                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
401         { "pll_p_out4", "pll_p",        216000000,      true,
402                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
403         { "hclk",       "sclk",         108000000,      true,
404                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
405         { "pclk",       "hclk",         54000000,       true,
406                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
407         { "mselect",    "pll_p",        108000000,      true,
408                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
409         { "host1x",     "pll_p",        108000000,      false,
410                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
411         { "cl_dvfs_ref", "clk_m",       13000000,       false,
412                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
413         { "cl_dvfs_soc", "clk_m",       13000000,       false,
414                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
415         { "vde",        "pll_c3",       48400000,       true,
416                 TEGRA_CLK_INIT_CPU_ASIM},
417 #endif
418 #ifdef CONFIG_TEGRA_SLOW_CSITE
419         { "csite",      "clk_m",        1000000,        true },
420 #else
421         { "csite",      NULL,           0,              true },
422 #endif
423         { "pll_u",      NULL,           480000000,      true },
424         { "pll_re_vco", NULL,           672000000,      false },
425         { "xusb_falcon_src",    "pll_re_out",   224000000,      false},
426         { "xusb_host_src",      "pll_re_out",   112000000,      false},
427         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
428         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
429         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
430         { "sdmmc1",     "pll_p",        48000000,       false},
431         { "sdmmc3",     "pll_p",        48000000,       false},
432         { "sdmmc4",     "pll_p",        48000000,       false},
433         { "sbc1.sclk",  NULL,           40000000,       false},
434         { "sbc2.sclk",  NULL,           40000000,       false},
435         { "sbc3.sclk",  NULL,           40000000,       false},
436         { "sbc4.sclk",  NULL,           40000000,       false},
437         { "sbc5.sclk",  NULL,           40000000,       false},
438         { "sbc6.sclk",  NULL,           40000000,       false},
439         { "gpu_ref",    NULL,           0,              true},
440 #ifdef CONFIG_TEGRA_PLLM_SCALED
441         { "vi",         "pll_p",        0,              false},
442         { "isp",        "pll_p",        0,              false},
443 #endif
444 #ifdef CONFIG_TEGRA_SOCTHERM
445         { "soc_therm",  "pll_p",        51000000,       false },
446         { "tsensor",    "clk_m",        500000,         false },
447 #endif
448         { NULL,         NULL,           0,              0},
449 };
450 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
451         /* Initialize c2bus, c3bus, or cbus at the end of the list
452          * after all the clocks are moved under the proper parents.
453          */
454 #ifdef CONFIG_TEGRA_DUAL_CBUS
455         { "c2bus",      "pll_c2",       250000000,      false },
456         { "c3bus",      "pll_c3",       250000000,      false },
457         { "pll_c",      NULL,           792000000,      false },
458 #else
459         { "cbus",       "pll_c",        200000000,      false },
460 #endif
461         { "pll_c_out1", "pll_c",        100000000,      false },
462         { "c4bus",      "pll_c4",       200000000,      false },
463         { NULL,         NULL,           0,              0},
464 };
465 #endif
466
467 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
468 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
469         /* name         parent          rate            enabled */
470         { "osc",        NULL,           0,              true },
471         { "clk_m",      "osc",          0,              true },
472         { "emc",        NULL,           0,              true },
473         { "cpu",        NULL,           0,              true },
474         { "kfuse",      NULL,           0,              true },
475         { "fuse",       NULL,           0,              true },
476         { "sclk",       NULL,           0,              true },
477 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
478         { "pll_p",      NULL,           0,              true },
479         { "pll_p_out1", "pll_p",        0,              false },
480         { "pll_p_out3", "pll_p",        0,              true },
481         { "pll_m_out1", "pll_m",        275000000,      false },
482         { "pll_p_out2",  "pll_p",       102000000,      false },
483         { "sclk",        "pll_p_out2",  102000000,      true },
484         { "pll_p_out4",  "pll_p",       204000000,      true },
485         { "hclk",       "sclk",         102000000,      true },
486         { "pclk",       "hclk",         51000000,       true },
487         { "mselect",    "pll_p",        102000000,      true },
488         { "host1x",     "pll_p",        102000000,      false },
489         { "cl_dvfs_ref", "pll_p",       51000000,       true },
490         { "cl_dvfs_soc", "pll_p",       51000000,       true },
491 #else
492         { "pll_p",      NULL,           0,              true },
493         { "pll_p_out1", "pll_p",        0,              false },
494         { "pll_p_out3", "pll_p",        0,              true },
495         { "pll_m_out1", "pll_m",        275000000,      true },
496         { "pll_p_out2", "pll_p",        108000000,      false },
497         { "sclk",       "pll_p_out2",   108000000,      true },
498         { "pll_p_out4", "pll_p",        216000000,      true },
499         { "host1x",     "pll_p",        108000000,      false },
500         { "cl_dvfs_ref", "clk_m",       13000000,       false },
501         { "cl_dvfs_soc", "clk_m",       13000000,       false },
502         { "hclk",       "sclk",         108000000,      true },
503         { "pclk",       "hclk",         54000000,       true },
504         { "wake.sclk",  NULL,           250000000,      true },
505         { "mselect",    "pll_p",        108000000,      true },
506 #endif
507 #ifdef CONFIG_TEGRA_SLOW_CSITE
508         { "csite",      "clk_m",        1000000,        true },
509 #else
510         { "csite",      NULL,           0,              true },
511 #endif
512         { "pll_u",      NULL,           480000000,      false },
513         { "sdmmc1",     "pll_p",        48000000,       false},
514         { "sdmmc3",     "pll_p",        48000000,       false},
515         { "sdmmc4",     "pll_p",        48000000,       false},
516         { "mon.avp",    NULL,           80000000,       true },
517         { "sbc1.sclk",  NULL,           20000000,       false},
518         { "sbc2.sclk",  NULL,           20000000,       false},
519         { "sbc3.sclk",  NULL,           20000000,       false},
520         { "msenc",      "pll_p",        108000000,      false },
521         { "tsec",       "pll_p",        108000000,      false },
522         { "mc_capa",    "emc",          0,              true },
523         { "mc_cbpa",    "emc",          0,              true },
524 #ifdef CONFIG_TEGRA_SOCTHERM
525         { "soc_therm",  "pll_p",        51000000,       false },
526         { "tsensor",    "clk_m",        400000,         false },
527 #endif
528         { NULL,         NULL,           0,              0},
529 };
530 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
531         /* Initialize c2bus, c3bus, or cbus at the end of the list
532          * after all the clocks are moved under the proper parents.
533          */
534 #ifdef CONFIG_TEGRA_DUAL_CBUS
535         { "c2bus",      "pll_c2",       200000000,      false },
536         { "c3bus",      "pll_c3",       200000000,      false },
537         { "pll_c",      NULL,           768000000,      false },
538 #else
539         { "cbus",       "pll_c",        200000000,      false },
540 #endif
541         { "pll_c_out1", "pll_c",        100000000,      false },
542         { NULL,         NULL,           0,              0},
543 };
544 #endif
545
546 #ifdef CONFIG_CACHE_L2X0
547 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
548 static void tegra_cache_smc(bool enable, u32 arg)
549 {
550         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
551         bool need_affinity_switch;
552         bool can_switch_affinity;
553         bool l2x0_enabled;
554         cpumask_t local_cpu_mask;
555         cpumask_t saved_cpu_mask;
556         unsigned long flags;
557         long ret;
558
559         /*
560          * ISSUE : Some registers of PL310 controler must be written
561          *              from Secure context (and from CPU0)!
562          *
563          * When called form Normal we obtain an abort or do nothing.
564          * Instructions that must be called in Secure:
565          *      - Write to Control register (L2X0_CTRL==0x100)
566          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
567          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
568          *              mandatory at boot time.
569          *      - Tag and Data RAM Latency Control Registers
570          *              (0x108 & 0x10C) must be written in Secure.
571          */
572         need_affinity_switch = (smp_processor_id() != 0);
573         can_switch_affinity = !irqs_disabled();
574
575         WARN_ON(need_affinity_switch && !can_switch_affinity);
576         if (need_affinity_switch && can_switch_affinity) {
577                 cpu_set(0, local_cpu_mask);
578                 sched_getaffinity(0, &saved_cpu_mask);
579                 ret = sched_setaffinity(0, &local_cpu_mask);
580                 WARN_ON(ret != 0);
581         }
582
583         local_irq_save(flags);
584         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
585         if (enable && !l2x0_enabled)
586                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
587         else if (!enable && l2x0_enabled)
588                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
589         local_irq_restore(flags);
590
591         if (need_affinity_switch && can_switch_affinity) {
592                 ret = sched_setaffinity(0, &saved_cpu_mask);
593                 WARN_ON(ret != 0);
594         }
595 }
596
597 static void tegra_l2x0_disable(void)
598 {
599         unsigned long flags;
600         static u32 l2x0_way_mask;
601
602         if (!l2x0_way_mask) {
603                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
604                 u32 aux_ctrl;
605                 u32 ways;
606
607                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
608                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
609                 l2x0_way_mask = (1 << ways) - 1;
610         }
611
612         local_irq_save(flags);
613         tegra_cache_smc(false, l2x0_way_mask);
614         local_irq_restore(flags);
615 }
616 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
617
618 void tegra_init_cache(bool init)
619 {
620         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
621         u32 aux_ctrl;
622 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
623         u32 cache_type;
624         u32 tag_latency, data_latency;
625 #endif
626
627 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
628         /* issue the SMC to enable the L2 */
629         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
630         trace_smc_init_cache(NVSEC_SMC_START);
631         tegra_cache_smc(true, aux_ctrl);
632         trace_smc_init_cache(NVSEC_SMC_DONE);
633
634         /* after init, reread aux_ctrl and register handlers */
635         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
636         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
637
638         /* override outer_disable() with our disable */
639         outer_cache.disable = tegra_l2x0_disable;
640 #else
641 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
642         tag_latency = 0x331;
643         data_latency = 0x441;
644 #else
645         if (!tegra_platform_is_silicon()) {
646                 tag_latency = 0x770;
647                 data_latency = 0x770;
648         } else if (is_lp_cluster()) {
649                 tag_latency = tegra_cpu_c1_l2_tag_latency;
650                 data_latency = tegra_cpu_c1_l2_data_latency;
651         } else {
652                 tag_latency = tegra_cpu_c0_l2_tag_latency;
653                 data_latency = tegra_cpu_c0_l2_data_latency;
654         }
655 #endif
656         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
657         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
658
659 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
660         if (!tegra_platform_is_fpga()) {
661 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
662                 /* Enable double line fill */
663                 writel(0x40000007, p + L2X0_PREFETCH_CTRL);
664 #else
665                 writel(0x7, p + L2X0_PREFETCH_CTRL);
666 #endif
667                 writel(0x3, p + L2X0_POWER_CTRL);
668         }
669 #endif
670         cache_type = readl(p + L2X0_CACHE_TYPE);
671         aux_ctrl = (cache_type & 0x700) << (17-8);
672         aux_ctrl |= 0x7C400001;
673         if (init) {
674                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
675         } else {
676                 u32 tmp;
677
678                 tmp = aux_ctrl;
679                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
680                 aux_ctrl &= 0x8200c3fe;
681                 aux_ctrl |= tmp;
682                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
683         }
684         l2x0_enable();
685 #endif
686 }
687 #endif
688
689 static void __init tegra_perf_init(void)
690 {
691         u32 reg;
692
693 #ifdef CONFIG_ARM64
694         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
695         reg >>= 11;
696         reg = (1 << (reg & 0x1f))-1;
697         reg |= 0x80000000;
698         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
699         reg = 1;
700         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
701 #else
702         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
703         reg >>= 11;
704         reg = (1 << (reg & 0x1f))-1;
705         reg |= 0x80000000;
706         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
707         reg = 1;
708         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
709 #endif
710 }
711
712 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
713 static void __init tegra_ramrepair_init(void)
714 {
715         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
716                 u32 reg;
717                 reg = readl(FLOW_CTRL_RAM_REPAIR);
718                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
719                 writel(reg, FLOW_CTRL_RAM_REPAIR);
720         }
721 }
722 #endif
723
724 static void __init tegra_init_power(void)
725 {
726 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
727         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
728 #endif
729 #if defined(CONFIG_ARCH_TEGRA_HAS_PCIE) && \
730                         !defined(CONFIG_TEGRA_PCIE_SKIP_POWERGATING)
731         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
732 #endif
733
734 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
735         /* powergate xusb partitions by default */
736         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
737         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
738         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
739 #endif
740
741 }
742
743 static inline unsigned long gizmo_readl(unsigned long offset)
744 {
745         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
746 }
747
748 static inline void gizmo_writel(unsigned long value, unsigned long offset)
749 {
750         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
751 }
752
753 static void __init tegra_init_ahb_gizmo_settings(void)
754 {
755         unsigned long val;
756
757         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
758         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
759
760         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
761                 val |= WR_WAIT_COMMIT_ON_1K;
762 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
763         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
764 #endif
765         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
766
767         val = gizmo_readl(AHB_GIZMO_USB);
768         val |= IMMEDIATE;
769         gizmo_writel(val, AHB_GIZMO_USB);
770
771         val = gizmo_readl(AHB_GIZMO_USB2);
772         val |= IMMEDIATE;
773         gizmo_writel(val, AHB_GIZMO_USB2);
774
775         val = gizmo_readl(AHB_GIZMO_USB3);
776         val |= IMMEDIATE;
777         gizmo_writel(val, AHB_GIZMO_USB3);
778
779         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
780         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
781                                 | AHB_PRIORITY_WEIGHT(7);
782 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
783         val |= PRIORITY_SELECT_SE;
784 #endif
785
786         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
787
788         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
789         val &= ~MST_ID(~0);
790         val |= PREFETCH_ENB | AHBDMA_MST_ID |
791                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
792         ahb_gizmo_writel(val,
793                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
794
795         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
796         val &= ~MST_ID(~0);
797         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
798                 INACTIVITY_TIMEOUT(0x1000);
799         ahb_gizmo_writel(val,
800                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
801
802         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
803         val &= ~MST_ID(~0);
804         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
805                 INACTIVITY_TIMEOUT(0x1000);
806         ahb_gizmo_writel(val,
807                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
808
809         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
810         val &= ~MST_ID(~0);
811         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
812                 INACTIVITY_TIMEOUT(0x1000);
813         ahb_gizmo_writel(val,
814                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
815
816         /*
817          * SDMMC controller is removed from AHB interface in T124 and
818          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
819          * in T11x and T14x SOCs.
820          */
821 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
822         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
823         val &= ~MST_ID(~0);
824         val |= PREFETCH_ENB | SDMMC4_MST_ID;
825         val &= ~SDMMC4_MST_ID;
826         ahb_gizmo_writel(val,
827                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
828 #endif
829
830 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
831         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
832         val &= ~MST_ID(~0);
833         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
834                 INACTIVITY_TIMEOUT(0x1000);
835         ahb_gizmo_writel(val,
836                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
837 #endif
838 }
839
840 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
841 void __init tegra20_init_early(void)
842 {
843 #ifndef CONFIG_SMP
844         /* For SMP system, initializing the reset handler here is too
845            late. For non-SMP systems, the function that calls the reset
846            handler initializer is not called, so do it here for non-SMP. */
847         tegra_cpu_reset_handler_init();
848 #endif
849         tegra_apb_io_init();
850         tegra_perf_init();
851         tegra_init_fuse();
852         tegra_init_cache(true);
853         tegra_pmc_init();
854         tegra_powergate_init();
855         tegra20_hotplug_init();
856         tegra_init_power();
857         tegra_init_ahb_gizmo_settings();
858         tegra_init_debug_uart_rate();
859         tegra_ram_console_debug_reserve(SZ_1M);
860 }
861 #endif
862 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
863 void __init tegra30_init_early(void)
864 {
865         u32 speedo;
866         u32 tag_latency, data_latency;
867
868 #ifndef CONFIG_SMP
869         /* For SMP system, initializing the reset handler here is too
870            late. For non-SMP systems, the function that calls the reset
871            handler initializer is not called, so do it here for non-SMP. */
872         tegra_cpu_reset_handler_init();
873 #endif
874         tegra_apb_io_init();
875         tegra_perf_init();
876         tegra_init_fuse();
877         /*
878          * Store G/LP cluster L2 latencies to IRAM and DRAM
879          */
880         tegra_cpu_c1_l2_tag_latency = 0x221;
881         tegra_cpu_c1_l2_data_latency = 0x221;
882         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
883         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
884         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
885         speedo = tegra_cpu_speedo_id();
886         if (speedo == 4 || speedo == 5 || speedo == 6 ||
887             speedo == 12 || speedo == 13) {
888                 tag_latency = 0x442;
889                 data_latency = 0x552;
890         } else {
891                 tag_latency = 0x441;
892                 data_latency = 0x551;
893         }
894         tegra_cpu_c0_l2_tag_latency = tag_latency;
895         tegra_cpu_c0_l2_data_latency = data_latency;
896         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
897         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
898         tegra_init_cache(true);
899         tegra_pmc_init();
900         tegra_powergate_init();
901         tegra30_hotplug_init();
902         tegra_init_power();
903         tegra_init_ahb_gizmo_settings();
904         tegra_init_debug_uart_rate();
905         tegra_ram_console_debug_reserve(SZ_1M);
906
907         init_dma_coherent_pool_size(SZ_1M);
908 }
909 #endif
910 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
911 void __init tegra11x_init_early(void)
912 {
913 #ifndef CONFIG_SMP
914         /* For SMP system, initializing the reset handler here is too
915            late. For non-SMP systems, the function that calls the reset
916            handler initializer is not called, so do it here for non-SMP. */
917         tegra_cpu_reset_handler_init();
918 #endif
919         tegra_apb_io_init();
920         tegra_perf_init();
921         tegra_init_fuse();
922         tegra_ramrepair_init();
923         tegra11x_init_clocks();
924         tegra11x_init_dvfs();
925         tegra_common_init_clock();
926         tegra_clk_init_from_table(tegra11x_clk_init_table);
927         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
928         tegra11x_clk_init_la();
929         tegra_pmc_init();
930         tegra_powergate_init();
931         tegra30_hotplug_init();
932         tegra_init_power();
933         tegra_init_ahb_gizmo_settings();
934         tegra_init_debug_uart_rate();
935
936         init_dma_coherent_pool_size(SZ_2M);
937 }
938 #endif
939 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
940 void __init tegra12x_init_early(void)
941 {
942 #ifndef CONFIG_SMP
943         /* For SMP system, initializing the reset handler here is too
944            late. For non-SMP systems, the function that calls the reset
945            handler initializer is not called, so do it here for non-SMP. */
946         tegra_cpu_reset_handler_init();
947 #endif
948         tegra_apb_io_init();
949         tegra_perf_init();
950         tegra_init_fuse();
951         tegra_ramrepair_init();
952         tegra12x_init_clocks();
953         tegra12x_init_dvfs();
954         tegra_common_init_clock();
955         tegra_clk_init_from_table(tegra12x_clk_init_table);
956         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
957         tegra_init_cache(true);
958         tegra_pmc_init();
959         tegra_powergate_init();
960         tegra30_hotplug_init();
961         tegra_init_power();
962         tegra_init_ahb_gizmo_settings();
963         tegra_init_debug_uart_rate();
964 }
965 #endif
966 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
967 void __init tegra14x_init_early(void)
968 {
969 #ifndef CONFIG_SMP
970         /* For SMP system, initializing the reset handler here is too
971            late. For non-SMP systems, the function that calls the reset
972            handler initializer is not called, so do it here for non-SMP. */
973         tegra_cpu_reset_handler_init();
974 #endif
975         tegra_apb_io_init();
976         tegra_perf_init();
977         tegra_init_fuse();
978         tegra_ramrepair_init();
979         tegra14x_init_clocks();
980         tegra14x_init_dvfs();
981         tegra_common_init_clock();
982         tegra_clk_init_from_table(tegra14x_clk_init_table);
983         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
984         tegra_cpu_c1_l2_tag_latency = 0x110;
985         tegra_cpu_c1_l2_data_latency = 0x331;
986         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
987         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
988         tegra_cpu_c0_l2_tag_latency = 0x111;
989         tegra_cpu_c0_l2_data_latency = 0x441;
990         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
991         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
992         tegra_init_cache(true);
993         tegra_pmc_init();
994         tegra_powergate_init();
995         tegra30_hotplug_init();
996         tegra_init_power();
997         tegra_init_ahb_gizmo_settings();
998         tegra_init_debug_uart_rate();
999         tegra_ram_console_debug_reserve(SZ_1M);
1000 }
1001 #endif
1002 static int __init tegra_lp0_vec_arg(char *options)
1003 {
1004         char *p = options;
1005
1006         tegra_lp0_vec_size = memparse(p, &p);
1007         if (*p == '@')
1008                 tegra_lp0_vec_start = memparse(p+1, &p);
1009         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1010                 tegra_lp0_vec_size = 0;
1011                 tegra_lp0_vec_start = 0;
1012         }
1013
1014         return 0;
1015 }
1016 early_param("lp0_vec", tegra_lp0_vec_arg);
1017
1018 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1019 static int __init tegra_wb0_params_arg(char *options)
1020 {
1021         char *p = options;
1022
1023         tegra_wb0_params_address = memparse(p, &p);
1024         if (*p == ',')
1025                 tegra_wb0_params_instances = memparse(p+1, &p);
1026         if (*p == ',')
1027                 tegra_wb0_params_block_size = memparse(p+1, &p);
1028
1029         return 0;
1030 }
1031 early_param("wb0_params", tegra_wb0_params_arg);
1032 #endif
1033
1034 #ifdef CONFIG_TEGRA_NVDUMPER
1035 static int __init tegra_nvdumper_arg(char *options)
1036 {
1037         char *p = options;
1038
1039         nvdumper_reserved = memparse(p, &p);
1040         return 0;
1041 }
1042 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1043 #endif
1044
1045 static int __init tegra_bootloader_fb_arg(char *options)
1046 {
1047         char *p = options;
1048
1049         tegra_bootloader_fb_size = memparse(p, &p);
1050         if (*p == '@')
1051                 tegra_bootloader_fb_start = memparse(p+1, &p);
1052
1053         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1054                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1055
1056         return 0;
1057 }
1058 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1059
1060 static int __init tegra_bootloader_fb2_arg(char *options)
1061 {
1062         char *p = options;
1063
1064         tegra_bootloader_fb2_size = memparse(p, &p);
1065         if (*p == '@')
1066                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1067
1068         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1069                 (u64)tegra_bootloader_fb2_size,
1070                 (u64)tegra_bootloader_fb2_start);
1071
1072         return 0;
1073 }
1074 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1075
1076 static int __init tegra_sku_override(char *id)
1077 {
1078         char *p = id;
1079
1080         sku_override = memparse(p, &p);
1081
1082         return 0;
1083 }
1084 early_param("sku_override", tegra_sku_override);
1085
1086 int tegra_get_sku_override(void)
1087 {
1088         return sku_override;
1089 }
1090
1091 static int __init tegra_vpr_arg(char *options)
1092 {
1093         char *p = options;
1094
1095         tegra_vpr_size = memparse(p, &p);
1096         if (*p == '@')
1097                 tegra_vpr_start = memparse(p+1, &p);
1098         pr_info("Found vpr, start=0x%llx size=%llx",
1099                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1100         return 0;
1101 }
1102 early_param("vpr", tegra_vpr_arg);
1103
1104 static int __init tegra_tsec_arg(char *options)
1105 {
1106         char *p = options;
1107
1108         tegra_tsec_size = memparse(p, &p);
1109         if (*p == '@')
1110                 tegra_tsec_start = memparse(p+1, &p);
1111         pr_info("Found tsec, start=0x%llx size=%llx",
1112                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1113         return 0;
1114 }
1115 early_param("tsec", tegra_tsec_arg);
1116
1117 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1118 static int __init tegra_tzram_arg(char *options)
1119 {
1120         char *p = options;
1121
1122         tegra_tzram_size = memparse(p, &p);
1123         if (*p == '@')
1124                 tegra_tzram_start = memparse(p + 1, &p);
1125         return 0;
1126 }
1127 early_param("tzram", tegra_tzram_arg);
1128 #endif
1129
1130 #ifdef CONFIG_TEGRA_USE_NCT
1131 static int __init tegra_nck_arg(char *options)
1132 {
1133         char *p = options;
1134
1135         tegra_nck_size = memparse(p, &p);
1136         if (*p == '@')
1137                 tegra_nck_start = memparse(p+1, &p);
1138         if (!tegra_nck_size || !tegra_nck_start) {
1139                 tegra_nck_size = 0;
1140                 tegra_nck_start = 0;
1141         }
1142
1143         return 0;
1144 }
1145 early_param("nck", tegra_nck_arg);
1146 #endif  /* CONFIG_TEGRA_USE_NCT */
1147
1148 enum panel_type get_panel_type(void)
1149 {
1150         return board_panel_type;
1151 }
1152 static int __init tegra_board_panel_type(char *options)
1153 {
1154         if (!strcmp(options, "lvds"))
1155                 board_panel_type = panel_type_lvds;
1156         else if (!strcmp(options, "dsi"))
1157                 board_panel_type = panel_type_dsi;
1158         else
1159                 return 0;
1160         return 1;
1161 }
1162 __setup("panel=", tegra_board_panel_type);
1163
1164 int tegra_get_board_panel_id(void)
1165 {
1166         return panel_id;
1167 }
1168 static int __init tegra_board_panel_id(char *options)
1169 {
1170         char *p = options;
1171         panel_id = memparse(p, &p);
1172         return panel_id;
1173 }
1174 __setup("display_panel=", tegra_board_panel_id);
1175
1176 int tegra_get_touch_vendor_id(void)
1177 {
1178         return touch_vendor_id;
1179 }
1180 int tegra_get_touch_panel_id(void)
1181 {
1182         return touch_panel_id;
1183 }
1184 static int __init tegra_touch_id(char *options)
1185 {
1186         char *p = options;
1187         touch_vendor_id = memparse(p, &p);
1188         if (*p == '@')
1189                 touch_panel_id = memparse(p+1, &p);
1190         return 1;
1191 }
1192 __setup("touch_id=", tegra_touch_id);
1193
1194 u8 get_power_config(void)
1195 {
1196         return power_config;
1197 }
1198 static int __init tegra_board_power_config(char *options)
1199 {
1200         char *p = options;
1201         power_config = memparse(p, &p);
1202         return 1;
1203 }
1204 __setup("power-config=", tegra_board_power_config);
1205
1206 u8 get_display_config(void)
1207 {
1208         return display_config;
1209 }
1210 static int __init tegra_board_display_config(char *options)
1211 {
1212         char *p = options;
1213         display_config = memparse(p, &p);
1214         return 1;
1215 }
1216 __setup("display-config=", tegra_board_display_config);
1217
1218 enum power_supply_type get_power_supply_type(void)
1219 {
1220         return pow_supply_type;
1221 }
1222 static int __init tegra_board_power_supply_type(char *options)
1223 {
1224         if (!strcmp(options, "Adapter"))
1225                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1226         if (!strcmp(options, "Mains"))
1227                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1228         else if (!strcmp(options, "Battery"))
1229                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1230         else
1231                 return 0;
1232         return 1;
1233 }
1234 __setup("power_supply=", tegra_board_power_supply_type);
1235
1236 int get_core_edp(void)
1237 {
1238         return pmu_core_edp;
1239 }
1240 static int __init tegra_pmu_core_edp(char *options)
1241 {
1242         char *p = options;
1243         int core_edp = memparse(p, &p);
1244         if (core_edp != 0)
1245                 pmu_core_edp = core_edp;
1246         return 0;
1247 }
1248 early_param("core_edp_mv", tegra_pmu_core_edp);
1249
1250 int get_maximum_cpu_current_supported(void)
1251 {
1252         return max_cpu_current;
1253 }
1254 static int __init tegra_max_cpu_current(char *options)
1255 {
1256         char *p = options;
1257         max_cpu_current = memparse(p, &p);
1258         return 1;
1259 }
1260 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1261
1262 int get_maximum_core_current_supported(void)
1263 {
1264         return max_core_current;
1265 }
1266 static int __init tegra_max_core_current(char *options)
1267 {
1268         char *p = options;
1269         max_core_current = memparse(p, &p);
1270         return 0;
1271 }
1272 early_param("core_edp_ma", tegra_max_core_current);
1273
1274 int get_emc_max_dvfs(void)
1275 {
1276         return emc_max_dvfs;
1277 }
1278 static int __init tegra_emc_max_dvfs(char *options)
1279 {
1280         char *p = options;
1281         emc_max_dvfs = memparse(p, &p);
1282         return 1;
1283 }
1284 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1285
1286 int tegra_get_memory_type(void)
1287 {
1288         return memory_type;
1289 }
1290 static int __init tegra_memory_type(char *options)
1291 {
1292         char *p = options;
1293         memory_type = memparse(p, &p);
1294         return 1;
1295 }
1296 __setup("memtype=", tegra_memory_type);
1297
1298 static int __init tegra_debug_uartport(char *info)
1299 {
1300         char *p = info;
1301         unsigned long long port_id;
1302         if (!strncmp(p, "hsport", 6))
1303                 is_tegra_debug_uart_hsport = true;
1304         else if (!strncmp(p, "lsport", 6))
1305                 is_tegra_debug_uart_hsport = false;
1306
1307         if (p[6] == ',') {
1308                 if (p[7] == '-') {
1309                         debug_uart_port_id = -1;
1310                 } else {
1311                         port_id = memparse(p + 7, &p);
1312                         debug_uart_port_id = (int) port_id;
1313                 }
1314         } else {
1315                 debug_uart_port_id = -1;
1316         }
1317
1318         return 1;
1319 }
1320
1321 bool is_tegra_debug_uartport_hs(void)
1322 {
1323         return is_tegra_debug_uart_hsport;
1324 }
1325
1326 int get_tegra_uart_debug_port_id(void)
1327 {
1328         return debug_uart_port_id;
1329 }
1330 __setup("debug_uartport=", tegra_debug_uartport);
1331
1332 static int __init tegra_image_type(char *options)
1333 {
1334         if (!strcmp(options, "RCK"))
1335                 board_image_type = rck_image;
1336
1337         return 0;
1338 }
1339
1340 enum image_type get_tegra_image_type(void)
1341 {
1342         return board_image_type;
1343 }
1344
1345 __setup("image=", tegra_image_type);
1346
1347 static int __init tegra_audio_codec_type(char *info)
1348 {
1349         char *p = info;
1350         if (!strncmp(p, "wm8903", 6))
1351                 audio_codec_name = audio_codec_wm8903;
1352         else
1353                 audio_codec_name = audio_codec_none;
1354
1355         return 1;
1356 }
1357
1358 enum audio_codec_type get_audio_codec_type(void)
1359 {
1360         return audio_codec_name;
1361 }
1362 __setup("audio_codec=", tegra_audio_codec_type);
1363
1364 static int tegra_get_pwr_i2c_clk_rate(char *options)
1365 {
1366         int clk = simple_strtol(options, NULL, 16);
1367         if (clk != 0)
1368                 pwr_i2c_clk = clk;
1369         return 0;
1370 }
1371
1372 int get_pwr_i2c_clk_rate(void)
1373 {
1374         return pwr_i2c_clk;
1375 }
1376 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1377
1378 static bool pmic_wdt_disable;
1379 bool is_pmic_wdt_disabled_at_boot(void)
1380 {
1381         return pmic_wdt_disable;
1382 }
1383
1384 static int parse_arg_pmic_wdt_disable(char *options)
1385 {
1386         /* no kernel command line argument "watchdog" interpreted as
1387          * watchdog enable
1388          */
1389         pmic_wdt_disable = false;
1390         if (!(strcmp(options, "enable")))
1391                 pmic_wdt_disable = false;
1392         else if (!(strcmp(options, "disable")))
1393                 pmic_wdt_disable = true;
1394         /* kernel command line from fastboot does not support
1395          * other values
1396          */
1397
1398         return 0;
1399 }
1400 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1401
1402 void tegra_get_board_info(struct board_info *bi)
1403 {
1404 #ifdef CONFIG_OF
1405         struct device_node *board_info;
1406         u32 prop_val;
1407         int err;
1408
1409         board_info = of_find_node_by_path("/chosen/board_info");
1410         if (!IS_ERR_OR_NULL(board_info)) {
1411                 memset(bi, 0, sizeof(*bi));
1412
1413                 err = of_property_read_u32(board_info, "id", &prop_val);
1414                 if (err)
1415                         pr_err("failed to read /chosen/board_info/id\n");
1416                 else
1417                         bi->board_id = prop_val;
1418
1419                 err = of_property_read_u32(board_info, "sku", &prop_val);
1420                 if (err)
1421                         pr_err("failed to read /chosen/board_info/sku\n");
1422                 else
1423                         bi->sku = prop_val;
1424
1425                 err = of_property_read_u32(board_info, "fab", &prop_val);
1426                 if (err)
1427                         pr_err("failed to read /chosen/board_info/fab\n");
1428                 else
1429                         bi->fab = prop_val;
1430
1431                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1432                 if (err)
1433                         pr_err("failed to read /chosen/board_info/major_revision\n");
1434                 else
1435                         bi->major_revision = prop_val;
1436
1437                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1438                 if (err)
1439                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1440                 else
1441                         bi->minor_revision = prop_val;
1442 #ifndef CONFIG_ARM64
1443                 system_serial_high = (bi->board_id << 16) | bi->sku;
1444                 system_serial_low = (bi->fab << 24) |
1445                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1446 #endif
1447         } else {
1448 #endif
1449 #ifdef CONFIG_ARM64
1450                 /* FIXME:
1451                  * use dummy values for now as system_serial_high/low
1452                  * are gone in arm64.
1453                  */
1454                 bi->board_id = 0xDEAD;
1455                 bi->sku = 0xDEAD;
1456                 bi->fab = 0xDD;
1457                 bi->major_revision = 0xDD;
1458                 bi->minor_revision = 0xDD;
1459 #else
1460                 if (system_serial_high || system_serial_low) {
1461                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1462                         bi->sku = (system_serial_high) & 0xFFFF;
1463                         bi->fab = (system_serial_low >> 24) & 0xFF;
1464                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1465                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1466                 } else {
1467                         memcpy(bi, &main_board_info, sizeof(struct board_info));
1468                 }
1469 #endif
1470 #ifdef CONFIG_OF
1471         }
1472 #endif
1473 }
1474
1475 static int __init tegra_main_board_info(char *info)
1476 {
1477         char *p = info;
1478         main_board_info.board_id = memparse(p, &p);
1479         main_board_info.sku = memparse(p+1, &p);
1480         main_board_info.fab = memparse(p+1, &p);
1481         main_board_info.major_revision = memparse(p+1, &p);
1482         main_board_info.minor_revision = memparse(p+1, &p);
1483         return 1;
1484 }
1485
1486 __setup("board_info=", tegra_main_board_info);
1487
1488 static int __init tegra_pmu_board_info(char *info)
1489 {
1490         char *p = info;
1491         pmu_board_info.board_id = memparse(p, &p);
1492         pmu_board_info.sku = memparse(p+1, &p);
1493         pmu_board_info.fab = memparse(p+1, &p);
1494         pmu_board_info.major_revision = memparse(p+1, &p);
1495         pmu_board_info.minor_revision = memparse(p+1, &p);
1496         return 0;
1497 }
1498
1499 void tegra_get_pmu_board_info(struct board_info *bi)
1500 {
1501         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1502 }
1503
1504 early_param("pmuboard", tegra_pmu_board_info);
1505
1506 static int __init tegra_display_board_info(char *info)
1507 {
1508         char *p = info;
1509         display_board_info.board_id = memparse(p, &p);
1510         display_board_info.sku = memparse(p+1, &p);
1511         display_board_info.fab = memparse(p+1, &p);
1512         display_board_info.major_revision = memparse(p+1, &p);
1513         display_board_info.minor_revision = memparse(p+1, &p);
1514         return 1;
1515 }
1516
1517 void tegra_get_display_board_info(struct board_info *bi)
1518 {
1519         memcpy(bi, &display_board_info, sizeof(struct board_info));
1520 }
1521
1522 __setup("displayboard=", tegra_display_board_info);
1523
1524 static int __init tegra_camera_board_info(char *info)
1525 {
1526         char *p = info;
1527         camera_board_info.board_id = memparse(p, &p);
1528         camera_board_info.sku = memparse(p+1, &p);
1529         camera_board_info.fab = memparse(p+1, &p);
1530         camera_board_info.major_revision = memparse(p+1, &p);
1531         camera_board_info.minor_revision = memparse(p+1, &p);
1532         return 1;
1533 }
1534
1535 void tegra_get_camera_board_info(struct board_info *bi)
1536 {
1537         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1538 }
1539
1540 __setup("cameraboard=", tegra_camera_board_info);
1541
1542 static int __init tegra_leftspeaker_board_info(char *info)
1543 {
1544         char *p = info;
1545         leftspeaker_board_info.board_id = memparse(p, &p);
1546         leftspeaker_board_info.sku = memparse(p+1, &p);
1547         leftspeaker_board_info.fab = memparse(p+1, &p);
1548         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1549         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1550         return 1;
1551 }
1552
1553 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1554 {
1555         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1556 }
1557
1558 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1559
1560 static int __init tegra_rightspeaker_board_info(char *info)
1561 {
1562         char *p = info;
1563         rightspeaker_board_info.board_id = memparse(p, &p);
1564         rightspeaker_board_info.sku = memparse(p+1, &p);
1565         rightspeaker_board_info.fab = memparse(p+1, &p);
1566         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1567         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1568         return 1;
1569 }
1570
1571 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1572 {
1573         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1574 }
1575
1576 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1577
1578 static int __init tegra_joystick_board_info(char *info)
1579 {
1580         char *p = info;
1581         joystick_board_info.board_id = memparse(p, &p);
1582         joystick_board_info.sku = memparse(p+1, &p);
1583         joystick_board_info.fab = memparse(p+1, &p);
1584         joystick_board_info.major_revision = memparse(p+1, &p);
1585         joystick_board_info.minor_revision = memparse(p+1, &p);
1586         return 1;
1587 }
1588
1589 void tegra_get_joystick_board_info(struct board_info *bi)
1590 {
1591         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1592 }
1593
1594 __setup("joystickboard=", tegra_joystick_board_info);
1595
1596 static int __init tegra_button_board_info(char *info)
1597 {
1598         char *p = info;
1599         button_board_info.board_id = memparse(p, &p);
1600         button_board_info.sku = memparse(p+1, &p);
1601         button_board_info.fab = memparse(p+1, &p);
1602         button_board_info.major_revision = memparse(p+1, &p);
1603         button_board_info.minor_revision = memparse(p+1, &p);
1604         return 1;
1605 }
1606
1607 void tegra_get_button_board_info(struct board_info *bi)
1608 {
1609         memcpy(bi, &button_board_info, sizeof(struct board_info));
1610 }
1611
1612 __setup("buttonboard=", tegra_button_board_info);
1613
1614 static int __init tegra_io_board_info(char *info)
1615 {
1616         char *p = info;
1617         io_board_info.board_id = memparse(p, &p);
1618         io_board_info.sku = memparse(p+1, &p);
1619         io_board_info.fab = memparse(p+1, &p);
1620         io_board_info.major_revision = memparse(p+1, &p);
1621         io_board_info.minor_revision = memparse(p+1, &p);
1622         return 1;
1623 }
1624
1625 void tegra_get_io_board_info(struct board_info *bi)
1626 {
1627         memcpy(bi, &io_board_info, sizeof(struct board_info));
1628 }
1629
1630 __setup("ioboard=", tegra_io_board_info);
1631
1632 static int __init tegra_modem_id(char *id)
1633 {
1634         char *p = id;
1635
1636         modem_id = memparse(p, &p);
1637         return 1;
1638 }
1639
1640 int tegra_get_modem_id(void)
1641 {
1642         return modem_id;
1643 }
1644
1645 __setup("modem_id=", tegra_modem_id);
1646
1647 static int __init tegra_usb_port_owner_info(char *id)
1648 {
1649         char *p = id;
1650
1651         usb_port_owner_info = memparse(p, &p);
1652         return 1;
1653 }
1654
1655 int tegra_get_usb_port_owner_info(void)
1656 {
1657         return usb_port_owner_info;
1658 }
1659
1660 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1661
1662 static int __init tegra_lane_owner_info(char *id)
1663 {
1664         char *p = id;
1665
1666         lane_owner_info = memparse(p, &p);
1667         return 1;
1668 }
1669
1670 int tegra_get_lane_owner_info(void)
1671 {
1672         return lane_owner_info;
1673 }
1674
1675 __setup("lane_owner_info=", tegra_lane_owner_info);
1676
1677 static int __init tegra_commchip_id(char *id)
1678 {
1679         char *p = id;
1680
1681         if (get_option(&p, &commchip_id) != 1)
1682                 return 0;
1683         return 1;
1684 }
1685
1686 int tegra_get_commchip_id(void)
1687 {
1688         return commchip_id;
1689 }
1690
1691 __setup("commchip_id=", tegra_commchip_id);
1692
1693 /*
1694  * Tegra has a protected aperture that prevents access by most non-CPU
1695  * memory masters to addresses above the aperture value.  Enabling it
1696  * secures the CPU's memory from the GPU, except through the GART.
1697  */
1698 void __init tegra_protected_aperture_init(unsigned long aperture)
1699 {
1700         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1701         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1702         writel(aperture, mc_base + MC_SECURITY_CFG2);
1703 }
1704
1705 /*
1706  * Due to conflicting restrictions on the placement of the framebuffer,
1707  * the bootloader is likely to leave the framebuffer pointed at a location
1708  * in memory that is outside the grhost aperture.  This function will move
1709  * the framebuffer contents from a physical address that is anywhere (lowmem,
1710  * highmem, or outside the memory map) to a physical address that is outside
1711  * the memory map.
1712  */
1713 void __tegra_move_framebuffer(struct platform_device *pdev,
1714         phys_addr_t to, phys_addr_t from,
1715         size_t size)
1716 {
1717         struct page *page;
1718         void __iomem *to_io;
1719         void *from_virt;
1720         unsigned long i;
1721
1722         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1723         BUG_ON(PAGE_ALIGN(from) != from);
1724         BUG_ON(PAGE_ALIGN(size) != size);
1725
1726         to_io = ioremap(to, size);
1727         if (!to_io) {
1728                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1729                 return;
1730         }
1731
1732         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1733                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1734                         page = phys_to_page(from + i);
1735                         from_virt = kmap(page);
1736                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1737                         kunmap(page);
1738                 }
1739         } else if (from) {
1740                 void __iomem *from_io = ioremap(from, size);
1741                 if (!from_io) {
1742                         pr_err("%s: Failed to map source framebuffer\n",
1743                                 __func__);
1744                         goto out;
1745                 }
1746
1747                 for (i = 0; i < size; i += 4)
1748                         writel(readl(from_io + i), to_io + i);
1749
1750                 iounmap(from_io);
1751         }
1752
1753 out:
1754         iounmap(to_io);
1755 }
1756
1757 void __tegra_clear_framebuffer(struct platform_device *pdev,
1758                                unsigned long to, unsigned long size)
1759 {
1760         void __iomem *to_io;
1761         unsigned long i;
1762
1763         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1764         BUG_ON(PAGE_ALIGN(size) != size);
1765
1766         to_io = ioremap(to, size);
1767         if (!to_io) {
1768                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1769                 return;
1770         }
1771
1772         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1773                 for (i = 0 ; i < size; i += PAGE_SIZE)
1774                         memset(to_io + i, 0, PAGE_SIZE);
1775         } else {
1776                 for (i = 0; i < size; i += 4)
1777                         writel(0, to_io + i);
1778         }
1779
1780         iounmap(to_io);
1781 }
1782
1783 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1784         unsigned long fb2_size)
1785 {
1786         const size_t avp_kernel_reserve = SZ_32M;
1787         int i = 0;
1788         struct iommu_linear_map map[4];
1789
1790 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1791         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1792         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1793         tegra_avp_kernel_size = SECTION_SIZE;
1794
1795         /*
1796          * Choose a DRAM region in which to allocate the AVP kernel, using the
1797          * following guidelines:
1798          *     - Choose a DRAM region which exists below the 4 GB physical
1799          *       address limit. This is necessary because AVP is a 32 bit
1800          *       processor and it cannot access physical addresses above 4 GB.
1801          *     - Out of the applicable DRAM regions (i.e. those which exist
1802          *       below 4 GB), choose the region with the highest starting
1803          *       physical address.
1804          */
1805         for (i = memblock.memory.cnt - 1; i >= 0; i--) {
1806                 if ((u64)(memblock.memory.regions[i].base) +
1807                         (u64)(memblock.memory.regions[i].size) <
1808                         (u64)(SZ_2G)*(u64)(2)) {
1809                         tegra_avp_kernel_start =
1810                                 memblock.memory.regions[i].base +
1811                                 memblock.memory.regions[i].size -
1812                                 avp_kernel_reserve;
1813                         break;
1814                 }
1815         }
1816         /*
1817          * If tegra_avp_kernel_start is still 0, that means we didn't find any
1818          * DRAM region below the 4 GB physical address limit. This is a problem
1819          * because the AVP kernel must reside below 4 GB.
1820          */
1821         BUG_ON(tegra_avp_kernel_start == 0);
1822
1823         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1824                 pr_err("Failed to remove AVP kernel load area %08lx@%08llx "
1825                                 "from memory map\n",
1826                         (unsigned long)avp_kernel_reserve,
1827                         (u64)tegra_avp_kernel_start);
1828                 tegra_avp_kernel_size = 0;
1829         }
1830 #endif
1831
1832         if (carveout_size) {
1833                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1834                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1835                         pr_err("Failed to remove carveout %08lx@%08llx "
1836                                 "from memory map\n",
1837                                 carveout_size, (u64)tegra_carveout_start);
1838                         tegra_carveout_start = 0;
1839                         tegra_carveout_size = 0;
1840                 } else
1841                         tegra_carveout_size = carveout_size;
1842         }
1843
1844         if (fb2_size) {
1845                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1846                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1847                         pr_err("Failed to remove second framebuffer "
1848                                 "%08lx@%08llx from memory map\n",
1849                                 fb2_size, (u64)tegra_fb2_start);
1850                         tegra_fb2_start = 0;
1851                         tegra_fb2_size = 0;
1852                 } else
1853                         tegra_fb2_size = fb2_size;
1854         }
1855
1856         if (fb_size) {
1857                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1858                 if (memblock_remove(tegra_fb_start, fb_size)) {
1859                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1860                                 "from memory map\n",
1861                                 fb_size, (u64)tegra_fb_start);
1862                         tegra_fb_start = 0;
1863                         tegra_fb_size = 0;
1864                 } else
1865                         tegra_fb_size = fb_size;
1866         }
1867
1868         if (tegra_cpu_is_asim()) {
1869                 if (tegra_split_mem_active()) {
1870                         tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1871                         tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1872
1873                         if (tegra_vpr_size == 0) {
1874                                 tegra_carveout_start =
1875                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1876                                 tegra_carveout_size =
1877                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1878                         } else if (
1879                                     (tegra_vpr_start <
1880                                      TEGRA_ASIM_QT_FB_START +
1881                                      TEGRA_ASIM_QT_FB_SIZE) ||
1882                                      (tegra_vpr_start + tegra_vpr_size - 1 >
1883                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1884                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1885                                 /*
1886                                  * On ASIM/ASIM + QT with
1887                                  * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1888                                  * the VPR region needs to be within the front
1889                                  * door memory region. Moreover, the VPR region
1890                                  * can't exist where the framebuffer resides.
1891                                  */
1892                                 BUG();
1893                         } else if (
1894                                         (tegra_vpr_start -
1895                                          (TEGRA_ASIM_QT_FB_START +
1896                                           TEGRA_ASIM_QT_FB_SIZE) <
1897                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1898                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1899                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1900                                          (tegra_vpr_start + tegra_vpr_size) <
1901                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1902                                 /*
1903                                  * The tegra ASIM/QT carveout has a min size:-
1904                                  * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1905                                  * regions in front door mem are smaller than
1906                                  * the min carveout size. Therefore, we can't
1907                                  * fit the carveout in front door mem.
1908                                  */
1909                                 BUG();
1910                         } else if (
1911                                         (tegra_vpr_start -
1912                                          (TEGRA_ASIM_QT_FB_START +
1913                                           TEGRA_ASIM_QT_FB_SIZE)) >=
1914                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1915                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1916                                          (tegra_vpr_start + tegra_vpr_size))) {
1917                                 /*
1918                                  * Place the tegra ASIM/QT carveout between the
1919                                  * framebuffer and VPR.
1920                                  */
1921                                 tegra_carveout_start =
1922                                   TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1923                                 tegra_carveout_size = tegra_vpr_start -
1924                                         (TEGRA_ASIM_QT_FB_START +
1925                                          TEGRA_ASIM_QT_FB_SIZE);
1926                         } else {
1927                                 /*
1928                                  * Place the tegra ASIM/QT carveout after VPR.
1929                                  */
1930                                 tegra_carveout_start = tegra_vpr_start +
1931                                                          tegra_vpr_size;
1932                                 tegra_carveout_size =
1933                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1934                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1935                                         (tegra_vpr_start + tegra_vpr_size);
1936                         }
1937                 } else if (tegra_vpr_size != 0) {
1938                         /*
1939                          * VPR cannot work on ASIM/ASIM + QT if split mem is not
1940                          * enabled.
1941                          */
1942                         BUG();
1943                 }
1944         }
1945
1946         if (tegra_fb_size)
1947                 tegra_grhost_aperture = tegra_fb_start;
1948
1949         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1950                 tegra_grhost_aperture = tegra_fb2_start;
1951
1952         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1953                 tegra_grhost_aperture = tegra_carveout_start;
1954
1955         if (tegra_lp0_vec_size &&
1956            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1957                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1958                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
1959                                 (u64)tegra_lp0_vec_size,
1960                                 (u64)tegra_lp0_vec_start);
1961                         tegra_lp0_vec_start = 0;
1962                         tegra_lp0_vec_size = 0;
1963                 }
1964                 tegra_lp0_vec_relocate = false;
1965         } else
1966                 tegra_lp0_vec_relocate = true;
1967
1968 #ifdef CONFIG_TEGRA_NVDUMPER
1969         if (nvdumper_reserved) {
1970                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1971                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1972                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1973                         nvdumper_reserved = 0;
1974                 }
1975         }
1976 #endif
1977
1978 #ifdef CONFIG_TEGRA_USE_NCT
1979         if (tegra_nck_size &&
1980            (tegra_nck_start < memblock_end_of_DRAM())) {
1981                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
1982                         pr_err("Failed to reserve nck %08lx@%08lx\n",
1983                                 tegra_nck_size, tegra_nck_start);
1984                         tegra_nck_start = 0;
1985                         tegra_nck_size = 0;
1986                 }
1987         }
1988 #endif
1989
1990         /*
1991          * We copy the bootloader's framebuffer to the framebuffer allocated
1992          * above, and then free this one.
1993          * */
1994         if (tegra_bootloader_fb_size) {
1995                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1996                 if (memblock_reserve(tegra_bootloader_fb_start,
1997                                 tegra_bootloader_fb_size)) {
1998                         pr_err("Failed to reserve bootloader frame buffer "
1999                                 "%08llx@%08llx\n",
2000                                 (u64)tegra_bootloader_fb_size,
2001                                 (u64)tegra_bootloader_fb_start);
2002                         tegra_bootloader_fb_start = 0;
2003                         tegra_bootloader_fb_size = 0;
2004                 }
2005         }
2006
2007         if (tegra_bootloader_fb2_size) {
2008                 tegra_bootloader_fb2_size =
2009                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2010                 if (memblock_reserve(tegra_bootloader_fb2_start,
2011                                 tegra_bootloader_fb2_size)) {
2012                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2013                                 (u64)tegra_bootloader_fb2_size,
2014                                 (u64)tegra_bootloader_fb2_start);
2015                         tegra_bootloader_fb2_start = 0;
2016                         tegra_bootloader_fb2_size = 0;
2017                 }
2018         }
2019
2020         pr_info("Tegra reserved memory:\n"
2021                 "LP0:                    %08llx - %08llx\n"
2022                 "Bootloader framebuffer: %08llx - %08llx\n"
2023                 "Bootloader framebuffer2: %08llx - %08llx\n"
2024                 "Framebuffer:            %08llx - %08llx\n"
2025                 "2nd Framebuffer:        %08llx - %08llx\n"
2026                 "Carveout:               %08llx - %08llx\n"
2027                 "Vpr:                    %08llx - %08llx\n"
2028                 "Tsec:                   %08llx - %08llx\n",
2029                 (u64)tegra_lp0_vec_start,
2030                 (u64)(tegra_lp0_vec_size ?
2031                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2032                 (u64)tegra_bootloader_fb_start,
2033                 (u64)(tegra_bootloader_fb_size ?
2034                         tegra_bootloader_fb_start +
2035                         tegra_bootloader_fb_size - 1 : 0),
2036                 (u64)tegra_bootloader_fb2_start,
2037                 (u64)(tegra_bootloader_fb2_size ?
2038                         tegra_bootloader_fb2_start +
2039                         tegra_bootloader_fb2_size - 1 : 0),
2040                 (u64)tegra_fb_start,
2041                 (u64)(tegra_fb_size ?
2042                         tegra_fb_start + tegra_fb_size - 1 : 0),
2043                 (u64)tegra_fb2_start,
2044                 (u64)(tegra_fb2_size ?
2045                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2046                 (u64)tegra_carveout_start,
2047                 (u64)(tegra_carveout_size ?
2048                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2049                 (u64)tegra_vpr_start,
2050                 (u64)(tegra_vpr_size ?
2051                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2052                 (u64)tegra_tsec_start,
2053                 (u64)(tegra_tsec_size ?
2054                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
2055
2056         if (tegra_avp_kernel_size) {
2057                 /* Return excessive memory reserved for AVP kernel */
2058                 if (tegra_avp_kernel_size < avp_kernel_reserve)
2059                         memblock_add(
2060                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
2061                                 avp_kernel_reserve - tegra_avp_kernel_size);
2062                 /* The AVP kernel should be loaded below the 4 GB physical
2063                    address limit. */
2064                 BUG_ON((u64)(tegra_avp_kernel_start) +
2065                         (u64)(tegra_avp_kernel_size) - (u64)(1) >=
2066                         (u64)(SZ_2G)*(u64)(2));
2067                 pr_info(
2068                 "AVP kernel: %08llx - %08llx\n",
2069                         (u64)tegra_avp_kernel_start,
2070                         (u64)(tegra_avp_kernel_start +
2071                                 tegra_avp_kernel_size - 1));
2072         }
2073
2074 #ifdef CONFIG_TEGRA_NVDUMPER
2075         if (nvdumper_reserved) {
2076                 pr_info("Nvdumper:               %08lx - %08lx\n",
2077                         nvdumper_reserved,
2078                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2079         }
2080 #endif
2081
2082 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
2083         pr_info("Tzram:               %08lx - %08lx\n",
2084                 tegra_tzram_start,
2085                 tegra_tzram_size ?
2086                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2087 #endif
2088
2089 #ifdef CONFIG_TEGRA_USE_NCT
2090         if (tegra_nck_size) {
2091                 pr_info("Nck:                    %08lx - %08lx\n",
2092                         tegra_nck_start,
2093                         tegra_nck_size ?
2094                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2095         }
2096 #endif
2097
2098         map[0].start = tegra_fb_start;
2099         map[0].size = tegra_fb_size;
2100         map[1].start = tegra_fb2_start;
2101         map[1].size = tegra_fb2_size;
2102         map[2].start = tegra_bootloader_fb_start;
2103         map[2].size = tegra_bootloader_fb_size;
2104         map[3].start = tegra_bootloader_fb2_start;
2105         map[3].size = tegra_bootloader_fb2_size;
2106
2107         tegra_fb_linear_set(map);
2108 }
2109
2110 #ifdef CONFIG_PSTORE_RAM
2111 static struct persistent_ram_descriptor desc = {
2112         .name = "ramoops",
2113 };
2114
2115 static struct persistent_ram ram = {
2116         .descs = &desc,
2117         .num_descs = 1,
2118 };
2119
2120 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
2121 {
2122         int ret;
2123
2124         ram.start = memblock_end_of_DRAM() - ram_console_size;
2125         ram.size = ram_console_size;
2126         ram.descs->size = ram_console_size;
2127
2128         INIT_LIST_HEAD(&ram.node);
2129
2130         ret = persistent_ram_early_init(&ram);
2131         if (ret)
2132                 goto fail;
2133
2134         return;
2135
2136 fail:
2137         pr_err("Failed to reserve memory block for ram console\n");
2138 }
2139 #endif
2140
2141 int __init tegra_register_fuse(void)
2142 {
2143         return platform_device_register(&tegra_fuse_device);
2144 }
2145
2146 int __init tegra_release_bootloader_fb(void)
2147 {
2148         /* Since bootloader fb is reserved in common.c, it is freed here. */
2149         if (tegra_bootloader_fb_size) {
2150                 if (memblock_free(tegra_bootloader_fb_start,
2151                                                 tegra_bootloader_fb_size))
2152                         pr_err("Failed to free bootloader fb.\n");
2153                 else
2154                         free_bootmem_late(tegra_bootloader_fb_start,
2155                                                 tegra_bootloader_fb_size);
2156         }
2157         if (tegra_bootloader_fb2_size) {
2158                 if (memblock_free(tegra_bootloader_fb2_start,
2159                                                 tegra_bootloader_fb2_size))
2160                         pr_err("Failed to free bootloader fb2.\n");
2161                 else
2162                         free_bootmem_late(tegra_bootloader_fb2_start,
2163                                                 tegra_bootloader_fb2_size);
2164         }
2165         return 0;
2166 }
2167 late_initcall(tegra_release_bootloader_fb);
2168
2169 static struct platform_device *pinmux_devices[] = {
2170         &tegra_gpio_device,
2171         &tegra_pinmux_device,
2172 };
2173
2174 void tegra_enable_pinmux(void)
2175 {
2176         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
2177 }
2178
2179 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2180         [TEGRA_REVISION_UNKNOWN] = "unknown",
2181         [TEGRA_REVISION_A01]     = "A01",
2182         [TEGRA_REVISION_A02]     = "A02",
2183         [TEGRA_REVISION_A03]     = "A03",
2184         [TEGRA_REVISION_A03p]    = "A03 prime",
2185         [TEGRA_REVISION_A04]     = "A04",
2186         [TEGRA_REVISION_A04p]    = "A04 prime",
2187 };
2188
2189 static const char * __init tegra_get_revision(void)
2190 {
2191         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2192 }
2193
2194 static const char * __init tegra_get_family(void)
2195 {
2196         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2197         u32 cid = readl(chip_id);
2198         cid = (cid >> 8) & 0xFF;
2199
2200         switch (cid) {
2201         case TEGRA_CHIPID_TEGRA2:
2202                 cid = 2;
2203                 break;
2204         case TEGRA_CHIPID_TEGRA3:
2205                 cid = 3;
2206                 break;
2207         case TEGRA_CHIPID_TEGRA11:
2208                 cid = 11;
2209                 break;
2210         case TEGRA_CHIPID_TEGRA12:
2211                 cid = 12;
2212                 break;
2213         case TEGRA_CHIPID_TEGRA14:
2214                 cid = 14;
2215                 break;
2216
2217         case TEGRA_CHIPID_UNKNOWN:
2218         default:
2219                 cid = 0;
2220         }
2221         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2222 }
2223
2224 static const char * __init tegra_get_soc_id(void)
2225 {
2226         int package_id = tegra_package_id();
2227         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2228                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
2229 }
2230
2231 static void __init tegra_soc_info_populate(struct soc_device_attribute
2232         *soc_dev_attr, const char *machine)
2233 {
2234         soc_dev_attr->soc_id = tegra_get_soc_id();
2235         soc_dev_attr->machine  = machine;
2236         soc_dev_attr->family   = tegra_get_family();
2237         soc_dev_attr->revision = tegra_get_revision();
2238 }
2239
2240 int __init tegra_soc_device_init(const char *machine)
2241 {
2242         struct soc_device *soc_dev;
2243         struct soc_device_attribute *soc_dev_attr;
2244
2245         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2246         if (!soc_dev_attr)
2247                 return -ENOMEM;
2248
2249         tegra_soc_info_populate(soc_dev_attr, machine);
2250
2251         soc_dev = soc_device_register(soc_dev_attr);
2252         if (IS_ERR_OR_NULL(soc_dev)) {
2253                 kfree(soc_dev_attr);
2254                 return -1;
2255         }
2256
2257         return 0;
2258 }
2259
2260 void __init tegra_init_late(void)
2261 {
2262 #ifndef CONFIG_COMMON_CLK
2263         tegra_clk_debugfs_init();
2264 #endif
2265         tegra_powergate_debugfs_init();
2266 }
2267
2268 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2269 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2270
2271 static void asim_power_off(void)
2272 {
2273         pr_err("ASIM Powering off the device\n");
2274         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2275         while (1)
2276                 ;
2277 }
2278
2279 static int __init asim_power_off_init(void)
2280 {
2281         if (tegra_cpu_is_asim())
2282                 pm_power_off = asim_power_off;
2283         return 0;
2284 }
2285
2286 arch_initcall(asim_power_off_init);
2287
2288 #if defined(CONFIG_SMC91X)
2289 static struct resource tegra_asim_smc91x_resources[] = {
2290         [0] = {
2291                 .start          = TEGRA_SIM_ETH_BASE,
2292                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2293                 .flags          = IORESOURCE_MEM,
2294         },
2295         [1] = {
2296                 .start          = IRQ_ETH,
2297                 .end            = IRQ_ETH,
2298                 .flags          = IORESOURCE_IRQ,
2299         },
2300 };
2301
2302 static struct platform_device tegra_asim_smc91x_device = {
2303         .name           = "smc91x",
2304         .id             = 0,
2305         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2306         .resource       = tegra_asim_smc91x_resources,
2307 };
2308
2309 static int __init asim_enet_smc91x_init(void)
2310 {
2311         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2312                 platform_device_register(&tegra_asim_smc91x_device);
2313         return 0;
2314 }
2315
2316 rootfs_initcall(asim_enet_smc91x_init);
2317 #endif
2318 #endif
2319
2320 #if defined(CONFIG_SMSC911X)
2321 static struct resource tegra_smsc911x_resources[] = {
2322         [0] = {
2323                 .start          = 0x4E000000,
2324                 .end            = 0x4E000000 + SZ_64K - 1,
2325                 .flags          = IORESOURCE_MEM,
2326         },
2327         [1] = {
2328                 .start          = IRQ_ETH,
2329                 .end            = IRQ_ETH,
2330                 .flags          = IORESOURCE_IRQ,
2331         },
2332 };
2333
2334 static struct smsc911x_platform_config tegra_smsc911x_config = {
2335         .flags          = SMSC911X_USE_32BIT,
2336         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2337         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2338         .phy_interface  = PHY_INTERFACE_MODE_MII,
2339 };
2340
2341 static struct platform_device tegra_smsc911x_device = {
2342         .name              = "smsc911x",
2343         .id                = 0,
2344         .resource          = tegra_smsc911x_resources,
2345         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2346         .dev.platform_data = &tegra_smsc911x_config,
2347 };
2348
2349 static int __init enet_smsc911x_init(void)
2350 {
2351         if (!tegra_cpu_is_dsim())
2352                 platform_device_register(&tegra_smsc911x_device);
2353         return 0;
2354 }
2355
2356 rootfs_initcall(enet_smsc911x_init);
2357 #endif
2358
2359 int tegra_split_mem_active(void)
2360 {
2361         return tegra_split_mem_set;
2362 }
2363
2364 static int __init set_tegra_split_mem(char *options)
2365 {
2366         tegra_split_mem_set = 1;
2367         return 0;
2368 }
2369 early_param("tegra_split_mem", set_tegra_split_mem);