arm: tegra: optimize L2 enable/disable paths for secureos
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/irqchip.h>
28 #include <linux/clk/tegra.h>
29 #include <linux/highmem.h>
30 #include <linux/memblock.h>
31 #include <linux/bitops.h>
32 #include <linux/sched.h>
33 #include <linux/of.h>
34 #include <linux/pstore_ram.h>
35 #include <linux/dma-mapping.h>
36
37 #include <asm/hardware/cache-l2x0.h>
38 #include <asm/system.h>
39 #include <asm/dma-mapping.h>
40
41 #include <mach/hardware.h>
42 #include <mach/powergate.h>
43 #include <mach/tegra_smmu.h>
44 #include <mach/gpio-tegra.h>
45
46 #include "apbio.h"
47 #include "board.h"
48 #include "clock.h"
49 #include "common.h"
50 #include "dvfs.h"
51 #include "fuse.h"
52 #include "iomap.h"
53 #include "pm.h"
54 #include "sleep.h"
55 #include "reset.h"
56 #include "devices.h"
57 #include "pmc.h"
58
59 #define MC_SECURITY_CFG2        0x7c
60
61 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
62 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
63 #define   PRIORITY_SELECT_USB   BIT(6)
64 #define   PRIORITY_SELECT_USB2  BIT(18)
65 #define   PRIORITY_SELECT_USB3  BIT(17)
66
67 #define AHB_GIZMO_AHB_MEM               0xc
68 #define   ENB_FAST_REARBITRATE  BIT(2)
69 #define   DONT_SPLIT_AHB_WR     BIT(7)
70
71 #define   RECOVERY_MODE BIT(31)
72 #define   BOOTLOADER_MODE       BIT(30)
73 #define   FORCED_RECOVERY_MODE  BIT(1)
74
75 #define AHB_GIZMO_USB           0x1c
76 #define AHB_GIZMO_USB2          0x78
77 #define AHB_GIZMO_USB3          0x7c
78 #define   IMMEDIATE     BIT(18)
79
80 #define AHB_MEM_PREFETCH_CFG3   0xe0
81 #define AHB_MEM_PREFETCH_CFG4   0xe4
82 #define AHB_MEM_PREFETCH_CFG1   0xec
83 #define AHB_MEM_PREFETCH_CFG2   0xf0
84 #define   PREFETCH_ENB  BIT(31)
85 #define   MST_ID(x)     (((x) & 0x1f) << 26)
86 #define   AHBDMA_MST_ID MST_ID(5)
87 #define   USB_MST_ID    MST_ID(6)
88 #define   USB2_MST_ID   MST_ID(18)
89 #define   USB3_MST_ID   MST_ID(17)
90 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
91 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
92
93 unsigned long tegra_avp_kernel_start;
94 unsigned long tegra_avp_kernel_size;
95 unsigned long tegra_bootloader_fb_start;
96 unsigned long tegra_bootloader_fb_size;
97 unsigned long tegra_fb_start;
98 unsigned long tegra_fb_size;
99 unsigned long tegra_fb2_start;
100 unsigned long tegra_fb2_size;
101 unsigned long tegra_carveout_start;
102 unsigned long tegra_carveout_size;
103 unsigned long tegra_vpr_start;
104 unsigned long tegra_vpr_size;
105 unsigned long tegra_tsec_start;
106 unsigned long tegra_tsec_size;
107 unsigned long tegra_lp0_vec_start;
108 unsigned long tegra_lp0_vec_size;
109 bool tegra_lp0_vec_relocate;
110 unsigned long tegra_grhost_aperture = ~0ul;
111 static   bool is_tegra_debug_uart_hsport;
112 static struct board_info pmu_board_info;
113 static struct board_info display_board_info;
114 static struct board_info camera_board_info;
115
116 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
117 static int board_panel_type;
118 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
119
120 /*
121  * Storage for debug-macro.S's state.
122  *
123  * This must be in .data not .bss so that it gets initialized each time the
124  * kernel is loaded. The data is declared here rather than debug-macro.S so
125  * that multiple inclusions of debug-macro.S point at the same data.
126  */
127 u32 tegra_uart_config[4] = {
128         /* Debug UART initialization required */
129         1,
130         /* Debug UART physical address */
131         0,
132         /* Debug UART virtual address */
133         0,
134         /* Scratch space for debug macro */
135         0,
136 };
137
138 #ifdef CONFIG_OF
139 void __init tegra_dt_init_irq(void)
140 {
141         tegra_clocks_init();
142         tegra_pmc_init();
143         tegra_init_irq();
144         irqchip_init();
145 }
146 #endif
147
148 #define NEVER_RESET 0
149
150 void tegra_assert_system_reset(char mode, const char *cmd)
151 {
152 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
153         pr_info("tegra_assert_system_reset() ignored.....");
154         do { } while (1);
155 #else
156         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
157         u32 reg;
158
159         reg = readl_relaxed(reset + PMC_SCRATCH0);
160         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
161         if (cmd) {
162                 if (!strcmp(cmd, "recovery"))
163                         reg |= RECOVERY_MODE;
164                 else if (!strcmp(cmd, "bootloader"))
165                         reg |= BOOTLOADER_MODE;
166                 else if (!strcmp(cmd, "forced-recovery"))
167                         reg |= FORCED_RECOVERY_MODE;
168                 else
169                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
170         }
171         else {
172                 /* Clearing SCRATCH0 31:30:1 on default reboot */
173                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
174         }
175         writel_relaxed(reg, reset + PMC_SCRATCH0);
176         reg = readl_relaxed(reset);
177         reg |= 0x10;
178         writel_relaxed(reg, reset);
179 #endif
180 }
181 static int modem_id;
182 static int commchip_id;
183 static int sku_override;
184 static int debug_uart_port_id;
185 static enum audio_codec_type audio_codec_name;
186 static enum image_type board_image_type = system_image;
187 static int max_cpu_current;
188
189 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
190 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
191         /* name         parent          rate            enabled */
192         { "clk_m",      NULL,           0,              true },
193         { "emc",        NULL,           0,              true },
194         { "cpu",        NULL,           0,              true },
195         { "kfuse",      NULL,           0,              true },
196         { "fuse",       NULL,           0,              true },
197         { "sclk",       NULL,           0,              true },
198         { "pll_p",      NULL,           0,              true },
199         { "pll_p_out1", "pll_p",        0,              false },
200         { "pll_p_out3", "pll_p",        0,              true },
201 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
202         { "pll_m_out1", "pll_m",        275000000,      false },
203         { "pll_p_out2",  "pll_p",       102000000,      false },
204         { "sclk",        "pll_p_out2",  102000000,      true },
205         { "pll_p_out4",  "pll_p",       204000000,      true },
206         { "hclk",       "sclk",         102000000,      true },
207         { "pclk",       "hclk",         51000000,       true },
208         { "mselect",    "pll_p",        102000000,      true },
209         { "host1x",     "pll_p",        102000000,      false },
210         { "cl_dvfs_ref", "pll_p",       54000000,       false },
211         { "cl_dvfs_soc", "pll_p",       54000000,       false },
212 #else
213         { "pll_m_out1", "pll_m",        275000000,      true },
214         { "pll_p_out2", "pll_p",        108000000,      false },
215         { "sclk",       "pll_p_out2",   108000000,      true },
216         { "pll_p_out4", "pll_p",        216000000,      true },
217         { "hclk",       "sclk",         108000000,      true },
218         { "pclk",       "hclk",         54000000,       true },
219         { "mselect",    "pll_p",        108000000,      true },
220         { "host1x",     "pll_p",        108000000,      false },
221         { "cl_dvfs_ref", "clk_m",       13000000,       false },
222         { "cl_dvfs_soc", "clk_m",       13000000,       false },
223 #endif
224 #ifdef CONFIG_TEGRA_SLOW_CSITE
225         { "csite",      "clk_m",        1000000,        true },
226 #else
227         { "csite",      NULL,           0,              true },
228 #endif
229         { "pll_u",      NULL,           480000000,      false },
230         { "sdmmc1",     "pll_p",        48000000,       false},
231         { "sdmmc3",     "pll_p",        48000000,       false},
232         { "sdmmc4",     "pll_p",        48000000,       false},
233         { "sbc1.sclk",  NULL,           40000000,       false},
234         { "sbc2.sclk",  NULL,           40000000,       false},
235         { "sbc3.sclk",  NULL,           40000000,       false},
236         { "sbc4.sclk",  NULL,           40000000,       false},
237         { "sbc5.sclk",  NULL,           40000000,       false},
238         { "sbc6.sclk",  NULL,           40000000,       false},
239 #ifdef CONFIG_TEGRA_DUAL_CBUS
240         { "c2bus",      "pll_c2",       300000000,      false },
241         { "c3bus",      "pll_c3",       300000000,      false },
242 #else
243         { "cbus",       "pll_c",        416000000,      false },
244         { "pll_c_out1", "pll_c",        208000000,      false },
245 #endif
246         { NULL,         NULL,           0,              0},
247 };
248 #endif
249
250 #ifdef CONFIG_TRUSTED_FOUNDATIONS
251 #define CACHE_LINE_SIZE         32
252 static inline void tegra_l2x0_disable_tz(void)
253 {
254         static u32 l2x0_way_mask;
255
256         BUG_ON(smp_processor_id() != 0);
257
258         if (!l2x0_way_mask) {
259                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
260                 u32 aux_ctrl;
261                 u32 ways;
262
263                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
264                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
265                 l2x0_way_mask = (1 << ways) - 1;
266         }
267
268 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
269         /* flush all ways on disable */
270         tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, l2x0_way_mask);
271 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
272         if (tegra_is_cpu_in_lp2(0)) {
273                 register unsigned long sp asm ("sp");
274                 /* flush only the stack, if entering LP2 */
275                 __cpuc_flush_dcache_area((void *)sp, (CACHE_LINE_SIZE * 2));
276                 outer_flush_range(__pa(sp), __pa(sp) + (CACHE_LINE_SIZE * 2));
277
278                 /* pass zero arg, so secureos flushes only its workspace */
279                 tegra_generic_smc_uncached(0xFFFFF100, 0x00000002,
280                         l2x0_way_mask);
281         } else {
282                 /* flush all ways on disable, if entering LP0/LP1 */
283                 tegra_generic_smc_uncached(0xFFFFF100, 0x00000002,
284                         l2x0_way_mask);
285         }
286 #endif
287 }
288
289 static inline void tegra_init_cache_tz(bool init)
290 {
291         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
292         u32 aux_ctrl;
293
294         BUG_ON(smp_processor_id() != 0);
295
296         if (init) {
297                 /* init L2 from secureos */
298                 tegra_generic_smc(0xFFFFF100, 0x00000001, 0x0);
299
300                 /* common init called for outer call hookup */
301                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
302                 l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
303
304 #ifdef CONFIG_OUTER_CACHE
305                 /* use our outer_disable() routine */
306                 outer_cache.disable = tegra_l2x0_disable_tz;
307 #endif
308         } else {
309                 /* reenable L2 in secureos */
310                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
311                 tegra_generic_smc_uncached(0xFFFFF100, 0x00000004, aux_ctrl);
312         }
313 }
314 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
315
316 #ifdef CONFIG_CACHE_L2X0
317 void tegra_init_cache(bool init)
318 {
319 #ifdef CONFIG_TRUSTED_FOUNDATIONS
320         /* enable/re-enable of L2 handled by secureos */
321         tegra_init_cache_tz(init);
322 #else
323         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
324         u32 aux_ctrl;
325         u32 cache_type;
326         u32 tag_latency = 0x770, data_latency = 0x770;
327 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
328         tag_latency = 0x331;
329         data_latency = 0x441;
330 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
331 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
332         if (is_lp_cluster()) {
333                 tag_latency = 0x221;
334                 data_latency = 0x221;
335         } else {
336                 u32 speedo;
337
338                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
339                 speedo = tegra_cpu_speedo_id();
340                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
341                     speedo == 12 || speedo == 13) {
342                         tag_latency = 0x442;
343                         data_latency = 0x552;
344                 } else {
345                         tag_latency = 0x441;
346                         data_latency = 0x551;
347                 }
348         }
349 #endif
350 #endif
351         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
352         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
353
354 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
355 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
356         writel(7, p + L2X0_PREFETCH_CTRL);
357         writel(2, p + L2X0_POWER_CTRL);
358 #endif
359 #endif
360
361         writel(0x3, p + L2X0_POWER_CTRL);
362         cache_type = readl(p + L2X0_CACHE_TYPE);
363         aux_ctrl = (cache_type & 0x700) << (17-8);
364         aux_ctrl |= 0x7C400001;
365         if (init) {
366                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
367         } else {
368                 u32 tmp;
369
370                 tmp = aux_ctrl;
371                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
372                 aux_ctrl &= 0x8200c3fe;
373                 aux_ctrl |= tmp;
374                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
375         }
376         l2x0_enable();
377 #endif /* CONFIG_TRUSTED_FOUNDATIONS */
378 }
379 #endif /* CONFIG_CACHE_L2X0 */
380
381 static void __init tegra_init_power(void)
382 {
383 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
384         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
385 #endif
386 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
387         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
388 #endif
389 }
390
391 static inline unsigned long gizmo_readl(unsigned long offset)
392 {
393         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
394 }
395
396 static inline void gizmo_writel(unsigned long value, unsigned long offset)
397 {
398         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
399 }
400
401 static void __init tegra_init_ahb_gizmo_settings(void)
402 {
403         unsigned long val;
404
405         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
406         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
407         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
408
409         val = gizmo_readl(AHB_GIZMO_USB);
410         val |= IMMEDIATE;
411         gizmo_writel(val, AHB_GIZMO_USB);
412
413         val = gizmo_readl(AHB_GIZMO_USB2);
414         val |= IMMEDIATE;
415         gizmo_writel(val, AHB_GIZMO_USB2);
416
417         val = gizmo_readl(AHB_GIZMO_USB3);
418         val |= IMMEDIATE;
419         gizmo_writel(val, AHB_GIZMO_USB3);
420
421         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
422         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
423                                 | AHB_PRIORITY_WEIGHT(7);
424         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
425
426         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
427         val &= ~MST_ID(~0);
428         val |= PREFETCH_ENB | AHBDMA_MST_ID |
429                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
430         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
431
432         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
433         val &= ~MST_ID(~0);
434         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
435                 INACTIVITY_TIMEOUT(0x1000);
436         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
437
438         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
439         val &= ~MST_ID(~0);
440         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
441                 INACTIVITY_TIMEOUT(0x1000);
442         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
443
444         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
445         val &= ~MST_ID(~0);
446         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
447                 INACTIVITY_TIMEOUT(0x1000);
448         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
449 }
450
451 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
452 void __init tegra20_init_early(void)
453 {
454 #ifndef CONFIG_SMP
455         /* For SMP system, initializing the reset handler here is too
456            late. For non-SMP systems, the function that calls the reset
457            handler initializer is not called, so do it here for non-SMP. */
458         tegra_cpu_reset_handler_init();
459 #endif
460         tegra_apb_io_init();
461         tegra_init_fuse();
462         tegra_init_cache(true);
463         tegra_powergate_init();
464         tegra20_hotplug_init();
465         tegra_init_power();
466         tegra_init_ahb_gizmo_settings();
467         tegra_init_debug_uart_rate();
468         tegra_gpio_resume_init();
469         tegra_ram_console_debug_reserve(SZ_1M);
470 }
471 #endif
472 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
473 void __init tegra30_init_early(void)
474 {
475 #ifndef CONFIG_SMP
476         /* For SMP system, initializing the reset handler here is too
477            late. For non-SMP systems, the function that calls the reset
478            handler initializer is not called, so do it here for non-SMP. */
479         tegra_cpu_reset_handler_init();
480 #endif
481         tegra_apb_io_init();
482         tegra_init_fuse();
483         tegra_init_cache(true);
484         tegra_pmc_init();
485         tegra_powergate_init();
486         tegra30_hotplug_init();
487         tegra_init_power();
488         tegra_init_ahb_gizmo_settings();
489         tegra_init_debug_uart_rate();
490         tegra_gpio_resume_init();
491         tegra_ram_console_debug_reserve(SZ_1M);
492
493         init_dma_coherent_pool_size(SZ_1M);
494 }
495 #endif
496 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
497 void __init tegra11x_init_early(void)
498 {
499 #ifndef CONFIG_SMP
500         /* For SMP system, initializing the reset handler here is too
501            late. For non-SMP systems, the function that calls the reset
502            handler initializer is not called, so do it here for non-SMP. */
503         tegra_cpu_reset_handler_init();
504 #endif
505         tegra_init_fuse();
506         tegra11x_init_clocks();
507         tegra11x_init_dvfs();
508         tegra_common_init_clock();
509         tegra_clk_init_from_table(tegra11x_clk_init_table);
510         tegra11x_clk_init_la();
511         tegra_pmc_init();
512         tegra_powergate_init();
513         tegra_init_power();
514         tegra_init_ahb_gizmo_settings();
515         tegra_init_debug_uart_rate();
516         tegra_gpio_resume_init();
517
518         init_dma_coherent_pool_size(SZ_1M);
519 }
520 #endif
521 static int __init tegra_lp0_vec_arg(char *options)
522 {
523         char *p = options;
524
525         tegra_lp0_vec_size = memparse(p, &p);
526         if (*p == '@')
527                 tegra_lp0_vec_start = memparse(p+1, &p);
528         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
529                 tegra_lp0_vec_size = 0;
530                 tegra_lp0_vec_start = 0;
531         }
532
533         return 0;
534 }
535 early_param("lp0_vec", tegra_lp0_vec_arg);
536
537 static int __init tegra_bootloader_fb_arg(char *options)
538 {
539         char *p = options;
540
541         tegra_bootloader_fb_size = memparse(p, &p);
542         if (*p == '@')
543                 tegra_bootloader_fb_start = memparse(p+1, &p);
544
545         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
546                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
547
548         return 0;
549 }
550 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
551
552 static int __init tegra_sku_override(char *id)
553 {
554         char *p = id;
555
556         sku_override = memparse(p, &p);
557
558         return 0;
559 }
560 early_param("sku_override", tegra_sku_override);
561
562 int tegra_get_sku_override(void)
563 {
564         return sku_override;
565 }
566
567 static int __init tegra_vpr_arg(char *options)
568 {
569         char *p = options;
570
571         tegra_vpr_size = memparse(p, &p);
572         if (*p == '@')
573                 tegra_vpr_start = memparse(p+1, &p);
574         pr_info("Found vpr, start=0x%lx size=%lx",
575                 tegra_vpr_start, tegra_vpr_size);
576         return 0;
577 }
578 early_param("vpr", tegra_vpr_arg);
579
580 static int __init tegra_tsec_arg(char *options)
581 {
582         char *p = options;
583
584         tegra_tsec_size = memparse(p, &p);
585         if (*p == '@')
586                 tegra_tsec_start = memparse(p+1, &p);
587         pr_info("Found tsec, start=0x%lx size=%lx",
588                 tegra_tsec_start, tegra_tsec_size);
589         return 0;
590 }
591 early_param("tsec", tegra_tsec_arg);
592
593 enum panel_type get_panel_type(void)
594 {
595         return board_panel_type;
596 }
597 static int __init tegra_board_panel_type(char *options)
598 {
599         if (!strcmp(options, "lvds"))
600                 board_panel_type = panel_type_lvds;
601         else if (!strcmp(options, "dsi"))
602                 board_panel_type = panel_type_dsi;
603         else
604                 return 0;
605         return 1;
606 }
607 __setup("panel=", tegra_board_panel_type);
608
609 enum power_supply_type get_power_supply_type(void)
610 {
611         return pow_supply_type;
612 }
613 static int __init tegra_board_power_supply_type(char *options)
614 {
615         if (!strcmp(options, "Adapter"))
616                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
617         if (!strcmp(options, "Mains"))
618                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
619         else if (!strcmp(options, "Battery"))
620                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
621         else
622                 return 0;
623         return 1;
624 }
625 __setup("power_supply=", tegra_board_power_supply_type);
626
627 int get_core_edp(void)
628 {
629         return pmu_core_edp;
630 }
631 static int __init tegra_pmu_core_edp(char *options)
632 {
633         char *p = options;
634         int core_edp = memparse(p, &p);
635         if (core_edp != 0)
636                 pmu_core_edp = core_edp;
637         return 0;
638 }
639 early_param("core_edp_mv", tegra_pmu_core_edp);
640
641 int get_maximum_cpu_current_supported(void)
642 {
643         return max_cpu_current;
644 }
645 static int __init tegra_max_cpu_current(char *options)
646 {
647         char *p = options;
648         max_cpu_current = memparse(p, &p);
649         return 1;
650 }
651 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
652
653 static int __init tegra_debug_uartport(char *info)
654 {
655         char *p = info;
656         unsigned long long port_id;
657         if (!strncmp(p, "hsport", 6))
658                 is_tegra_debug_uart_hsport = true;
659         else if (!strncmp(p, "lsport", 6))
660                 is_tegra_debug_uart_hsport = false;
661
662         if (p[6] == ',') {
663                 if (p[7] == '-') {
664                         debug_uart_port_id = -1;
665                 } else {
666                         port_id = memparse(p + 7, &p);
667                         debug_uart_port_id = (int) port_id;
668                 }
669         } else {
670                 debug_uart_port_id = -1;
671         }
672
673         return 1;
674 }
675
676 bool is_tegra_debug_uartport_hs(void)
677 {
678         return is_tegra_debug_uart_hsport;
679 }
680
681 int get_tegra_uart_debug_port_id(void)
682 {
683         return debug_uart_port_id;
684 }
685 __setup("debug_uartport=", tegra_debug_uartport);
686
687 static int __init tegra_image_type(char *options)
688 {
689         if (!strcmp(options, "RCK"))
690                 board_image_type = rck_image;
691
692         return 0;
693 }
694
695 enum image_type get_tegra_image_type(void)
696 {
697         return board_image_type;
698 }
699
700 __setup("image=", tegra_image_type);
701
702 static int __init tegra_audio_codec_type(char *info)
703 {
704         char *p = info;
705         if (!strncmp(p, "wm8903", 6))
706                 audio_codec_name = audio_codec_wm8903;
707         else
708                 audio_codec_name = audio_codec_none;
709
710         return 1;
711 }
712
713 enum audio_codec_type get_audio_codec_type(void)
714 {
715         return audio_codec_name;
716 }
717 __setup("audio_codec=", tegra_audio_codec_type);
718
719
720 void tegra_get_board_info(struct board_info *bi)
721 {
722 #ifdef CONFIG_OF
723         struct device_node *board_info;
724         u32 prop_val;
725         int err;
726
727         board_info = of_find_node_by_path("/chosen/board_info");
728         if (!IS_ERR_OR_NULL(board_info)) {
729                 memset(bi, 0, sizeof(*bi));
730
731                 err = of_property_read_u32(board_info, "id", &prop_val);
732                 if (err)
733                         pr_err("failed to read /chosen/board_info/id\n");
734                 else
735                         bi->board_id = prop_val;
736
737                 err = of_property_read_u32(board_info, "sku", &prop_val);
738                 if (err)
739                         pr_err("failed to read /chosen/board_info/sku\n");
740                 else
741                         bi->sku = prop_val;
742
743                 err = of_property_read_u32(board_info, "fab", &prop_val);
744                 if (err)
745                         pr_err("failed to read /chosen/board_info/fab\n");
746                 else
747                         bi->fab = prop_val;
748
749                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
750                 if (err)
751                         pr_err("failed to read /chosen/board_info/major_revision\n");
752                 else
753                         bi->major_revision = prop_val;
754
755                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
756                 if (err)
757                         pr_err("failed to read /chosen/board_info/minor_revision\n");
758                 else
759                         bi->minor_revision = prop_val;
760         } else {
761 #endif
762                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
763                 bi->sku = (system_serial_high) & 0xFFFF;
764                 bi->fab = (system_serial_low >> 24) & 0xFF;
765                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
766                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
767 #ifdef CONFIG_OF
768         }
769 #endif
770 }
771
772 static int __init tegra_pmu_board_info(char *info)
773 {
774         char *p = info;
775         pmu_board_info.board_id = memparse(p, &p);
776         pmu_board_info.sku = memparse(p+1, &p);
777         pmu_board_info.fab = memparse(p+1, &p);
778         pmu_board_info.major_revision = memparse(p+1, &p);
779         pmu_board_info.minor_revision = memparse(p+1, &p);
780         return 1;
781 }
782
783 void tegra_get_pmu_board_info(struct board_info *bi)
784 {
785         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
786 }
787
788 __setup("pmuboard=", tegra_pmu_board_info);
789
790 static int __init tegra_display_board_info(char *info)
791 {
792         char *p = info;
793         display_board_info.board_id = memparse(p, &p);
794         display_board_info.sku = memparse(p+1, &p);
795         display_board_info.fab = memparse(p+1, &p);
796         display_board_info.major_revision = memparse(p+1, &p);
797         display_board_info.minor_revision = memparse(p+1, &p);
798         return 1;
799 }
800
801 void tegra_get_display_board_info(struct board_info *bi)
802 {
803         memcpy(bi, &display_board_info, sizeof(struct board_info));
804 }
805
806 __setup("displayboard=", tegra_display_board_info);
807
808 static int __init tegra_camera_board_info(char *info)
809 {
810         char *p = info;
811         camera_board_info.board_id = memparse(p, &p);
812         camera_board_info.sku = memparse(p+1, &p);
813         camera_board_info.fab = memparse(p+1, &p);
814         camera_board_info.major_revision = memparse(p+1, &p);
815         camera_board_info.minor_revision = memparse(p+1, &p);
816         return 1;
817 }
818
819 void tegra_get_camera_board_info(struct board_info *bi)
820 {
821         memcpy(bi, &camera_board_info, sizeof(struct board_info));
822 }
823
824 __setup("cameraboard=", tegra_camera_board_info);
825
826 static int __init tegra_modem_id(char *id)
827 {
828         char *p = id;
829
830         modem_id = memparse(p, &p);
831         return 1;
832 }
833
834 int tegra_get_modem_id(void)
835 {
836         return modem_id;
837 }
838
839 __setup("modem_id=", tegra_modem_id);
840
841 static int __init tegra_commchip_id(char *id)
842 {
843         char *p = id;
844
845         if (get_option(&p, &commchip_id) != 1)
846                 return 0;
847         return 1;
848 }
849
850 int tegra_get_commchip_id(void)
851 {
852         return commchip_id;
853 }
854
855 __setup("commchip_id=", tegra_commchip_id);
856
857 /*
858  * Tegra has a protected aperture that prevents access by most non-CPU
859  * memory masters to addresses above the aperture value.  Enabling it
860  * secures the CPU's memory from the GPU, except through the GART.
861  */
862 void __init tegra_protected_aperture_init(unsigned long aperture)
863 {
864 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
865         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
866         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
867         writel(aperture, mc_base + MC_SECURITY_CFG2);
868 #else
869         pr_err("Tegra protected aperture disabled because nvmap is using "
870                 "system memory\n");
871 #endif
872 }
873
874 /*
875  * Due to conflicting restrictions on the placement of the framebuffer,
876  * the bootloader is likely to leave the framebuffer pointed at a location
877  * in memory that is outside the grhost aperture.  This function will move
878  * the framebuffer contents from a physical address that is anywhere (lowmem,
879  * highmem, or outside the memory map) to a physical address that is outside
880  * the memory map.
881  */
882 void tegra_move_framebuffer(unsigned long to, unsigned long from,
883         unsigned long size)
884 {
885         struct page *page;
886         void __iomem *to_io;
887         void *from_virt;
888         unsigned long i, addr[] = { to, from, };
889
890         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
891         BUG_ON(PAGE_ALIGN(from) != from);
892         BUG_ON(PAGE_ALIGN(size) != size);
893
894         to_io = ioremap(to, size);
895         if (!to_io) {
896                 pr_err("%s: Failed to map target framebuffer\n", __func__);
897                 return;
898         }
899
900         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
901                 for (i = 0 ; i < size; i += PAGE_SIZE) {
902                         page = phys_to_page(from + i);
903                         from_virt = kmap(page);
904                         memcpy(to_io + i, from_virt, PAGE_SIZE);
905                         kunmap(page);
906                 }
907         } else {
908                 void __iomem *from_io = ioremap(from, size);
909                 if (!from_io) {
910                         pr_err("%s: Failed to map source framebuffer\n",
911                                 __func__);
912                         goto out;
913                 }
914
915                 for (i = 0; i < size; i += 4)
916                         writel(readl(from_io + i), to_io + i);
917
918                 iounmap(from_io);
919         }
920
921         for (i = 0; i < ARRAY_SIZE(addr); i++)
922                 dma_map_linear_at(NULL, addr[i], size, DMA_TO_DEVICE);
923 out:
924         iounmap(to_io);
925 }
926
927 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
928         unsigned long fb2_size)
929 {
930         const size_t avp_kernel_reserve = SZ_32M;
931 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
932         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
933         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
934         tegra_avp_kernel_size = SZ_1M;
935         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
936         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
937                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
938                                 "from memory map\n",
939                         (unsigned long)avp_kernel_reserve,
940                         tegra_avp_kernel_start);
941                 tegra_avp_kernel_size = 0;
942         }
943 #endif
944
945         if (carveout_size) {
946                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
947                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
948                         pr_err("Failed to remove carveout %08lx@%08lx "
949                                 "from memory map\n",
950                                 carveout_size, tegra_carveout_start);
951                         tegra_carveout_start = 0;
952                         tegra_carveout_size = 0;
953                 } else
954                         tegra_carveout_size = carveout_size;
955         }
956
957         if (fb2_size) {
958                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
959                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
960                         pr_err("Failed to remove second framebuffer "
961                                 "%08lx@%08lx from memory map\n",
962                                 fb2_size, tegra_fb2_start);
963                         tegra_fb2_start = 0;
964                         tegra_fb2_size = 0;
965                 } else
966                         tegra_fb2_size = fb2_size;
967         }
968
969         if (fb_size) {
970                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
971                 if (memblock_remove(tegra_fb_start, fb_size)) {
972                         pr_err("Failed to remove framebuffer %08lx@%08lx "
973                                 "from memory map\n",
974                                 fb_size, tegra_fb_start);
975                         tegra_fb_start = 0;
976                         tegra_fb_size = 0;
977                 } else
978                         tegra_fb_size = fb_size;
979         }
980
981         if (tegra_fb_size)
982                 tegra_grhost_aperture = tegra_fb_start;
983
984         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
985                 tegra_grhost_aperture = tegra_fb2_start;
986
987         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
988                 tegra_grhost_aperture = tegra_carveout_start;
989
990         if (tegra_lp0_vec_size &&
991            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
992                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
993                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
994                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
995                         tegra_lp0_vec_start = 0;
996                         tegra_lp0_vec_size = 0;
997                 }
998                 tegra_lp0_vec_relocate = false;
999         } else
1000                 tegra_lp0_vec_relocate = true;
1001
1002         /*
1003          * We copy the bootloader's framebuffer to the framebuffer allocated
1004          * above, and then free this one.
1005          * */
1006         if (tegra_bootloader_fb_size) {
1007                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1008                 if (memblock_reserve(tegra_bootloader_fb_start,
1009                                 tegra_bootloader_fb_size)) {
1010                         pr_err("Failed to reserve bootloader frame buffer "
1011                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1012                                 tegra_bootloader_fb_start);
1013                         tegra_bootloader_fb_start = 0;
1014                         tegra_bootloader_fb_size = 0;
1015                 }
1016         }
1017
1018         pr_info("Tegra reserved memory:\n"
1019                 "LP0:                    %08lx - %08lx\n"
1020                 "Bootloader framebuffer: %08lx - %08lx\n"
1021                 "Framebuffer:            %08lx - %08lx\n"
1022                 "2nd Framebuffer:        %08lx - %08lx\n"
1023                 "Carveout:               %08lx - %08lx\n"
1024                 "Vpr:                    %08lx - %08lx\n"
1025                 "Tsec:                   %08lx - %08lx\n",
1026                 tegra_lp0_vec_start,
1027                 tegra_lp0_vec_size ?
1028                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1029                 tegra_bootloader_fb_start,
1030                 tegra_bootloader_fb_size ?
1031                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1
1032                         : 0,
1033                 tegra_fb_start,
1034                 tegra_fb_size ?
1035                         tegra_fb_start + tegra_fb_size - 1 : 0,
1036                 tegra_fb2_start,
1037                 tegra_fb2_size ?
1038                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1039                 tegra_carveout_start,
1040                 tegra_carveout_size ?
1041                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1042                 tegra_vpr_start,
1043                 tegra_vpr_size ?
1044                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1045                 tegra_tsec_start,
1046                 tegra_tsec_size ?
1047                         tegra_tsec_start + tegra_tsec_size - 1 : 0);
1048
1049         if (tegra_avp_kernel_size) {
1050                 /* Return excessive memory reserved for AVP kernel */
1051                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1052                         memblock_add(
1053                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1054                                 avp_kernel_reserve - tegra_avp_kernel_size);
1055                 pr_info(
1056                 "AVP kernel: %08lx - %08lx\n",
1057                         tegra_avp_kernel_start,
1058                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1059         }
1060 }
1061
1062 #ifdef CONFIG_PSTORE_RAM
1063 static struct persistent_ram_descriptor desc = {
1064         .name = "ramoops",
1065 };
1066
1067 static struct persistent_ram ram = {
1068         .descs = &desc,
1069         .num_descs = 1,
1070 };
1071
1072 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1073 {
1074         int ret;
1075
1076         ram.start = memblock_end_of_DRAM() - ram_console_size;
1077         ram.size = ram_console_size;
1078         ram.descs->size = ram_console_size;
1079
1080         INIT_LIST_HEAD(&ram.node);
1081
1082         ret = persistent_ram_early_init(&ram);
1083         if (ret)
1084                 goto fail;
1085
1086         return;
1087
1088 fail:
1089         pr_err("Failed to reserve memory block for ram console\n");
1090 }
1091 #endif
1092
1093 void __init tegra_release_bootloader_fb(void)
1094 {
1095         /* Since bootloader fb is reserved in common.c, it is freed here. */
1096         if (tegra_bootloader_fb_size)
1097                 if (memblock_free(tegra_bootloader_fb_start,
1098                                                 tegra_bootloader_fb_size))
1099                         pr_err("Failed to free bootloader fb.\n");
1100 }
1101
1102 static struct platform_device *pinmux_devices[] = {
1103         &tegra_gpio_device,
1104         &tegra_pinmux_device,
1105 };
1106
1107 void tegra_enable_pinmux(void)
1108 {
1109         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1110 }
1111
1112 void __init tegra_init_late(void)
1113 {
1114 #ifndef CONFIG_COMMON_CLK
1115         tegra_clk_debugfs_init();
1116 #endif
1117         tegra_powergate_debugfs_init();
1118 }