ARM: Tegra: Add CONFIG_TEGRA_USE_SECURE_KERNEL
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36
37 #include <trace/events/nvsecurity.h>
38
39 #include <asm/hardware/cache-l2x0.h>
40 #include <asm/system.h>
41 #include <asm/dma-mapping.h>
42
43 #include <mach/hardware.h>
44 #include <mach/powergate.h>
45 #include <mach/tegra_smmu.h>
46 #include <mach/gpio-tegra.h>
47
48 #include "apbio.h"
49 #include "board.h"
50 #include "clock.h"
51 #include "common.h"
52 #include "dvfs.h"
53 #include "fuse.h"
54 #include "iomap.h"
55 #include "pm.h"
56 #include "sleep.h"
57 #include "reset.h"
58 #include "devices.h"
59 #include "pmc.h"
60
61 #define MC_SECURITY_CFG2        0x7c
62
63 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
64 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
65 #define   PRIORITY_SELECT_USB   BIT(6)
66 #define PRIORITY_SELECT_SDMMC4  BIT(12)
67 #define   PRIORITY_SELECT_USB2  BIT(18)
68 #define   PRIORITY_SELECT_USB3  BIT(17)
69 #define   PRIORITY_SELECT_SE BIT(14)
70
71 #define AHB_GIZMO_AHB_MEM               0xc
72 #define   ENB_FAST_REARBITRATE  BIT(2)
73 #define   DONT_SPLIT_AHB_WR     BIT(7)
74
75 #define   RECOVERY_MODE BIT(31)
76 #define   BOOTLOADER_MODE       BIT(30)
77 #define   FORCED_RECOVERY_MODE  BIT(1)
78
79 #define AHB_GIZMO_USB           0x1c
80 #define AHB_GIZMO_SDMMC4        0x44
81 #define AHB_GIZMO_USB2          0x78
82 #define AHB_GIZMO_USB3          0x7c
83 #define AHB_GIZMO_SE            0x4c
84 #define   IMMEDIATE     BIT(18)
85
86 #define AHB_MEM_PREFETCH_CFG5   0xc8
87 #define AHB_MEM_PREFETCH_CFG3   0xe0
88 #define AHB_MEM_PREFETCH_CFG4   0xe4
89 #define AHB_MEM_PREFETCH_CFG1   0xec
90 #define AHB_MEM_PREFETCH_CFG2   0xf0
91 #define AHB_MEM_PREFETCH_CFG6   0xcc
92 #define   PREFETCH_ENB  BIT(31)
93 #define   MST_ID(x)     (((x) & 0x1f) << 26)
94 #define   AHBDMA_MST_ID MST_ID(5)
95 #define   USB_MST_ID    MST_ID(6)
96 #define SDMMC4_MST_ID   MST_ID(12)
97 #define   USB2_MST_ID   MST_ID(18)
98 #define   USB3_MST_ID   MST_ID(17)
99 #define   SE_MST_ID     MST_ID(14)
100 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
101 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
102
103 unsigned long tegra_avp_kernel_start;
104 unsigned long tegra_avp_kernel_size;
105 unsigned long tegra_bootloader_fb_start;
106 unsigned long tegra_bootloader_fb_size;
107 unsigned long tegra_bootloader_fb2_start;
108 unsigned long tegra_bootloader_fb2_size;
109 unsigned long tegra_fb_start;
110 unsigned long tegra_fb_size;
111 unsigned long tegra_fb2_start;
112 unsigned long tegra_fb2_size;
113 unsigned long tegra_carveout_start;
114 unsigned long tegra_carveout_size;
115 unsigned long tegra_vpr_start;
116 unsigned long tegra_vpr_size;
117 unsigned long tegra_tsec_start;
118 unsigned long tegra_tsec_size;
119 unsigned long tegra_lp0_vec_start;
120 unsigned long tegra_lp0_vec_size;
121 #ifdef CONFIG_TEGRA_NVDUMPER
122 unsigned long nvdumper_reserved;
123 #endif
124 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
125 unsigned long tegra_tzram_start;
126 unsigned long tegra_tzram_size;
127 #endif
128 bool tegra_lp0_vec_relocate;
129 unsigned long tegra_grhost_aperture = ~0ul;
130 static   bool is_tegra_debug_uart_hsport;
131 static struct board_info pmu_board_info;
132 static struct board_info display_board_info;
133 static int panel_id;
134 static struct board_info camera_board_info;
135 static int touch_id;
136
137 static int pmu_core_edp;
138 static int board_panel_type;
139 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
140 static int pwr_i2c_clk = 400;
141 static u8 power_config;
142 /*
143  * Storage for debug-macro.S's state.
144  *
145  * This must be in .data not .bss so that it gets initialized each time the
146  * kernel is loaded. The data is declared here rather than debug-macro.S so
147  * that multiple inclusions of debug-macro.S point at the same data.
148  */
149 u32 tegra_uart_config[4] = {
150         /* Debug UART initialization required */
151         1,
152         /* Debug UART physical address */
153         0,
154         /* Debug UART virtual address */
155         0,
156         /* Scratch space for debug macro */
157         0,
158 };
159
160
161 #define NEVER_RESET 0
162
163 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
164 {
165         unsigned long check;
166         int retry = 10;
167
168         /* Read and check if write is successful,
169          * if val doesn't match with read, retry write.
170          */
171         do {
172                 writel(val, reg);
173                 check = readl(reg);
174                 if (likely(check == val))
175                         break;
176                 else
177                         pr_err("AHB register access fail for reg\n");
178         } while (--retry);
179 }
180
181 void tegra_assert_system_reset(char mode, const char *cmd)
182 {
183 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
184         pr_info("tegra_assert_system_reset() ignored.....");
185         do { } while (1);
186 #else
187         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
188         u32 reg;
189
190         reg = readl_relaxed(reset + PMC_SCRATCH0);
191         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
192         if (cmd) {
193                 if (!strcmp(cmd, "recovery"))
194                         reg |= RECOVERY_MODE;
195                 else if (!strcmp(cmd, "bootloader"))
196                         reg |= BOOTLOADER_MODE;
197                 else if (!strcmp(cmd, "forced-recovery"))
198                         reg |= FORCED_RECOVERY_MODE;
199                 else
200                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
201         }
202         else {
203                 /* Clearing SCRATCH0 31:30:1 on default reboot */
204                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
205         }
206         writel_relaxed(reg, reset + PMC_SCRATCH0);
207         reg = readl_relaxed(reset);
208         reg |= 0x10;
209         writel_relaxed(reg, reset);
210 #endif
211 }
212 static int modem_id;
213 static int commchip_id;
214 static int sku_override;
215 static int debug_uart_port_id;
216 static enum audio_codec_type audio_codec_name;
217 static enum image_type board_image_type = system_image;
218 static int max_cpu_current;
219 static int max_core_current;
220 static int emc_max_dvfs;
221 static int usb_port_owner_info;
222
223 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
224 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
225         /* name         parent          rate            enabled */
226         { "clk_m",      NULL,           0,              true },
227         { "emc",        NULL,           0,              true },
228         { "cpu",        NULL,           0,              true },
229         { "kfuse",      NULL,           0,              true },
230         { "fuse",       NULL,           0,              true },
231         { "sclk",       NULL,           0,              true },
232         { "pll_p",      NULL,           0,              true },
233         { "pll_p_out1", "pll_p",        0,              false },
234         { "pll_p_out3", "pll_p",        0,              false },
235 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
236         { "pll_m_out1", "pll_m",        275000000,      false },
237         { "pll_p_out2",  "pll_p",       102000000,      false },
238         { "sclk",        "pll_p_out2",  102000000,      true },
239         { "pll_p_out4",  "pll_p",       204000000,      true },
240         { "hclk",       "sclk",         102000000,      true },
241         { "pclk",       "hclk",         51000000,       true },
242         { "mselect",    "pll_p",        102000000,      true },
243         { "host1x",     "pll_p",        102000000,      false },
244         { "cl_dvfs_ref", "pll_p",       51000000,       true },
245         { "cl_dvfs_soc", "pll_p",       51000000,       true },
246 #else
247         { "pll_m_out1", "pll_m",        275000000,      true },
248         { "pll_p_out2", "pll_p",        108000000,      false },
249         { "sclk",       "pll_p_out2",   108000000,      true },
250         { "pll_p_out4", "pll_p",        216000000,      true },
251         { "hclk",       "sclk",         108000000,      true },
252         { "pclk",       "hclk",         54000000,       true },
253         { "mselect",    "pll_p",        108000000,      true },
254         { "host1x",     "pll_p",        108000000,      false },
255         { "cl_dvfs_ref", "clk_m",       13000000,       false },
256         { "cl_dvfs_soc", "clk_m",       13000000,       false },
257 #endif
258 #ifdef CONFIG_TEGRA_SLOW_CSITE
259         { "csite",      "clk_m",        1000000,        true },
260 #else
261         { "csite",      NULL,           0,              true },
262 #endif
263         { "pll_u",      NULL,           480000000,      true },
264         { "pll_re_vco", NULL,           672000000,      false },
265         { "xusb_falcon_src",    "pll_re_vco",   224000000,      false},
266         { "xusb_host_src",      "pll_re_vco",   112000000,      false},
267         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
268         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
269         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
270         { "sdmmc1",     "pll_p",        48000000,       false},
271         { "sdmmc3",     "pll_p",        48000000,       false},
272         { "sdmmc4",     "pll_p",        48000000,       false},
273         { "sbc1.sclk",  NULL,           40000000,       false},
274         { "sbc2.sclk",  NULL,           40000000,       false},
275         { "sbc3.sclk",  NULL,           40000000,       false},
276         { "sbc4.sclk",  NULL,           40000000,       false},
277         { "sbc5.sclk",  NULL,           40000000,       false},
278         { "sbc6.sclk",  NULL,           40000000,       false},
279 #ifdef CONFIG_TEGRA_DUAL_CBUS
280         { "c2bus",      "pll_c2",       250000000,      false },
281         { "c3bus",      "pll_c3",       250000000,      false },
282         { "pll_c",      NULL,           624000000,      false },
283 #else
284         { "cbus",       "pll_c",        250000000,      false },
285 #endif
286         { "pll_c_out1", "pll_c",        150000000,      false },
287 #ifdef CONFIG_TEGRA_PLLM_SCALED
288         { "vi",         "pll_p",        0,              false},
289 #endif
290 #ifdef CONFIG_TEGRA_SOCTHERM
291         { "soc_therm",  "pll_p",        51000000,       false },
292         { "tsensor",    "clk_m",        500000,         false },
293 #endif
294         { NULL,         NULL,           0,              0},
295 };
296 #endif
297 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
298 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
299         /* name         parent          rate            enabled */
300         { "osc",        NULL,           0,              true },
301         { "clk_m",      "osc",          0,              true },
302         { "emc",        NULL,           0,              true },
303         { "cpu",        NULL,           0,              true },
304         { "kfuse",      NULL,           0,              true },
305         { "fuse",       NULL,           0,              true },
306         { "sclk",       NULL,           0,              true },
307 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
308         { "pll_p",      NULL,           0,              true },
309         { "pll_p_out1", "pll_p",        0,              false },
310         { "pll_p_out3", "pll_p",        0,              true },
311         { "pll_m_out1", "pll_m",        275000000,      false },
312         { "pll_p_out2",  "pll_p",       102000000,      false },
313         { "sclk",        "pll_p_out2",  102000000,      true },
314         { "pll_p_out4",  "pll_p",       204000000,      true },
315         { "hclk",       "sclk",         102000000,      true },
316         { "pclk",       "hclk",         51000000,       true },
317         { "mselect",    "pll_p",        102000000,      true },
318         { "host1x",     "pll_p",        102000000,      false },
319         { "cl_dvfs_ref", "pll_p",       51000000,       true },
320         { "cl_dvfs_soc", "pll_p",       51000000,       true },
321 #else
322         { "pll_p",      NULL,           0,              true },
323         { "pll_p_out1", "pll_p",        0,              false },
324         { "pll_p_out3", "pll_p",        0,              true },
325         { "pll_m_out1", "pll_m",        275000000,      true },
326         { "pll_p_out2", "pll_p",        108000000,      false },
327         { "sclk",       "pll_p_out2",   108000000,      true },
328         { "pll_p_out4", "pll_p",        216000000,      true },
329         { "host1x",     "pll_p",        108000000,      false },
330         { "cl_dvfs_ref", "clk_m",       13000000,       false },
331         { "cl_dvfs_soc", "clk_m",       13000000,       false },
332         { "hclk",       "sclk",         108000000,      true },
333         { "pclk",       "hclk",         54000000,       true },
334         { "wake.sclk",  NULL,           250000000,      true },
335         { "mselect",    "pll_p",        108000000,      true },
336 #endif
337 #ifdef CONFIG_TEGRA_SLOW_CSITE
338         { "csite",      "clk_m",        1000000,        true },
339 #else
340         { "csite",      NULL,           0,              true },
341 #endif
342         { "pll_u",      NULL,           480000000,      false },
343         { "sdmmc1",     "pll_p",        48000000,       false},
344         { "sdmmc3",     "pll_p",        48000000,       false},
345         { "sdmmc4",     "pll_p",        48000000,       false},
346         { "sbc1.sclk",  NULL,           40000000,       false},
347         { "sbc2.sclk",  NULL,           40000000,       false},
348         { "sbc3.sclk",  NULL,           40000000,       false},
349         { "msenc",      "pll_p",        108000000,      false },
350         { "tsec",       "pll_p",        108000000,      false },
351         { "mc_capa",    "emc",          0,              true },
352         { "mc_cbpa",    "emc",          0,              true },
353         /* Initialize c2bus, c3bus, or cbus at the end of the list
354          * after all the clocks are moved under the proper parents.
355          */
356 #ifdef CONFIG_TEGRA_DUAL_CBUS
357         { "c2bus",      "pll_c2",       200000000,      false },
358         { "c3bus",      "pll_c3",       200000000,      false },
359         { "pll_c",      NULL,           768000000,      false },
360 #else
361         { "cbus",       "pll_c",        200000000,      false },
362 #endif
363         { "pll_c_out1", "pll_c",        100000000,      false },
364 #ifdef CONFIG_TEGRA_SOCTHERM
365         { "soc_therm",  "pll_p",        51000000,       false },
366         { "tsensor",    "clk_m",        400000,         false },
367 #endif
368         { NULL,         NULL,           0,              0},
369 };
370 #endif
371
372 #ifdef CONFIG_CACHE_L2X0
373 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
374 static void tegra_cache_smc(bool enable, u32 arg)
375 {
376         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
377         bool need_affinity_switch;
378         bool can_switch_affinity;
379         bool l2x0_enabled;
380         cpumask_t local_cpu_mask;
381         cpumask_t saved_cpu_mask;
382         unsigned long flags;
383         long ret;
384
385         /*
386          * ISSUE : Some registers of PL310 controler must be written
387          *              from Secure context (and from CPU0)!
388          *
389          * When called form Normal we obtain an abort or do nothing.
390          * Instructions that must be called in Secure:
391          *      - Write to Control register (L2X0_CTRL==0x100)
392          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
393          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
394          *              mandatory at boot time.
395          *      - Tag and Data RAM Latency Control Registers
396          *              (0x108 & 0x10C) must be written in Secure.
397          */
398         need_affinity_switch = (smp_processor_id() != 0);
399         can_switch_affinity = !irqs_disabled();
400
401         WARN_ON(need_affinity_switch && !can_switch_affinity);
402         if (need_affinity_switch && can_switch_affinity) {
403                 cpu_set(0, local_cpu_mask);
404                 sched_getaffinity(0, &saved_cpu_mask);
405                 ret = sched_setaffinity(0, &local_cpu_mask);
406                 WARN_ON(ret != 0);
407         }
408
409         local_irq_save(flags);
410         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
411         if (enable && !l2x0_enabled)
412                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
413         else if (!enable && l2x0_enabled)
414                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
415         local_irq_restore(flags);
416
417         if (need_affinity_switch && can_switch_affinity) {
418                 ret = sched_setaffinity(0, &saved_cpu_mask);
419                 WARN_ON(ret != 0);
420         }
421 }
422
423 static void tegra_l2x0_disable(void)
424 {
425         unsigned long flags;
426         static u32 l2x0_way_mask;
427
428         if (!l2x0_way_mask) {
429                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
430                 u32 aux_ctrl;
431                 u32 ways;
432
433                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
434                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
435                 l2x0_way_mask = (1 << ways) - 1;
436         }
437
438         local_irq_save(flags);
439         tegra_cache_smc(false, l2x0_way_mask);
440         local_irq_restore(flags);
441 }
442 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
443
444 void tegra_init_cache(bool init)
445 {
446         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
447         u32 aux_ctrl;
448 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
449         u32 cache_type;
450         u32 tag_latency, data_latency;
451 #endif
452
453 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
454         /* issue the SMC to enable the L2 */
455         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
456         trace_smc_init_cache(NVSEC_SMC_START);
457         tegra_cache_smc(true, aux_ctrl);
458         trace_smc_init_cache(NVSEC_SMC_DONE);
459
460         /* after init, reread aux_ctrl and register handlers */
461         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
462         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
463
464         /* override outer_disable() with our disable */
465         outer_cache.disable = tegra_l2x0_disable;
466 #else
467 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
468         tag_latency = 0x331;
469         data_latency = 0x441;
470 #else
471 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
472         if (is_lp_cluster()) {
473                 tag_latency = tegra_cpu_c1_l2_tag_latency;
474                 data_latency = tegra_cpu_c1_l2_data_latency;
475         } else {
476                 tag_latency = tegra_cpu_c0_l2_tag_latency;
477                 data_latency = tegra_cpu_c0_l2_data_latency;
478         }
479 #else
480         tag_latency = 0x770;
481         data_latency = 0x770;
482 #endif
483 #endif
484         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
485         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
486
487 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
488 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
489 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
490         /* Enable double line fill */
491         writel(0x40000007, p + L2X0_PREFETCH_CTRL);
492 #else
493         writel(0x7, p + L2X0_PREFETCH_CTRL);
494 #endif
495         writel(0x3, p + L2X0_POWER_CTRL);
496 #endif
497 #endif
498         cache_type = readl(p + L2X0_CACHE_TYPE);
499         aux_ctrl = (cache_type & 0x700) << (17-8);
500         aux_ctrl |= 0x7C400001;
501         if (init) {
502                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
503         } else {
504                 u32 tmp;
505
506                 tmp = aux_ctrl;
507                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
508                 aux_ctrl &= 0x8200c3fe;
509                 aux_ctrl |= tmp;
510                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
511         }
512         l2x0_enable();
513 #endif
514 }
515 #endif
516
517 static void __init tegra_perf_init(void)
518 {
519         u32 reg;
520
521         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
522         reg >>= 11;
523         reg = (1 << (reg & 0x1f))-1;
524         reg |= 0x80000000;
525         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
526         reg = 1;
527         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
528 }
529
530 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
531 static void __init tegra_ramrepair_init(void)
532 {
533         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
534                 u32 reg;
535                 reg = readl(FLOW_CTRL_RAM_REPAIR);
536                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
537                 writel(reg, FLOW_CTRL_RAM_REPAIR);
538         }
539 }
540 #endif
541
542 static void __init tegra_init_power(void)
543 {
544 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
545         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
546 #endif
547 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
548         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
549 #endif
550 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
551         /* some partitions need to be powergated by default for t11x */
552         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
553         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
554         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
555 #endif
556 }
557
558 static inline unsigned long gizmo_readl(unsigned long offset)
559 {
560         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
561 }
562
563 static inline void gizmo_writel(unsigned long value, unsigned long offset)
564 {
565         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
566 }
567
568 static void __init tegra_init_ahb_gizmo_settings(void)
569 {
570         unsigned long val;
571
572         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
573         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
574         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
575
576         val = gizmo_readl(AHB_GIZMO_USB);
577         val |= IMMEDIATE;
578         gizmo_writel(val, AHB_GIZMO_USB);
579
580         val = gizmo_readl(AHB_GIZMO_USB2);
581         val |= IMMEDIATE;
582         gizmo_writel(val, AHB_GIZMO_USB2);
583
584         val = gizmo_readl(AHB_GIZMO_USB3);
585         val |= IMMEDIATE;
586         gizmo_writel(val, AHB_GIZMO_USB3);
587
588 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
589         val = gizmo_readl(AHB_GIZMO_SE);
590         val |= IMMEDIATE;
591         gizmo_writel(val, AHB_GIZMO_SE);
592 #endif
593
594         /*
595          * SDMMC controller is removed from AHB interface in T124 and
596          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
597          * in T11x and T14x SOCs.
598          */
599 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
600         val = gizmo_readl(AHB_GIZMO_SDMMC4);
601         val |= IMMEDIATE;
602         gizmo_writel(val, AHB_GIZMO_SDMMC4);
603 #endif
604
605         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
606         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
607                                 | AHB_PRIORITY_WEIGHT(7);
608 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
609         val |= PRIORITY_SELECT_SE;
610 #endif
611
612 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
613         val |= PRIORITY_SELECT_SDMMC4;
614 #endif
615         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
616
617         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
618         val &= ~MST_ID(~0);
619         val |= PREFETCH_ENB | AHBDMA_MST_ID |
620                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
621         ahb_gizmo_writel(val,
622                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
623
624         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
625         val &= ~MST_ID(~0);
626         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
627                 INACTIVITY_TIMEOUT(0x1000);
628         ahb_gizmo_writel(val,
629                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
630
631         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
632         val &= ~MST_ID(~0);
633         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
634                 INACTIVITY_TIMEOUT(0x1000);
635         ahb_gizmo_writel(val,
636                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
637
638         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
639         val &= ~MST_ID(~0);
640         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
641                 INACTIVITY_TIMEOUT(0x1000);
642         ahb_gizmo_writel(val,
643                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
644
645         /*
646          * SDMMC controller is removed from AHB interface in T124 and
647          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
648          * in T11x and T14x SOCs.
649          */
650 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
651         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
652         val &= ~MST_ID(~0);
653         val |= PREFETCH_ENB | SDMMC4_MST_ID | ADDR_BNDRY(0xc) |
654                 INACTIVITY_TIMEOUT(0x1000);
655         val &= ~SDMMC4_MST_ID;
656         ahb_gizmo_writel(val,
657                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
658 #endif
659
660 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
661         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
662         val &= ~MST_ID(~0);
663         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
664                 INACTIVITY_TIMEOUT(0x1000);
665         ahb_gizmo_writel(val,
666                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
667 #endif
668 }
669
670 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
671 void __init tegra20_init_early(void)
672 {
673 #ifndef CONFIG_SMP
674         /* For SMP system, initializing the reset handler here is too
675            late. For non-SMP systems, the function that calls the reset
676            handler initializer is not called, so do it here for non-SMP. */
677         tegra_cpu_reset_handler_init();
678 #endif
679         tegra_apb_io_init();
680         tegra_perf_init();
681         tegra_init_fuse();
682         tegra_init_cache(true);
683         tegra_pmc_init();
684         tegra_powergate_init();
685         tegra20_hotplug_init();
686         tegra_init_power();
687         tegra_init_ahb_gizmo_settings();
688         tegra_init_debug_uart_rate();
689         tegra_gpio_resume_init();
690         tegra_ram_console_debug_reserve(SZ_1M);
691 }
692 #endif
693 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
694 void __init tegra30_init_early(void)
695 {
696         u32 speedo;
697         u32 tag_latency, data_latency;
698
699 #ifndef CONFIG_SMP
700         /* For SMP system, initializing the reset handler here is too
701            late. For non-SMP systems, the function that calls the reset
702            handler initializer is not called, so do it here for non-SMP. */
703         tegra_cpu_reset_handler_init();
704 #endif
705         tegra_apb_io_init();
706         tegra_perf_init();
707         tegra_init_fuse();
708         /*
709          * Store G/LP cluster L2 latencies to IRAM and DRAM
710          */
711         tegra_cpu_c1_l2_tag_latency = 0x221;
712         tegra_cpu_c1_l2_data_latency = 0x221;
713         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
714         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
715         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
716         speedo = tegra_cpu_speedo_id();
717         if (speedo == 4 || speedo == 5 || speedo == 6 ||
718             speedo == 12 || speedo == 13) {
719                 tag_latency = 0x442;
720                 data_latency = 0x552;
721         } else {
722                 tag_latency = 0x441;
723                 data_latency = 0x551;
724         }
725         tegra_cpu_c0_l2_tag_latency = tag_latency;
726         tegra_cpu_c0_l2_data_latency = data_latency;
727         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
728         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
729         tegra_init_cache(true);
730         tegra_pmc_init();
731         tegra_powergate_init();
732         tegra30_hotplug_init();
733         tegra_init_power();
734         tegra_init_ahb_gizmo_settings();
735         tegra_init_debug_uart_rate();
736         tegra_gpio_resume_init();
737         tegra_ram_console_debug_reserve(SZ_1M);
738
739         init_dma_coherent_pool_size(SZ_1M);
740 }
741 #endif
742 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
743 void __init tegra11x_init_early(void)
744 {
745 #ifndef CONFIG_SMP
746         /* For SMP system, initializing the reset handler here is too
747            late. For non-SMP systems, the function that calls the reset
748            handler initializer is not called, so do it here for non-SMP. */
749         tegra_cpu_reset_handler_init();
750 #endif
751         tegra_apb_io_init();
752         tegra_perf_init();
753         tegra_init_fuse();
754         tegra_ramrepair_init();
755         tegra11x_init_clocks();
756         tegra11x_init_dvfs();
757         tegra_common_init_clock();
758         tegra_clk_init_from_table(tegra11x_clk_init_table);
759         tegra11x_clk_init_la();
760         tegra_pmc_init();
761         tegra_powergate_init();
762         tegra30_hotplug_init();
763         tegra_init_power();
764         tegra_init_ahb_gizmo_settings();
765         tegra_init_debug_uart_rate();
766         tegra_gpio_resume_init();
767
768         init_dma_coherent_pool_size(SZ_2M);
769 }
770 #endif
771 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
772 void __init tegra14x_init_early(void)
773 {
774 #ifndef CONFIG_SMP
775         /* For SMP system, initializing the reset handler here is too
776            late. For non-SMP systems, the function that calls the reset
777            handler initializer is not called, so do it here for non-SMP. */
778         tegra_cpu_reset_handler_init();
779 #endif
780         tegra_apb_io_init();
781         tegra_perf_init();
782         tegra_init_fuse();
783         tegra_ramrepair_init();
784         tegra14x_init_clocks();
785         tegra14x_init_dvfs();
786         tegra_common_init_clock();
787         tegra_clk_init_from_table(tegra14x_clk_init_table);
788         tegra_cpu_c1_l2_tag_latency = 0x110;
789         tegra_cpu_c1_l2_data_latency = 0x331;
790         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
791         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
792         tegra_cpu_c0_l2_tag_latency = 0x111;
793         tegra_cpu_c0_l2_data_latency = 0x441;
794         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
795         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
796         tegra_init_cache(true);
797         tegra_pmc_init();
798         tegra_powergate_init();
799         tegra30_hotplug_init();
800         tegra_init_power();
801         tegra_init_ahb_gizmo_settings();
802         tegra_init_debug_uart_rate();
803         tegra_gpio_resume_init();
804         tegra_ram_console_debug_reserve(SZ_1M);
805 }
806 #endif
807 static int __init tegra_lp0_vec_arg(char *options)
808 {
809         char *p = options;
810
811         tegra_lp0_vec_size = memparse(p, &p);
812         if (*p == '@')
813                 tegra_lp0_vec_start = memparse(p+1, &p);
814         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
815                 tegra_lp0_vec_size = 0;
816                 tegra_lp0_vec_start = 0;
817         }
818
819         return 0;
820 }
821 early_param("lp0_vec", tegra_lp0_vec_arg);
822
823 #ifdef CONFIG_TEGRA_NVDUMPER
824 static int __init tegra_nvdumper_arg(char *options)
825 {
826         char *p = options;
827
828         nvdumper_reserved = memparse(p, &p);
829         return 0;
830 }
831 early_param("nvdumper_reserved", tegra_nvdumper_arg);
832 #endif
833
834 static int __init tegra_bootloader_fb_arg(char *options)
835 {
836         char *p = options;
837
838         tegra_bootloader_fb_size = memparse(p, &p);
839         if (*p == '@')
840                 tegra_bootloader_fb_start = memparse(p+1, &p);
841
842         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
843                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
844
845         return 0;
846 }
847 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
848
849 static int __init tegra_bootloader_fb2_arg(char *options)
850 {
851         char *p = options;
852
853         tegra_bootloader_fb2_size = memparse(p, &p);
854         if (*p == '@')
855                 tegra_bootloader_fb2_start = memparse(p+1, &p);
856
857         pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
858                 tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
859
860         return 0;
861 }
862 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
863
864 static int __init tegra_sku_override(char *id)
865 {
866         char *p = id;
867
868         sku_override = memparse(p, &p);
869
870         return 0;
871 }
872 early_param("sku_override", tegra_sku_override);
873
874 int tegra_get_sku_override(void)
875 {
876         return sku_override;
877 }
878
879 static int __init tegra_vpr_arg(char *options)
880 {
881         char *p = options;
882
883         tegra_vpr_size = memparse(p, &p);
884         if (*p == '@')
885                 tegra_vpr_start = memparse(p+1, &p);
886         pr_info("Found vpr, start=0x%lx size=%lx",
887                 tegra_vpr_start, tegra_vpr_size);
888         return 0;
889 }
890 early_param("vpr", tegra_vpr_arg);
891
892 static int __init tegra_tsec_arg(char *options)
893 {
894         char *p = options;
895
896         tegra_tsec_size = memparse(p, &p);
897         if (*p == '@')
898                 tegra_tsec_start = memparse(p+1, &p);
899         pr_info("Found tsec, start=0x%lx size=%lx",
900                 tegra_tsec_start, tegra_tsec_size);
901         return 0;
902 }
903 early_param("tsec", tegra_tsec_arg);
904
905 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
906 static int __init tegra_tzram_arg(char *options)
907 {
908         char *p = options;
909
910         tegra_tzram_size = memparse(p, &p);
911         if (*p == '@')
912                 tegra_tzram_start = memparse(p + 1, &p);
913         return 0;
914 }
915 early_param("tzram", tegra_tzram_arg);
916 #endif
917
918 enum panel_type get_panel_type(void)
919 {
920         return board_panel_type;
921 }
922 static int __init tegra_board_panel_type(char *options)
923 {
924         if (!strcmp(options, "lvds"))
925                 board_panel_type = panel_type_lvds;
926         else if (!strcmp(options, "dsi"))
927                 board_panel_type = panel_type_dsi;
928         else
929                 return 0;
930         return 1;
931 }
932 __setup("panel=", tegra_board_panel_type);
933
934 int tegra_get_board_panel_id(void)
935 {
936         return panel_id;
937 }
938 static int __init tegra_board_panel_id(char *options)
939 {
940         char *p = options;
941         panel_id = memparse(p, &p);
942         return panel_id;
943 }
944 __setup("display_panel=", tegra_board_panel_id);
945
946 int tegra_get_touch_id(void)
947 {
948         return touch_id;
949 }
950 static int __init tegra_touch_id(char *options)
951 {
952         char *p = options;
953         touch_id = memparse(p, &p);
954         return touch_id;
955 }
956 __setup("touch_type=", tegra_touch_id);
957
958
959 u8 get_power_config(void)
960 {
961         return power_config;
962 }
963 static int __init tegra_board_power_config(char *options)
964 {
965         char *p = options;
966         power_config = memparse(p, &p);
967         return 1;
968 }
969 __setup("power-config=", tegra_board_power_config);
970
971 enum power_supply_type get_power_supply_type(void)
972 {
973         return pow_supply_type;
974 }
975 static int __init tegra_board_power_supply_type(char *options)
976 {
977         if (!strcmp(options, "Adapter"))
978                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
979         if (!strcmp(options, "Mains"))
980                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
981         else if (!strcmp(options, "Battery"))
982                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
983         else
984                 return 0;
985         return 1;
986 }
987 __setup("power_supply=", tegra_board_power_supply_type);
988
989 int get_core_edp(void)
990 {
991         return pmu_core_edp;
992 }
993 static int __init tegra_pmu_core_edp(char *options)
994 {
995         char *p = options;
996         int core_edp = memparse(p, &p);
997         if (core_edp != 0)
998                 pmu_core_edp = core_edp;
999         return 0;
1000 }
1001 early_param("core_edp_mv", tegra_pmu_core_edp);
1002
1003 int get_maximum_cpu_current_supported(void)
1004 {
1005         return max_cpu_current;
1006 }
1007 static int __init tegra_max_cpu_current(char *options)
1008 {
1009         char *p = options;
1010         max_cpu_current = memparse(p, &p);
1011         return 1;
1012 }
1013 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1014
1015 int get_maximum_core_current_supported(void)
1016 {
1017         return max_core_current;
1018 }
1019 static int __init tegra_max_core_current(char *options)
1020 {
1021         char *p = options;
1022         max_core_current = memparse(p, &p);
1023         return 1;
1024 }
1025 __setup("core_edp_ma=", tegra_max_core_current);
1026
1027 int get_emc_max_dvfs(void)
1028 {
1029         return emc_max_dvfs;
1030 }
1031 static int __init tegra_emc_max_dvfs(char *options)
1032 {
1033         char *p = options;
1034         emc_max_dvfs = memparse(p, &p);
1035         return 1;
1036 }
1037 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1038
1039 static int __init tegra_debug_uartport(char *info)
1040 {
1041         char *p = info;
1042         unsigned long long port_id;
1043         if (!strncmp(p, "hsport", 6))
1044                 is_tegra_debug_uart_hsport = true;
1045         else if (!strncmp(p, "lsport", 6))
1046                 is_tegra_debug_uart_hsport = false;
1047
1048         if (p[6] == ',') {
1049                 if (p[7] == '-') {
1050                         debug_uart_port_id = -1;
1051                 } else {
1052                         port_id = memparse(p + 7, &p);
1053                         debug_uart_port_id = (int) port_id;
1054                 }
1055         } else {
1056                 debug_uart_port_id = -1;
1057         }
1058
1059         return 1;
1060 }
1061
1062 bool is_tegra_debug_uartport_hs(void)
1063 {
1064         return is_tegra_debug_uart_hsport;
1065 }
1066
1067 int get_tegra_uart_debug_port_id(void)
1068 {
1069         return debug_uart_port_id;
1070 }
1071 __setup("debug_uartport=", tegra_debug_uartport);
1072
1073 static int __init tegra_image_type(char *options)
1074 {
1075         if (!strcmp(options, "RCK"))
1076                 board_image_type = rck_image;
1077
1078         return 0;
1079 }
1080
1081 enum image_type get_tegra_image_type(void)
1082 {
1083         return board_image_type;
1084 }
1085
1086 __setup("image=", tegra_image_type);
1087
1088 static int __init tegra_audio_codec_type(char *info)
1089 {
1090         char *p = info;
1091         if (!strncmp(p, "wm8903", 6))
1092                 audio_codec_name = audio_codec_wm8903;
1093         else
1094                 audio_codec_name = audio_codec_none;
1095
1096         return 1;
1097 }
1098
1099 enum audio_codec_type get_audio_codec_type(void)
1100 {
1101         return audio_codec_name;
1102 }
1103 __setup("audio_codec=", tegra_audio_codec_type);
1104
1105 static int tegra_get_pwr_i2c_clk_rate(char *options)
1106 {
1107         int clk = simple_strtol(options, NULL, 16);
1108         if (clk != 0)
1109                 pwr_i2c_clk = clk;
1110         return 0;
1111 }
1112
1113 int get_pwr_i2c_clk_rate(void)
1114 {
1115         return pwr_i2c_clk;
1116 }
1117 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1118
1119 void tegra_get_board_info(struct board_info *bi)
1120 {
1121 #ifdef CONFIG_OF
1122         struct device_node *board_info;
1123         u32 prop_val;
1124         int err;
1125
1126         board_info = of_find_node_by_path("/chosen/board_info");
1127         if (!IS_ERR_OR_NULL(board_info)) {
1128                 memset(bi, 0, sizeof(*bi));
1129
1130                 err = of_property_read_u32(board_info, "id", &prop_val);
1131                 if (err)
1132                         pr_err("failed to read /chosen/board_info/id\n");
1133                 else
1134                         bi->board_id = prop_val;
1135
1136                 err = of_property_read_u32(board_info, "sku", &prop_val);
1137                 if (err)
1138                         pr_err("failed to read /chosen/board_info/sku\n");
1139                 else
1140                         bi->sku = prop_val;
1141
1142                 err = of_property_read_u32(board_info, "fab", &prop_val);
1143                 if (err)
1144                         pr_err("failed to read /chosen/board_info/fab\n");
1145                 else
1146                         bi->fab = prop_val;
1147
1148                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1149                 if (err)
1150                         pr_err("failed to read /chosen/board_info/major_revision\n");
1151                 else
1152                         bi->major_revision = prop_val;
1153
1154                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1155                 if (err)
1156                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1157                 else
1158                         bi->minor_revision = prop_val;
1159                 system_serial_high = (bi->board_id << 16) | bi->sku;
1160                 system_serial_low = (bi->fab << 24) |
1161                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1162         } else {
1163 #endif
1164                 bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1165                 bi->sku = (system_serial_high) & 0xFFFF;
1166                 bi->fab = (system_serial_low >> 24) & 0xFF;
1167                 bi->major_revision = (system_serial_low >> 16) & 0xFF;
1168                 bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1169 #ifdef CONFIG_OF
1170         }
1171 #endif
1172 }
1173
1174 static int __init tegra_pmu_board_info(char *info)
1175 {
1176         char *p = info;
1177         pmu_board_info.board_id = memparse(p, &p);
1178         pmu_board_info.sku = memparse(p+1, &p);
1179         pmu_board_info.fab = memparse(p+1, &p);
1180         pmu_board_info.major_revision = memparse(p+1, &p);
1181         pmu_board_info.minor_revision = memparse(p+1, &p);
1182         return 1;
1183 }
1184
1185 void tegra_get_pmu_board_info(struct board_info *bi)
1186 {
1187         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1188 }
1189
1190 __setup("pmuboard=", tegra_pmu_board_info);
1191
1192 static int __init tegra_display_board_info(char *info)
1193 {
1194         char *p = info;
1195         display_board_info.board_id = memparse(p, &p);
1196         display_board_info.sku = memparse(p+1, &p);
1197         display_board_info.fab = memparse(p+1, &p);
1198         display_board_info.major_revision = memparse(p+1, &p);
1199         display_board_info.minor_revision = memparse(p+1, &p);
1200         return 1;
1201 }
1202
1203 void tegra_get_display_board_info(struct board_info *bi)
1204 {
1205         memcpy(bi, &display_board_info, sizeof(struct board_info));
1206 }
1207
1208 __setup("displayboard=", tegra_display_board_info);
1209
1210 static int __init tegra_camera_board_info(char *info)
1211 {
1212         char *p = info;
1213         camera_board_info.board_id = memparse(p, &p);
1214         camera_board_info.sku = memparse(p+1, &p);
1215         camera_board_info.fab = memparse(p+1, &p);
1216         camera_board_info.major_revision = memparse(p+1, &p);
1217         camera_board_info.minor_revision = memparse(p+1, &p);
1218         return 1;
1219 }
1220
1221 void tegra_get_camera_board_info(struct board_info *bi)
1222 {
1223         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1224 }
1225
1226 __setup("cameraboard=", tegra_camera_board_info);
1227
1228 static int __init tegra_modem_id(char *id)
1229 {
1230         char *p = id;
1231
1232         modem_id = memparse(p, &p);
1233         return 1;
1234 }
1235
1236 int tegra_get_modem_id(void)
1237 {
1238         return modem_id;
1239 }
1240
1241 __setup("modem_id=", tegra_modem_id);
1242
1243 static int __init tegra_usb_port_owner_info(char *id)
1244 {
1245         char *p = id;
1246
1247         usb_port_owner_info = memparse(p, &p);
1248         return 1;
1249 }
1250
1251 int tegra_get_usb_port_owner_info(void)
1252 {
1253         return usb_port_owner_info;
1254 }
1255
1256 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1257
1258 static int __init tegra_commchip_id(char *id)
1259 {
1260         char *p = id;
1261
1262         if (get_option(&p, &commchip_id) != 1)
1263                 return 0;
1264         return 1;
1265 }
1266
1267 int tegra_get_commchip_id(void)
1268 {
1269         return commchip_id;
1270 }
1271
1272 __setup("commchip_id=", tegra_commchip_id);
1273
1274 /*
1275  * Tegra has a protected aperture that prevents access by most non-CPU
1276  * memory masters to addresses above the aperture value.  Enabling it
1277  * secures the CPU's memory from the GPU, except through the GART.
1278  */
1279 void __init tegra_protected_aperture_init(unsigned long aperture)
1280 {
1281 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
1282         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1283         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1284         writel(aperture, mc_base + MC_SECURITY_CFG2);
1285 #else
1286         pr_err("Tegra protected aperture disabled because nvmap is using "
1287                 "system memory\n");
1288 #endif
1289 }
1290
1291 /*
1292  * Due to conflicting restrictions on the placement of the framebuffer,
1293  * the bootloader is likely to leave the framebuffer pointed at a location
1294  * in memory that is outside the grhost aperture.  This function will move
1295  * the framebuffer contents from a physical address that is anywhere (lowmem,
1296  * highmem, or outside the memory map) to a physical address that is outside
1297  * the memory map.
1298  */
1299 void __tegra_move_framebuffer(struct platform_device *pdev,
1300         unsigned long to, unsigned long from,
1301         unsigned long size)
1302 {
1303         struct page *page;
1304         void __iomem *to_io;
1305         void *from_virt;
1306         unsigned long i, addr[] = { to, from, };
1307
1308         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1309         BUG_ON(PAGE_ALIGN(from) != from);
1310         BUG_ON(PAGE_ALIGN(size) != size);
1311
1312         to_io = ioremap(to, size);
1313         if (!to_io) {
1314                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1315                 return;
1316         }
1317
1318         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
1319                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1320                         page = phys_to_page(from + i);
1321                         from_virt = kmap(page);
1322                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1323                         kunmap(page);
1324                 }
1325         } else {
1326                 void __iomem *from_io = ioremap(from, size);
1327                 if (!from_io) {
1328                         pr_err("%s: Failed to map source framebuffer\n",
1329                                 __func__);
1330                         goto out;
1331                 }
1332
1333                 for (i = 0; i < size; i += 4)
1334                         writel(readl(from_io + i), to_io + i);
1335
1336                 iounmap(from_io);
1337         }
1338
1339         if (!pdev)
1340                 goto out;
1341
1342         for (i = 0; i < ARRAY_SIZE(addr); i++)
1343                 dma_map_linear(&pdev->dev, addr[i], size, DMA_TO_DEVICE);
1344 out:
1345         iounmap(to_io);
1346 }
1347
1348 void __tegra_clear_framebuffer(struct platform_device *pdev,
1349                                unsigned long to, unsigned long size)
1350 {
1351         void __iomem *to_io;
1352         unsigned long i;
1353
1354         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1355         BUG_ON(PAGE_ALIGN(size) != size);
1356
1357         to_io = ioremap(to, size);
1358         if (!to_io) {
1359                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1360                 return;
1361         }
1362
1363         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1364                 for (i = 0 ; i < size; i += PAGE_SIZE)
1365                         memset(to_io + i, 0, PAGE_SIZE);
1366         } else {
1367                 for (i = 0; i < size; i += 4)
1368                         writel(0, to_io + i);
1369         }
1370
1371         if (!pdev)
1372                 goto out;
1373
1374         dma_map_linear(&pdev->dev, to, size, DMA_TO_DEVICE);
1375 out:
1376         iounmap(to_io);
1377 }
1378
1379 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1380         unsigned long fb2_size)
1381 {
1382         const size_t avp_kernel_reserve = SZ_32M;
1383 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1384         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1385         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1386         tegra_avp_kernel_size = SZ_1M;
1387         tegra_avp_kernel_start = memblock_end_of_DRAM() - avp_kernel_reserve;
1388         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1389                 pr_err("Failed to remove AVP kernel load area %08lx@%08lx "
1390                                 "from memory map\n",
1391                         (unsigned long)avp_kernel_reserve,
1392                         tegra_avp_kernel_start);
1393                 tegra_avp_kernel_size = 0;
1394         }
1395 #endif
1396
1397         if (carveout_size) {
1398                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1399                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1400                         pr_err("Failed to remove carveout %08lx@%08lx "
1401                                 "from memory map\n",
1402                                 carveout_size, tegra_carveout_start);
1403                         tegra_carveout_start = 0;
1404                         tegra_carveout_size = 0;
1405                 } else
1406                         tegra_carveout_size = carveout_size;
1407         }
1408
1409         if (fb2_size) {
1410                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1411                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1412                         pr_err("Failed to remove second framebuffer "
1413                                 "%08lx@%08lx from memory map\n",
1414                                 fb2_size, tegra_fb2_start);
1415                         tegra_fb2_start = 0;
1416                         tegra_fb2_size = 0;
1417                 } else
1418                         tegra_fb2_size = fb2_size;
1419         }
1420
1421         if (fb_size) {
1422                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1423                 if (memblock_remove(tegra_fb_start, fb_size)) {
1424                         pr_err("Failed to remove framebuffer %08lx@%08lx "
1425                                 "from memory map\n",
1426                                 fb_size, tegra_fb_start);
1427                         tegra_fb_start = 0;
1428                         tegra_fb_size = 0;
1429                 } else
1430                         tegra_fb_size = fb_size;
1431         }
1432
1433         if (tegra_fb_size)
1434                 tegra_grhost_aperture = tegra_fb_start;
1435
1436         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1437                 tegra_grhost_aperture = tegra_fb2_start;
1438
1439         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1440                 tegra_grhost_aperture = tegra_carveout_start;
1441
1442         if (tegra_lp0_vec_size &&
1443            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1444                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1445                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
1446                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
1447                         tegra_lp0_vec_start = 0;
1448                         tegra_lp0_vec_size = 0;
1449                 }
1450                 tegra_lp0_vec_relocate = false;
1451         } else
1452                 tegra_lp0_vec_relocate = true;
1453
1454 #ifdef CONFIG_TEGRA_NVDUMPER
1455         if (nvdumper_reserved) {
1456                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1457                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1458                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1459                         nvdumper_reserved = 0;
1460                 }
1461         }
1462 #endif
1463
1464         /*
1465          * We copy the bootloader's framebuffer to the framebuffer allocated
1466          * above, and then free this one.
1467          * */
1468         if (tegra_bootloader_fb_size) {
1469                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
1470                 if (memblock_reserve(tegra_bootloader_fb_start,
1471                                 tegra_bootloader_fb_size)) {
1472                         pr_err("Failed to reserve bootloader frame buffer "
1473                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
1474                                 tegra_bootloader_fb_start);
1475                         tegra_bootloader_fb_start = 0;
1476                         tegra_bootloader_fb_size = 0;
1477                 }
1478         }
1479
1480         if (tegra_bootloader_fb2_size) {
1481                 tegra_bootloader_fb2_size =
1482                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
1483                 if (memblock_reserve(tegra_bootloader_fb2_start,
1484                                 tegra_bootloader_fb2_size)) {
1485                         pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
1486                                 tegra_bootloader_fb2_size,
1487                                 tegra_bootloader_fb2_start);
1488                         tegra_bootloader_fb2_start = 0;
1489                         tegra_bootloader_fb2_size = 0;
1490                 }
1491         }
1492
1493         pr_info("Tegra reserved memory:\n"
1494                 "LP0:                    %08lx - %08lx\n"
1495                 "Bootloader framebuffer: %08lx - %08lx\n"
1496                 "Bootloader framebuffer2: %08lx - %08lx\n"
1497                 "Framebuffer:            %08lx - %08lx\n"
1498                 "2nd Framebuffer:        %08lx - %08lx\n"
1499                 "Carveout:               %08lx - %08lx\n"
1500                 "Vpr:                    %08lx - %08lx\n"
1501                 "Tsec:                   %08lx - %08lx\n",
1502                 tegra_lp0_vec_start,
1503                 tegra_lp0_vec_size ?
1504                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
1505                 tegra_bootloader_fb_start,
1506                 tegra_bootloader_fb_size ?
1507                  tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
1508                 tegra_bootloader_fb2_start,
1509                 tegra_bootloader_fb2_size ?
1510                  tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
1511                 tegra_fb_start,
1512                 tegra_fb_size ?
1513                         tegra_fb_start + tegra_fb_size - 1 : 0,
1514                 tegra_fb2_start,
1515                 tegra_fb2_size ?
1516                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
1517                 tegra_carveout_start,
1518                 tegra_carveout_size ?
1519                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
1520                 tegra_vpr_start,
1521                 tegra_vpr_size ?
1522                         tegra_vpr_start + tegra_vpr_size - 1 : 0,
1523                 tegra_tsec_start,
1524                 tegra_tsec_size ?
1525                 tegra_tsec_start + tegra_tsec_size - 1 : 0);
1526
1527         if (tegra_avp_kernel_size) {
1528                 /* Return excessive memory reserved for AVP kernel */
1529                 if (tegra_avp_kernel_size < avp_kernel_reserve)
1530                         memblock_add(
1531                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
1532                                 avp_kernel_reserve - tegra_avp_kernel_size);
1533                 pr_info(
1534                 "AVP kernel: %08lx - %08lx\n",
1535                         tegra_avp_kernel_start,
1536                         tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
1537         }
1538
1539 #ifdef CONFIG_TEGRA_NVDUMPER
1540         if (nvdumper_reserved) {
1541                 pr_info("Nvdumper:               %08lx - %08lx\n",
1542                         nvdumper_reserved,
1543                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
1544         }
1545 #endif
1546
1547 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1548         pr_info("Tzram:               %08lx - %08lx\n",
1549                 tegra_tzram_start,
1550                 tegra_tzram_size ?
1551                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
1552 #endif
1553 }
1554
1555 #ifdef CONFIG_PSTORE_RAM
1556 static struct persistent_ram_descriptor desc = {
1557         .name = "ramoops",
1558 };
1559
1560 static struct persistent_ram ram = {
1561         .descs = &desc,
1562         .num_descs = 1,
1563 };
1564
1565 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
1566 {
1567         int ret;
1568
1569         ram.start = memblock_end_of_DRAM() - ram_console_size;
1570         ram.size = ram_console_size;
1571         ram.descs->size = ram_console_size;
1572
1573         INIT_LIST_HEAD(&ram.node);
1574
1575         ret = persistent_ram_early_init(&ram);
1576         if (ret)
1577                 goto fail;
1578
1579         return;
1580
1581 fail:
1582         pr_err("Failed to reserve memory block for ram console\n");
1583 }
1584 #endif
1585
1586 int __init tegra_register_fuse(void)
1587 {
1588         return platform_device_register(&tegra_fuse_device);
1589 }
1590
1591 void __init tegra_release_bootloader_fb(void)
1592 {
1593         /* Since bootloader fb is reserved in common.c, it is freed here. */
1594         if (tegra_bootloader_fb_size)
1595                 if (memblock_free(tegra_bootloader_fb_start,
1596                                                 tegra_bootloader_fb_size))
1597                         pr_err("Failed to free bootloader fb.\n");
1598         if (tegra_bootloader_fb2_size)
1599                 if (memblock_free(tegra_bootloader_fb2_start,
1600                                                 tegra_bootloader_fb2_size))
1601                         pr_err("Failed to free bootloader fb2.\n");
1602 }
1603
1604 static struct platform_device *pinmux_devices[] = {
1605         &tegra_gpio_device,
1606         &tegra_pinmux_device,
1607 };
1608
1609 void tegra_enable_pinmux(void)
1610 {
1611         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
1612 }
1613
1614 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
1615         [TEGRA_REVISION_UNKNOWN] = "unknown",
1616         [TEGRA_REVISION_A01]     = "A01",
1617         [TEGRA_REVISION_A02]     = "A02",
1618         [TEGRA_REVISION_A03]     = "A03",
1619         [TEGRA_REVISION_A03p]    = "A03 prime",
1620         [TEGRA_REVISION_A04]     = "A04",
1621         [TEGRA_REVISION_A04p]    = "A04 prime",
1622 };
1623
1624 static const char * __init tegra_get_revision(void)
1625 {
1626         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
1627 }
1628
1629 static const char * __init tegra_get_family(void)
1630 {
1631         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
1632         u32 cid = readl(chip_id);
1633         cid = (cid >> 8) & 0xFF;
1634
1635         switch (cid) {
1636         case TEGRA_CHIPID_TEGRA2:
1637                 cid = 2;
1638                 break;
1639         case TEGRA_CHIPID_TEGRA3:
1640                 cid = 3;
1641                 break;
1642         case TEGRA_CHIPID_TEGRA11:
1643                 cid = 11;
1644                 break;
1645         case TEGRA_CHIPID_TEGRA14:
1646                 cid = 14;
1647                 break;
1648
1649         case TEGRA_CHIPID_UNKNOWN:
1650         default:
1651                 cid = 0;
1652         }
1653         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
1654 }
1655
1656 static const char * __init tegra_get_soc_id(void)
1657 {
1658         int package_id = tegra_package_id();
1659         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
1660                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
1661 }
1662
1663 static void __init tegra_soc_info_populate(struct soc_device_attribute
1664         *soc_dev_attr, const char *machine)
1665 {
1666         soc_dev_attr->soc_id = tegra_get_soc_id();
1667         soc_dev_attr->machine  = machine;
1668         soc_dev_attr->family   = tegra_get_family();
1669         soc_dev_attr->revision = tegra_get_revision();
1670 }
1671
1672 int __init tegra_soc_device_init(const char *machine)
1673 {
1674         struct soc_device *soc_dev;
1675         struct soc_device_attribute *soc_dev_attr;
1676
1677         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1678         if (!soc_dev_attr)
1679                 return -ENOMEM;
1680
1681         tegra_soc_info_populate(soc_dev_attr, machine);
1682
1683         soc_dev = soc_device_register(soc_dev_attr);
1684         if (IS_ERR_OR_NULL(soc_dev)) {
1685                 kfree(soc_dev_attr);
1686                 return -1;
1687         }
1688
1689         return 0;
1690 }
1691
1692 void __init tegra_init_late(void)
1693 {
1694 #ifndef CONFIG_COMMON_CLK
1695         tegra_clk_debugfs_init();
1696 #endif
1697         tegra_powergate_debugfs_init();
1698 }
1699
1700 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
1701 #define ASIM_SHUTDOWN_REG       0x538f0ffc
1702
1703 static void asim_power_off(void)
1704 {
1705         pr_err("ASIM Powering off the device\n");
1706         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
1707         while (1)
1708                 ;
1709 }
1710
1711 static int __init asim_power_off_init(void)
1712 {
1713         if (tegra_cpu_is_asim())
1714                 pm_power_off = asim_power_off;
1715         return 0;
1716 }
1717
1718 arch_initcall(asim_power_off_init);
1719
1720 #if defined(CONFIG_SMC91X)
1721 static struct resource tegra_asim_smc91x_resources[] = {
1722         [0] = {
1723                 .start          = TEGRA_SIM_ETH_BASE,
1724                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
1725                 .flags          = IORESOURCE_MEM,
1726         },
1727         [1] = {
1728                 .start          = IRQ_ETH,
1729                 .end            = IRQ_ETH,
1730                 .flags          = IORESOURCE_IRQ,
1731         },
1732 };
1733
1734 static struct platform_device tegra_asim_smc91x_device = {
1735         .name           = "smc91x",
1736         .id             = 0,
1737         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
1738         .resource       = tegra_asim_smc91x_resources,
1739 };
1740
1741 static int __init asim_enet_init(void)
1742 {
1743         if (tegra_cpu_is_asim())
1744                 platform_device_register(&tegra_asim_smc91x_device);
1745         return 0;
1746 }
1747
1748 rootfs_initcall(asim_enet_init);
1749 #endif
1750
1751 #endif