2 * arch/arm/mach-tegra/common.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/of_irq.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/hardware/gic.h>
29 #include <mach/powergate.h>
42 * Storage for debug-macro.S's state.
44 * This must be in .data not .bss so that it gets initialized each time the
45 * kernel is loaded. The data is declared here rather than debug-macro.S so
46 * that multiple inclusions of debug-macro.S point at the same data.
48 u32 tegra_uart_config[4] = {
49 /* Debug UART initialization required */
51 /* Debug UART physical address */
53 /* Debug UART virtual address */
55 /* Scratch space for debug macro */
60 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
61 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
65 void __init tegra_dt_init_irq(void)
68 of_irq_init(tegra_dt_irq_match);
72 void tegra_assert_system_reset(char mode, const char *cmd)
74 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
77 reg = readl_relaxed(reset);
79 writel_relaxed(reg, reset);
82 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
83 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
84 /* name parent rate enabled */
85 { "clk_m", NULL, 0, true },
86 { "pll_p", "clk_m", 216000000, true },
87 { "pll_p_out1", "pll_p", 28800000, true },
88 { "pll_p_out2", "pll_p", 48000000, true },
89 { "pll_p_out3", "pll_p", 72000000, true },
90 { "pll_p_out4", "pll_p", 24000000, true },
91 { "pll_c", "clk_m", 600000000, true },
92 { "pll_c_out1", "pll_c", 120000000, true },
93 { "sclk", "pll_c_out1", 120000000, true },
94 { "hclk", "sclk", 120000000, true },
95 { "pclk", "hclk", 60000000, true },
96 { "csite", NULL, 0, true },
97 { "emc", NULL, 0, true },
98 { "cpu", NULL, 0, true },
103 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
104 static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
105 /* name parent rate enabled */
106 { "clk_m", NULL, 0, true },
107 { "pll_p", "clk_m", 408000000, true },
108 { "pll_p_out1", "pll_p", 9600000, true },
109 { "pll_p_out4", "pll_p", 102000000, true },
110 { "sclk", "pll_p_out4", 102000000, true },
111 { "hclk", "sclk", 102000000, true },
112 { "pclk", "hclk", 51000000, true },
113 { "csite", NULL, 0, true },
119 static void __init tegra_init_cache(void)
121 #ifdef CONFIG_CACHE_L2X0
123 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
124 u32 aux_ctrl, cache_type;
126 cache_type = readl(p + L2X0_CACHE_TYPE);
127 aux_ctrl = (cache_type & 0x700) << (17-8);
128 aux_ctrl |= 0x7C400001;
130 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
132 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
137 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
138 void __init tegra20_init_early(void)
142 tegra2_init_clocks();
143 tegra_clk_init_from_table(tegra20_clk_init_table);
146 tegra_powergate_init();
147 tegra20_hotplug_init();
150 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
151 void __init tegra30_init_early(void)
155 tegra30_init_clocks();
156 tegra_clk_init_from_table(tegra30_clk_init_table);
159 tegra_powergate_init();
160 tegra30_hotplug_init();
164 void __init tegra_init_late(void)
166 tegra_powergate_debugfs_init();