ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / clock.h
1 /*
2  * arch/arm/mach-tegra/include/mach/clock.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@google.com>
9  *
10  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
11  *
12  * This software is licensed under the terms of the GNU General Public
13  * License version 2, as published by the Free Software Foundation, and
14  * may be copied, distributed, and modified under those terms.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  */
22
23 #ifndef __MACH_TEGRA_CLOCK_H
24 #define __MACH_TEGRA_CLOCK_H
25
26 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
27 #define USE_PLL_LOCK_BITS 0     /* Never use lock bits on Tegra2 */
28 #else
29 #define USE_PLL_LOCK_BITS 1     /* Use lock bits for PLL stabiliation */
30 #define USE_PLLE_SS 1           /* Use spread spectrum coefficients for PLLE */
31 #define PLL_PRE_LOCK_DELAY  2   /* Delay 1st lock bit read after pll enabled */
32 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
33 #define PLL_POST_LOCK_DELAY 50  /* Safety delay after lock is detected */
34 #else
35 #define USE_PLLE_SWCTL 0        /* Use s/w controls for PLLE */
36 #define PLL_POST_LOCK_DELAY 10  /* Safety delay after lock is detected */
37 #endif
38 #endif
39
40 #define RESET_PROPAGATION_DELAY 5
41
42 #ifndef __ASSEMBLY__
43
44 #include <linux/clk-provider.h>
45 #include <linux/clkdev.h>
46 #include <linux/clk.h>
47 #include <linux/list.h>
48 #include <linux/lockdep.h>
49 #include <linux/mutex.h>
50 #include <linux/spinlock.h>
51 #include <linux/clk/tegra.h>
52 #include <trace/events/power.h>
53 #include <asm/cputime.h>
54
55 #define MAX_SAME_LIMIT_SKU_IDS  16
56
57 struct clk;
58
59 #define DIV_BUS                 (1 << 0)
60 #define DIV_U71                 (1 << 1)
61 #define DIV_U71_FIXED           (1 << 2)
62 #define DIV_2                   (1 << 3)
63 #define DIV_U16                 (1 << 4)
64 #define PLL_FIXED               (1 << 5)
65 #define PLL_HAS_CPCON           (1 << 6)
66 #define MUX                     (1 << 7)
67 #define PLLD                    (1 << 8)
68 #define PERIPH_NO_RESET         (1 << 9)
69 #define PERIPH_NO_ENB           (1 << 10)
70 #define PERIPH_EMC_ENB          (1 << 11)
71 #define PERIPH_MANUAL_RESET     (1 << 12)
72 #define PLL_ALT_MISC_REG        (1 << 13)
73 #define PLLU                    (1 << 14)
74 #define PLLX                    (1 << 15)
75 #define MUX_PWM                 (1 << 16)
76 #define MUX8                    (1 << 17)
77 #define DIV_U151_UART           (1 << 18)
78 #define MUX_CLK_OUT             (1 << 19)
79 #define PLLM                    (1 << 20)
80 #define DIV_U71_INT             (1 << 21)
81 #define DIV_U71_IDLE            (1 << 22)
82 #define DIV_U151                (1 << 23)
83 #define DFLL                    (1 << 24)
84 #define ENABLE_ON_INIT          (1 << 28)
85 #define PERIPH_ON_APB           (1 << 29)
86 #define PERIPH_ON_CBUS          (1 << 30)
87 #define BUS_RATE_LIMIT          (1 << 31)
88
89 #define SHARED_BUS_RETENTION    (1 << 0)
90
91 #define PERIPH_DIV              (DIV_U71 | DIV_U151 | DIV_U16)
92
93 #ifdef CONFIG_COMMON_CLK
94 struct clk_tegra;
95 #define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
96 #endif
97
98 struct clk_mux_sel {
99         struct clk      *input;
100         u32             value;
101 };
102
103 struct clk_backup {
104         struct clk      *input;
105         u32             value;
106         unsigned long   bus_rate;
107 };
108
109 struct clk_pll_freq_table {
110         unsigned long   input_rate;
111         unsigned long   output_rate;
112         u16             n;
113         u16             m;
114         u8              p;
115         u8              cpcon;
116 };
117
118 enum clk_state {
119         UNINITIALIZED = 0,
120         ON,
121         OFF,
122 };
123
124 #ifndef CONFIG_COMMON_CLK
125 struct clk_ops {
126         void            (*init)(struct clk *);
127         int             (*enable)(struct clk *);
128         void            (*disable)(struct clk *);
129         int             (*set_parent)(struct clk *, struct clk *);
130         int             (*set_rate)(struct clk *, unsigned long);
131         long            (*round_rate)(struct clk *, unsigned long);
132         void            (*reset)(struct clk *, bool);
133         int             (*shared_bus_update)(struct clk *);
134         int             (*clk_cfg_ex)(struct clk *,
135                                 enum tegra_clk_ex_param, u32);
136         long            (*round_rate_updown)(struct clk *, unsigned long, bool);
137 };
138
139 struct clk_stats {
140         cputime64_t     time_on;
141         u64             last_update;
142 };
143
144 enum cpu_mode {
145         MODE_G = 0,
146         MODE_LP,
147 };
148
149 enum shared_bus_users_mode {
150         SHARED_FLOOR = 0,
151         SHARED_BW,
152         SHARED_CEILING,
153         SHARED_AUTO,
154         SHARED_OVERRIDE,
155         SHARED_ISO_BW,
156         SHARED_CEILING_BUT_ISO,
157 };
158
159 struct clk {
160         /* node for master clocks list */
161         struct list_head        node;           /* node for list of all clocks */
162         struct dvfs             *dvfs;
163         struct clk_lookup       lookup;
164
165 #ifdef CONFIG_DEBUG_FS
166         struct dentry           *dent;
167 #endif
168         bool                    set;
169         struct clk_ops          *ops;
170         unsigned long           dvfs_rate;
171         unsigned long           rate;
172         unsigned long           boot_rate;
173         unsigned long           max_rate;
174         unsigned long           min_rate;
175         bool                    auto_dvfs;
176         bool                    cansleep;
177         u32                     flags;
178         const char              *name;
179
180         u32                     refcnt;
181         enum clk_state          state;
182         struct clk              *parent;
183         u32                     div;
184         u32                     mul;
185         struct clk_stats        stats;
186
187         const struct clk_mux_sel        *inputs;
188         u32                             reg;
189         u32                             reg_shift;
190
191 #ifdef CONFIG_LOCKDEP
192         struct lock_class_key   lockdep_class;
193 #endif
194
195         struct list_head                shared_bus_list;
196         struct clk_backup               shared_bus_backup;
197         struct clk                      *child_bus;
198         unsigned long                   override_rate;
199         u32                             shared_bus_flags;
200
201         union {
202                 struct {
203                         unsigned int                    clk_num;
204                         u32                             src_mask;
205                         u32                             src_shift;
206                         struct clk                      *pll_low;
207                         struct clk                      *pll_high;
208                         struct clk                      *pll_selected;
209                         unsigned long                   threshold;
210                         int                             min_div_low;
211                         int                             min_div_high;
212                 } periph;
213                 struct {
214                         unsigned long                   input_min;
215                         unsigned long                   input_max;
216                         unsigned long                   cf_min;
217                         unsigned long                   cf_max;
218                         unsigned long                   vco_min;
219                         unsigned long                   vco_max;
220                         u8                              cpcon_default;
221                         const struct clk_pll_freq_table *freq_table;
222                         int                             lock_delay;
223                         unsigned long                   fixed_rate;
224                         u32                             misc1;
225                         u32     (*round_p_to_pdiv)(u32 p, u32 *pdiv);
226                 } pll;
227                 struct {
228                         void                            *cl_dvfs;
229                 } dfll;
230                 struct {
231                         unsigned long                   default_rate;
232                 } pll_div;
233                 struct {
234                         u32                             sel;
235                         u32                             reg_mask;
236                 } mux;
237                 struct {
238                         struct clk                      *main;
239                         struct clk                      *backup;
240                         struct clk                      *dynamic;
241                         unsigned long                   backup_rate;
242                         seqcount_t                      backup_seqcnt;
243                         enum cpu_mode                   mode;
244                 } cpu;
245                 struct {
246                         u32                             div71;
247                 } cclk;
248                 struct {
249                         struct clk                      *pclk;
250                         struct clk                      *hclk;
251                         struct clk                      *sclk_low;
252                         struct clk                      *sclk_high;
253                         unsigned long                   threshold;
254                 } system;
255                 struct {
256                         struct clk                      *top_user;
257                         struct clk                      *slow_user;
258                 } cbus;
259                 struct {
260                         struct list_head                node;
261                         bool                            enabled;
262                         unsigned long                   rate;
263                         const char                      *client_id;
264                         struct clk                      *client;
265                         u32                             client_div;
266                         enum shared_bus_users_mode      mode;
267                         u32                             usage_flag;
268                 } shared_bus_user;
269                 struct {
270                         struct tegra_clk_export_ops     *ops;
271                 } export_clk;
272         } u;
273
274         struct raw_notifier_head                        *rate_change_nh;
275
276         struct mutex *cross_clk_mutex;
277         struct mutex mutex;
278         spinlock_t spinlock;
279 };
280
281 #else
282
283 struct clk_tegra {
284         /* node for master clocks list */
285         struct list_head        node;   /* node for list of all clocks */
286         struct clk_lookup       lookup;
287         struct clk_hw           hw;
288
289         bool                    set;
290         unsigned long           fixed_rate;
291         unsigned long           max_rate;
292         unsigned long           min_rate;
293         u32                     flags;
294         const char              *name;
295
296         enum clk_state          state;
297         u32                     div;
298         u32                     mul;
299
300         u32                             reg;
301         u32                             reg_shift;
302
303         struct list_head                shared_bus_list;
304
305         union {
306                 struct {
307                         unsigned int                    clk_num;
308                 } periph;
309                 struct {
310                         unsigned long                   input_min;
311                         unsigned long                   input_max;
312                         unsigned long                   cf_min;
313                         unsigned long                   cf_max;
314                         unsigned long                   vco_min;
315                         unsigned long                   vco_max;
316                         const struct clk_pll_freq_table *freq_table;
317                         int                             lock_delay;
318                         unsigned long                   fixed_rate;
319                 } pll;
320                 struct {
321                         u32                             sel;
322                         u32                             reg_mask;
323                 } mux;
324                 struct {
325                         struct clk                      *main;
326                         struct clk                      *backup;
327                 } cpu;
328                 struct {
329                         struct list_head                node;
330                         bool                            enabled;
331                         unsigned long                   rate;
332                 } shared_bus_user;
333         } u;
334
335         void (*reset)(struct clk_hw *, bool);
336         int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
337 };
338 #endif /* !CONFIG_COMMON_CLK */
339
340 struct clk_duplicate {
341         const char *name;
342         struct clk_lookup lookup;
343 };
344
345 struct tegra_clk_init_table {
346         const char *name;
347         const char *parent;
348         unsigned long rate;
349         bool enabled;
350         unsigned long platform;
351 };
352
353 #define TEGRA_CLK_INIT_PLATFORM_ALL     0
354 #define TEGRA_CLK_INIT_PLATFORM_SI      BIT(0)
355 #define TEGRA_CLK_INIT_PLATFORM_QT      BIT(1)
356 #define TEGRA_CLK_INIT_PLATFORM_FPGA    BIT(2)
357 #define TEGRA_CLK_INIT_PLATFORM_LINSIM  BIT(3)
358 #define TEGRA_CLK_INIT_CPU_ASIM         BIT(4)
359 #define TEGRA_CLK_INIT_PLATFORM_NON_SI  (BIT(1) | BIT(2) | BIT(3))
360
361 #ifndef CONFIG_COMMON_CLK
362 void tegra_init_max_rate(struct clk *c, unsigned long max_rate);
363 void tegra_clk_preset_emc_monitor(unsigned long rate);
364 void tegra_periph_clk_safe_rate_init(struct clk *c);
365 void tegra_clk_verify_parents(void);
366 void clk_init(struct clk *clk);
367 unsigned long tegra_clk_measure_input_freq(void);
368 unsigned long clk_get_rate_locked(struct clk *c);
369 void tegra_clk_init_cbus_plls_from_table(struct tegra_clk_init_table *table);
370 void clk_set_cansleep(struct clk *c);
371 unsigned long clk_get_min_rate(struct clk *c);
372 unsigned long clk_get_max_rate(struct clk *c);
373 bool tegra_is_clk_initialized(struct clk *c);
374
375 int clk_set_rate_locked(struct clk *c, unsigned long rate);
376 int clk_rate_change_notify(struct clk *c, unsigned long rate);
377 int clk_set_parent_locked(struct clk *c, struct clk *parent);
378 int clk_reparent(struct clk *c, struct clk *parent);
379 long clk_round_rate_locked(struct clk *c, unsigned long rate);
380 int tegra_clk_shared_bus_update(struct clk *c);
381 void tegra3_set_cpu_skipper_delay(int delay);
382 unsigned long tegra_clk_measure_input_freq(void);
383 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
384 static inline bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
385 { return true; }
386 #else
387 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p);
388 #endif
389 #endif /* !CONFIG_COMMON_CLK */
390
391 struct tegra_sku_rate_limit {
392         const char *clk_name;
393         unsigned long max_rate;
394         int sku_ids[MAX_SAME_LIMIT_SKU_IDS];
395 };
396
397 void tegra2_init_clocks(void);
398 void tegra30_init_clocks(void);
399 void tegra11x_init_clocks(void);
400 void tegra12x_init_clocks(void);
401 void tegra14x_init_clocks(void);
402 void tegra11x_clk_init_la(void);
403 void tegra_common_init_clock(void);
404 struct clk *tegra_get_clock_by_name(const char *name);
405 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
406
407 #ifndef CONFIG_COMMON_CLK
408 static inline bool clk_is_auto_dvfs(struct clk *c)
409 {
410         return c->auto_dvfs;
411 }
412
413 static inline bool clk_is_dvfs(struct clk *c)
414 {
415         return (c->dvfs != NULL);
416 }
417
418 static inline bool clk_cansleep(struct clk *c)
419 {
420         return c->cansleep;
421 }
422
423 static inline void clk_lock_save(struct clk *c, unsigned long *flags)
424 {
425         if (clk_cansleep(c)) {
426                 *flags = 0;
427                 mutex_lock(&c->mutex);
428                 if (c->cross_clk_mutex)
429                         mutex_lock(c->cross_clk_mutex);
430         } else {
431                 spin_lock_irqsave(&c->spinlock, *flags);
432         }
433 }
434
435 static inline void clk_unlock_restore(struct clk *c, unsigned long *flags)
436 {
437         if (clk_cansleep(c)) {
438                 if (c->cross_clk_mutex)
439                         mutex_unlock(c->cross_clk_mutex);
440                 mutex_unlock(&c->mutex);
441         } else {
442                 spin_unlock_irqrestore(&c->spinlock, *flags);
443         }
444 }
445
446 static inline int tegra_clk_prepare_enable(struct clk *c)
447 {
448         if (clk_cansleep(c))
449                 return clk_prepare_enable(c);
450         return clk_enable(c);
451 }
452
453 static inline void tegra_clk_disable_unprepare(struct clk *c)
454 {
455         if (clk_cansleep(c))
456                 clk_disable_unprepare(c);
457         else
458                 clk_disable(c);
459 }
460
461 static inline void clk_lock_init(struct clk *c)
462 {
463         mutex_init(&c->mutex);
464         spin_lock_init(&c->spinlock);
465 }
466 #endif
467
468 #ifdef CONFIG_CPU_FREQ
469 struct cpufreq_frequency_table;
470
471 struct tegra_cpufreq_table_data {
472         struct cpufreq_frequency_table *freq_table;
473         int throttle_lowest_index;
474         int throttle_highest_index;
475         int suspend_index;
476 };
477 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void);
478 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate);
479 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
480 static inline int tegra_update_mselect_rate(unsigned long cpu_rate)
481 { return 0; }
482 #else
483 int tegra_update_mselect_rate(unsigned long cpu_rate);
484 #endif
485 #else
486 static inline unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
487 { return 0; }
488 #endif
489
490 #endif
491 #endif