ARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2
[linux-3.10.git] / arch / arm / mach-tegra / clock.h
1 /*
2  * arch/arm/mach-tegra/include/mach/clock.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@google.com>
9  *
10  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
11  *
12  * This software is licensed under the terms of the GNU General Public
13  * License version 2, as published by the Free Software Foundation, and
14  * may be copied, distributed, and modified under those terms.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  */
22
23 #ifndef __MACH_TEGRA_CLOCK_H
24 #define __MACH_TEGRA_CLOCK_H
25
26 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
27 #define USE_PLL_LOCK_BITS 0     /* Never use lock bits on Tegra2 */
28 #else
29 #define USE_PLL_LOCK_BITS 1     /* Use lock bits for PLL stabiliation */
30 #define USE_PLLE_SS 1           /* Use spread spectrum coefficients for PLLE */
31 #define PLL_PRE_LOCK_DELAY  2   /* Delay 1st lock bit read after pll enabled */
32 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
33 #define PLL_POST_LOCK_DELAY 50  /* Safety delay after lock is detected */
34 #else
35 #define USE_PLLE_SWCTL 0        /* Use s/w controls for PLLE */
36 #define PLL_POST_LOCK_DELAY 10  /* Safety delay after lock is detected */
37 #endif
38 #endif
39
40 #define RESET_PROPAGATION_DELAY 5
41
42 #ifndef __ASSEMBLY__
43
44 #include <linux/clk-provider.h>
45 #include <linux/clkdev.h>
46 #include <linux/clk.h>
47 #include <linux/list.h>
48 #include <linux/lockdep.h>
49 #include <linux/mutex.h>
50 #include <linux/spinlock.h>
51 #include <linux/clk/tegra.h>
52 #include <trace/events/power.h>
53 #include <asm/cputime.h>
54
55 #define MAX_SAME_LIMIT_SKU_IDS  16
56
57 struct clk;
58
59 #define DIV_BUS                 (1 << 0)
60 #define DIV_U71                 (1 << 1)
61 #define DIV_U71_FIXED           (1 << 2)
62 #define DIV_2                   (1 << 3)
63 #define DIV_U16                 (1 << 4)
64 #define PLL_FIXED               (1 << 5)
65 #define PLL_HAS_CPCON           (1 << 6)
66 #define MUX                     (1 << 7)
67 #define PLLD                    (1 << 8)
68 #define PERIPH_NO_RESET         (1 << 9)
69 #define PERIPH_NO_ENB           (1 << 10)
70 #define PERIPH_EMC_ENB          (1 << 11)
71 #define PERIPH_MANUAL_RESET     (1 << 12)
72 #define PLL_ALT_MISC_REG        (1 << 13)
73 #define PLLU                    (1 << 14)
74 #define PLLX                    (1 << 15)
75 #define MUX_PWM                 (1 << 16)
76 #define MUX8                    (1 << 17)
77 #define DIV_U151_UART           (1 << 18)
78 #define MUX_CLK_OUT             (1 << 19)
79 #define PLLM                    (1 << 20)
80 #define DIV_U71_INT             (1 << 21)
81 #define DIV_U71_IDLE            (1 << 22)
82 #define DIV_U151                (1 << 23)
83 #define DFLL                    (1 << 24)
84 #define ENABLE_ON_INIT          (1 << 28)
85 #define PERIPH_ON_APB           (1 << 29)
86 #define PERIPH_ON_CBUS          (1 << 30)
87
88 #ifdef CONFIG_COMMON_CLK
89 struct clk_tegra;
90 #define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
91 #endif
92
93 struct clk_mux_sel {
94         struct clk      *input;
95         u32             value;
96 };
97
98 struct clk_backup {
99         struct clk      *input;
100         u32             value;
101         unsigned long   bus_rate;
102 };
103
104 struct clk_pll_freq_table {
105         unsigned long   input_rate;
106         unsigned long   output_rate;
107         u16             n;
108         u16             m;
109         u8              p;
110         u8              cpcon;
111 };
112
113 enum clk_state {
114         UNINITIALIZED = 0,
115         ON,
116         OFF,
117 };
118
119 #ifndef CONFIG_COMMON_CLK
120 struct clk_ops {
121         void            (*init)(struct clk *);
122         int             (*enable)(struct clk *);
123         void            (*disable)(struct clk *);
124         int             (*set_parent)(struct clk *, struct clk *);
125         int             (*set_rate)(struct clk *, unsigned long);
126         long            (*round_rate)(struct clk *, unsigned long);
127         void            (*reset)(struct clk *, bool);
128         int             (*shared_bus_update)(struct clk *);
129         int             (*clk_cfg_ex)(struct clk *,
130                                 enum tegra_clk_ex_param, u32);
131         long            (*round_rate_updown)(struct clk *, unsigned long, bool);
132 };
133
134 struct clk_stats {
135         cputime64_t     time_on;
136         u64             last_update;
137 };
138
139 enum cpu_mode {
140         MODE_G = 0,
141         MODE_LP,
142 };
143
144 enum shared_bus_users_mode {
145         SHARED_FLOOR = 0,
146         SHARED_BW,
147         SHARED_CEILING,
148         SHARED_AUTO,
149         SHARED_OVERRIDE,
150         SHARED_ISO_BW,
151         SHARED_CEILING_BUT_ISO,
152 };
153
154 struct clk {
155         /* node for master clocks list */
156         struct list_head        node;           /* node for list of all clocks */
157         struct dvfs             *dvfs;
158         struct clk_lookup       lookup;
159
160 #ifdef CONFIG_DEBUG_FS
161         struct dentry           *dent;
162 #endif
163         bool                    set;
164         struct clk_ops          *ops;
165         unsigned long           dvfs_rate;
166         unsigned long           rate;
167         unsigned long           boot_rate;
168         unsigned long           max_rate;
169         unsigned long           min_rate;
170         bool                    auto_dvfs;
171         bool                    cansleep;
172         u32                     flags;
173         const char              *name;
174
175         u32                     refcnt;
176         enum clk_state          state;
177         struct clk              *parent;
178         u32                     div;
179         u32                     mul;
180         struct clk_stats        stats;
181
182         const struct clk_mux_sel        *inputs;
183         u32                             reg;
184         u32                             reg_shift;
185
186 #ifdef CONFIG_LOCKDEP
187         struct lock_class_key   lockdep_class;
188 #endif
189
190         struct list_head                shared_bus_list;
191         struct clk_backup               shared_bus_backup;
192         struct clk                      *child_bus;
193         unsigned long                   override_rate;
194
195         union {
196                 struct {
197                         unsigned int                    clk_num;
198                         u32                             src_mask;
199                         u32                             src_shift;
200                         struct clk                      *pll_low;
201                         struct clk                      *pll_high;
202                         unsigned long                   threshold;
203                         int                             min_div_low;
204                         int                             min_div_high;
205                 } periph;
206                 struct {
207                         unsigned long                   input_min;
208                         unsigned long                   input_max;
209                         unsigned long                   cf_min;
210                         unsigned long                   cf_max;
211                         unsigned long                   vco_min;
212                         unsigned long                   vco_max;
213                         u8                              cpcon_default;
214                         const struct clk_pll_freq_table *freq_table;
215                         int                             lock_delay;
216                         unsigned long                   fixed_rate;
217                         u32                             misc1;
218                         u32     (*round_p_to_pdiv)(u32 p, u32 *pdiv);
219                 } pll;
220                 struct {
221                         void                            *cl_dvfs;
222                 } dfll;
223                 struct {
224                         unsigned long                   default_rate;
225                 } pll_div;
226                 struct {
227                         u32                             sel;
228                         u32                             reg_mask;
229                 } mux;
230                 struct {
231                         struct clk                      *main;
232                         struct clk                      *backup;
233                         struct clk                      *dynamic;
234                         unsigned long                   backup_rate;
235                         enum cpu_mode                   mode;
236                 } cpu;
237                 struct {
238                         u32                             div71;
239                 } cclk;
240                 struct {
241                         struct clk                      *pclk;
242                         struct clk                      *hclk;
243                         struct clk                      *sclk_low;
244                         struct clk                      *sclk_high;
245                         unsigned long                   threshold;
246                 } system;
247                 struct {
248                         struct clk                      *top_user;
249                         struct clk                      *slow_user;
250                 } cbus;
251                 struct {
252                         struct list_head                node;
253                         bool                            enabled;
254                         unsigned long                   rate;
255                         const char                      *client_id;
256                         struct clk                      *client;
257                         u32                             client_div;
258                         enum shared_bus_users_mode      mode;
259                         u32                             usage_flag;
260                 } shared_bus_user;
261         } u;
262
263         struct raw_notifier_head                        *rate_change_nh;
264
265         struct mutex *cross_clk_mutex;
266         struct mutex mutex;
267         spinlock_t spinlock;
268 };
269
270 #else
271
272 struct clk_tegra {
273         /* node for master clocks list */
274         struct list_head        node;   /* node for list of all clocks */
275         struct clk_lookup       lookup;
276         struct clk_hw           hw;
277
278         bool                    set;
279         unsigned long           fixed_rate;
280         unsigned long           max_rate;
281         unsigned long           min_rate;
282         u32                     flags;
283         const char              *name;
284
285         enum clk_state          state;
286         u32                     div;
287         u32                     mul;
288
289         u32                             reg;
290         u32                             reg_shift;
291
292         struct list_head                shared_bus_list;
293
294         union {
295                 struct {
296                         unsigned int                    clk_num;
297                 } periph;
298                 struct {
299                         unsigned long                   input_min;
300                         unsigned long                   input_max;
301                         unsigned long                   cf_min;
302                         unsigned long                   cf_max;
303                         unsigned long                   vco_min;
304                         unsigned long                   vco_max;
305                         const struct clk_pll_freq_table *freq_table;
306                         int                             lock_delay;
307                         unsigned long                   fixed_rate;
308                 } pll;
309                 struct {
310                         u32                             sel;
311                         u32                             reg_mask;
312                 } mux;
313                 struct {
314                         struct clk                      *main;
315                         struct clk                      *backup;
316                 } cpu;
317                 struct {
318                         struct list_head                node;
319                         bool                            enabled;
320                         unsigned long                   rate;
321                 } shared_bus_user;
322         } u;
323
324         void (*reset)(struct clk_hw *, bool);
325         int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
326 };
327 #endif /* !CONFIG_COMMON_CLK */
328
329 struct clk_duplicate {
330         const char *name;
331         struct clk_lookup lookup;
332 };
333
334 struct tegra_clk_init_table {
335         const char *name;
336         const char *parent;
337         unsigned long rate;
338         bool enabled;
339 };
340
341 #ifndef CONFIG_COMMON_CLK
342 void tegra_init_max_rate(struct clk *c, unsigned long max_rate);
343 void tegra_clk_preset_emc_monitor(unsigned long rate);
344 void tegra_clk_verify_parents(void);
345 void clk_init(struct clk *clk);
346 unsigned long tegra_clk_measure_input_freq(void);
347 unsigned long clk_get_rate_locked(struct clk *c);
348 void tegra_clk_init_cbus_plls_from_table(struct tegra_clk_init_table *table);
349 void clk_set_cansleep(struct clk *c);
350 unsigned long clk_get_min_rate(struct clk *c);
351 unsigned long clk_get_max_rate(struct clk *c);
352 int clk_set_rate_locked(struct clk *c, unsigned long rate);
353 int clk_rate_change_notify(struct clk *c, unsigned long rate);
354 int clk_set_parent_locked(struct clk *c, struct clk *parent);
355 int clk_reparent(struct clk *c, struct clk *parent);
356 long clk_round_rate_locked(struct clk *c, unsigned long rate);
357 int tegra_clk_shared_bus_update(struct clk *c);
358 void tegra3_set_cpu_skipper_delay(int delay);
359 unsigned long tegra_clk_measure_input_freq(void);
360 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
361 static inline bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
362 { return true; }
363 #else
364 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p);
365 #endif
366 #endif /* !CONFIG_COMMON_CLK */
367
368 struct tegra_sku_rate_limit {
369         const char *clk_name;
370         unsigned long max_rate;
371         int sku_ids[MAX_SAME_LIMIT_SKU_IDS];
372 };
373
374 void tegra2_init_clocks(void);
375 void tegra30_init_clocks(void);
376 void tegra11x_init_clocks(void);
377 void tegra12x_init_clocks(void);
378 void tegra14x_init_clocks(void);
379 void tegra11x_clk_init_la(void);
380 void tegra_common_init_clock(void);
381 struct clk *tegra_get_clock_by_name(const char *name);
382 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
383
384 #ifndef CONFIG_COMMON_CLK
385 static inline bool clk_is_auto_dvfs(struct clk *c)
386 {
387         return c->auto_dvfs;
388 }
389
390 static inline bool clk_is_dvfs(struct clk *c)
391 {
392         return (c->dvfs != NULL);
393 }
394
395 static inline bool clk_cansleep(struct clk *c)
396 {
397         return c->cansleep;
398 }
399
400 static inline void clk_lock_save(struct clk *c, unsigned long *flags)
401 {
402         trace_clock_lock(c->name, c->rate, raw_smp_processor_id());
403
404         if (clk_cansleep(c)) {
405                 *flags = 0;
406                 mutex_lock(&c->mutex);
407                 if (c->cross_clk_mutex)
408                         mutex_lock(c->cross_clk_mutex);
409         } else {
410                 spin_lock_irqsave(&c->spinlock, *flags);
411         }
412 }
413
414 static inline void clk_unlock_restore(struct clk *c, unsigned long *flags)
415 {
416         if (clk_cansleep(c)) {
417                 if (c->cross_clk_mutex)
418                         mutex_unlock(c->cross_clk_mutex);
419                 mutex_unlock(&c->mutex);
420         } else {
421                 spin_unlock_irqrestore(&c->spinlock, *flags);
422         }
423
424         trace_clock_unlock(c->name, c->rate, raw_smp_processor_id());
425 }
426
427 static inline int tegra_clk_prepare_enable(struct clk *c)
428 {
429         if (clk_cansleep(c))
430                 return clk_prepare_enable(c);
431         return clk_enable(c);
432 }
433
434 static inline void tegra_clk_disable_unprepare(struct clk *c)
435 {
436         if (clk_cansleep(c))
437                 clk_disable_unprepare(c);
438         else
439                 clk_disable(c);
440 }
441
442 static inline void clk_lock_init(struct clk *c)
443 {
444         mutex_init(&c->mutex);
445         spin_lock_init(&c->spinlock);
446 }
447 #endif
448
449 #ifdef CONFIG_CPU_FREQ
450 struct cpufreq_frequency_table;
451
452 struct tegra_cpufreq_table_data {
453         struct cpufreq_frequency_table *freq_table;
454         int throttle_lowest_index;
455         int throttle_highest_index;
456         int suspend_index;
457 };
458 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void);
459 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate);
460 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
461 static inline int tegra_update_mselect_rate(unsigned long cpu_rate)
462 { return 0; }
463 #else
464 int tegra_update_mselect_rate(unsigned long cpu_rate);
465 #endif
466 #endif
467
468 #endif
469 #endif