ARM: tegra12: vcm30t124: Set clocks at POR
[linux-3.10.git] / arch / arm / mach-tegra / board-vcm30_t124.c
1 /*
2  * arch/arm/mach-tegra/board-vcm30_t124.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/platform_device.h>
20 #include <linux/i2c-tegra.h>
21 #include <linux/i2c.h>
22 #include <linux/platform_data/serial-tegra.h>
23 #include <linux/platform_data/tegra_usb.h>
24 #include <linux/platform_data/tegra_nor.h>
25 #include <linux/platform_data/tegra_ahci.h>
26 #include <linux/of_platform.h>
27 #include <linux/kernel.h>
28 #include <linux/clocksource.h>
29 #include <linux/irqchip.h>
30 #include <linux/pci-tegra.h>
31
32 #include <mach/tegra_asoc_pdata.h>
33 #include <mach/io_dpd.h>
34 #include <asm/mach/arch.h>
35 #include <mach/isomgr.h>
36
37 #include "iomap.h"
38 #include "board.h"
39 #include "clock.h"
40 #include "board-vcm30_t124.h"
41 #include "devices.h"
42 #include "board-common.h"
43 #include "common.h"
44
45 #include <asm/mach-types.h>
46 #include "tegra-of-dev-auxdata.h"
47
48 static struct board_info board_info, display_board_info;
49
50 /*
51  * Set clock values as per automotive POR
52  */
53 static __initdata struct tegra_clk_init_table vcm30_t124_clk_init_table[] = {
54         /* name                 parent          rate    enabled (always on)*/
55
56         { "pll_c",              NULL,           792000000,      true},
57
58         { "automotive.sclk",    NULL,           316800000,      true},
59         { "automotive.hclk",    NULL,           316800000,      true},
60         { "automotive.pclk",    NULL,           158400000,      true},
61
62         { "mselect",            "pll_p",        408000000,      true},
63         /* FIXME: Remove this once the issue with cap.vcore.mselect is fixed */
64         { "override.mselect",   NULL,           408000000,      true},
65
66         { "se.cbus",            NULL,           432000000,      false},
67         { "msenc.cbus",         NULL,           432000000,      false},
68         { "vde.cbus",           NULL,           432000000,      false},
69
70         { "vic03.cbus",         NULL,           660000000,      false},
71         { "tsec.cbus",          NULL,           660000000,      false},
72
73         { "vi.c4bus",           NULL,           600000000,      false},
74         { "isp.c4bus",          NULL,           600000000,      false},
75
76         { "pll_d_out0",         "pll_d",        474000000,      true},
77         { "disp2",              "pll_d_out0",   474000000,      false},
78         { "disp1",              "pll_d_out0",   474000000,      false},
79
80         { "pll_d2",             NULL,           297000000,      true},
81         { "hdmi",               "pll_d2",       297000000,      false},
82
83         { "pll_a_out0",         NULL,           24600000,       true},
84         { "i2s0",               "pll_a_out0",   24600000,       false},
85         { "i2s1",               "pll_a_out0",   24600000,       false},
86         { "i2s2",               "pll_a_out0",   24600000,       false},
87         { "i2s3",               "pll_a_out0",   24600000,       false},
88         { "i2s4",               "pll_a_out0",   24600000,       false},
89
90         { "dam0",               "pll_p",        19900000,       false},
91         { "dam1",               "pll_p",        19900000,       false},
92         { "dam2",               "pll_p",        19900000,       false},
93         { "adx",                "pll_p",        19900000,       false},
94         { "adx1",               "pll_p",        19900000,       false},
95         { "amx",                "pll_p",        19900000,       false},
96         { "amx1",               "pll_p",        19900000,       false},
97
98         { "spdif_out",          "pll_a_out0",   24600000,       false},
99         { "hda",                "pll_p",        48000000,       false},
100         { "cilab",              "pll_p",        10200000,       false},
101         { "cilcd",              "pll_p",        10200000,       false},
102         { "cile",               "pll_p",        10200000,       false},
103
104         { "nor",                "pll_p",        102000000,      false},
105
106         { "sbc1",               "pll_p",        25000000,       false},
107         { "sbc2",               "pll_p",        25000000,       false},
108         { "sbc3",               "pll_p",        25000000,       false},
109         { "sbc4",               "pll_p",        25000000,       false},
110         { "sbc5",               "pll_p",        25000000,       false},
111         { "sbc6",               "pll_p",        25000000,       false},
112
113         { "uarta",              "pll_p",        408000000,      false},
114         { "uartb",              "pll_p",        408000000,      false},
115         { "uartc",              "pll_p",        408000000,      false},
116         { "uartd",              "pll_p",        408000000,      false},
117
118         { NULL,                 NULL,           0,              0},
119 };
120
121 static struct tegra_i2c_platform_data vcm30_t124_i2c1_platform_data = {
122         .bus_clk_rate   = 100000,
123         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
124         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
125 };
126
127 static struct tegra_i2c_platform_data vcm30_t124_i2c2_platform_data = {
128         .bus_clk_rate   = 100000,
129         .is_clkon_always = true,
130         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
131         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
132 };
133
134 static struct tegra_i2c_platform_data vcm30_t124_i2c3_platform_data = {
135         .bus_clk_rate   = 400000,
136         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
137         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
138 };
139
140 static struct tegra_i2c_platform_data vcm30_t124_i2c4_platform_data = {
141         .bus_clk_rate   = 10000,
142         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
143         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
144 };
145
146 static struct tegra_i2c_platform_data vcm30_t124_i2c5_platform_data = {
147         .bus_clk_rate   = 400000,
148         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
149         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
150 };
151
152 static struct tegra_nor_platform_data vcm30_t124_nor_data = {
153         .flash = {
154                 .map_name = "cfi_probe",
155                 .width = 2,
156         },
157         .chip_parms = {
158                 .MuxMode = NorMuxMode_ADNonMux,
159                 .ReadMode = NorReadMode_Page,
160                 .PageLength = NorPageLength_8Word,
161                 .ReadyActive = NorReadyActive_WithData,
162                 /* FIXME: Need to use characterized value */
163                 .timing_default = {
164                         .timing0 = 0x30300273,
165                         .timing1 = 0x00030302,
166                 },
167                 .timing_read = {
168                         .timing0 = 0x30300273,
169                         .timing1 = 0x00030302,
170                 },
171         },
172 };
173
174 static struct cs_info vcm30_t124_cs_info[] = {
175         {
176                 .cs = CS_0,
177                 .num_cs_gpio = 0,
178                 .virt = IO_ADDRESS(TEGRA_NOR_FLASH_BASE),
179                 .size = SZ_64M,
180                 .phys = TEGRA_NOR_FLASH_BASE,
181         },
182 };
183
184 static void vcm30_t124_nor_init(void)
185 {
186         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
187
188         vcm30_t124_nor_data.info.cs = kzalloc(sizeof(struct cs_info) *
189                                         ARRAY_SIZE(vcm30_t124_cs_info),
190                                         GFP_KERNEL);
191         if (!vcm30_t124_nor_data.info.cs)
192                 BUG();
193
194         vcm30_t124_nor_data.info.num_chips = ARRAY_SIZE(vcm30_t124_cs_info);
195
196         memcpy(vcm30_t124_nor_data.info.cs, vcm30_t124_cs_info,
197                                 sizeof(struct cs_info) * ARRAY_SIZE(vcm30_t124_cs_info));
198
199         tegra_nor_device.dev.platform_data = &vcm30_t124_nor_data;
200         platform_device_register(&tegra_nor_device);
201 }
202
203 static struct i2c_board_info __initdata wm8731_board_info = {
204         I2C_BOARD_INFO("wm8731", 0x1a),
205 };
206
207 static struct i2c_board_info __initdata ad1937_board_info = {
208         I2C_BOARD_INFO("ad1937", 0x07),
209 };
210
211 static void vcm30_t124_i2c_init(void)
212 {
213         struct board_info board_info;
214         tegra_get_board_info(&board_info);
215         /* T124 does not use device tree as of now */
216         tegra12_i2c_device1.dev.platform_data = &vcm30_t124_i2c1_platform_data;
217         tegra12_i2c_device2.dev.platform_data = &vcm30_t124_i2c2_platform_data;
218         tegra12_i2c_device3.dev.platform_data = &vcm30_t124_i2c3_platform_data;
219         tegra12_i2c_device4.dev.platform_data = &vcm30_t124_i2c4_platform_data;
220         tegra12_i2c_device5.dev.platform_data = &vcm30_t124_i2c5_platform_data;
221
222         platform_device_register(&tegra12_i2c_device5);
223         platform_device_register(&tegra12_i2c_device4);
224         platform_device_register(&tegra12_i2c_device3);
225         platform_device_register(&tegra12_i2c_device2);
226         platform_device_register(&tegra12_i2c_device1);
227
228         i2c_register_board_info(0, &wm8731_board_info, 1);
229         i2c_register_board_info(0, &ad1937_board_info, 1);
230 }
231
232 /* Register debug UART in old fashion and use DT for all others */
233 #ifndef CONFIG_USE_OF
234 static struct platform_device *vcm30_t124_uart_devices[] __initdata = {
235         &tegra_uarta_device,
236         &tegra_uartb_device,
237         &tegra_uartd_device,
238 };
239
240 static struct tegra_serial_platform_data vcm30_t124_uarta_pdata = {
241         .dma_req_selector = 8,
242         .modem_interrupt = false,
243 };
244
245 static struct tegra_serial_platform_data vcm30_t124_uartb_pdata = {
246         .dma_req_selector = 9,
247         .modem_interrupt = false,
248 };
249
250 static struct tegra_serial_platform_data vcm30_t124_uartd_pdata = {
251         .dma_req_selector = 19,
252         .modem_interrupt = false,
253 };
254 #endif
255
256 static struct tegra_serial_platform_data vcm30_t124_uartc_pdata = {
257         .dma_req_selector = 10,
258         .modem_interrupt = false,
259 };
260
261 static void __init vcm30_t124_uart_init(void)
262 {
263         int debug_port_id;
264
265 #ifndef CONFIG_USE_OF
266         tegra_uarta_device.dev.platform_data = &vcm30_t124_uarta_pdata;
267         tegra_uartb_device.dev.platform_data = &vcm30_t124_uartb_pdata;
268         tegra_uartd_device.dev.platform_data = &vcm30_t124_uartd_pdata;
269         platform_add_devices(vcm30_t124_uart_devices,
270                         ARRAY_SIZE(vcm30_t124_uart_devices));
271 #endif
272         tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
273         if (!is_tegra_debug_uartport_hs()) {
274                 debug_port_id = uart_console_debug_init(2);
275                 if (debug_port_id < 0)
276                         return;
277
278                 platform_device_register(uart_console_debug_device);
279         } else {
280                 tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
281                 platform_device_register(&tegra_uartc_device);
282         }
283
284 }
285
286 static struct resource tegra_rtc_resources[] = {
287         [0] = {
288                 .start = TEGRA_RTC_BASE,
289                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
290                 .flags = IORESOURCE_MEM,
291         },
292         [1] = {
293                 .start = INT_RTC,
294                 .end = INT_RTC,
295                 .flags = IORESOURCE_IRQ,
296         },
297 };
298
299 static struct platform_device tegra_rtc_device = {
300         .name = "tegra_rtc",
301         .id   = -1,
302         .resource = tegra_rtc_resources,
303         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
304 };
305
306 static struct tegra_pci_platform_data vcm30_t124_pcie_platform_data = {
307         .port_status[0] = 1,
308         .port_status[1] = 1,
309         .gpio_hot_plug  = TEGRA_GPIO_PO1,
310         .gpio_x1_slot   = PMU_TCA6416_GPIO(12),
311 };
312
313 static void vcm30_t124_pcie_init(void)
314 {
315 /* FIXME: Check this for VCM30_T124 */
316 #if 0
317         struct board_info board_info;
318         /* root port 1(x1 slot) is supported only on of ERS-S board */
319         laguna_pcie_platform_data.port_status[1] = 0;
320
321         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
322         platform_device_register(&tegra_pci_device);
323 #endif
324 }
325
326 #ifdef CONFIG_SATA_AHCI_TEGRA
327 static struct tegra_ahci_platform_data ahci_plat_data = {
328         .gen2_rx_eq = 7,
329 };
330
331 static void vcm30_t124_sata_init(void)
332 {
333         tegra_sata_device.dev.platform_data = &ahci_plat_data;
334         platform_device_register(&tegra_sata_device);
335 }
336 #else
337 static void vcm30_t124_sata_init(void) { }
338 #endif
339
340 static struct platform_device tegra_snd_vcm30t124 = {
341         .name = "tegra-snd-vcm30t124",
342         .id = 0,
343 };
344
345 /* FIXME: Check which devices are needed from the below list */
346 static struct platform_device *vcm30_t124_devices[] __initdata = {
347         &tegra_pmu_device,
348         &tegra_rtc_device,
349         &tegra_udc_device,
350 #if defined(CONFIG_TEGRA_AVP)
351         &tegra_avp_device,
352 #endif
353 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
354         &tegra12_se_device,
355 #endif
356         &tegra_snd_vcm30t124,
357 };
358
359 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
360         .port_otg = false,
361         .has_hostpc = true,
362         .unaligned_dma_buf_supported = true,
363         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
364         .op_mode = TEGRA_USB_OPMODE_HOST,
365         .u_data.host = {
366                 .vbus_gpio = -1,
367                 .hot_plug = false,
368                 .remote_wakeup_supported = false,
369                 .power_off_on_suspend = true,
370                 .turn_off_vbus_on_lp0 = true,
371         },
372         .u_cfg.utmi = {
373                 .hssync_start_delay = 0,
374                 .elastic_limit = 16,
375                 .idle_wait_delay = 17,
376                 .term_range_adj = 6,
377                 .xcvr_setup = 15,
378                 .xcvr_lsfslew = 2,
379                 .xcvr_lsrslew = 2,
380                 .xcvr_setup_offset = 0,
381                 .xcvr_use_fuses = 1,
382                 .vbus_oc_map = 0x4,
383         },
384 };
385
386 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
387         .port_otg = false,
388         .has_hostpc = true,
389         .unaligned_dma_buf_supported = true,
390         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
391         .op_mode = TEGRA_USB_OPMODE_HOST,
392         .u_data.host = {
393                 /* FIXME: Set this only for E1855. */
394                 .vbus_gpio = TEGRA_GPIO_PN5,
395                 .hot_plug = true,
396                 .remote_wakeup_supported = false,
397                 .power_off_on_suspend = true,
398                 .turn_off_vbus_on_lp0 = true,
399         },
400         .u_cfg.utmi = {
401                 .hssync_start_delay = 0,
402                 .elastic_limit = 16,
403                 .idle_wait_delay = 17,
404                 .term_range_adj = 6,
405                 .xcvr_setup = 8,
406                 .xcvr_lsfslew = 2,
407                 .xcvr_lsrslew = 2,
408                 .xcvr_setup_offset = 0,
409                 .xcvr_use_fuses = 1,
410                 .vbus_oc_map = 0x5,
411         },
412 };
413
414 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
415         .port_otg = false,
416         .has_hostpc = true,
417         .unaligned_dma_buf_supported = true,
418         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
419         .op_mode = TEGRA_USB_OPMODE_HOST,
420         .u_data.host = {
421                 .vbus_gpio = -1,
422                 .hot_plug = true,
423                 .remote_wakeup_supported = false,
424                 .power_off_on_suspend = true,
425                 .turn_off_vbus_on_lp0 = true,
426         },
427         .u_cfg.utmi = {
428         .hssync_start_delay = 0,
429                 .elastic_limit = 16,
430                 .idle_wait_delay = 17,
431                 .term_range_adj = 6,
432                 .xcvr_setup = 8,
433                 .xcvr_lsfslew = 2,
434                 .xcvr_lsrslew = 2,
435                 .xcvr_setup_offset = 0,
436                 .xcvr_use_fuses = 1,
437                 .vbus_oc_map = 0x5,
438         },
439 };
440
441 static struct tegra_usb_otg_data tegra_otg_pdata = {
442         .ehci_device = &tegra_ehci1_device,
443         .ehci_pdata = &tegra_ehci1_utmi_pdata,
444 };
445
446 static void vcm30_t124_usb_init(void)
447 {
448         int usb_port_owner_info = tegra_get_usb_port_owner_info();
449
450         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
451                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
452                 platform_device_register(&tegra_ehci2_device);
453         }
454
455         if (!(usb_port_owner_info & UTMI3_PORT_OWNER_XUSB)) {
456                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
457                 platform_device_register(&tegra_ehci3_device);
458         }
459 }
460
461 #ifdef CONFIG_USE_OF
462 struct of_dev_auxdata vcm30_t124_auxdata_lookup[] __initdata = {
463         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTA_BASE,
464                                 "serial-tegra.0", NULL),
465         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTB_BASE,
466                                 "serial-tegra.1", NULL),
467         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTD_BASE,
468                                 "serial-tegra.3", NULL),
469         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
470                 NULL),
471         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE, "gk20a.0", NULL),
472         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
473         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
474                 NULL),
475         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
476         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
477         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
478         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
479         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
480                                 NULL),
481         OF_DEV_AUXDATA("nvidia,tegra124-ahub", 0x70300000,
482                                 "tegra30-ahub-apbif", NULL),
483         T124_SPI_OF_DEV_AUXDATA,
484
485         {}
486 };
487 #endif
488
489 static void __init tegra_vcm30_t124_early_init(void)
490 {
491         tegra_clk_init_from_table(vcm30_t124_clk_init_table);
492         tegra_clk_verify_parents();
493         tegra_soc_device_init("vcm30t124");
494 }
495
496 static void __init tegra_vcm30_t124_late_init(void)
497 {
498         struct board_info board_info;
499         tegra_get_board_info(&board_info);
500         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
501                 board_info.board_id, board_info.sku,
502                 board_info.fab, board_info.major_revision,
503                 board_info.minor_revision);
504         platform_device_register(&tegra124_pinctrl_device);
505         vcm30_t124_pinmux_init();
506         vcm30_t124_usb_init();
507 /*      vcm30_t124_xusb_init(); */
508         vcm30_t124_nor_init();
509         vcm30_t124_i2c_init();
510         vcm30_t124_uart_init();
511         vcm30_t124_pca953x_init();
512         platform_add_devices(vcm30_t124_devices,
513                         ARRAY_SIZE(vcm30_t124_devices));
514         tegra_io_dpd_init();
515         vcm30_t124_sdhci_init();
516         vcm30_t124_regulator_init();
517         vcm30_t124_suspend_init();
518 #if 0
519         vcm30_t124_emc_init();
520         vcm30_t124_edp_init();
521 #endif
522         isomgr_init();
523         /* vcm30_t124_panel_init(); */
524         /* vcm30_t124_pmon_init(); */
525         vcm30_t124_pcie_init();
526         vcm30_t124_sata_init();
527 #ifdef CONFIG_TEGRA_WDT_RECOVERY
528         tegra_wdt_recovery_init();
529 #endif
530         /* FIXME: Required? */
531 #if 0
532         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
533
534         vcm30_t124_sensors_init();
535         vcm30_t124_soctherm_init();
536 #endif
537         tegra_register_fuse();
538         vcm30_t124_panel_init();
539 }
540
541 static void __init vcm30_t124_ramconsole_reserve(unsigned long size)
542 {
543         tegra_ram_console_debug_reserve(SZ_1M);
544 }
545
546 static void __init tegra_vcm30_t124_dt_init(void)
547 {
548         tegra_get_board_info(&board_info);
549         tegra_get_display_board_info(&display_board_info);
550
551         tegra_vcm30_t124_early_init();
552 #ifdef CONFIG_USE_OF
553         of_platform_populate(NULL,
554                 of_default_bus_match_table, vcm30_t124_auxdata_lookup,
555                 &platform_bus);
556 #endif
557
558         tegra_vcm30_t124_late_init();
559 }
560
561 static void __init tegra_vcm30_t124_reserve(void)
562 {
563 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
564         /* 1920*1200*4*2 = 18432000 bytes */
565         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
566 #else
567         tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
568 #endif
569         vcm30_t124_ramconsole_reserve(SZ_1M);
570 }
571
572 static const char * const vcm30_t124_dt_board_compat[] = {
573         "nvidia,vcm30t124",
574         NULL
575 };
576
577 DT_MACHINE_START(VCM30_T124, "vcm30t124")
578         .atag_offset    = 0x100,
579         .smp            = smp_ops(tegra_smp_ops),
580         .map_io         = tegra_map_common_io,
581         .reserve        = tegra_vcm30_t124_reserve,
582         .init_early     = tegra12x_init_early,
583         .init_irq       = irqchip_init,
584         .init_time      = clocksource_of_init,
585         .init_machine   = tegra_vcm30_t124_dt_init,
586         .restart        = tegra_assert_system_reset,
587         .dt_compat      = vcm30_t124_dt_board_compat,
588         .init_late      = tegra_init_late
589 MACHINE_END