arm: tegra: vcm3.0: t124: Add initial board files.
[linux-3.10.git] / arch / arm / mach-tegra / board-vcm30_t124.c
1 /*
2  * arch/arm/mach-tegra/board-vcm30_t124.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/platform_device.h>
20 #include <linux/i2c-tegra.h>
21 #include <linux/i2c.h>
22 #include <linux/platform_data/serial-tegra.h>
23 #include <linux/platform_data/tegra_usb.h>
24 #include <linux/spi/spi-tegra.h>
25 #include <linux/of_platform.h>
26
27 #include <mach/tegra_asoc_pdata.h>
28 #include <mach/pci.h>
29 #include <mach/iomap.h>
30 #include <mach/io_dpd.h>
31 #include <asm/mach/arch.h>
32 #include <mach/isomgr.h>
33 #include <asm/hardware/gic.h>
34
35 #include "board.h"
36 #include "clock.h"
37 #include "board-vcm30_t124.h"
38 #include "devices.h"
39 #include "board-common.h"
40 #include "common.h"
41
42 #include <asm/mach-types.h>
43
44 static struct board_info board_info, display_board_info;
45
46 static __initdata struct tegra_clk_init_table vcm30_t124_clk_init_table[] = {
47         /* name         parent          rate            enabled (always on)*/
48         { "pll_m",      NULL,           0,              false},
49         { "hda",        "pll_p",        108000000,      false},
50         { "hda2codec_2x", "pll_p",      48000000,       false},
51         { "pwm",        "pll_p",        3187500,        false},
52         { "i2s1",       "pll_a_out0",   0,              false},
53         { "i2s3",       "pll_a_out0",   0,              false},
54         { "i2s4",       "pll_a_out0",   0,              false},
55         { "spdif_out",  "pll_a_out0",   0,              false},
56         { "d_audio",    "clk_m",        12000000,       false},
57         { "dam0",       "clk_m",        12000000,       false},
58         { "dam1",       "clk_m",        12000000,       false},
59         { "dam2",       "clk_m",        12000000,       false},
60         { "audio1",     "i2s1_sync",    0,              false},
61         { "audio3",     "i2s3_sync",    0,              false},
62         { "vi_sensor",  "pll_p",        150000000,      false},
63         { "vi_sensor2", "pll_p",        150000000,      false},
64         { "cilab",      "pll_p",        150000000,      false},
65         { "cilcd",      "pll_p",        150000000,      false},
66         { "cile",       "pll_p",        150000000,      false},
67         { "i2c1",       "pll_p",        3200000,        false},
68         { "i2c2",       "pll_p",        3200000,        false},
69         { "i2c3",       "pll_p",        3200000,        false},
70         { "i2c4",       "pll_p",        3200000,        false},
71         { "i2c5",       "pll_p",        3200000,        false},
72         { "sbc1",       "pll_p",        25000000,       false},
73         { "sbc2",       "pll_p",        25000000,       false},
74         { "sbc3",       "pll_p",        25000000,       false},
75         { "sbc4",       "pll_p",        25000000,       false},
76         { "sbc5",       "pll_p",        25000000,       false},
77         { "sbc6",       "pll_p",        25000000,       false},
78         { "uarta",      "pll_p",        408000000,      false},
79         { "uartb",      "pll_p",        408000000,      false},
80         { "uartc",      "pll_p",        408000000,      false},
81         { "uartd",      "pll_p",        408000000,      false},
82         { NULL,         NULL,           0,              0},
83 };
84
85 static struct tegra_i2c_platform_data vcm30_t124_i2c1_platform_data = {
86         .bus_clk_rate   = 100000,
87         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
88         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
89 };
90
91 static struct tegra_i2c_platform_data vcm30_t124_i2c2_platform_data = {
92         .bus_clk_rate   = 100000,
93         .is_clkon_always = true,
94         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
95         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
96 };
97
98 static struct tegra_i2c_platform_data vcm30_t124_i2c3_platform_data = {
99         .bus_clk_rate   = 400000,
100         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
101         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
102 };
103
104 static struct tegra_i2c_platform_data vcm30_t124_i2c4_platform_data = {
105         .bus_clk_rate   = 10000,
106         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
107         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
108 };
109
110 static struct tegra_i2c_platform_data vcm30_t124_i2c5_platform_data = {
111         .bus_clk_rate   = 400000,
112         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
113         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
114 };
115
116 static void vcm30_t124_i2c_init(void)
117 {
118         struct board_info board_info;
119         tegra_get_board_info(&board_info);
120         /* T124 does not use device tree as of now */
121         tegra12_i2c_device1.dev.platform_data = &vcm30_t124_i2c1_platform_data;
122         tegra12_i2c_device2.dev.platform_data = &vcm30_t124_i2c2_platform_data;
123         tegra12_i2c_device3.dev.platform_data = &vcm30_t124_i2c3_platform_data;
124         tegra12_i2c_device4.dev.platform_data = &vcm30_t124_i2c4_platform_data;
125         tegra12_i2c_device5.dev.platform_data = &vcm30_t124_i2c5_platform_data;
126
127         platform_device_register(&tegra12_i2c_device5);
128         platform_device_register(&tegra12_i2c_device4);
129         platform_device_register(&tegra12_i2c_device3);
130         platform_device_register(&tegra12_i2c_device2);
131         platform_device_register(&tegra12_i2c_device1);
132 }
133
134 /* Register debug UART in old fashion and use DT for all others */
135 #ifndef CONFIG_USE_OF
136 static struct platform_device *vcm30_t124_uart_devices[] __initdata = {
137         &tegra_uarta_device,
138         &tegra_uartb_device,
139         &tegra_uartd_device,
140 };
141
142 static struct tegra_serial_platform_data vcm30_t124_uarta_pdata = {
143         .dma_req_selector = 8,
144         .modem_interrupt = false,
145 };
146
147 static struct tegra_serial_platform_data vcm30_t124_uartb_pdata = {
148         .dma_req_selector = 9,
149         .modem_interrupt = false,
150 };
151
152 static struct tegra_serial_platform_data vcm30_t124_uartd_pdata = {
153         .dma_req_selector = 19,
154         .modem_interrupt = false,
155 };
156 #endif
157
158 static struct tegra_serial_platform_data vcm30_t124_uartc_pdata = {
159         .dma_req_selector = 10,
160         .modem_interrupt = false,
161 };
162
163 static void __init vcm30_t124_uart_init(void)
164 {
165         int debug_port_id;
166
167 #ifndef CONFIG_USE_OF
168         tegra_uarta_device.dev.platform_data = &vcm30_t124_uarta_pdata;
169         tegra_uartb_device.dev.platform_data = &vcm30_t124_uartb_pdata;
170         tegra_uartd_device.dev.platform_data = &vcm30_t124_uartd_pdata;
171         platform_add_devices(vcm30_t124_uart_devices,
172                         ARRAY_SIZE(vcm30_t124_uart_devices));
173 #endif
174         tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
175         if (!is_tegra_debug_uartport_hs()) {
176                 debug_port_id = uart_console_debug_init(2);
177                 if (debug_port_id < 0)
178                         return;
179
180                 platform_device_register(uart_console_debug_device);
181         } else {
182                 tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
183                 platform_device_register(&tegra_uartc_device);
184         }
185
186 }
187
188 static struct resource tegra_rtc_resources[] = {
189         [0] = {
190                 .start = TEGRA_RTC_BASE,
191                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
192                 .flags = IORESOURCE_MEM,
193         },
194         [1] = {
195                 .start = INT_RTC,
196                 .end = INT_RTC,
197                 .flags = IORESOURCE_IRQ,
198         },
199 };
200
201 static struct platform_device tegra_rtc_device = {
202         .name = "tegra_rtc",
203         .id   = -1,
204         .resource = tegra_rtc_resources,
205         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
206 };
207
208 static struct tegra_pci_platform_data vcm30_t124_pcie_platform_data = {
209         .port_status[0] = 1,
210         .port_status[1] = 1,
211         .use_dock_detect        = 1,
212         .gpio   = TEGRA_GPIO_PO1,
213         .gpio_x1_slot   = PMU_TCA6416_GPIO(12),
214 };
215
216 static void vcm30_t124_pcie_init(void)
217 {
218 /* FIXME: Check this for VCM30_T124 */
219 #if 0
220         struct board_info board_info;
221         /* root port 1(x1 slot) is supported only on of ERS-S board */
222         laguna_pcie_platform_data.port_status[1] = 0;
223
224         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
225         platform_device_register(&tegra_pci_device);
226 #endif
227 }
228
229 /* FIXME: Check which devices are needed from the below list */
230 static struct platform_device *vcm30_t124_devices[] __initdata = {
231         &tegra_pmu_device,
232         &tegra_rtc_device,
233         &tegra_udc_device,
234 #if defined(CONFIG_TEGRA_AVP)
235         &tegra_avp_device,
236 #endif
237 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
238         &tegra12_se_device,
239 #endif
240         &tegra_ahub_device,
241         &tegra_dam_device0,
242         &tegra_dam_device1,
243         &tegra_dam_device2,
244         &tegra_i2s_device1,
245         &tegra_i2s_device3,
246         &tegra_i2s_device4,
247         &tegra_spdif_device,
248         &spdif_dit_device,
249         &bluetooth_dit_device,
250         &tegra_hda_device,
251 };
252
253 static struct tegra_usb_platform_data tegra_udc_pdata = {
254         .port_otg = true,
255         .has_hostpc = true,
256         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
257         .op_mode = TEGRA_USB_OPMODE_DEVICE,
258         .u_data.dev = {
259                 .vbus_pmu_irq = 0,
260                 .vbus_gpio = -1,
261                 .charging_supported = false,
262                 .remote_wakeup_supported = false,
263         },
264         .u_cfg.utmi = {
265                 .hssync_start_delay = 0,
266                 .elastic_limit = 16,
267                 .idle_wait_delay = 17,
268                 .term_range_adj = 6,
269                 .xcvr_setup = 8,
270                 .xcvr_lsfslew = 2,
271                 .xcvr_lsrslew = 2,
272                 .xcvr_setup_offset = 0,
273                 .xcvr_use_fuses = 1,
274         },
275 };
276
277 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
278         .port_otg = true,
279         .has_hostpc = true,
280         .unaligned_dma_buf_supported = true,
281         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
282         .op_mode = TEGRA_USB_OPMODE_HOST,
283         .u_data.host = {
284                 .vbus_gpio = -1,
285                 .hot_plug = false,
286                 .remote_wakeup_supported = true,
287                 .power_off_on_suspend = true,
288         },
289         .u_cfg.utmi = {
290                 .hssync_start_delay = 0,
291                 .elastic_limit = 16,
292                 .idle_wait_delay = 17,
293                 .term_range_adj = 6,
294                 .xcvr_setup = 15,
295                 .xcvr_lsfslew = 2,
296                 .xcvr_lsrslew = 2,
297                 .xcvr_setup_offset = 0,
298                 .xcvr_use_fuses = 1,
299                 .vbus_oc_map = 0x4,
300         },
301 };
302
303 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
304         .port_otg = false,
305         .has_hostpc = true,
306         .unaligned_dma_buf_supported = true,
307         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
308         .op_mode = TEGRA_USB_OPMODE_HOST,
309         .u_data.host = {
310                 /* FIXME: Set this only for E1855. */
311                 .vbus_gpio = TEGRA_GPIO_PN5,
312                 .hot_plug = false,
313                 .remote_wakeup_supported = true,
314                 .power_off_on_suspend = true,
315         },
316         .u_cfg.utmi = {
317                 .hssync_start_delay = 0,
318                 .elastic_limit = 16,
319                 .idle_wait_delay = 17,
320                 .term_range_adj = 6,
321                 .xcvr_setup = 8,
322                 .xcvr_lsfslew = 2,
323                 .xcvr_lsrslew = 2,
324                 .xcvr_setup_offset = 0,
325                 .xcvr_use_fuses = 1,
326                 .vbus_oc_map = 0x5,
327         },
328 };
329
330 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
331         .port_otg = false,
332         .has_hostpc = true,
333         .unaligned_dma_buf_supported = true,
334         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
335         .op_mode = TEGRA_USB_OPMODE_HOST,
336         .u_data.host = {
337                 .vbus_gpio = -1,
338                 .hot_plug = false,
339                 .remote_wakeup_supported = true,
340                 .power_off_on_suspend = true,
341         },
342         .u_cfg.utmi = {
343         .hssync_start_delay = 0,
344                 .elastic_limit = 16,
345                 .idle_wait_delay = 17,
346                 .term_range_adj = 6,
347                 .xcvr_setup = 8,
348                 .xcvr_lsfslew = 2,
349                 .xcvr_lsrslew = 2,
350                 .xcvr_setup_offset = 0,
351                 .xcvr_use_fuses = 1,
352                 .vbus_oc_map = 0x5,
353         },
354 };
355
356 static struct tegra_usb_otg_data tegra_otg_pdata = {
357         .ehci_device = &tegra_ehci1_device,
358         .ehci_pdata = &tegra_ehci1_utmi_pdata,
359 };
360
361 static void vcm30_t124_usb_init(void)
362 {
363         int usb_port_owner_info = tegra_get_usb_port_owner_info();
364
365         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
366                 tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
367                 platform_device_register(&tegra_otg_device);
368                 /* Setup the udc platform data */
369                 tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
370         }
371
372         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
373                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
374                 platform_device_register(&tegra_ehci2_device);
375         }
376
377         if (!(usb_port_owner_info & UTMI3_PORT_OWNER_XUSB)) {
378                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
379                 platform_device_register(&tegra_ehci3_device);
380         }
381 }
382
383 #ifndef CONFIG_USE_OF
384 static struct platform_device *vcm30_t124_spi_devices[] __initdata = {
385         &tegra11_spi_device1,
386         &tegra11_spi_device4,
387 };
388
389 static struct tegra_spi_platform_data vcm30_t124_spi1_pdata = {
390         .dma_req_sel            = 15,
391         .spi_max_frequency      = 25000000,
392         .clock_always_on        = false,
393 };
394
395 static struct tegra_spi_platform_data vcm30_t124_spi4_pdata = {
396         .dma_req_sel            = 18,
397         .spi_max_frequency      = 25000000,
398         .clock_always_on        = false,
399 };
400
401 static void __init vcm30_t124_spi_init(void)
402 {
403         tegra11_spi_device1.dev.platform_data = &vcm30_t124_spi1_pdata;
404         tegra11_spi_device4.dev.platform_data = &vcm30_t124_spi4_pdata;
405         platform_add_devices(vcm30_t124_spi_devices,
406                         ARRAY_SIZE(vcm30_t124_spi_devices));
407 }
408 #else
409 static void __init vcm30_t124_spi_init(void)
410 {
411 }
412 #endif
413
414 #ifdef CONFIG_USE_OF
415 struct of_dev_auxdata vcm30_t124_auxdata_lookup[] __initdata = {
416         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTA_BASE,
417                                 "serial-tegra.0", NULL),
418         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTB_BASE,
419                                 "serial-tegra.1", NULL),
420         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTD_BASE,
421                                 "serial-tegra.3", NULL),
422         {}
423 };
424 #endif
425
426 static void __init tegra_vcm30_t124_early_init(void)
427 {
428         tegra_clk_init_from_table(vcm30_t124_clk_init_table);
429         tegra_clk_verify_parents();
430         tegra_soc_device_init("vcm30_t124");
431 }
432
433 static void __init tegra_vcm30_t124_late_init(void)
434 {
435         struct board_info board_info;
436         tegra_get_board_info(&board_info);
437         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
438                 board_info.board_id, board_info.sku,
439                 board_info.fab, board_info.major_revision,
440                 board_info.minor_revision);
441         platform_device_register(&tegra_pinmux_device);
442         vcm30_t124_pinmux_init();
443         vcm30_t124_usb_init();
444 /*      vcm30_t124_xusb_init(); */
445         vcm30_t124_i2c_init();
446         vcm30_t124_spi_init();
447         vcm30_t124_uart_init();
448         platform_add_devices(vcm30_t124_devices,
449                         ARRAY_SIZE(vcm30_t124_devices));
450         tegra_ram_console_debug_init();
451         tegra_io_dpd_init();
452         /* vcm30_t124_sdhci_init(); */
453         vcm30_t124_regulator_init();
454         /* vcm30_t124_suspend_init(); */
455 #if 0
456         vcm30_t124_emc_init();
457         vcm30_t124_edp_init();
458 #endif
459         isomgr_init();
460         /* vcm30_t124_panel_init(); */
461         /* vcm30_t124_pmon_init(); */
462         tegra_release_bootloader_fb();
463         vcm30_t124_pcie_init();
464 #ifdef CONFIG_TEGRA_WDT_RECOVERY
465         tegra_wdt_recovery_init();
466 #endif
467         /* FIXME: Required? */
468 #if 0
469         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
470
471         vcm30_t124_sensors_init();
472         vcm30_t124_soctherm_init();
473 #endif
474         tegra_register_fuse();
475 }
476
477 static void __init vcm30_t124_ramconsole_reserve(unsigned long size)
478 {
479         tegra_ram_console_debug_reserve(SZ_1M);
480 }
481
482 static void __init tegra_vcm30_t124_dt_init(void)
483 {
484         tegra_get_board_info(&board_info);
485         tegra_get_display_board_info(&display_board_info);
486
487         tegra_vcm30_t124_early_init();
488 #ifdef CONFIG_USE_OF
489         of_platform_populate(NULL,
490                 of_default_bus_match_table, vcm30_t124_auxdata_lookup,
491                 &platform_bus);
492 #endif
493
494         tegra_vcm30_t124_late_init();
495 }
496
497 static void __init tegra_vcm30_t124_reserve(void)
498 {
499 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
500         /* 1920*1200*4*2 = 18432000 bytes */
501         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
502 #else
503         tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
504 #endif
505         vcm30_t124_ramconsole_reserve(SZ_1M);
506 }
507
508 static const char * const vcm30_t124_dt_board_compat[] = {
509         "nvidia,vcm30_t124",
510         NULL
511 };
512
513 DT_MACHINE_START(VCM30_T124, "vcm30_t124")
514         .atag_offset    = 0x100,
515         .smp            = smp_ops(tegra_smp_ops),
516         .map_io         = tegra_map_common_io,
517         .reserve        = tegra_vcm30_t124_reserve,
518         .init_early     = tegra12x_init_early,
519         .init_irq       = tegra_dt_init_irq,
520         .handle_irq     = gic_handle_irq,
521         .timer          = &tegra_sys_timer,
522         .init_machine   = tegra_vcm30_t124_dt_init,
523         .restart        = tegra_assert_system_reset,
524         .dt_compat      = vcm30_t124_dt_board_compat,
525 MACHINE_END