arm: tegra: vcm3.0: t124: Add panel file
[linux-3.10.git] / arch / arm / mach-tegra / board-vcm30_t124.c
1 /*
2  * arch/arm/mach-tegra/board-vcm30_t124.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/platform_device.h>
20 #include <linux/i2c-tegra.h>
21 #include <linux/i2c.h>
22 #include <linux/platform_data/serial-tegra.h>
23 #include <linux/platform_data/tegra_usb.h>
24 #include <linux/platform_data/tegra_nor.h>
25 #include <linux/platform_data/tegra_ahci.h>
26 #include <linux/spi/spi-tegra.h>
27 #include <linux/of_platform.h>
28 #include <linux/kernel.h>
29 #include <linux/clocksource.h>
30
31 #include <mach/tegra_asoc_pdata.h>
32 #include <mach/pci.h>
33 #include <mach/io_dpd.h>
34 #include <asm/mach/arch.h>
35 #include <mach/isomgr.h>
36
37 #include "iomap.h"
38 #include "board.h"
39 #include "clock.h"
40 #include "board-vcm30_t124.h"
41 #include "devices.h"
42 #include "board-common.h"
43 #include "common.h"
44
45 #include <asm/mach-types.h>
46
47 static struct board_info board_info, display_board_info;
48
49 static __initdata struct tegra_clk_init_table vcm30_t124_clk_init_table[] = {
50         /* name         parent          rate            enabled (always on)*/
51         { "pll_m",      NULL,           0,              false},
52         { "hda",        "pll_p",        108000000,      false},
53         { "hda2codec_2x", "pll_p",      48000000,       false},
54         { "pwm",        "pll_p",        3187500,        false},
55         { "i2s1",       "pll_a_out0",   0,              false},
56         { "i2s3",       "pll_a_out0",   0,              false},
57         { "i2s4",       "pll_a_out0",   0,              false},
58         { "spdif_out",  "pll_a_out0",   0,              false},
59         { "d_audio",    "clk_m",        12000000,       false},
60         { "dam0",       "clk_m",        12000000,       false},
61         { "dam1",       "clk_m",        12000000,       false},
62         { "dam2",       "clk_m",        12000000,       false},
63         { "audio1",     "i2s1_sync",    0,              false},
64         { "audio3",     "i2s3_sync",    0,              false},
65         { "vi_sensor",  "pll_p",        150000000,      false},
66         { "vi_sensor2", "pll_p",        150000000,      false},
67         { "cilab",      "pll_p",        150000000,      false},
68         { "cilcd",      "pll_p",        150000000,      false},
69         { "cile",       "pll_p",        150000000,      false},
70         { "i2c1",       "pll_p",        3200000,        false},
71         { "i2c2",       "pll_p",        3200000,        false},
72         { "i2c3",       "pll_p",        3200000,        false},
73         { "i2c4",       "pll_p",        3200000,        false},
74         { "i2c5",       "pll_p",        3200000,        false},
75         { "sbc1",       "pll_p",        25000000,       false},
76         { "sbc2",       "pll_p",        25000000,       false},
77         { "sbc3",       "pll_p",        25000000,       false},
78         { "sbc4",       "pll_p",        25000000,       false},
79         { "sbc5",       "pll_p",        25000000,       false},
80         { "sbc6",       "pll_p",        25000000,       false},
81         { "uarta",      "pll_p",        408000000,      false},
82         { "uartb",      "pll_p",        408000000,      false},
83         { "uartc",      "pll_p",        408000000,      false},
84         { "uartd",      "pll_p",        408000000,      false},
85         { "nor",        "pll_p",        102000000,      true},
86         { NULL,         NULL,           0,              0},
87 };
88
89 static struct tegra_i2c_platform_data vcm30_t124_i2c1_platform_data = {
90         .bus_clk_rate   = 100000,
91         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
92         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
93 };
94
95 static struct tegra_i2c_platform_data vcm30_t124_i2c2_platform_data = {
96         .bus_clk_rate   = 100000,
97         .is_clkon_always = true,
98         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
99         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
100 };
101
102 static struct tegra_i2c_platform_data vcm30_t124_i2c3_platform_data = {
103         .bus_clk_rate   = 400000,
104         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
105         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
106 };
107
108 static struct tegra_i2c_platform_data vcm30_t124_i2c4_platform_data = {
109         .bus_clk_rate   = 10000,
110         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
111         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
112 };
113
114 static struct tegra_i2c_platform_data vcm30_t124_i2c5_platform_data = {
115         .bus_clk_rate   = 400000,
116         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
117         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
118 };
119
120 static struct tegra_nor_platform_data vcm30_t124_nor_data = {
121         .flash = {
122                 .map_name = "cfi_probe",
123                 .width = 2,
124         },
125         .chip_parms = {
126                 .MuxMode = NorMuxMode_ADNonMux,
127                 .ReadMode = NorReadMode_Page,
128                 .PageLength = NorPageLength_8Word,
129                 .ReadyActive = NorReadyActive_WithData,
130                 /* FIXME: Need to use characterized value */
131                 .timing_default = {
132                         .timing0 = 0x30300273,
133                         .timing1 = 0x00030302,
134                 },
135                 .timing_read = {
136                         .timing0 = 0x30300273,
137                         .timing1 = 0x00030302,
138                 },
139         },
140 };
141
142 static struct cs_info vcm30_t124_cs_info[] = {
143         {
144                 .cs = CS_0,
145                 .num_cs_gpio = 0,
146                 .virt = IO_ADDRESS(TEGRA_NOR_FLASH_BASE),
147                 .size = SZ_64M,
148                 .phys = TEGRA_NOR_FLASH_BASE,
149         },
150 };
151
152 static void vcm30_t124_nor_init(void)
153 {
154         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
155
156         vcm30_t124_nor_data.info.cs = kzalloc(sizeof(struct cs_info) *
157                                         ARRAY_SIZE(vcm30_t124_cs_info),
158                                         GFP_KERNEL);
159         if (!vcm30_t124_nor_data.info.cs)
160                 BUG();
161
162         vcm30_t124_nor_data.info.num_chips = ARRAY_SIZE(vcm30_t124_cs_info);
163
164         memcpy(vcm30_t124_nor_data.info.cs, vcm30_t124_cs_info,
165                                 sizeof(struct cs_info) * ARRAY_SIZE(vcm30_t124_cs_info));
166
167         tegra_nor_device.dev.platform_data = &vcm30_t124_nor_data;
168         platform_device_register(&tegra_nor_device);
169 }
170
171
172 static void vcm30_t124_i2c_init(void)
173 {
174         struct board_info board_info;
175         tegra_get_board_info(&board_info);
176         /* T124 does not use device tree as of now */
177         tegra12_i2c_device1.dev.platform_data = &vcm30_t124_i2c1_platform_data;
178         tegra12_i2c_device2.dev.platform_data = &vcm30_t124_i2c2_platform_data;
179         tegra12_i2c_device3.dev.platform_data = &vcm30_t124_i2c3_platform_data;
180         tegra12_i2c_device4.dev.platform_data = &vcm30_t124_i2c4_platform_data;
181         tegra12_i2c_device5.dev.platform_data = &vcm30_t124_i2c5_platform_data;
182
183         platform_device_register(&tegra12_i2c_device5);
184         platform_device_register(&tegra12_i2c_device4);
185         platform_device_register(&tegra12_i2c_device3);
186         platform_device_register(&tegra12_i2c_device2);
187         platform_device_register(&tegra12_i2c_device1);
188 }
189
190 /* Register debug UART in old fashion and use DT for all others */
191 #ifndef CONFIG_USE_OF
192 static struct platform_device *vcm30_t124_uart_devices[] __initdata = {
193         &tegra_uarta_device,
194         &tegra_uartb_device,
195         &tegra_uartd_device,
196 };
197
198 static struct tegra_serial_platform_data vcm30_t124_uarta_pdata = {
199         .dma_req_selector = 8,
200         .modem_interrupt = false,
201 };
202
203 static struct tegra_serial_platform_data vcm30_t124_uartb_pdata = {
204         .dma_req_selector = 9,
205         .modem_interrupt = false,
206 };
207
208 static struct tegra_serial_platform_data vcm30_t124_uartd_pdata = {
209         .dma_req_selector = 19,
210         .modem_interrupt = false,
211 };
212 #endif
213
214 static struct tegra_serial_platform_data vcm30_t124_uartc_pdata = {
215         .dma_req_selector = 10,
216         .modem_interrupt = false,
217 };
218
219 static void __init vcm30_t124_uart_init(void)
220 {
221         int debug_port_id;
222
223 #ifndef CONFIG_USE_OF
224         tegra_uarta_device.dev.platform_data = &vcm30_t124_uarta_pdata;
225         tegra_uartb_device.dev.platform_data = &vcm30_t124_uartb_pdata;
226         tegra_uartd_device.dev.platform_data = &vcm30_t124_uartd_pdata;
227         platform_add_devices(vcm30_t124_uart_devices,
228                         ARRAY_SIZE(vcm30_t124_uart_devices));
229 #endif
230         tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
231         if (!is_tegra_debug_uartport_hs()) {
232                 debug_port_id = uart_console_debug_init(2);
233                 if (debug_port_id < 0)
234                         return;
235
236                 platform_device_register(uart_console_debug_device);
237         } else {
238                 tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
239                 platform_device_register(&tegra_uartc_device);
240         }
241
242 }
243
244 static struct resource tegra_rtc_resources[] = {
245         [0] = {
246                 .start = TEGRA_RTC_BASE,
247                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
248                 .flags = IORESOURCE_MEM,
249         },
250         [1] = {
251                 .start = INT_RTC,
252                 .end = INT_RTC,
253                 .flags = IORESOURCE_IRQ,
254         },
255 };
256
257 static struct platform_device tegra_rtc_device = {
258         .name = "tegra_rtc",
259         .id   = -1,
260         .resource = tegra_rtc_resources,
261         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
262 };
263
264 static struct tegra_pci_platform_data vcm30_t124_pcie_platform_data = {
265         .port_status[0] = 1,
266         .port_status[1] = 1,
267         .use_dock_detect        = 1,
268         .gpio   = TEGRA_GPIO_PO1,
269         .gpio_x1_slot   = PMU_TCA6416_GPIO(12),
270 };
271
272 static void vcm30_t124_pcie_init(void)
273 {
274 /* FIXME: Check this for VCM30_T124 */
275 #if 0
276         struct board_info board_info;
277         /* root port 1(x1 slot) is supported only on of ERS-S board */
278         laguna_pcie_platform_data.port_status[1] = 0;
279
280         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
281         platform_device_register(&tegra_pci_device);
282 #endif
283 }
284
285 #ifdef CONFIG_SATA_AHCI_TEGRA
286 static struct tegra_ahci_platform_data ahci_plat_data = {
287         .gen2_rx_eq = 7,
288 };
289
290 static void vcm30_t124_sata_init(void)
291 {
292         tegra_sata_device.dev.platform_data = &ahci_plat_data;
293         platform_device_register(&tegra_sata_device);
294 }
295 #else
296 static void vcm30_t124_sata_init(void) { }
297 #endif
298
299 /* FIXME: Check which devices are needed from the below list */
300 static struct platform_device *vcm30_t124_devices[] __initdata = {
301         &tegra_pmu_device,
302         &tegra_rtc_device,
303         &tegra_udc_device,
304 #if defined(CONFIG_TEGRA_AVP)
305         &tegra_avp_device,
306 #endif
307 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
308         &tegra12_se_device,
309 #endif
310         &tegra_ahub_device,
311         &tegra_dam_device0,
312         &tegra_dam_device1,
313         &tegra_dam_device2,
314         &tegra_i2s_device1,
315         &tegra_i2s_device3,
316         &tegra_i2s_device4,
317         &tegra_spdif_device,
318         &spdif_dit_device,
319         &bluetooth_dit_device,
320         &tegra_hda_device,
321 };
322
323 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
324         .port_otg = false,
325         .has_hostpc = true,
326         .unaligned_dma_buf_supported = true,
327         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
328         .op_mode = TEGRA_USB_OPMODE_HOST,
329         .u_data.host = {
330                 .vbus_gpio = -1,
331                 .hot_plug = false,
332                 .remote_wakeup_supported = false,
333                 .power_off_on_suspend = true,
334                 .turn_off_vbus_on_lp0 = true,
335         },
336         .u_cfg.utmi = {
337                 .hssync_start_delay = 0,
338                 .elastic_limit = 16,
339                 .idle_wait_delay = 17,
340                 .term_range_adj = 6,
341                 .xcvr_setup = 15,
342                 .xcvr_lsfslew = 2,
343                 .xcvr_lsrslew = 2,
344                 .xcvr_setup_offset = 0,
345                 .xcvr_use_fuses = 1,
346                 .vbus_oc_map = 0x4,
347         },
348 };
349
350 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
351         .port_otg = false,
352         .has_hostpc = true,
353         .unaligned_dma_buf_supported = true,
354         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
355         .op_mode = TEGRA_USB_OPMODE_HOST,
356         .u_data.host = {
357                 /* FIXME: Set this only for E1855. */
358                 .vbus_gpio = TEGRA_GPIO_PN5,
359                 .hot_plug = false,
360                 .remote_wakeup_supported = false,
361                 .power_off_on_suspend = true,
362                 .turn_off_vbus_on_lp0 = true,
363         },
364         .u_cfg.utmi = {
365                 .hssync_start_delay = 0,
366                 .elastic_limit = 16,
367                 .idle_wait_delay = 17,
368                 .term_range_adj = 6,
369                 .xcvr_setup = 8,
370                 .xcvr_lsfslew = 2,
371                 .xcvr_lsrslew = 2,
372                 .xcvr_setup_offset = 0,
373                 .xcvr_use_fuses = 1,
374                 .vbus_oc_map = 0x5,
375         },
376 };
377
378 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
379         .port_otg = false,
380         .has_hostpc = true,
381         .unaligned_dma_buf_supported = true,
382         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
383         .op_mode = TEGRA_USB_OPMODE_HOST,
384         .u_data.host = {
385                 .vbus_gpio = -1,
386                 .hot_plug = false,
387                 .remote_wakeup_supported = false,
388                 .power_off_on_suspend = true,
389                 .turn_off_vbus_on_lp0 = true,
390         },
391         .u_cfg.utmi = {
392         .hssync_start_delay = 0,
393                 .elastic_limit = 16,
394                 .idle_wait_delay = 17,
395                 .term_range_adj = 6,
396                 .xcvr_setup = 8,
397                 .xcvr_lsfslew = 2,
398                 .xcvr_lsrslew = 2,
399                 .xcvr_setup_offset = 0,
400                 .xcvr_use_fuses = 1,
401                 .vbus_oc_map = 0x5,
402         },
403 };
404
405 static struct tegra_usb_otg_data tegra_otg_pdata = {
406         .ehci_device = &tegra_ehci1_device,
407         .ehci_pdata = &tegra_ehci1_utmi_pdata,
408 };
409
410 static void vcm30_t124_usb_init(void)
411 {
412         int usb_port_owner_info = tegra_get_usb_port_owner_info();
413
414         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
415                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
416                 platform_device_register(&tegra_ehci2_device);
417         }
418
419         if (!(usb_port_owner_info & UTMI3_PORT_OWNER_XUSB)) {
420                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
421                 platform_device_register(&tegra_ehci3_device);
422         }
423 }
424
425 #ifndef CONFIG_USE_OF
426 static struct platform_device *vcm30_t124_spi_devices[] __initdata = {
427         &tegra11_spi_device1,
428         &tegra11_spi_device4,
429 };
430
431 static struct tegra_spi_platform_data vcm30_t124_spi1_pdata = {
432         .dma_req_sel            = 15,
433         .spi_max_frequency      = 25000000,
434         .clock_always_on        = false,
435 };
436
437 static struct tegra_spi_platform_data vcm30_t124_spi4_pdata = {
438         .dma_req_sel            = 18,
439         .spi_max_frequency      = 25000000,
440         .clock_always_on        = false,
441 };
442
443 static void __init vcm30_t124_spi_init(void)
444 {
445         tegra11_spi_device1.dev.platform_data = &vcm30_t124_spi1_pdata;
446         tegra11_spi_device4.dev.platform_data = &vcm30_t124_spi4_pdata;
447         platform_add_devices(vcm30_t124_spi_devices,
448                         ARRAY_SIZE(vcm30_t124_spi_devices));
449 }
450 #else
451 static void __init vcm30_t124_spi_init(void)
452 {
453 }
454 #endif
455
456 #ifdef CONFIG_USE_OF
457 struct of_dev_auxdata vcm30_t124_auxdata_lookup[] __initdata = {
458         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTA_BASE,
459                                 "serial-tegra.0", NULL),
460         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTB_BASE,
461                                 "serial-tegra.1", NULL),
462         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTD_BASE,
463                                 "serial-tegra.3", NULL),
464         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
465                 NULL),
466         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", 0x538F0000, "gk20a", NULL),
467         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03", NULL),
468         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
469                 NULL),
470         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
471         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp", NULL),
472         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
473         {}
474 };
475 #endif
476
477 static void __init tegra_vcm30_t124_early_init(void)
478 {
479         tegra_clk_init_from_table(vcm30_t124_clk_init_table);
480         tegra_clk_verify_parents();
481         tegra_soc_device_init("vcm30_t124");
482 }
483
484 static void __init tegra_vcm30_t124_late_init(void)
485 {
486         struct board_info board_info;
487         tegra_get_board_info(&board_info);
488         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
489                 board_info.board_id, board_info.sku,
490                 board_info.fab, board_info.major_revision,
491                 board_info.minor_revision);
492         platform_device_register(&tegra_pinmux_device);
493         vcm30_t124_pinmux_init();
494         vcm30_t124_usb_init();
495 /*      vcm30_t124_xusb_init(); */
496         vcm30_t124_nor_init();
497         vcm30_t124_i2c_init();
498         vcm30_t124_spi_init();
499         vcm30_t124_uart_init();
500         platform_add_devices(vcm30_t124_devices,
501                         ARRAY_SIZE(vcm30_t124_devices));
502         tegra_io_dpd_init();
503         vcm30_t124_sdhci_init();
504         vcm30_t124_regulator_init();
505         vcm30_t124_suspend_init();
506 #if 0
507         vcm30_t124_emc_init();
508         vcm30_t124_edp_init();
509 #endif
510         isomgr_init();
511         /* vcm30_t124_panel_init(); */
512         /* vcm30_t124_pmon_init(); */
513         vcm30_t124_pcie_init();
514         vcm30_t124_sata_init();
515 #ifdef CONFIG_TEGRA_WDT_RECOVERY
516         tegra_wdt_recovery_init();
517 #endif
518         /* FIXME: Required? */
519 #if 0
520         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
521
522         vcm30_t124_sensors_init();
523         vcm30_t124_soctherm_init();
524 #endif
525         tegra_register_fuse();
526         vcm30_t124_panel_init();
527 }
528
529 static void __init vcm30_t124_ramconsole_reserve(unsigned long size)
530 {
531         tegra_ram_console_debug_reserve(SZ_1M);
532 }
533
534 static void __init tegra_vcm30_t124_dt_init(void)
535 {
536         tegra_get_board_info(&board_info);
537         tegra_get_display_board_info(&display_board_info);
538
539         tegra_vcm30_t124_early_init();
540 #ifdef CONFIG_USE_OF
541         of_platform_populate(NULL,
542                 of_default_bus_match_table, vcm30_t124_auxdata_lookup,
543                 &platform_bus);
544 #endif
545
546         tegra_vcm30_t124_late_init();
547 }
548
549 static void __init tegra_vcm30_t124_reserve(void)
550 {
551 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
552         /* 1920*1200*4*2 = 18432000 bytes */
553         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
554 #else
555         tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
556 #endif
557         vcm30_t124_ramconsole_reserve(SZ_1M);
558 }
559
560 static const char * const vcm30_t124_dt_board_compat[] = {
561         "nvidia,vcm30_t124",
562         NULL
563 };
564
565 DT_MACHINE_START(VCM30_T124, "vcm30_t124")
566         .atag_offset    = 0x100,
567         .smp            = smp_ops(tegra_smp_ops),
568         .map_io         = tegra_map_common_io,
569         .reserve        = tegra_vcm30_t124_reserve,
570         .init_early     = tegra12x_init_early,
571         .init_irq       = tegra_dt_init_irq,
572         .init_time      = clocksource_of_init,
573         .init_machine   = tegra_vcm30_t124_dt_init,
574         .restart        = tegra_assert_system_reset,
575         .dt_compat      = vcm30_t124_dt_board_compat,
576         .init_late      = tegra_init_late
577 MACHINE_END