ARM: vcm30-t124: Add suspend support
[linux-3.10.git] / arch / arm / mach-tegra / board-vcm30_t124.c
1 /*
2  * arch/arm/mach-tegra/board-vcm30_t124.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/platform_device.h>
20 #include <linux/i2c-tegra.h>
21 #include <linux/i2c.h>
22 #include <linux/platform_data/serial-tegra.h>
23 #include <linux/platform_data/tegra_usb.h>
24 #include <linux/platform_data/tegra_nor.h>
25 #include <linux/platform_data/tegra_ahci.h>
26 #include <linux/spi/spi-tegra.h>
27 #include <linux/of_platform.h>
28 #include <linux/kernel.h>
29
30 #include <mach/tegra_asoc_pdata.h>
31 #include <mach/pci.h>
32 #include <mach/io_dpd.h>
33 #include <asm/mach/arch.h>
34 #include <mach/isomgr.h>
35
36 #include "iomap.h"
37 #include "board.h"
38 #include "clock.h"
39 #include "board-vcm30_t124.h"
40 #include "devices.h"
41 #include "board-common.h"
42 #include "common.h"
43
44 #include <asm/mach-types.h>
45
46 static struct board_info board_info, display_board_info;
47
48 static __initdata struct tegra_clk_init_table vcm30_t124_clk_init_table[] = {
49         /* name         parent          rate            enabled (always on)*/
50         { "pll_m",      NULL,           0,              false},
51         { "hda",        "pll_p",        108000000,      false},
52         { "hda2codec_2x", "pll_p",      48000000,       false},
53         { "pwm",        "pll_p",        3187500,        false},
54         { "i2s1",       "pll_a_out0",   0,              false},
55         { "i2s3",       "pll_a_out0",   0,              false},
56         { "i2s4",       "pll_a_out0",   0,              false},
57         { "spdif_out",  "pll_a_out0",   0,              false},
58         { "d_audio",    "clk_m",        12000000,       false},
59         { "dam0",       "clk_m",        12000000,       false},
60         { "dam1",       "clk_m",        12000000,       false},
61         { "dam2",       "clk_m",        12000000,       false},
62         { "audio1",     "i2s1_sync",    0,              false},
63         { "audio3",     "i2s3_sync",    0,              false},
64         { "vi_sensor",  "pll_p",        150000000,      false},
65         { "vi_sensor2", "pll_p",        150000000,      false},
66         { "cilab",      "pll_p",        150000000,      false},
67         { "cilcd",      "pll_p",        150000000,      false},
68         { "cile",       "pll_p",        150000000,      false},
69         { "i2c1",       "pll_p",        3200000,        false},
70         { "i2c2",       "pll_p",        3200000,        false},
71         { "i2c3",       "pll_p",        3200000,        false},
72         { "i2c4",       "pll_p",        3200000,        false},
73         { "i2c5",       "pll_p",        3200000,        false},
74         { "sbc1",       "pll_p",        25000000,       false},
75         { "sbc2",       "pll_p",        25000000,       false},
76         { "sbc3",       "pll_p",        25000000,       false},
77         { "sbc4",       "pll_p",        25000000,       false},
78         { "sbc5",       "pll_p",        25000000,       false},
79         { "sbc6",       "pll_p",        25000000,       false},
80         { "uarta",      "pll_p",        408000000,      false},
81         { "uartb",      "pll_p",        408000000,      false},
82         { "uartc",      "pll_p",        408000000,      false},
83         { "uartd",      "pll_p",        408000000,      false},
84         { "nor",        "pll_p",        102000000,      true},
85         { NULL,         NULL,           0,              0},
86 };
87
88 static struct tegra_i2c_platform_data vcm30_t124_i2c1_platform_data = {
89         .bus_clk_rate   = 100000,
90         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
91         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
92 };
93
94 static struct tegra_i2c_platform_data vcm30_t124_i2c2_platform_data = {
95         .bus_clk_rate   = 100000,
96         .is_clkon_always = true,
97         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
98         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
99 };
100
101 static struct tegra_i2c_platform_data vcm30_t124_i2c3_platform_data = {
102         .bus_clk_rate   = 400000,
103         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
104         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
105 };
106
107 static struct tegra_i2c_platform_data vcm30_t124_i2c4_platform_data = {
108         .bus_clk_rate   = 10000,
109         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
110         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
111 };
112
113 static struct tegra_i2c_platform_data vcm30_t124_i2c5_platform_data = {
114         .bus_clk_rate   = 400000,
115         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
116         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
117 };
118
119 static struct tegra_nor_platform_data vcm30_t124_nor_data = {
120         .flash = {
121                 .map_name = "cfi_probe",
122                 .width = 2,
123         },
124         .chip_parms = {
125                 .MuxMode = NorMuxMode_ADNonMux,
126                 .ReadMode = NorReadMode_Page,
127                 .PageLength = NorPageLength_8Word,
128                 .ReadyActive = NorReadyActive_WithData,
129                 /* FIXME: Need to use characterized value */
130                 .timing_default = {
131                         .timing0 = 0x30300273,
132                         .timing1 = 0x00030302,
133                 },
134                 .timing_read = {
135                         .timing0 = 0x30300273,
136                         .timing1 = 0x00030302,
137                 },
138         },
139 };
140
141 static struct cs_info vcm30_t124_cs_info[] = {
142         {
143                 .cs = CS_0,
144                 .num_cs_gpio = 0,
145                 .virt = IO_ADDRESS(TEGRA_NOR_FLASH_BASE),
146                 .size = SZ_64M,
147                 .phys = TEGRA_NOR_FLASH_BASE,
148         },
149 };
150
151 static void vcm30_t124_nor_init(void)
152 {
153         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
154
155         vcm30_t124_nor_data.info.cs = kzalloc(sizeof(struct cs_info) *
156                                         ARRAY_SIZE(vcm30_t124_cs_info),
157                                         GFP_KERNEL);
158         if (!vcm30_t124_nor_data.info.cs)
159                 BUG();
160
161         vcm30_t124_nor_data.info.num_chips = ARRAY_SIZE(vcm30_t124_cs_info);
162
163         memcpy(vcm30_t124_nor_data.info.cs, vcm30_t124_cs_info,
164                                 sizeof(struct cs_info) * ARRAY_SIZE(vcm30_t124_cs_info));
165
166         tegra_nor_device.dev.platform_data = &vcm30_t124_nor_data;
167         platform_device_register(&tegra_nor_device);
168 }
169
170
171 static void vcm30_t124_i2c_init(void)
172 {
173         struct board_info board_info;
174         tegra_get_board_info(&board_info);
175         /* T124 does not use device tree as of now */
176         tegra12_i2c_device1.dev.platform_data = &vcm30_t124_i2c1_platform_data;
177         tegra12_i2c_device2.dev.platform_data = &vcm30_t124_i2c2_platform_data;
178         tegra12_i2c_device3.dev.platform_data = &vcm30_t124_i2c3_platform_data;
179         tegra12_i2c_device4.dev.platform_data = &vcm30_t124_i2c4_platform_data;
180         tegra12_i2c_device5.dev.platform_data = &vcm30_t124_i2c5_platform_data;
181
182         platform_device_register(&tegra12_i2c_device5);
183         platform_device_register(&tegra12_i2c_device4);
184         platform_device_register(&tegra12_i2c_device3);
185         platform_device_register(&tegra12_i2c_device2);
186         platform_device_register(&tegra12_i2c_device1);
187 }
188
189 /* Register debug UART in old fashion and use DT for all others */
190 #ifndef CONFIG_USE_OF
191 static struct platform_device *vcm30_t124_uart_devices[] __initdata = {
192         &tegra_uarta_device,
193         &tegra_uartb_device,
194         &tegra_uartd_device,
195 };
196
197 static struct tegra_serial_platform_data vcm30_t124_uarta_pdata = {
198         .dma_req_selector = 8,
199         .modem_interrupt = false,
200 };
201
202 static struct tegra_serial_platform_data vcm30_t124_uartb_pdata = {
203         .dma_req_selector = 9,
204         .modem_interrupt = false,
205 };
206
207 static struct tegra_serial_platform_data vcm30_t124_uartd_pdata = {
208         .dma_req_selector = 19,
209         .modem_interrupt = false,
210 };
211 #endif
212
213 static struct tegra_serial_platform_data vcm30_t124_uartc_pdata = {
214         .dma_req_selector = 10,
215         .modem_interrupt = false,
216 };
217
218 static void __init vcm30_t124_uart_init(void)
219 {
220         int debug_port_id;
221
222 #ifndef CONFIG_USE_OF
223         tegra_uarta_device.dev.platform_data = &vcm30_t124_uarta_pdata;
224         tegra_uartb_device.dev.platform_data = &vcm30_t124_uartb_pdata;
225         tegra_uartd_device.dev.platform_data = &vcm30_t124_uartd_pdata;
226         platform_add_devices(vcm30_t124_uart_devices,
227                         ARRAY_SIZE(vcm30_t124_uart_devices));
228 #endif
229         tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
230         if (!is_tegra_debug_uartport_hs()) {
231                 debug_port_id = uart_console_debug_init(2);
232                 if (debug_port_id < 0)
233                         return;
234
235                 platform_device_register(uart_console_debug_device);
236         } else {
237                 tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
238                 platform_device_register(&tegra_uartc_device);
239         }
240
241 }
242
243 static struct resource tegra_rtc_resources[] = {
244         [0] = {
245                 .start = TEGRA_RTC_BASE,
246                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
247                 .flags = IORESOURCE_MEM,
248         },
249         [1] = {
250                 .start = INT_RTC,
251                 .end = INT_RTC,
252                 .flags = IORESOURCE_IRQ,
253         },
254 };
255
256 static struct platform_device tegra_rtc_device = {
257         .name = "tegra_rtc",
258         .id   = -1,
259         .resource = tegra_rtc_resources,
260         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
261 };
262
263 static struct tegra_pci_platform_data vcm30_t124_pcie_platform_data = {
264         .port_status[0] = 1,
265         .port_status[1] = 1,
266         .use_dock_detect        = 1,
267         .gpio   = TEGRA_GPIO_PO1,
268         .gpio_x1_slot   = PMU_TCA6416_GPIO(12),
269 };
270
271 static void vcm30_t124_pcie_init(void)
272 {
273 /* FIXME: Check this for VCM30_T124 */
274 #if 0
275         struct board_info board_info;
276         /* root port 1(x1 slot) is supported only on of ERS-S board */
277         laguna_pcie_platform_data.port_status[1] = 0;
278
279         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
280         platform_device_register(&tegra_pci_device);
281 #endif
282 }
283
284 #ifdef CONFIG_SATA_AHCI_TEGRA
285 static struct tegra_ahci_platform_data ahci_plat_data = {
286         .gen2_rx_eq = 7,
287 };
288
289 static void vcm30_t124_sata_init(void)
290 {
291         tegra_sata_device.dev.platform_data = &ahci_plat_data;
292         platform_device_register(&tegra_sata_device);
293 }
294 #else
295 static void vcm30_t124_sata_init(void) { }
296 #endif
297
298 /* FIXME: Check which devices are needed from the below list */
299 static struct platform_device *vcm30_t124_devices[] __initdata = {
300         &tegra_pmu_device,
301         &tegra_rtc_device,
302         &tegra_udc_device,
303 #if defined(CONFIG_TEGRA_AVP)
304         &tegra_avp_device,
305 #endif
306 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
307         &tegra12_se_device,
308 #endif
309         &tegra_ahub_device,
310         &tegra_dam_device0,
311         &tegra_dam_device1,
312         &tegra_dam_device2,
313         &tegra_i2s_device1,
314         &tegra_i2s_device3,
315         &tegra_i2s_device4,
316         &tegra_spdif_device,
317         &spdif_dit_device,
318         &bluetooth_dit_device,
319         &tegra_hda_device,
320 };
321
322 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
323         .port_otg = false,
324         .has_hostpc = true,
325         .unaligned_dma_buf_supported = true,
326         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
327         .op_mode = TEGRA_USB_OPMODE_HOST,
328         .u_data.host = {
329                 .vbus_gpio = -1,
330                 .hot_plug = false,
331                 .remote_wakeup_supported = false,
332                 .power_off_on_suspend = true,
333                 .turn_off_vbus_on_lp0 = true,
334         },
335         .u_cfg.utmi = {
336                 .hssync_start_delay = 0,
337                 .elastic_limit = 16,
338                 .idle_wait_delay = 17,
339                 .term_range_adj = 6,
340                 .xcvr_setup = 15,
341                 .xcvr_lsfslew = 2,
342                 .xcvr_lsrslew = 2,
343                 .xcvr_setup_offset = 0,
344                 .xcvr_use_fuses = 1,
345                 .vbus_oc_map = 0x4,
346         },
347 };
348
349 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
350         .port_otg = false,
351         .has_hostpc = true,
352         .unaligned_dma_buf_supported = true,
353         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
354         .op_mode = TEGRA_USB_OPMODE_HOST,
355         .u_data.host = {
356                 /* FIXME: Set this only for E1855. */
357                 .vbus_gpio = TEGRA_GPIO_PN5,
358                 .hot_plug = false,
359                 .remote_wakeup_supported = false,
360                 .power_off_on_suspend = true,
361                 .turn_off_vbus_on_lp0 = true,
362         },
363         .u_cfg.utmi = {
364                 .hssync_start_delay = 0,
365                 .elastic_limit = 16,
366                 .idle_wait_delay = 17,
367                 .term_range_adj = 6,
368                 .xcvr_setup = 8,
369                 .xcvr_lsfslew = 2,
370                 .xcvr_lsrslew = 2,
371                 .xcvr_setup_offset = 0,
372                 .xcvr_use_fuses = 1,
373                 .vbus_oc_map = 0x5,
374         },
375 };
376
377 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
378         .port_otg = false,
379         .has_hostpc = true,
380         .unaligned_dma_buf_supported = true,
381         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
382         .op_mode = TEGRA_USB_OPMODE_HOST,
383         .u_data.host = {
384                 .vbus_gpio = -1,
385                 .hot_plug = false,
386                 .remote_wakeup_supported = false,
387                 .power_off_on_suspend = true,
388                 .turn_off_vbus_on_lp0 = true,
389         },
390         .u_cfg.utmi = {
391         .hssync_start_delay = 0,
392                 .elastic_limit = 16,
393                 .idle_wait_delay = 17,
394                 .term_range_adj = 6,
395                 .xcvr_setup = 8,
396                 .xcvr_lsfslew = 2,
397                 .xcvr_lsrslew = 2,
398                 .xcvr_setup_offset = 0,
399                 .xcvr_use_fuses = 1,
400                 .vbus_oc_map = 0x5,
401         },
402 };
403
404 static struct tegra_usb_otg_data tegra_otg_pdata = {
405         .ehci_device = &tegra_ehci1_device,
406         .ehci_pdata = &tegra_ehci1_utmi_pdata,
407 };
408
409 static void vcm30_t124_usb_init(void)
410 {
411         int usb_port_owner_info = tegra_get_usb_port_owner_info();
412
413         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
414                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
415                 platform_device_register(&tegra_ehci2_device);
416         }
417
418         if (!(usb_port_owner_info & UTMI3_PORT_OWNER_XUSB)) {
419                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
420                 platform_device_register(&tegra_ehci3_device);
421         }
422 }
423
424 #ifndef CONFIG_USE_OF
425 static struct platform_device *vcm30_t124_spi_devices[] __initdata = {
426         &tegra11_spi_device1,
427         &tegra11_spi_device4,
428 };
429
430 static struct tegra_spi_platform_data vcm30_t124_spi1_pdata = {
431         .dma_req_sel            = 15,
432         .spi_max_frequency      = 25000000,
433         .clock_always_on        = false,
434 };
435
436 static struct tegra_spi_platform_data vcm30_t124_spi4_pdata = {
437         .dma_req_sel            = 18,
438         .spi_max_frequency      = 25000000,
439         .clock_always_on        = false,
440 };
441
442 static void __init vcm30_t124_spi_init(void)
443 {
444         tegra11_spi_device1.dev.platform_data = &vcm30_t124_spi1_pdata;
445         tegra11_spi_device4.dev.platform_data = &vcm30_t124_spi4_pdata;
446         platform_add_devices(vcm30_t124_spi_devices,
447                         ARRAY_SIZE(vcm30_t124_spi_devices));
448 }
449 #else
450 static void __init vcm30_t124_spi_init(void)
451 {
452 }
453 #endif
454
455 #ifdef CONFIG_USE_OF
456 struct of_dev_auxdata vcm30_t124_auxdata_lookup[] __initdata = {
457         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTA_BASE,
458                                 "serial-tegra.0", NULL),
459         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTB_BASE,
460                                 "serial-tegra.1", NULL),
461         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTD_BASE,
462                                 "serial-tegra.3", NULL),
463         {}
464 };
465 #endif
466
467 static void __init tegra_vcm30_t124_early_init(void)
468 {
469         tegra_clk_init_from_table(vcm30_t124_clk_init_table);
470         tegra_clk_verify_parents();
471         tegra_soc_device_init("vcm30_t124");
472 }
473
474 static void __init tegra_vcm30_t124_late_init(void)
475 {
476         struct board_info board_info;
477         tegra_get_board_info(&board_info);
478         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
479                 board_info.board_id, board_info.sku,
480                 board_info.fab, board_info.major_revision,
481                 board_info.minor_revision);
482         platform_device_register(&tegra_pinmux_device);
483         vcm30_t124_pinmux_init();
484         vcm30_t124_usb_init();
485 /*      vcm30_t124_xusb_init(); */
486         vcm30_t124_nor_init();
487         vcm30_t124_i2c_init();
488         vcm30_t124_spi_init();
489         vcm30_t124_uart_init();
490         platform_add_devices(vcm30_t124_devices,
491                         ARRAY_SIZE(vcm30_t124_devices));
492         tegra_io_dpd_init();
493         vcm30_t124_sdhci_init();
494         vcm30_t124_regulator_init();
495         vcm30_t124_suspend_init();
496 #if 0
497         vcm30_t124_emc_init();
498         vcm30_t124_edp_init();
499 #endif
500         isomgr_init();
501         /* vcm30_t124_panel_init(); */
502         /* vcm30_t124_pmon_init(); */
503         vcm30_t124_pcie_init();
504         vcm30_t124_sata_init();
505 #ifdef CONFIG_TEGRA_WDT_RECOVERY
506         tegra_wdt_recovery_init();
507 #endif
508         /* FIXME: Required? */
509 #if 0
510         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
511
512         vcm30_t124_sensors_init();
513         vcm30_t124_soctherm_init();
514 #endif
515         tegra_register_fuse();
516 }
517
518 static void __init vcm30_t124_ramconsole_reserve(unsigned long size)
519 {
520         tegra_ram_console_debug_reserve(SZ_1M);
521 }
522
523 static void __init tegra_vcm30_t124_dt_init(void)
524 {
525         tegra_get_board_info(&board_info);
526         tegra_get_display_board_info(&display_board_info);
527
528         tegra_vcm30_t124_early_init();
529 #ifdef CONFIG_USE_OF
530         of_platform_populate(NULL,
531                 of_default_bus_match_table, vcm30_t124_auxdata_lookup,
532                 &platform_bus);
533 #endif
534
535         tegra_vcm30_t124_late_init();
536 }
537
538 static void __init tegra_vcm30_t124_reserve(void)
539 {
540 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
541         /* 1920*1200*4*2 = 18432000 bytes */
542         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
543 #else
544         tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
545 #endif
546         vcm30_t124_ramconsole_reserve(SZ_1M);
547 }
548
549 static const char * const vcm30_t124_dt_board_compat[] = {
550         "nvidia,vcm30_t124",
551         NULL
552 };
553
554 DT_MACHINE_START(VCM30_T124, "vcm30_t124")
555         .atag_offset    = 0x100,
556         .smp            = smp_ops(tegra_smp_ops),
557         .map_io         = tegra_map_common_io,
558         .reserve        = tegra_vcm30_t124_reserve,
559         .init_early     = tegra12x_init_early,
560         .init_irq       = tegra_dt_init_irq,
561         .init_time      = tegra_init_timer,
562         .init_machine   = tegra_vcm30_t124_dt_init,
563         .restart        = tegra_assert_system_reset,
564         .dt_compat      = vcm30_t124_dt_board_compat,
565         .init_late      = tegra_init_late
566 MACHINE_END