eebf65a5656135e1c66c0bdc03bb175fe0d3e358
[linux-3.10.git] / arch / arm / mach-tegra / board-vcm30_t124.c
1 /*
2  * arch/arm/mach-tegra/board-vcm30_t124.c
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/platform_device.h>
20 #include <linux/i2c-tegra.h>
21 #include <linux/i2c.h>
22 #include <linux/platform_data/serial-tegra.h>
23 #include <linux/platform_data/tegra_usb.h>
24 #include <linux/platform_data/tegra_nor.h>
25 #include <linux/platform_data/tegra_ahci.h>
26 #include <linux/of_platform.h>
27 #include <linux/kernel.h>
28 #include <linux/clocksource.h>
29 #include <linux/irqchip.h>
30 #include <linux/pci-tegra.h>
31
32 #include <mach/tegra_asoc_pdata.h>
33 #include <mach/io_dpd.h>
34 #include <asm/mach/arch.h>
35 #include <mach/isomgr.h>
36
37 #include "iomap.h"
38 #include "board.h"
39 #include "clock.h"
40 #include "board-vcm30_t124.h"
41 #include "devices.h"
42 #include "board-common.h"
43 #include "common.h"
44
45 #include <asm/mach-types.h>
46 #include "tegra-of-dev-auxdata.h"
47
48 static struct board_info board_info, display_board_info;
49
50 /*
51  * Set clock values as per automotive POR
52  */
53 static __initdata struct tegra_clk_init_table vcm30_t124_clk_init_table[] = {
54         /* name                 parent          rate    enabled (always on)*/
55
56         { "pll_c",              NULL,           792000000,      true},
57
58         { "automotive.sclk",    NULL,           316800000,      true},
59         { "automotive.hclk",    NULL,           316800000,      true},
60         { "automotive.pclk",    NULL,           158400000,      true},
61
62         { "mselect",            "pll_p",        408000000,      true},
63         { "automotive.mselect", NULL,           408000000,      true},
64
65         { "se.cbus",            NULL,           432000000,      false},
66         { "msenc.cbus",         NULL,           432000000,      false},
67         { "vde.cbus",           NULL,           432000000,      false},
68
69         { "vic03.cbus",         NULL,           660000000,      false},
70         { "tsec.cbus",          NULL,           660000000,      false},
71
72         { "vi.c4bus",           NULL,           600000000,      false},
73         { "isp.c4bus",          NULL,           600000000,      false},
74
75         { "pll_d_out0",         "pll_d",        474000000,      true},
76         { "disp2",              "pll_d_out0",   474000000,      false},
77         { "disp1",              "pll_d_out0",   474000000,      false},
78
79         { "pll_d2",             NULL,           297000000,      true},
80         { "hdmi",               "pll_d2",       297000000,      false},
81
82         { "pll_a_out0",         NULL,           24600000,       true},
83         { "i2s0",               "pll_a_out0",   24600000,       false},
84         { "i2s1",               "pll_a_out0",   24600000,       false},
85         { "i2s2",               "pll_a_out0",   24600000,       false},
86         { "i2s3",               "pll_a_out0",   24600000,       false},
87         { "i2s4",               "pll_a_out0",   24600000,       false},
88
89         { "dam0",               "pll_p",        19900000,       false},
90         { "dam1",               "pll_p",        19900000,       false},
91         { "dam2",               "pll_p",        19900000,       false},
92         { "adx",                "pll_p",        19900000,       false},
93         { "adx1",               "pll_p",        19900000,       false},
94         { "amx",                "pll_p",        19900000,       false},
95         { "amx1",               "pll_p",        19900000,       false},
96
97         { "spdif_out",          "pll_a_out0",   24600000,       false},
98         { "hda",                "pll_p",        48000000,       false},
99         { "cilab",              "pll_p",        10200000,       false},
100         { "cilcd",              "pll_p",        10200000,       false},
101         { "cile",               "pll_p",        10200000,       false},
102
103         { "nor",                "pll_p",        102000000,      false},
104
105         { "sbc1",               "pll_p",        25000000,       false},
106         { "sbc2",               "pll_p",        25000000,       false},
107         { "sbc3",               "pll_p",        25000000,       false},
108         { "sbc4",               "pll_p",        25000000,       false},
109         { "sbc5",               "pll_p",        25000000,       false},
110         { "sbc6",               "pll_p",        25000000,       false},
111
112         { "uarta",              "pll_p",        408000000,      false},
113         { "uartb",              "pll_p",        408000000,      false},
114         { "uartc",              "pll_p",        408000000,      false},
115         { "uartd",              "pll_p",        408000000,      false},
116
117         { NULL,                 NULL,           0,              0},
118 };
119
120 static struct tegra_nor_platform_data vcm30_t124_nor_data = {
121         .flash = {
122                 .map_name = "cfi_probe",
123                 .width = 2,
124         },
125         .chip_parms = {
126                 .MuxMode = NorMuxMode_ADNonMux,
127                 .ReadMode = NorReadMode_Page,
128                 .PageLength = NorPageLength_8Word,
129                 .ReadyActive = NorReadyActive_WithData,
130                 /* FIXME: Need to use characterized value */
131                 .timing_default = {
132                         .timing0 = 0x30300273,
133                         .timing1 = 0x00030302,
134                 },
135                 .timing_read = {
136                         .timing0 = 0x30300273,
137                         .timing1 = 0x00030302,
138                 },
139         },
140 };
141
142 static struct cs_info vcm30_t124_cs_info[] = {
143         {
144                 .cs = CS_0,
145                 .num_cs_gpio = 0,
146                 .virt = IO_ADDRESS(TEGRA_NOR_FLASH_BASE),
147                 .size = SZ_64M,
148                 .phys = TEGRA_NOR_FLASH_BASE,
149         },
150 };
151
152 static void vcm30_t124_nor_init(void)
153 {
154         tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1;
155
156         vcm30_t124_nor_data.info.cs = kzalloc(sizeof(struct cs_info) *
157                                         ARRAY_SIZE(vcm30_t124_cs_info),
158                                         GFP_KERNEL);
159         if (!vcm30_t124_nor_data.info.cs)
160                 BUG();
161
162         vcm30_t124_nor_data.info.num_chips = ARRAY_SIZE(vcm30_t124_cs_info);
163
164         memcpy(vcm30_t124_nor_data.info.cs, vcm30_t124_cs_info,
165                                 sizeof(struct cs_info) * ARRAY_SIZE(vcm30_t124_cs_info));
166
167         tegra_nor_device.dev.platform_data = &vcm30_t124_nor_data;
168         platform_device_register(&tegra_nor_device);
169 }
170
171 static struct i2c_board_info __initdata wm8731_board_info = {
172         I2C_BOARD_INFO("wm8731", 0x1a),
173 };
174
175 static struct i2c_board_info __initdata ad1937_board_info = {
176         I2C_BOARD_INFO("ad1937", 0x07),
177 };
178
179 static void vcm30_t124_i2c_init(void)
180 {
181         struct board_info board_info;
182
183         tegra_get_board_info(&board_info);
184         i2c_register_board_info(0, &wm8731_board_info, 1);
185         i2c_register_board_info(0, &ad1937_board_info, 1);
186 }
187
188 /* Register debug UART in old fashion and use DT for all others */
189 #ifndef CONFIG_USE_OF
190 static struct platform_device *vcm30_t124_uart_devices[] __initdata = {
191         &tegra_uarta_device,
192         &tegra_uartb_device,
193         &tegra_uartd_device,
194 };
195
196 static struct tegra_serial_platform_data vcm30_t124_uarta_pdata = {
197         .dma_req_selector = 8,
198         .modem_interrupt = false,
199 };
200
201 static struct tegra_serial_platform_data vcm30_t124_uartb_pdata = {
202         .dma_req_selector = 9,
203         .modem_interrupt = false,
204 };
205
206 static struct tegra_serial_platform_data vcm30_t124_uartd_pdata = {
207         .dma_req_selector = 19,
208         .modem_interrupt = false,
209 };
210 #endif
211
212 static struct tegra_serial_platform_data vcm30_t124_uartc_pdata = {
213         .dma_req_selector = 10,
214         .modem_interrupt = false,
215 };
216
217 static void __init vcm30_t124_uart_init(void)
218 {
219         int debug_port_id;
220
221 #ifndef CONFIG_USE_OF
222         tegra_uarta_device.dev.platform_data = &vcm30_t124_uarta_pdata;
223         tegra_uartb_device.dev.platform_data = &vcm30_t124_uartb_pdata;
224         tegra_uartd_device.dev.platform_data = &vcm30_t124_uartd_pdata;
225         platform_add_devices(vcm30_t124_uart_devices,
226                         ARRAY_SIZE(vcm30_t124_uart_devices));
227 #endif
228         tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
229         if (!is_tegra_debug_uartport_hs()) {
230                 debug_port_id = uart_console_debug_init(2);
231                 if (debug_port_id < 0)
232                         return;
233
234                 platform_device_register(uart_console_debug_device);
235         } else {
236                 tegra_uartc_device.dev.platform_data = &vcm30_t124_uartc_pdata;
237                 platform_device_register(&tegra_uartc_device);
238         }
239
240 }
241
242 static struct resource tegra_rtc_resources[] = {
243         [0] = {
244                 .start = TEGRA_RTC_BASE,
245                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
246                 .flags = IORESOURCE_MEM,
247         },
248         [1] = {
249                 .start = INT_RTC,
250                 .end = INT_RTC,
251                 .flags = IORESOURCE_IRQ,
252         },
253 };
254
255 static struct platform_device tegra_rtc_device = {
256         .name = "tegra_rtc",
257         .id   = -1,
258         .resource = tegra_rtc_resources,
259         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
260 };
261
262 static struct tegra_pci_platform_data vcm30_t124_pcie_platform_data = {
263         .port_status[0] = 1,
264         .port_status[1] = 1,
265         .gpio_hot_plug = -1,
266         .gpio_wake = -1,
267         .gpio_x1_slot = -1,
268 };
269
270 static void vcm30_t124_pcie_init(void)
271 {
272         tegra_pci_device.dev.platform_data = &vcm30_t124_pcie_platform_data;
273         platform_device_register(&tegra_pci_device);
274 }
275
276 #ifdef CONFIG_SATA_AHCI_TEGRA
277 static struct tegra_ahci_platform_data ahci_plat_data = {
278         .gen2_rx_eq = 7,
279 };
280
281 static void vcm30_t124_sata_init(void)
282 {
283         tegra_sata_device.dev.platform_data = &ahci_plat_data;
284         platform_device_register(&tegra_sata_device);
285 }
286 #else
287 static void vcm30_t124_sata_init(void) { }
288 #endif
289
290 static struct platform_device tegra_snd_vcm30t124 = {
291         .name = "tegra-snd-vcm30t124",
292         .id = 0,
293 };
294
295 /* FIXME: Check which devices are needed from the below list */
296 static struct platform_device *vcm30_t124_devices[] __initdata = {
297         &tegra_pmu_device,
298         &tegra_rtc_device,
299         &tegra_udc_device,
300 #if defined(CONFIG_TEGRA_AVP)
301         &tegra_avp_device,
302 #endif
303 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
304         &tegra12_se_device,
305 #endif
306         &tegra_snd_vcm30t124,
307 };
308
309 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
310         .port_otg = false,
311         .has_hostpc = true,
312         .unaligned_dma_buf_supported = true,
313         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
314         .op_mode = TEGRA_USB_OPMODE_HOST,
315         .u_data.host = {
316                 .vbus_gpio = -1,
317                 .hot_plug = false,
318                 .remote_wakeup_supported = false,
319                 .power_off_on_suspend = true,
320                 .turn_off_vbus_on_lp0 = true,
321         },
322         .u_cfg.utmi = {
323                 .hssync_start_delay = 0,
324                 .elastic_limit = 16,
325                 .idle_wait_delay = 17,
326                 .term_range_adj = 6,
327                 .xcvr_setup = 15,
328                 .xcvr_lsfslew = 2,
329                 .xcvr_lsrslew = 2,
330                 .xcvr_setup_offset = 0,
331                 .xcvr_use_fuses = 1,
332                 .vbus_oc_map = 0x4,
333         },
334 };
335
336 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
337         .port_otg = false,
338         .has_hostpc = true,
339         .unaligned_dma_buf_supported = true,
340         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
341         .op_mode = TEGRA_USB_OPMODE_HOST,
342         .u_data.host = {
343                 /* FIXME: Set this only for E1855. */
344                 .vbus_gpio = TEGRA_GPIO_PN5,
345                 .hot_plug = true,
346                 .remote_wakeup_supported = false,
347                 .power_off_on_suspend = true,
348                 .turn_off_vbus_on_lp0 = true,
349         },
350         .u_cfg.utmi = {
351                 .hssync_start_delay = 0,
352                 .elastic_limit = 16,
353                 .idle_wait_delay = 17,
354                 .term_range_adj = 6,
355                 .xcvr_setup = 8,
356                 .xcvr_lsfslew = 2,
357                 .xcvr_lsrslew = 2,
358                 .xcvr_setup_offset = 0,
359                 .xcvr_use_fuses = 1,
360                 .vbus_oc_map = 0x5,
361         },
362 };
363
364 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
365         .port_otg = false,
366         .has_hostpc = true,
367         .unaligned_dma_buf_supported = true,
368         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
369         .op_mode = TEGRA_USB_OPMODE_HOST,
370         .u_data.host = {
371                 .vbus_gpio = -1,
372                 .hot_plug = true,
373                 .remote_wakeup_supported = false,
374                 .power_off_on_suspend = true,
375                 .turn_off_vbus_on_lp0 = true,
376         },
377         .u_cfg.utmi = {
378         .hssync_start_delay = 0,
379                 .elastic_limit = 16,
380                 .idle_wait_delay = 17,
381                 .term_range_adj = 6,
382                 .xcvr_setup = 8,
383                 .xcvr_lsfslew = 2,
384                 .xcvr_lsrslew = 2,
385                 .xcvr_setup_offset = 0,
386                 .xcvr_use_fuses = 1,
387                 .vbus_oc_map = 0x5,
388         },
389 };
390
391 static struct tegra_usb_otg_data tegra_otg_pdata = {
392         .ehci_device = &tegra_ehci1_device,
393         .ehci_pdata = &tegra_ehci1_utmi_pdata,
394 };
395
396 static void vcm30_t124_usb_init(void)
397 {
398         int usb_port_owner_info = tegra_get_usb_port_owner_info();
399
400         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
401                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
402                 platform_device_register(&tegra_ehci2_device);
403         }
404
405         if (!(usb_port_owner_info & UTMI3_PORT_OWNER_XUSB)) {
406                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
407                 platform_device_register(&tegra_ehci3_device);
408         }
409 }
410
411 #ifdef CONFIG_USE_OF
412 struct of_dev_auxdata vcm30_t124_auxdata_lookup[] __initdata = {
413         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTA_BASE,
414                                 "serial-tegra.0", NULL),
415         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTB_BASE,
416                                 "serial-tegra.1", NULL),
417         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", TEGRA_UARTD_BASE,
418                                 "serial-tegra.3", NULL),
419         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
420                 NULL),
421         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE, "gk20a.0", NULL),
422         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
423         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
424                 NULL),
425         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
426         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
427         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
428         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
429         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
430                                 NULL),
431         OF_DEV_AUXDATA("nvidia,tegra124-ahub", 0x70300000,
432                                 "tegra30-ahub-apbif", NULL),
433         T124_I2C_OF_DEV_AUXDATA,
434         T124_SPI_OF_DEV_AUXDATA,
435
436         {}
437 };
438 #endif
439
440 static void __init tegra_vcm30_t124_early_init(void)
441 {
442         tegra_clk_init_from_table(vcm30_t124_clk_init_table);
443         tegra_clk_verify_parents();
444         tegra_soc_device_init("vcm30t124");
445 }
446
447 static void __init tegra_vcm30_t124_late_init(void)
448 {
449         struct board_info board_info;
450         tegra_get_board_info(&board_info);
451         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
452                 board_info.board_id, board_info.sku,
453                 board_info.fab, board_info.major_revision,
454                 board_info.minor_revision);
455         vcm30_t124_usb_init();
456 /*      vcm30_t124_xusb_init(); */
457         vcm30_t124_nor_init();
458         vcm30_t124_i2c_init();
459         vcm30_t124_uart_init();
460         vcm30_t124_pca953x_init();
461         platform_add_devices(vcm30_t124_devices,
462                         ARRAY_SIZE(vcm30_t124_devices));
463         tegra_io_dpd_init();
464         vcm30_t124_sdhci_init();
465         vcm30_t124_regulator_init();
466         vcm30_t124_suspend_init();
467 #if 0
468         vcm30_t124_emc_init();
469         vcm30_t124_edp_init();
470 #endif
471         isomgr_init();
472         /* vcm30_t124_panel_init(); */
473         /* vcm30_t124_pmon_init(); */
474         vcm30_t124_pcie_init();
475         vcm30_t124_sata_init();
476 #ifdef CONFIG_TEGRA_WDT_RECOVERY
477         tegra_wdt_recovery_init();
478 #endif
479         /* FIXME: Required? */
480 #if 0
481         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
482
483         vcm30_t124_sensors_init();
484         vcm30_t124_soctherm_init();
485 #endif
486         tegra_register_fuse();
487         vcm30_t124_panel_init();
488 }
489
490 static void __init tegra_vcm30_t124_dt_init(void)
491 {
492         tegra_get_board_info(&board_info);
493         tegra_get_display_board_info(&display_board_info);
494
495         tegra_vcm30_t124_early_init();
496 #ifdef CONFIG_USE_OF
497         of_platform_populate(NULL,
498                 of_default_bus_match_table, vcm30_t124_auxdata_lookup,
499                 &platform_bus);
500 #endif
501
502         tegra_vcm30_t124_late_init();
503 }
504
505 static void __init tegra_vcm30_t124_reserve(void)
506 {
507 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
508         /* 1920*1200*4*2 = 18432000 bytes */
509         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
510 #else
511         tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
512 #endif
513 }
514
515 static const char * const vcm30_t124_dt_board_compat[] = {
516         "nvidia,vcm30t124",
517         NULL
518 };
519
520 DT_MACHINE_START(VCM30_T124, "vcm30t124")
521         .atag_offset    = 0x100,
522         .smp            = smp_ops(tegra_smp_ops),
523         .map_io         = tegra_map_common_io,
524         .reserve        = tegra_vcm30_t124_reserve,
525         .init_early     = tegra12x_init_early,
526         .init_irq       = irqchip_init,
527         .init_time      = clocksource_of_init,
528         .init_machine   = tegra_vcm30_t124_dt_init,
529         .restart        = tegra_assert_system_reset,
530         .dt_compat      = vcm30_t124_dt_board_compat,
531         .init_late      = tegra_init_late
532 MACHINE_END