arm: tegra: vcm3.0: t124: Add panel file
[linux-3.10.git] / arch / arm / mach-tegra / board-vcm30_t124-power.c
1 /*
2  * arch/arm/mach-tegra/board-vcm30_t124-power.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 #include <linux/i2c.h>
19 #include <linux/io.h>
20 #include <linux/mfd/max77663-core.h>
21 #include <linux/regulator/max77663-regulator.h>
22 #include <linux/regulator/max15569-regulator.h>
23
24 #include <mach/edp.h>
25
26 #include "pm.h"
27 #include "board.h"
28 #include "gpio-names.h"
29 #include "board-common.h"
30 #include "board-vcm30_t124.h"
31 #include "tegra_cl_dvfs.h"
32 #include "devices.h"
33 #include "tegra11_soctherm.h"
34 #include "tegra3_tsensor.h"
35
36 #define PMC_CTRL                0x0
37 #define PMC_CTRL_INTR_LOW       (1 << 17)
38
39
40 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
41         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
42         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
43         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
44 };
45
46 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
47         {
48                 .src = FPS_SRC_0,
49                 .en_src = FPS_EN_SRC_EN0,
50                 .time_period = FPS_TIME_PERIOD_DEF,
51         },
52         {
53                 .src = FPS_SRC_1,
54                 .en_src = FPS_EN_SRC_EN1,
55                 .time_period = FPS_TIME_PERIOD_DEF,
56         },
57         {
58                 .src = FPS_SRC_2,
59                 .en_src = FPS_EN_SRC_EN0,
60                 .time_period = FPS_TIME_PERIOD_DEF,
61         },
62 };
63
64 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg, \
65                 _always_on, _boot_on, _apply_uV, \
66                 _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
67         static struct regulator_init_data max77663_regulator_idata_##_id = { \
68                 .supply_regulator = _supply_reg, \
69                 .constraints = { \
70                         .name = max77663_rails(_id), \
71                         .min_uV = _min_uV, \
72                         .max_uV = _max_uV, \
73                         .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
74                                         REGULATOR_MODE_STANDBY), \
75                         .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
76                                         REGULATOR_CHANGE_STATUS | \
77                                         REGULATOR_CHANGE_VOLTAGE), \
78                         .always_on = _always_on, \
79                         .boot_on = _boot_on, \
80                         .apply_uV = _apply_uV, \
81                 }, \
82                 .num_consumer_supplies = \
83                 ARRAY_SIZE(max77663_##_id##_supply), \
84                 .consumer_supplies = max77663_##_id##_supply, \
85         }; \
86         static struct max77663_regulator_platform_data \
87                 max77663_regulator_pdata_##_id = \
88         { \
89                 .reg_init_data = &max77663_regulator_idata_##_id, \
90                 .id = MAX77663_REGULATOR_ID_##_rid, \
91                 .fps_src = _fps_src, \
92                 .fps_pu_period = _fps_pu_period, \
93                 .fps_pd_period = _fps_pd_period, \
94                 .fps_cfgs = max77663_fps_cfgs, \
95                 .flags = _flags, \
96         }
97
98 MAX77663_PDATA_INIT(LDO5, ldo5, 800000, 2800000, NULL, 0, 1, 0,
99                 FPS_SRC_1, FPS_POWER_PERIOD_7, FPS_POWER_PERIOD_0, 0);
100
101 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
102
103 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
104         MAX77663_REG(LDO5, ldo5),
105 };
106
107 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
108         {
109                 .gpio = MAX77663_GPIO5,
110                 .dir = GPIO_DIR_OUT,
111                 .dout = GPIO_DOUT_HIGH,
112                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
113                 .alternate = GPIO_ALT_DISABLE,
114         },
115 };
116
117 static struct max77663_platform_data max77663_pdata = {
118         .irq_base       = MAX77663_IRQ_BASE,
119         .gpio_base      = MAX77663_GPIO_BASE,
120
121         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
122         .gpio_cfgs      = max77663_gpio_cfgs,
123
124         .regulator_pdata = max77663_reg_pdata,
125         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
126
127         .rtc_i2c_addr   = 0x68,
128
129         .use_power_off  = false,
130 };
131
132 static struct i2c_board_info __initdata max77663_regulators[] = {
133         {
134                 /* The I2C address was determined by OTP factory setting */
135                 I2C_BOARD_INFO("max77663", 0x3c),
136                 .irq            = INT_EXTERNAL_PMU,
137                 .platform_data  = &max77663_pdata,
138         },
139 };
140
141 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
142 /* board parameters for cpu dfll */
143 static struct tegra_cl_dvfs_cfg_param vcm30_t124_cl_dvfs_param = {
144         .sample_rate = 12500,
145
146         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
147         .cf = 10,
148         .ci = 0,
149         .cg = 2,
150
151         .droop_cut_value = 0xF,
152         .droop_restore_ramp = 0x0,
153         .scale_out_ramp = 0x0,
154 };
155
156 /* MAX15569: fixed 10mV steps from 600mV to 1400mV, with offset 0x0b */
157 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
158 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
159 static inline void fill_reg_map(void)
160 {
161         int i;
162         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
163                 pmu_cpu_vdd_map[i].reg_value = i + 0x0b;
164                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
165         }
166 }
167
168 static struct tegra_cl_dvfs_platform_data vcm30_t124_cl_dvfs_data = {
169         .dfll_clk_name = "dfll_cpu",
170         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
171         .u.pmu_i2c = {
172                 .fs_rate = 400000,
173                 .slave_addr = 0x3a,
174                 .reg = 0x07,
175         },
176         .vdd_map = pmu_cpu_vdd_map,
177         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
178
179         .cfg_param = &vcm30_t124_cl_dvfs_param,
180 };
181
182 static int __init vcm30_t124_cl_dvfs_init(void)
183 {
184         fill_reg_map();
185 #if 0
186         if (tegra_revision < TEGRA_REVISION_A02)
187                 vcm30_t124_cl_dvfs_data.out_quiet_then_disable = true;
188 #endif
189         tegra_cl_dvfs_device.dev.platform_data = &vcm30_t124_cl_dvfs_data;
190         platform_device_register(&tegra_cl_dvfs_device);
191
192         return 0;
193 }
194 #endif
195
196 static int __init vcm30_t124_max77663_regulator_init(void)
197 {
198         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
199         u32 pmc_ctrl;
200
201         /* configure the power management controller to trigger PMU
202          * interrupts when low */
203         pmc_ctrl = readl(pmc + PMC_CTRL);
204         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
205
206         i2c_register_board_info(4, max77663_regulators,
207                                 ARRAY_SIZE(max77663_regulators));
208
209         return 0;
210 }
211
212 int __init vcm30_t124_regulator_init(void)
213 {
214 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
215         vcm30_t124_cl_dvfs_init();
216 #endif
217         vcm30_t124_max77663_regulator_init();
218
219         return 0;
220 }
221
222 static struct tegra_suspend_platform_data vcm30_t124_suspend_data = {
223         .cpu_timer      = 2000,
224         .cpu_off_timer  = 2000,
225         .suspend_mode   = TEGRA_SUSPEND_LP0,
226         .core_timer     = 0xfefe,
227         .core_off_timer = 2000,
228         .corereq_high   = true,
229         .sysclkreq_high = true,
230         .cpu_lp2_min_residency = 1000,
231 };
232
233 int __init vcm30_t124_suspend_init(void)
234 {
235         tegra_init_suspend(&vcm30_t124_suspend_data);
236         return 0;
237 }
238
239 /* FIXME: Should this be called? */
240 int __init vcm30_t124_edp_init(void)
241 {
242         unsigned int regulator_mA;
243
244         regulator_mA = get_maximum_cpu_current_supported();
245         if (!regulator_mA)
246                 regulator_mA = 14000;
247
248         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
249         tegra_init_cpu_edp_limits(regulator_mA);
250
251         regulator_mA = get_maximum_core_current_supported();
252         if (!regulator_mA)
253                 regulator_mA = 14000;
254
255         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
256         tegra_init_core_edp_limits(regulator_mA);
257
258         return 0;
259 }
260
261 static struct thermal_zone_params soctherm_tzp = {
262         .governor_name = "pid_thermal_gov",
263 };
264
265 static struct tegra_tsensor_pmu_data tpdata_palmas = {
266         .reset_tegra = 1,
267         .pmu_16bit_ops = 0,
268         .controller_type = 0,
269         .pmu_i2c_addr = 0x58,
270         .i2c_controller_id = 4,
271         .poweroff_reg_addr = 0xa0,
272         .poweroff_reg_data = 0x0,
273 };
274
275 static struct tegra_tsensor_pmu_data tpdata_max77663 = {
276         .reset_tegra = 1,
277         .pmu_16bit_ops = 0,
278         .controller_type = 0,
279         .pmu_i2c_addr = 0x3c,
280         .i2c_controller_id = 4,
281         .poweroff_reg_addr = 0x41,
282         .poweroff_reg_data = 0x80,
283 };
284
285 static struct soctherm_platform_data vcm30_t124_soctherm_data = {
286         .therm = {
287                 [THERM_CPU] = {
288                         .zone_enable = true,
289                         .passive_delay = 1000,
290                         .hotspot_offset = 6000,
291                         .num_trips = 3,
292                         .trips = {
293                                 {
294                                         .cdev_type = "tegra-balanced",
295                                         .trip_temp = 90000,
296                                         .trip_type = THERMAL_TRIP_PASSIVE,
297                                         .upper = THERMAL_NO_LIMIT,
298                                         .lower = THERMAL_NO_LIMIT,
299                                 },
300                                 {
301                                         .cdev_type = "tegra-heavy",
302                                         .trip_temp = 100000,
303                                         .trip_type = THERMAL_TRIP_HOT,
304                                         .upper = THERMAL_NO_LIMIT,
305                                         .lower = THERMAL_NO_LIMIT,
306                                 },
307                                 {
308                                         .cdev_type = "tegra-shutdown",
309                                         .trip_temp = 102000,
310                                         .trip_type = THERMAL_TRIP_CRITICAL,
311                                         .upper = THERMAL_NO_LIMIT,
312                                         .lower = THERMAL_NO_LIMIT,
313                                 },
314                         },
315                         .tzp = &soctherm_tzp,
316                 },
317                 [THERM_GPU] = {
318                         .zone_enable = true,
319                         .passive_delay = 1000,
320                         .hotspot_offset = 6000,
321                         .num_trips = 3,
322                         .trips = {
323                                 {
324                                         .cdev_type = "tegra-balanced",
325                                         .trip_temp = 90000,
326                                         .trip_type = THERMAL_TRIP_PASSIVE,
327                                         .upper = THERMAL_NO_LIMIT,
328                                         .lower = THERMAL_NO_LIMIT,
329                                 },
330                                 {
331                                         .cdev_type = "tegra-heavy",
332                                         .trip_temp = 100000,
333                                         .trip_type = THERMAL_TRIP_HOT,
334                                         .upper = THERMAL_NO_LIMIT,
335                                         .lower = THERMAL_NO_LIMIT,
336                                 },
337                                 {
338                                         .cdev_type = "tegra-shutdown",
339                                         .trip_temp = 102000,
340                                         .trip_type = THERMAL_TRIP_CRITICAL,
341                                         .upper = THERMAL_NO_LIMIT,
342                                         .lower = THERMAL_NO_LIMIT,
343                                 },
344                         },
345                         .tzp = &soctherm_tzp,
346                 },
347                 [THERM_PLL] = {
348                         .zone_enable = true,
349                 },
350         },
351         .throttle = {
352                 [THROTTLE_HEAVY] = {
353                         .priority = 100,
354                         .devs = {
355                                 [THROTTLE_DEV_CPU] = {
356                                         .enable = true,
357                                         .depth = 80,
358                                 },
359                         },
360                 },
361         },
362         .tshut_pmu_trip_data = &tpdata_palmas,
363 };
364
365 /* FIXME: Needed? */
366 int __init vcm30_t124_soctherm_init(void)
367 {
368
369         vcm30_t124_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
370
371         tegra_platform_edp_init(vcm30_t124_soctherm_data.therm[THERM_CPU].trips,
372                         &vcm30_t124_soctherm_data.therm[THERM_CPU].num_trips,
373                         8000); /* edp temperature margin */
374         tegra_add_tj_trips(vcm30_t124_soctherm_data.therm[THERM_CPU].trips,
375                         &vcm30_t124_soctherm_data.therm[THERM_CPU].num_trips);
376         /*tegra_add_vc_trips(vcm30_t124_soctherm_data.therm[THERM_CPU].trips,
377                         &vcm30_t124_soctherm_data.therm[THERM_CPU].num_trips);
378 */
379         return tegra11_soctherm_init(&vcm30_t124_soctherm_data);
380 }