7a5eb11ce709a75a4895a13c5ac1bbf0186afa8b
[linux-3.10.git] / arch / arm / mach-tegra / board-tn8-power.c
1 /*
2  * arch/arm/mach-tegra/board-tn8-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/io.h>
24 #include <linux/regulator/fixed.h>
25 #include <linux/mfd/palmas.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/irq.h>
28
29 #include <mach/irqs.h>
30 #include <mach/hardware.h>
31
32
33 #include <asm/mach-types.h>
34
35 #include "pm.h"
36 #include "board.h"
37 #include "tegra-board-id.h"
38 #include "board-common.h"
39 #include "board-ardbeg.h"
40 #include "board-pmu-defines.h"
41 #include "devices.h"
42 #include "iomap.h"
43 #include "tegra-board-id.h"
44
45 #define PMC_CTRL                0x0
46 #define PMC_CTRL_INTR_LOW       (1 << 17)
47
48 static struct regulator_consumer_supply palmas_smps123_supply[] = {
49         REGULATOR_SUPPLY("vdd_cpu", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps45_supply[] = {
53         REGULATOR_SUPPLY("vdd_gpu", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps6_supply[] = {
57         REGULATOR_SUPPLY("vddio_ddr", NULL),
58         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
59         REGULATOR_SUPPLY("vddio_ddr3", NULL),
60         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
61 };
62
63 static struct regulator_consumer_supply palmas_smps7_supply[] = {
64         REGULATOR_SUPPLY("vdd_core", NULL),
65 };
66
67 static struct regulator_consumer_supply palmas_smps8_supply[] = {
68         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
69         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
70         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
71         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
72         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
73         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
74         REGULATOR_SUPPLY("avdd_osc", NULL),
75         REGULATOR_SUPPLY("vddio_sys", NULL),
76         REGULATOR_SUPPLY("vddio_sys_2", NULL),
77         REGULATOR_SUPPLY("vddio_gmi", NULL),
78         REGULATOR_SUPPLY("pwrdet_nand", NULL),
79         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
80         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
81         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
82         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
83 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
84         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
85         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
86         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
87         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
88         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
89 #endif
90         REGULATOR_SUPPLY("vddio_audio", NULL),
91         REGULATOR_SUPPLY("pwrdet_audio", NULL),
92         REGULATOR_SUPPLY("vddio_uart", NULL),
93         REGULATOR_SUPPLY("pwrdet_uart", NULL),
94         REGULATOR_SUPPLY("vddio_bb", NULL),
95         REGULATOR_SUPPLY("pwrdet_bb", NULL),
96         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
97         REGULATOR_SUPPLY("vdd_dtv", NULL),
98         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
99         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
100         REGULATOR_SUPPLY("vddio_cam", "vi"),
101         REGULATOR_SUPPLY("pwrdet_cam", NULL),
102         REGULATOR_SUPPLY("dvdd", "spi0.0"),
103         REGULATOR_SUPPLY("vlogic", "0-0069"),
104         REGULATOR_SUPPLY("vid", "0-000c"),
105         REGULATOR_SUPPLY("vddio", "0-0077"),
106         REGULATOR_SUPPLY("dvdd_lcd", NULL),
107         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
108 };
109
110 static struct regulator_consumer_supply palmas_smps9_supply[] = {
111         REGULATOR_SUPPLY("vdd_snsr", NULL),
112         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
113         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
114         REGULATOR_SUPPLY("vdd_3v3_gps", NULL),
115         REGULATOR_SUPPLY("vdd_3v3_nfc", NULL),
116         REGULATOR_SUPPLY("vdd", "0-0069"),
117         REGULATOR_SUPPLY("vdd", "0-000c"),
118         REGULATOR_SUPPLY("vdd", "0-0077"),
119         REGULATOR_SUPPLY("vdd", "1-004c"),
120 };
121
122 static struct regulator_consumer_supply palmas_smps10_supply[] = {
123         REGULATOR_SUPPLY("vdd_5v0_mdm", NULL),
124         REGULATOR_SUPPLY("vdd_5v0_snsr", NULL),
125         REGULATOR_SUPPLY("vdd_5v0_dis", NULL),
126         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
127         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
128         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
129         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
130         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
131 };
132
133 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
134         REGULATOR_SUPPLY("avdd_pll_m", NULL),
135         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
136         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
137         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
138         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
139         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
140         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
141         REGULATOR_SUPPLY("avdd_pll_x", NULL),
142         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
143         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
144         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
145 };
146
147 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
148         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
149         REGULATOR_SUPPLY("imx135_reg2", NULL),
150         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
151         REGULATOR_SUPPLY("vdig", "2-0010"),
152         REGULATOR_SUPPLY("vdig", "2-0036"),
153 };
154
155 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
156         REGULATOR_SUPPLY("avdd", "spi0.0"),
157 };
158
159
160 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
161         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
162         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
163         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
164         REGULATOR_SUPPLY("avdd_cam3_cam", NULL),
165         REGULATOR_SUPPLY("vana", "2-0010"),
166         REGULATOR_SUPPLY("vana", "2-0036"),
167 };
168
169 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
170         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
171         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
172         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
173         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
174         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
175         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
176         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
177         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
178         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
179         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
180 };
181
182 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
183         REGULATOR_SUPPLY("vdd_cam1_1v8_cam", NULL),
184         REGULATOR_SUPPLY("vdd_cam2_1v8_cam", NULL),
185         REGULATOR_SUPPLY("vif", "2-0010"),
186         REGULATOR_SUPPLY("vif", "2-0036"),
187         REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
188
189 };
190
191 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
192         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
193         REGULATOR_SUPPLY("imx135_reg1", NULL),
194         REGULATOR_SUPPLY("vdd", "2-000c"),
195 };
196
197 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
198         REGULATOR_SUPPLY("vdd_rtc", NULL),
199 };
200
201
202 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
203         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
204         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
205 };
206
207 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
208         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
209         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
210         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
211         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
212         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
213         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
214         REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
215         REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
216 };
217
218 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
219         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
220         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
221         REGULATOR_SUPPLY("pwrdet_hv", NULL),
222         REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
223 };
224
225 PALMAS_PDATA_INIT(smps123, 900, 1400, NULL, 1, 1, 1, NORMAL);
226 PALMAS_PDATA_INIT(smps45, 900, 1400, NULL, 1, 1, 1, NORMAL);
227 PALMAS_PDATA_INIT(smps6, 1350, 1350, NULL, 1, 1, 1, NORMAL);
228 PALMAS_PDATA_INIT(smps7, 900, 1400, NULL, 1, 1, 1, NORMAL);
229 PALMAS_PDATA_INIT(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL);
230 PALMAS_PDATA_INIT(smps9, 3300, 3300, NULL, 0, 0, 1, NORMAL);
231 PALMAS_PDATA_INIT(smps10, 5000, 5000, NULL, 0, 0, 1, 0);
232 PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps6), 1, 1, 1, 0);
233 PALMAS_PDATA_INIT(ldo2, 1050, 1200, palmas_rails(smps6), 0, 0, 1, 0);
234 PALMAS_PDATA_INIT(ldo3, 3300, 3300, NULL, 0, 0, 1, 0);
235 PALMAS_PDATA_INIT(ldo4, 2700, 2700, NULL, 0, 0, 1, 0);
236 PALMAS_PDATA_INIT(ldo5, 1200, 1200, palmas_rails(smps8), 0, 0, 1, 0);
237 PALMAS_PDATA_INIT(ldo6, 1800, 1800, palmas_rails(smps9), 0, 0, 1, 0);
238 PALMAS_PDATA_INIT(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0);
239 PALMAS_PDATA_INIT(ldo8, 1000, 1000, NULL, 1, 1, 1, 0);
240 PALMAS_PDATA_INIT(ldo9, 1800, 3300, palmas_rails(smps9), 0, 0, 1, 0);
241 PALMAS_PDATA_INIT(ldoln, 3300, 3300, palmas_rails(smps10), 1, 1, 1, 0);
242 PALMAS_PDATA_INIT(ldousb, 3000, 3300, NULL, 1, 1, 1, 0);
243
244 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
245 static struct regulator_init_data *tn8_reg_data[PALMAS_NUM_REGS] = {
246         NULL,
247         PALMAS_REG_PDATA(smps123),
248         NULL,
249         PALMAS_REG_PDATA(smps45),
250         NULL,
251         PALMAS_REG_PDATA(smps6),
252         PALMAS_REG_PDATA(smps7),
253         PALMAS_REG_PDATA(smps8),
254         PALMAS_REG_PDATA(smps9),
255         PALMAS_REG_PDATA(smps10),
256         PALMAS_REG_PDATA(ldo1),
257         PALMAS_REG_PDATA(ldo2),
258         PALMAS_REG_PDATA(ldo3),
259         PALMAS_REG_PDATA(ldo4),
260         PALMAS_REG_PDATA(ldo5),
261         PALMAS_REG_PDATA(ldo6),
262         PALMAS_REG_PDATA(ldo7),
263         PALMAS_REG_PDATA(ldo8),
264         PALMAS_REG_PDATA(ldo9),
265         NULL,
266         NULL,
267         NULL,
268         NULL,
269         NULL,
270         PALMAS_REG_PDATA(ldoln),
271         PALMAS_REG_PDATA(ldousb),
272         NULL,
273         NULL,
274         NULL,
275         NULL,
276         NULL,
277 };
278
279 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
280                 _vsel)                                          \
281         static struct palmas_reg_init reg_init_data_##_name = {         \
282                 .warm_reset = _warm_reset,                              \
283                 .roof_floor =   _roof_floor,                            \
284                 .mode_sleep = _mode_sleep,              \
285                 .vsel = _vsel,          \
286         }
287
288 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0);
289 PALMAS_REG_INIT(smps45, 0, 0, 0, 0);
290 PALMAS_REG_INIT(smps6, 0, 0, 0, 0);
291 PALMAS_REG_INIT(smps7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0);
292 PALMAS_REG_INIT(smps8, 0, 0, 0, 0);
293 PALMAS_REG_INIT(smps9, 0, 0, 0, 0);
294 PALMAS_REG_INIT(smps10, 0, 0, 0, 0);
295 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0);
296 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0);
297 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0);
298 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0);
299 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0);
300 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0);
301 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0);
302 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0);
303 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0);
304 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0);
305 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0);
306
307 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
308 static struct palmas_reg_init *tn8_reg_init[PALMAS_NUM_REGS] = {
309         NULL,
310         PALMAS_REG_INIT_DATA(smps123),
311         NULL,
312         PALMAS_REG_INIT_DATA(smps45),
313         NULL,
314         PALMAS_REG_INIT_DATA(smps6),
315         PALMAS_REG_INIT_DATA(smps7),
316         PALMAS_REG_INIT_DATA(smps8),
317         PALMAS_REG_INIT_DATA(smps9),
318         PALMAS_REG_INIT_DATA(smps10),
319         PALMAS_REG_INIT_DATA(ldo1),
320         PALMAS_REG_INIT_DATA(ldo2),
321         PALMAS_REG_INIT_DATA(ldo3),
322         PALMAS_REG_INIT_DATA(ldo4),
323         PALMAS_REG_INIT_DATA(ldo5),
324         PALMAS_REG_INIT_DATA(ldo6),
325         PALMAS_REG_INIT_DATA(ldo7),
326         PALMAS_REG_INIT_DATA(ldo8),
327         PALMAS_REG_INIT_DATA(ldo9),
328         NULL,
329         NULL,
330         NULL,
331         NULL,
332         NULL,
333         PALMAS_REG_INIT_DATA(ldoln),
334         PALMAS_REG_INIT_DATA(ldousb),
335         NULL,
336         NULL,
337         NULL,
338         NULL,
339         NULL,
340 };
341
342 static struct palmas_pinctrl_config palmas_pincfg[] = {
343         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
344         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
345         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
346         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
347         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
348         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
349         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
350         PALMAS_PINMUX(GPIO5, CLK32KGAUDIO, DEFAULT, DEFAULT),
351         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
352         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
353 };
354
355 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
356         .pincfg = palmas_pincfg,
357         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
358         .dvfs1_enable = true,
359         .dvfs2_enable = false,
360 };
361
362 static struct palmas_pmic_platform_data pmic_platform = {
363 };
364
365 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
366         {
367                 .clk32k_id = PALMAS_CLOCK32KG,
368                 .enable = true,
369         }, {
370                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
371                 .enable = true,
372         },
373 };
374
375 static struct palmas_platform_data palmas_pdata = {
376         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
377         .irq_base = PALMAS_TEGRA_IRQ_BASE,
378         .pmic_pdata = &pmic_platform,
379         .use_power_off = true,
380         .pinctrl_pdata = &palmas_pinctrl_pdata,
381         .clk32k_init_data =  palmas_clk32k_idata,
382         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
383 };
384
385 static struct i2c_board_info palma_device[] = {
386         {
387                 I2C_BOARD_INFO("tps65913", 0x58),
388                 .irq            = INT_EXTERNAL_PMU,
389                 .platform_data  = &palmas_pdata,
390         },
391 };
392
393 int __init tn8_regulator_init(void)
394 {
395         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
396         u32 pmc_ctrl;
397         int i;
398
399         /* TPS65913: Normal state of INT request line is LOW.
400          * configure the power management controller to trigger PMU
401          * interrupts when HIGH.
402          */
403         pmc_ctrl = readl(pmc + PMC_CTRL);
404         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
405         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
406                 pmic_platform.reg_data[i] = tn8_reg_data[i];
407                 pmic_platform.reg_init[i] = tn8_reg_init[i];
408         }
409
410         /* Tracking configuration */
411         /* TODO
412         reg_init_data_ldo8.config_flags =
413                 PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
414                 PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
415         */
416         reg_idata_smps45.constraints.init_uV = 1000000;
417
418         i2c_register_board_info(4, palma_device,
419                         ARRAY_SIZE(palma_device));
420         return 0;
421 }
422 /* Macro for defining fixed regulator sub device data */
423 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
424 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
425         _always_on, _boot_on, _gpio_nr, _open_drain,            \
426         _active_high, _boot_state, _millivolts, _sdelay)        \
427 static struct regulator_init_data ri_data_##_var =              \
428 {                                                               \
429         .supply_regulator = _in_supply,                         \
430         .num_consumer_supplies =                                \
431         ARRAY_SIZE(fixed_reg_en_##_name##_supply),              \
432         .consumer_supplies = fixed_reg_en_##_name##_supply,     \
433         .constraints = {                                        \
434                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
435                                 REGULATOR_MODE_STANDBY),        \
436                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
437                                 REGULATOR_CHANGE_STATUS |       \
438                                 REGULATOR_CHANGE_VOLTAGE),      \
439                 .always_on = _always_on,                        \
440                 .boot_on = _boot_on,                            \
441         },                                                      \
442 };                                                              \
443 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata =        \
444 {                                                               \
445         .supply_name = FIXED_SUPPLY(_name),                     \
446         .microvolts = _millivolts * 1000,                       \
447         .gpio = _gpio_nr,                                       \
448         .gpio_is_open_drain = _open_drain,                      \
449         .enable_high = _active_high,                            \
450         .enabled_at_boot = _boot_state,                         \
451         .init_data = &ri_data_##_var,                           \
452         .startup_delay = _sdelay                                \
453 };                                                              \
454 static struct platform_device fixed_reg_en_##_var##_dev = {     \
455         .name = "reg-fixed-voltage",                            \
456         .id = _id,                                              \
457         .dev = {                                                \
458                 .platform_data = &fixed_reg_en_##_var##_pdata,  \
459         },                                                      \
460 }
461
462 /* Always ON Battery regulator */
463 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
464                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
465 };
466
467 static struct regulator_consumer_supply fixed_reg_en_usb0_vbus_supply[] = {
468         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
469         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
470 };
471
472 static struct regulator_consumer_supply fixed_reg_en_usb1_vbus_supply[] = {
473         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
474         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
475 };
476
477 static struct regulator_consumer_supply fixed_reg_en_usb2_vbus_supply[] = {
478         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
479         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
480 };
481
482 static struct regulator_consumer_supply fixed_reg_en_palmas_gpio3_supply[] = {
483         REGULATOR_SUPPLY("avdd_lcd", NULL),
484 };
485
486 static struct regulator_consumer_supply fixed_reg_en_palmas_gpio4_supply[] = {
487         REGULATOR_SUPPLY("vdd_lcd_1v2_s", NULL),
488 };
489
490 static struct regulator_consumer_supply fixed_reg_en_palmas_gpio6_supply[] = {
491         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639"),
492 };
493
494 static struct regulator_consumer_supply fixed_reg_en_palmas_gpio7_supply[] = {
495         REGULATOR_SUPPLY("vpp_fuse", NULL),
496 };
497
498 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_en_supply[] = {
499         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
500 };
501
502 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
503         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
504 };
505
506 FIXED_REG(0,    battery,        battery,        NULL,
507         0,      0,      -1,
508         false,  true,   0,      3300, 0);
509
510 FIXED_REG(1,    usb0_vbus,      usb0_vbus,      NULL,
511         0,      0,      TEGRA_GPIO_PN4,
512         false,  true,   0,      5000,   0);
513
514 FIXED_REG(2,    usb1_vbus,      usb1_vbus,      palmas_rails(smps10),
515         0,      0,      TEGRA_GPIO_PN5,
516         false,  true,   0,      5000,   0);
517
518 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
519 FIXED_REG(3,    usb2_vbus,      usb2_vbus,      palmas_rails(smps10),
520         0,      0,      TEGRA_GPIO_PFF1,
521         false,  true,   0,      5000,   0);
522 #else
523 FIXED_REG(3,    usb2_vbus,      usb2_vbus,      palmas_rails(smps10),
524         0,      0,      -1,
525         false,  true,   0,      5000,   0);
526 #endif
527
528 FIXED_REG(4,    palmas_gpio3,   palmas_gpio3,   palmas_rails(smps9),
529         0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,
530         false,  true,   0,      3300,   0);
531
532 FIXED_REG(5,    palmas_gpio4,   palmas_gpio4,   palmas_rails(smps8),
533         0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,
534         false,  true,   0,      1200,   0);
535
536 FIXED_REG(6,    palmas_gpio6,   palmas_gpio6,   palmas_rails(smps8),
537         0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,
538         false,  true,   0,      1200,   0);
539
540 FIXED_REG(7,    palmas_gpio7,   palmas_gpio7,   palmas_rails(smps8),
541         0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO7,
542         false,  true,   0,      1800,   0);
543
544 FIXED_REG(8,    lcd_bl_en,      lcd_bl_en, NULL,
545         0,      0, TEGRA_GPIO_PH2,
546         false,  true,   0,      5000,   0);
547
548 FIXED_REG(9,    vdd_hdmi_5v0,   vdd_hdmi_5v0, palmas_rails(smps10),
549         0,      0, TEGRA_GPIO_PK6,
550         false,  true,   0,      5000,   0);
551
552 /*
553  * Creating fixed regulator device tables
554  */
555 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
556 #define TN8_E1736_FIXED_REG             \
557         ADD_FIXED_REG(battery),         \
558         ADD_FIXED_REG(usb0_vbus),       \
559         ADD_FIXED_REG(usb1_vbus),       \
560         ADD_FIXED_REG(usb2_vbus),       \
561         ADD_FIXED_REG(palmas_gpio3),    \
562         ADD_FIXED_REG(palmas_gpio4),    \
563         ADD_FIXED_REG(palmas_gpio6),    \
564         ADD_FIXED_REG(palmas_gpio7),    \
565         ADD_FIXED_REG(lcd_bl_en),       \
566         ADD_FIXED_REG(vdd_hdmi_5v0),
567
568
569 static struct platform_device *fixed_reg_devs_e1736[] = {
570         TN8_E1736_FIXED_REG
571 };
572
573 static int __init tn8_fixed_regulator_init(void)
574 {
575         struct board_info pmu_board_info;
576
577         if (!of_machine_is_compatible("nvidia,ardbeg"))
578                 return 0;
579
580         tegra_get_pmu_board_info(&pmu_board_info);
581
582         if (pmu_board_info.board_id == BOARD_E1736)
583                 return platform_add_devices(fixed_reg_devs_e1736,
584                         ARRAY_SIZE(fixed_reg_devs_e1736));
585
586         return 0;
587 }
588
589 subsys_initcall_sync(tn8_fixed_regulator_init);