ARM: tegra: enable unaligned_dma_buf_support
[linux-3.10.git] / arch / arm / mach-tegra / board-roth.c
1 /*
2  * arch/arm/mach-tegra/board-roth.c
3  *
4  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/delay.h>
30 #include <linux/i2c-tegra.h>
31 #include <linux/gpio.h>
32 #include <linux/input.h>
33 #include <linux/platform_data/tegra_usb.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/rm31080a_ts.h>
36 #include <linux/spi-tegra.h>
37 #include <linux/tegra_uart.h>
38 #include <linux/memblock.h>
39 #include <linux/rfkill-gpio.h>
40 #include <linux/skbuff.h>
41 #include <linux/ti_wilink_st.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/max17048_battery.h>
44 #include <linux/leds.h>
45 #include <linux/leds_pwm.h>
46 #include <linux/i2c/at24.h>
47 #include <linux/of_platform.h>
48 #include <linux/usb/tegra_usb_phy.h>
49 #include <asm/hardware/gic.h>
50
51 #include <mach/clk.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/pinmux-tegra30.h>
55 #include <mach/io_dpd.h>
56 #include <mach/i2s.h>
57 #include <mach/isomgr.h>
58 #include <mach/tegra_asoc_pdata.h>
59 #include <asm/mach-types.h>
60 #include <asm/mach/arch.h>
61 #include <mach/gpio-tegra.h>
62 #include <mach/tegra_fiq_debugger.h>
63 #include <mach/edp.h>
64 #include <mach/hardware.h>
65
66 #include "board.h"
67 #include "board-common.h"
68 #include "clock.h"
69 #include "board-roth.h"
70 #include "devices.h"
71 #include "gpio-names.h"
72 #include "fuse.h"
73 #include "iomap.h"
74 #include "pm.h"
75 #include "common.h"
76 #include "tegra-board-id.h"
77 #include "board-touch-raydium.h"
78
79 #ifdef CONFIG_BT_BLUESLEEP
80 static struct rfkill_gpio_platform_data roth_bt_rfkill_pdata = {
81                 .name           = "bt_rfkill",
82                 .shutdown_gpio  = TEGRA_GPIO_PQ7,
83                 .type           = RFKILL_TYPE_BLUETOOTH,
84 };
85
86 static struct platform_device roth_bt_rfkill_device = {
87         .name = "rfkill_gpio",
88         .id             = -1,
89         .dev = {
90                 .platform_data = &roth_bt_rfkill_pdata,
91         },
92 };
93
94 static struct resource roth_bluesleep_resources[] = {
95         [0] = {
96                 .name = "gpio_host_wake",
97                         .start  = TEGRA_GPIO_PU6,
98                         .end    = TEGRA_GPIO_PU6,
99                         .flags  = IORESOURCE_IO,
100         },
101         [1] = {
102                 .name = "gpio_ext_wake",
103                         .start  = TEGRA_GPIO_PEE1,
104                         .end    = TEGRA_GPIO_PEE1,
105                         .flags  = IORESOURCE_IO,
106         },
107         [2] = {
108                 .name = "host_wake",
109                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
110         },
111 };
112
113 static struct platform_device roth_bluesleep_device = {
114         .name           = "bluesleep",
115         .id             = -1,
116         .num_resources  = ARRAY_SIZE(roth_bluesleep_resources),
117         .resource       = roth_bluesleep_resources,
118 };
119
120 static noinline void __init roth_setup_bt_rfkill(void)
121 {
122                 roth_bt_rfkill_pdata.reset_gpio = TEGRA_GPIO_PQ6;
123         platform_device_register(&roth_bt_rfkill_device);
124 }
125
126 static noinline void __init roth_setup_bluesleep(void)
127 {
128         roth_bluesleep_resources[2].start =
129                 roth_bluesleep_resources[2].end =
130                         gpio_to_irq(TEGRA_GPIO_PU6);
131         platform_device_register(&roth_bluesleep_device);
132         return;
133 }
134 #elif defined CONFIG_BLUEDROID_PM
135 static struct resource roth_bluedroid_pm_resources[] = {
136         [0] = {
137                 .name   = "shutdown_gpio",
138                 .start  = TEGRA_GPIO_PQ7,
139                 .end    = TEGRA_GPIO_PQ7,
140                 .flags  = IORESOURCE_IO,
141         },
142         [1] = {
143                 .name = "host_wake",
144                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
145         },
146         [2] = {
147                 .name = "gpio_ext_wake",
148                 .start  = TEGRA_GPIO_PEE1,
149                 .end    = TEGRA_GPIO_PEE1,
150                 .flags  = IORESOURCE_IO,
151         },
152         [3] = {
153                 .name = "gpio_host_wake",
154                 .start  = TEGRA_GPIO_PU6,
155                 .end    = TEGRA_GPIO_PU6,
156                 .flags  = IORESOURCE_IO,
157         },
158 };
159
160 static struct platform_device roth_bluedroid_pm_device = {
161         .name = "bluedroid_pm",
162         .id             = 0,
163         .num_resources  = ARRAY_SIZE(roth_bluedroid_pm_resources),
164         .resource       = roth_bluedroid_pm_resources,
165 };
166
167 static noinline void __init roth_setup_bluedroid_pm(void)
168 {
169         roth_bluedroid_pm_resources[1].start =
170                 roth_bluedroid_pm_resources[1].end =
171                                 gpio_to_irq(TEGRA_GPIO_PU6);
172         platform_device_register(&roth_bluedroid_pm_device);
173 }
174 #endif
175 static __initdata struct tegra_clk_init_table roth_clk_init_table[] = {
176         /* name         parent          rate            enabled */
177         { "pll_m",      NULL,           0,              false},
178         { "hda",        "pll_p",        108000000,      false},
179         { "hda2codec_2x", "pll_p",      48000000,       false},
180         { "pwm",        "pll_p",        37000000,       false},
181         { "blink",      "clk_32k",      32768,          true},
182         { "i2s1",       "pll_a_out0",   0,              false},
183         { "i2s3",       "pll_a_out0",   0,              false},
184         { "i2s4",       "pll_a_out0",   0,              false},
185         { "spdif_out",  "pll_a_out0",   0,              false},
186         { "d_audio",    "clk_m",        12000000,       false},
187         { "dam0",       "clk_m",        12000000,       false},
188         { "dam1",       "clk_m",        12000000,       false},
189         { "dam2",       "clk_m",        12000000,       false},
190         { "audio1",     "i2s1_sync",    0,              false},
191         { "audio3",     "i2s3_sync",    0,              false},
192         /* Setting vi_sensor-clk to true for validation purpose, will imapact
193          * power, later set to be false.*/
194         { "vi_sensor",  "pll_p",        150000000,      false},
195         { "cilab",      "pll_p",        150000000,      false},
196         { "cilcd",      "pll_p",        150000000,      false},
197         { "cile",       "pll_p",        150000000,      false},
198         { "i2c1",       "pll_p",        3200000,        false},
199         { "i2c2",       "pll_p",        3200000,        false},
200         { "i2c3",       "pll_p",        3200000,        false},
201         { "i2c4",       "pll_p",        3200000,        false},
202         { "i2c5",       "pll_p",        3200000,        false},
203         { NULL,         NULL,           0,              0},
204 };
205
206 static struct tegra_i2c_platform_data roth_i2c1_platform_data = {
207         .bus_clk_rate   = 100000,
208         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
209         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
210 };
211
212 static struct tegra_i2c_platform_data roth_i2c2_platform_data = {
213         .bus_clk_rate   = 100000,
214         .is_clkon_always = true,
215         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
216         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
217 };
218
219 static struct tegra_i2c_platform_data roth_i2c3_platform_data = {
220         .bus_clk_rate   = 100000,
221         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
222         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
223 };
224
225 static struct tegra_i2c_platform_data roth_i2c4_platform_data = {
226         .bus_clk_rate   = 10000,
227         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
228         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
229 };
230
231 static struct tegra_i2c_platform_data roth_i2c5_platform_data = {
232         .bus_clk_rate   = 400000,
233         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
234         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
235         .needs_cl_dvfs_clock = true,
236 };
237
238 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
239 static struct i2c_board_info __initdata rt5640_board_info = {
240         I2C_BOARD_INFO("rt5640", 0x1c),
241 };
242
243 static struct i2c_board_info __initdata roth_codec_tfa9887R_info = {
244         I2C_BOARD_INFO("tfa9887R", 0x37),
245 };
246
247 static struct i2c_board_info __initdata roth_codec_tfa9887L_info = {
248         I2C_BOARD_INFO("tfa9887L", 0x34),
249 };
250
251 /* On A01, Left Speaker is moved to 0x34 */
252 static struct i2c_board_info __initdata roth_codec_tfa9887L_info_a01 = {
253         I2C_BOARD_INFO("tfa9887L", 0x34),
254 };
255 #endif
256
257 static void roth_i2c_init(void)
258 {
259         struct board_info board_info;
260
261         tegra_get_board_info(&board_info);
262
263         tegra11_i2c_device1.dev.platform_data = &roth_i2c1_platform_data;
264         tegra11_i2c_device2.dev.platform_data = &roth_i2c2_platform_data;
265         tegra11_i2c_device3.dev.platform_data = &roth_i2c3_platform_data;
266         tegra11_i2c_device4.dev.platform_data = &roth_i2c4_platform_data;
267         tegra11_i2c_device5.dev.platform_data = &roth_i2c5_platform_data;
268
269         platform_device_register(&tegra11_i2c_device5);
270         platform_device_register(&tegra11_i2c_device4);
271         platform_device_register(&tegra11_i2c_device3);
272         platform_device_register(&tegra11_i2c_device2);
273         platform_device_register(&tegra11_i2c_device1);
274
275         i2c_register_board_info(0, &rt5640_board_info, 1);
276         i2c_register_board_info(0, &roth_codec_tfa9887R_info, 1);
277
278         if (board_info.fab >= BOARD_FAB_A01)
279                 i2c_register_board_info(0, &roth_codec_tfa9887L_info_a01, 1);
280         else
281                 i2c_register_board_info(0, &roth_codec_tfa9887L_info, 1);
282 }
283
284 static struct platform_device *roth_uart_devices[] __initdata = {
285         &tegra_uarta_device,
286         &tegra_uartb_device,
287         &tegra_uartc_device,
288         &tegra_uartd_device,
289 };
290 static struct uart_clk_parent uart_parent_clk[] = {
291         [0] = {.name = "clk_m"},
292         [1] = {.name = "pll_p"},
293 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
294         [2] = {.name = "pll_m"},
295 #endif
296 };
297
298 static struct tegra_uart_platform_data roth_uart_pdata;
299 static struct tegra_uart_platform_data roth_loopback_uart_pdata;
300
301 static void __init uart_debug_init(void)
302 {
303         int debug_port_id;
304
305         debug_port_id = uart_console_debug_init(3);
306         if (debug_port_id < 0)
307                 return;
308
309         roth_uart_devices[debug_port_id] = uart_console_debug_device;
310 }
311
312 static void __init roth_uart_init(void)
313 {
314         struct clk *c;
315         int i;
316
317         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
318                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
319                 if (IS_ERR_OR_NULL(c)) {
320                         pr_err("Not able to get the clock for %s\n",
321                                                 uart_parent_clk[i].name);
322                         continue;
323                 }
324                 uart_parent_clk[i].parent_clk = c;
325                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
326         }
327         roth_uart_pdata.parent_clk_list = uart_parent_clk;
328         roth_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
329         roth_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
330         roth_loopback_uart_pdata.parent_clk_count =
331                                                 ARRAY_SIZE(uart_parent_clk);
332         roth_loopback_uart_pdata.is_loopback = true;
333         tegra_uarta_device.dev.platform_data = &roth_uart_pdata;
334         tegra_uartb_device.dev.platform_data = &roth_uart_pdata;
335         tegra_uartc_device.dev.platform_data = &roth_uart_pdata;
336         tegra_uartd_device.dev.platform_data = &roth_uart_pdata;
337
338         /* Register low speed only if it is selected */
339         if (!is_tegra_debug_uartport_hs())
340                 uart_debug_init();
341
342         platform_add_devices(roth_uart_devices,
343                                 ARRAY_SIZE(roth_uart_devices));
344 }
345
346 static struct resource tegra_rtc_resources[] = {
347         [0] = {
348                 .start = TEGRA_RTC_BASE,
349                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
350                 .flags = IORESOURCE_MEM,
351         },
352         [1] = {
353                 .start = INT_RTC,
354                 .end = INT_RTC,
355                 .flags = IORESOURCE_IRQ,
356         },
357 };
358
359 static struct platform_device tegra_rtc_device = {
360         .name = "tegra_rtc",
361         .id   = -1,
362         .resource = tegra_rtc_resources,
363         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
364 };
365
366 static struct tegra_asoc_platform_data roth_audio_pdata = {
367         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
368         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
369         .gpio_hp_mute           = -1,
370         .gpio_int_mic_en        = TEGRA_GPIO_INT_MIC_EN,
371         .gpio_ext_mic_en        = TEGRA_GPIO_EXT_MIC_EN,
372         .gpio_ldo1_en           = TEGRA_GPIO_LDO1_EN,
373         .gpio_codec1 = TEGRA_GPIO_CODEC1_EN,
374         .gpio_codec2 = TEGRA_GPIO_CODEC2_EN,
375         .gpio_codec3 = TEGRA_GPIO_CODEC3_EN,
376         .i2s_param[HIFI_CODEC]  = {
377                 .audio_port_id  = 1,
378                 .is_i2s_master  = 1,
379                 .i2s_mode       = TEGRA_DAIFMT_I2S,
380         },
381         .i2s_param[BT_SCO]      = {
382                 .audio_port_id  = 3,
383                 .is_i2s_master  = 1,
384                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
385         },
386 };
387
388 static struct platform_device roth_audio_device = {
389         .name   = "tegra-snd-rt5640",
390         .id     = 0,
391         .dev    = {
392                 .platform_data = &roth_audio_pdata,
393         },
394 };
395
396 static struct platform_device tegra_camera = {
397         .name = "tegra_camera",
398         .id = -1,
399 };
400
401 static struct led_pwm roth_led_info[] = {
402         {
403                 .name                   = "roth-led",
404                 .default_trigger        = "none",
405                 .pwm_id                 = 2,
406                 .active_low             = 0,
407                 .max_brightness         = 255,
408                 .pwm_period_ns          = 10000000,
409         },
410 };
411
412 static struct led_pwm_platform_data roth_leds_pdata = {
413         .leds           = roth_led_info,
414         .num_leds       = ARRAY_SIZE(roth_led_info),
415 };
416
417 static struct platform_device roth_leds_pwm_device = {
418         .name   = "leds_pwm",
419         .id     = -1,
420         .dev    = {
421                 .platform_data = &roth_leds_pdata,
422         },
423 };
424
425
426 static struct platform_device *roth_devices[] __initdata = {
427         &tegra_pmu_device,
428         &tegra_rtc_device,
429         &tegra_udc_device,
430 #if defined(CONFIG_TEGRA_AVP)
431         &tegra_avp_device,
432 #endif
433         &tegra_camera,
434 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
435         &tegra11_se_device,
436 #endif
437         &tegra_ahub_device,
438         &tegra_dam_device0,
439         &tegra_dam_device1,
440         &tegra_dam_device2,
441         &tegra_i2s_device1,
442         &tegra_i2s_device3,
443         &tegra_i2s_device4,
444         &tegra_spdif_device,
445         &spdif_dit_device,
446         &bluetooth_dit_device,
447         &roth_audio_device,
448         &tegra_hda_device,
449 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
450         &tegra_aes_device,
451 #endif
452
453         &tegra_pwfm_device,
454         &roth_leds_pwm_device,
455 };
456
457 #ifdef CONFIG_USB_SUPPORT
458 static struct tegra_usb_platform_data tegra_udc_pdata = {
459         .port_otg = true,
460         .has_hostpc = true,
461         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
462         .op_mode = TEGRA_USB_OPMODE_DEVICE,
463         .u_data.dev = {
464                 .vbus_pmu_irq = 0,
465                 .vbus_gpio = -1,
466                 .charging_supported = false,
467                 .remote_wakeup_supported = false,
468         },
469         .u_cfg.utmi = {
470                 .hssync_start_delay = 0,
471                 .elastic_limit = 16,
472                 .idle_wait_delay = 17,
473                 .term_range_adj = 6,
474                 .xcvr_setup = 8,
475                 .xcvr_lsfslew = 2,
476                 .xcvr_lsrslew = 2,
477                 .xcvr_setup_offset = 0,
478                 .xcvr_use_fuses = 1,
479         },
480 };
481
482 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
483         .port_otg = true,
484         .has_hostpc = true,
485         .unaligned_dma_buf_supported = false,
486         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
487         .op_mode = TEGRA_USB_OPMODE_HOST,
488         .u_data.host = {
489                 .vbus_gpio = -1,
490                 .hot_plug = true,
491                 .remote_wakeup_supported = true,
492                 .power_off_on_suspend = false,
493         },
494         .u_cfg.utmi = {
495                 .hssync_start_delay = 0,
496                 .elastic_limit = 16,
497                 .idle_wait_delay = 17,
498                 .term_range_adj = 6,
499                 .xcvr_setup = 15,
500                 .xcvr_lsfslew = 2,
501                 .xcvr_lsrslew = 2,
502                 .xcvr_setup_offset = 0,
503                 .xcvr_use_fuses = 1,
504                 .vbus_oc_map = 0x4,
505         },
506 };
507
508 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
509         .port_otg = false,
510         .has_hostpc = true,
511         .unaligned_dma_buf_supported = false,
512         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
513         .op_mode = TEGRA_USB_OPMODE_HOST,
514         .u_data.host = {
515                 .vbus_gpio = -1,
516                 .hot_plug = true,
517                 .remote_wakeup_supported = true,
518                 .power_off_on_suspend = false,
519         },
520         .u_cfg.utmi = {
521         .hssync_start_delay = 0,
522                 .elastic_limit = 16,
523                 .idle_wait_delay = 17,
524                 .term_range_adj = 6,
525                 .xcvr_setup = 8,
526                 .xcvr_lsfslew = 2,
527                 .xcvr_lsrslew = 2,
528                 .xcvr_setup_offset = 0,
529                 .xcvr_use_fuses = 1,
530                 .vbus_oc_map = 0x5,
531         },
532 };
533
534 static struct tegra_usb_otg_data tegra_otg_pdata = {
535         .ehci_device = &tegra_ehci1_device,
536         .ehci_pdata = &tegra_ehci1_utmi_pdata,
537 };
538
539 static void roth_usb_init(void)
540 {
541         if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
542                 && (tegra_revision == TEGRA_REVISION_A02)) {
543                 tegra_ehci1_utmi_pdata \
544                 .unaligned_dma_buf_supported = true;
545                 tegra_udc_pdata.unaligned_dma_buf_supported = true;
546                 tegra_ehci3_utmi_pdata \
547                 .unaligned_dma_buf_supported = true;
548         }
549         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
550         platform_device_register(&tegra_otg_device);
551
552         /* Setup the udc platform data */
553         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
554
555         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
556         platform_device_register(&tegra_ehci3_device);
557 }
558
559 #else
560 static void roth_usb_init(void) { }
561 #endif
562
563 static void roth_audio_init(void)
564 {
565         struct board_info board_info;
566
567         tegra_get_board_info(&board_info);
568
569         roth_audio_pdata.codec_name = "rt5640.0-001c";
570         roth_audio_pdata.codec_dai_name = "rt5640-aif1";
571 }
572
573
574 static struct platform_device *roth_spi_devices[] __initdata = {
575         &tegra11_spi_device4,
576 };
577
578 struct spi_clk_parent spi_parent_clk_roth[] = {
579         [0] = {.name = "pll_p"},
580 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
581         [1] = {.name = "pll_m"},
582         [2] = {.name = "clk_m"},
583 #else
584         [1] = {.name = "clk_m"},
585 #endif
586 };
587
588 static struct tegra_spi_platform_data roth_spi_pdata = {
589         .is_dma_based           = false,
590         .max_dma_buffer         = 16 * 1024,
591         .is_clkon_always        = false,
592         .max_rate               = 25000000,
593 };
594
595 static void __init roth_spi_init(void)
596 {
597         int i;
598         struct clk *c;
599
600         for (i = 0; i < ARRAY_SIZE(spi_parent_clk_roth); ++i) {
601                 c = tegra_get_clock_by_name(spi_parent_clk_roth[i].name);
602                 if (IS_ERR_OR_NULL(c)) {
603                         pr_err("Not able to get the clock for %s\n",
604                                 spi_parent_clk_roth[i].name);
605                         continue;
606                 }
607                 spi_parent_clk_roth[i].parent_clk = c;
608                 spi_parent_clk_roth[i].fixed_clk_rate = clk_get_rate(c);
609         }
610         roth_spi_pdata.parent_clk_list = spi_parent_clk_roth;
611         roth_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk_roth);
612         tegra11_spi_device4.dev.platform_data = &roth_spi_pdata;
613         platform_add_devices(roth_spi_devices,
614                 ARRAY_SIZE(roth_spi_devices));
615 }
616
617 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
618         /* name         parent          rate            enabled */
619         { "extern2",    "pll_p",        41000000,       false},
620         { "clk_out_2",  "extern2",      40800000,       false},
621         { NULL,         NULL,           0,              0},
622 };
623
624 struct rm_spi_ts_platform_data rm31080ts_roth_data = {
625         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
626         .config = 0,
627         .platform_id = RM_PLATFORM_D010,
628         .name_of_clock = "clk_out_2",
629         .name_of_clock_con = "extern2",
630 };
631
632 static struct tegra_spi_device_controller_data dev_cdata = {
633         .rx_clk_tap_delay = 0,
634         .tx_clk_tap_delay = 16,
635 };
636
637 struct spi_board_info rm31080a_roth_spi_board[1] = {
638         {
639          .modalias = "rm_ts_spidev",
640          .bus_num = 3,
641          .chip_select = 2,
642          .max_speed_hz = 12 * 1000 * 1000,
643          .mode = SPI_MODE_0,
644          .controller_data = &dev_cdata,
645          .platform_data = &rm31080ts_roth_data,
646          },
647 };
648
649 static int __init roth_touch_init(void)
650 {
651         tegra_clk_init_from_table(touch_clk_init_table);
652         rm31080ts_roth_data.platform_id = RM_PLATFORM_R005;
653         rm31080a_roth_spi_board[0].irq =
654                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
655         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
656                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
657                                 &rm31080ts_roth_data,
658                                 &rm31080a_roth_spi_board[0],
659                                 ARRAY_SIZE(rm31080a_roth_spi_board));
660         return 0;
661 }
662
663 static void __init tegra_roth_init(void)
664 {
665         tegra_clk_init_from_table(roth_clk_init_table);
666         tegra_clk_verify_parents();
667         tegra_soc_device_init("roth");
668         tegra_enable_pinmux();
669         roth_pinmux_init();
670         roth_i2c_init();
671         roth_spi_init();
672         roth_usb_init();
673         roth_uart_init();
674         roth_audio_init();
675         platform_add_devices(roth_devices, ARRAY_SIZE(roth_devices));
676         //tegra_ram_console_debug_init();
677         tegra_io_dpd_init();
678         roth_regulator_init();
679         roth_sdhci_init();
680         roth_suspend_init();
681         roth_emc_init();
682         roth_edp_init();
683         isomgr_init();
684         roth_touch_init();
685         /* roth will pass a null board id to panel_init */
686         roth_panel_init(0);
687         roth_kbc_init();
688         roth_pmon_init();
689 #ifdef CONFIG_BT_BLUESLEEP
690         roth_setup_bluesleep();
691         roth_setup_bt_rfkill();
692 #elif defined CONFIG_BLUEDROID_PM
693         roth_setup_bluedroid_pm();
694 #endif
695         tegra_release_bootloader_fb();
696 #ifdef CONFIG_TEGRA_WDT_RECOVERY
697         tegra_wdt_recovery_init();
698 #endif
699         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
700         roth_sensors_init();
701         roth_soctherm_init();
702         roth_fan_init();
703         tegra_register_fuse();
704 }
705
706 static void __init roth_ramconsole_reserve(unsigned long size)
707 {
708         tegra_ram_console_debug_reserve(SZ_1M);
709 }
710
711 #ifdef CONFIG_USE_OF
712 struct of_dev_auxdata roth_auxdata_lookup[] __initdata = {
713         OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x",
714                 NULL),
715         OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d", NULL),
716         OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d", NULL),
717         OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc",
718                 NULL),
719         OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi", NULL),
720         OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp", NULL),
721         OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
722         {}
723 };
724 #endif
725
726 static void __init tegra_roth_dt_init(void)
727 {
728 #ifdef CONFIG_USE_OF
729         of_platform_populate(NULL,
730                 of_default_bus_match_table, roth_auxdata_lookup,
731                 &platform_bus);
732 #endif
733
734         tegra_roth_init();
735 }
736
737 static void __init tegra_roth_reserve(void)
738 {
739 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
740         /* 1920*1200*4*2 = 18432000 bytes */
741         tegra_reserve(0, SZ_16M + SZ_2M, SZ_4M);
742 #else
743         tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M);
744 #endif
745         roth_ramconsole_reserve(SZ_1M);
746 }
747
748 static const char * const roth_dt_board_compat[] = {
749         "nvidia,roth",
750         NULL
751 };
752
753 MACHINE_START(ROTH, "roth")
754         .atag_offset    = 0x100,
755         .smp            = smp_ops(tegra_smp_ops),
756         .map_io         = tegra_map_common_io,
757         .reserve        = tegra_roth_reserve,
758         .init_early     = tegra11x_init_early,
759         .init_irq       = tegra_dt_init_irq,
760         .handle_irq     = gic_handle_irq,
761         .timer          = &tegra_sys_timer,
762         .init_machine   = tegra_roth_dt_init,
763         .restart        = tegra_assert_system_reset,
764         .dt_compat      = roth_dt_board_compat,
765 MACHINE_END