ARM: tegra: roth: initialize soc therm in arch init
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/gpio.h>
31 #include <linux/regulator/userspace-consumer.h>
32
33 #include <asm/mach-types.h>
34
35 #include <mach/iomap.h>
36 #include <mach/irqs.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "cpu-tegra.h"
41 #include "pm.h"
42 #include "tegra-board-id.h"
43 #include "board.h"
44 #include "gpio-names.h"
45 #include "board-roth.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49
50 #define PMC_CTRL                0x0
51 #define PMC_CTRL_INTR_LOW       (1 << 17)
52
53 /* TPS51632 DC-DC converter */
54 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
55         REGULATOR_SUPPLY("vdd_cpu", NULL),
56 };
57
58 static struct regulator_init_data tps51632_init_data = {
59         .constraints = {                                                \
60                 .min_uV = 500000,                                       \
61                 .max_uV = 1520000,                                      \
62                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
63                                         REGULATOR_MODE_STANDBY),        \
64                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
65                                         REGULATOR_CHANGE_STATUS |       \
66                                         REGULATOR_CHANGE_VOLTAGE),      \
67                 .always_on = 1,                                         \
68                 .boot_on =  1,                                          \
69                 .apply_uV = 0,                                          \
70         },                                                              \
71         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
72                 .consumer_supplies = tps51632_dcdc_supply,              \
73 };
74
75 static struct tps51632_regulator_platform_data tps51632_pdata = {
76         .reg_init_data = &tps51632_init_data,           \
77         .enable_pwm = false,                            \
78         .max_voltage_uV = 1520000,                      \
79         .base_voltage_uV = 500000,                      \
80         .slew_rate_uv_per_us = 6000,                    \
81 };
82
83 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
84         {
85                 I2C_BOARD_INFO("tps51632", 0x43),
86                 .platform_data  = &tps51632_pdata,
87         },
88 };
89
90 /************************ Palmas based regulator ****************/
91 static struct regulator_consumer_supply palmas_smps12_supply[] = {
92         REGULATOR_SUPPLY("vddio_ddr0", NULL),
93         REGULATOR_SUPPLY("vddio_ddr1", NULL),
94 };
95
96 static struct regulator_consumer_supply palmas_smps3_supply[] = {
97         REGULATOR_SUPPLY("avdd_osc", NULL),
98         REGULATOR_SUPPLY("vddio_sys", NULL),
99         REGULATOR_SUPPLY("vddio_gmi", NULL),
100         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
101         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
102         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
103         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
104         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
105         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
106         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
107         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
108         REGULATOR_SUPPLY("vddio_audio", NULL),
109         REGULATOR_SUPPLY("pwrdet_audio", NULL),
110         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
111         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
112         REGULATOR_SUPPLY("vddio_uart", NULL),
113         REGULATOR_SUPPLY("pwrdet_uart", NULL),
114         REGULATOR_SUPPLY("dbvdd", NULL),
115 };
116
117 static struct regulator_consumer_supply palmas_smps45_supply[] = {
118         REGULATOR_SUPPLY("vdd_core", NULL),
119 };
120
121 static struct regulator_consumer_supply palmas_smps8_supply[] = {
122         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
123         REGULATOR_SUPPLY("avdd_pllx", NULL),
124         REGULATOR_SUPPLY("avdd_pllm", NULL),
125         REGULATOR_SUPPLY("avdd_pllu", NULL),
126         REGULATOR_SUPPLY("avdd_plle", NULL),
127         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
128         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
129         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
130         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
131         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
132         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
133         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
134 };
135
136 static struct regulator_consumer_supply palmas_smps9_supply[] = {
137         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
138 };
139
140 static struct regulator_consumer_supply palmas_smps10_supply[] = {
141         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
142         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
143         REGULATOR_SUPPLY("vdd_lcd", NULL),
144         REGULATOR_SUPPLY("vdd_5v0", NULL),
145 };
146
147 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
148         REGULATOR_SUPPLY("vdd_2v8_display", NULL),
149         REGULATOR_SUPPLY("vci_2v8", NULL),
150 };
151
152 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
153         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
154         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
155         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
156         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
157 };
158
159 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
160         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
161 };
162
163 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
164         REGULATOR_SUPPLY("vdd_rtc", NULL),
165 };
166
167 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
168         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
169         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
170 };
171
172 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
173         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
174         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
175         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
176         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
177         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
178         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
179 };
180
181 static struct regulator_consumer_supply palmas_regen1_supply[] = {
182         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
183         REGULATOR_SUPPLY("vdd", "4-004c"),
184         REGULATOR_SUPPLY("vdd", "0-004c"),
185         REGULATOR_SUPPLY("vdd", "0-004d"),
186 };
187
188 static struct regulator_consumer_supply palmas_regen2_supply[] = {
189         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
190 };
191
192 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
193         _boot_on, _apply_uv)                                            \
194         static struct regulator_init_data reg_idata_##_name = {         \
195                 .constraints = {                                        \
196                         .name = palmas_rails(_name),                    \
197                         .min_uV = (_minmv)*1000,                        \
198                         .max_uV = (_maxmv)*1000,                        \
199                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
200                                         REGULATOR_MODE_STANDBY),        \
201                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
202                                         REGULATOR_CHANGE_STATUS |       \
203                                         REGULATOR_CHANGE_VOLTAGE),      \
204                         .always_on = _always_on,                        \
205                         .boot_on = _boot_on,                            \
206                         .apply_uV = _apply_uv,                          \
207                 },                                                      \
208                 .num_consumer_supplies =                                \
209                         ARRAY_SIZE(palmas_##_name##_supply),            \
210                 .consumer_supplies = palmas_##_name##_supply,           \
211                 .supply_regulator = _supply_reg,                        \
212         }
213
214 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
215 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
216 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
217 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 0, 1, 1);
218 PALMAS_PDATA_INIT(smps9, 2850,  2850, NULL, 0, 0, 0);
219 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
220 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
221 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 0, 0, 1);
222 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
223 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
224 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
225 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
226 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
227 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
228
229 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
230 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
231         PALMAS_REG_PDATA(smps12),
232         NULL,
233         PALMAS_REG_PDATA(smps3),
234         PALMAS_REG_PDATA(smps45),
235         NULL,
236         NULL,
237         NULL,
238         PALMAS_REG_PDATA(smps8),
239         PALMAS_REG_PDATA(smps9),
240         PALMAS_REG_PDATA(smps10),
241         NULL,   /* LDO1 */
242         PALMAS_REG_PDATA(ldo2),
243         PALMAS_REG_PDATA(ldo3),
244         NULL,
245         NULL,
246         PALMAS_REG_PDATA(ldo6),
247         NULL,
248         PALMAS_REG_PDATA(ldo8),
249         PALMAS_REG_PDATA(ldo9),
250         NULL,
251         PALMAS_REG_PDATA(ldousb),
252         PALMAS_REG_PDATA(regen1),
253         PALMAS_REG_PDATA(regen2),
254         NULL,
255         NULL,
256         NULL,
257 };
258
259 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
260                 _tstep, _vsel)                                          \
261         static struct palmas_reg_init reg_init_data_##_name = {         \
262                 .warm_reset = _warm_reset,                              \
263                 .roof_floor =   _roof_floor,                            \
264                 .mode_sleep = _mode_sleep,                              \
265                 .tstep = _tstep,                                        \
266                 .vsel = _vsel,                                          \
267         }
268
269 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
270 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
271 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
272 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
273 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
274 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
275 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
276 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
277 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
278 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
279 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
280 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
281 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
282 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
283 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
284 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
285 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
286 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
287 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
288 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
289 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
291 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
295
296 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
297 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
298         PALMAS_REG_INIT_DATA(smps12),
299         PALMAS_REG_INIT_DATA(smps123),
300         PALMAS_REG_INIT_DATA(smps3),
301         PALMAS_REG_INIT_DATA(smps45),
302         PALMAS_REG_INIT_DATA(smps457),
303         PALMAS_REG_INIT_DATA(smps6),
304         PALMAS_REG_INIT_DATA(smps7),
305         PALMAS_REG_INIT_DATA(smps8),
306         PALMAS_REG_INIT_DATA(smps9),
307         PALMAS_REG_INIT_DATA(smps10),
308         PALMAS_REG_INIT_DATA(ldo1),
309         PALMAS_REG_INIT_DATA(ldo2),
310         PALMAS_REG_INIT_DATA(ldo3),
311         PALMAS_REG_INIT_DATA(ldo4),
312         PALMAS_REG_INIT_DATA(ldo5),
313         PALMAS_REG_INIT_DATA(ldo6),
314         PALMAS_REG_INIT_DATA(ldo7),
315         PALMAS_REG_INIT_DATA(ldo8),
316         PALMAS_REG_INIT_DATA(ldo9),
317         PALMAS_REG_INIT_DATA(ldoln),
318         PALMAS_REG_INIT_DATA(ldousb),
319         PALMAS_REG_INIT_DATA(regen1),
320         PALMAS_REG_INIT_DATA(regen2),
321         PALMAS_REG_INIT_DATA(regen3),
322         PALMAS_REG_INIT_DATA(sysen1),
323         PALMAS_REG_INIT_DATA(sysen2),
324 };
325
326 static struct palmas_pmic_platform_data pmic_platform = {
327         .enable_ldo8_tracking = true,
328         .disabe_ldo8_tracking_suspend = true,
329 };
330
331 static struct palmas_platform_data palmas_pdata = {
332         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
333         .irq_base = PALMAS_TEGRA_IRQ_BASE,
334         .pmic_pdata = &pmic_platform,
335         .mux_from_pdata = true,
336         .pad1 = 0,
337         .pad2 = 0,
338         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
339         .use_power_off = true,
340 };
341
342 static struct i2c_board_info palma_device[] = {
343         {
344                 I2C_BOARD_INFO("tps65913", 0x58),
345                 .irq            = INT_EXTERNAL_PMU,
346                 .platform_data  = &palmas_pdata,
347         },
348 };
349
350 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
351         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
352 };
353
354 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
355         REGULATOR_SUPPLY("fan_5v0", NULL),
356 };
357
358 /* LCD_BL_EN GMI_AD10 */
359 static struct regulator_consumer_supply fixed_reg_lcd_bl_supply[] = {
360         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
361 };
362
363 /* Touch 3v3 GMI_AD13 */
364 static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
365         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
366         REGULATOR_SUPPLY("vdd_display", NULL),
367 };
368
369 /* VDD_3V3_COM controled by Wifi */
370 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
371         REGULATOR_SUPPLY("vdd_3v3_com", NULL),
372 };
373
374 /* VDD_1v8_COM controled by Wifi */
375 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
376         REGULATOR_SUPPLY("vdd_1v8_com", NULL),
377 };
378
379 /* vdd_3v3_sd PH0 */
380 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
381         REGULATOR_SUPPLY("vdd_3v3_sd", NULL),
382 };
383
384 /* Macro for defining fixed regulator sub device data */
385 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
386 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
387         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
388         static struct regulator_init_data ri_data_##_var =              \
389         {                                                               \
390                 .supply_regulator = _in_supply,                         \
391                 .num_consumer_supplies =                                \
392                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
393                 .consumer_supplies = fixed_reg_##_name##_supply,        \
394                 .constraints = {                                        \
395                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
396                                         REGULATOR_MODE_STANDBY),        \
397                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
398                                         REGULATOR_CHANGE_STATUS |       \
399                                         REGULATOR_CHANGE_VOLTAGE),      \
400                         .always_on = _always_on,                        \
401                         .boot_on = _boot_on,                            \
402                 },                                                      \
403         };                                                              \
404         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
405         {                                                               \
406                 .supply_name = FIXED_SUPPLY(_name),                     \
407                 .microvolts = _millivolts * 1000,                       \
408                 .gpio = _gpio_nr,                                       \
409                 .gpio_is_open_drain = _open_drain,                      \
410                 .enable_high = _active_high,                            \
411                 .enabled_at_boot = _boot_state,                         \
412                 .init_data = &ri_data_##_var,                           \
413         };                                                              \
414         static struct platform_device fixed_reg_##_var##_dev = {        \
415                 .name = "reg-fixed-voltage",                            \
416                 .id = _id,                                              \
417                 .dev = {                                                \
418                         .platform_data = &fixed_reg_##_var##_pdata,     \
419                 },                                                      \
420         }
421
422 FIXED_REG(3,    fan_5v0,        fan_5v0,
423         palmas_rails(smps10),   0,      0,
424         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
425
426 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
427         palmas_rails(smps10),   0,      0,
428         TEGRA_GPIO_PK1, false,  true,   0,      5000);
429
430 FIXED_REG(3,    lcd_bl, lcd_bl,
431         NULL,   0,      0,
432         TEGRA_GPIO_PH2, false,  true,   0,      5000);
433
434 FIXED_REG(3,    ts_3v3, ts_3v3,
435         palmas_rails(regen1),   0,      0,
436         TEGRA_GPIO_PH5, false,  true,   0,      3300);
437
438 FIXED_REG(3,    com_3v3,        com_3v3,
439         palmas_rails(regen1),   0,      0,
440         -1,     false,  true,   0,      3300);
441
442 FIXED_REG(3,    sd_3v3, sd_3v3,
443         palmas_rails(regen1),   0,      0,
444         TEGRA_GPIO_PH0, false,  true,   0,      3300);
445
446 FIXED_REG(3,    com_1v8,        com_1v8,
447         palmas_rails(smps3),    0,      0,
448         -1,     false,  true,   0,      1800);
449
450 /*
451  * Creating the fixed regulator device tables
452  */
453
454 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
455
456 #define ROTH_COMMON_FIXED_REG           \
457         ADD_FIXED_REG(usb1_vbus),               \
458         ADD_FIXED_REG(usb3_vbus),               \
459         ADD_FIXED_REG(vdd_hdmi_5v0),
460
461 #define E1612_FIXED_REG                         \
462         ADD_FIXED_REG(avdd_usb_hdmi),           \
463         ADD_FIXED_REG(en_1v8_cam),              \
464         ADD_FIXED_REG(vpp_fuse),                \
465
466 #define ROTH_FIXED_REG                          \
467         ADD_FIXED_REG(en_1v8_cam_roth),
468
469 /* Gpio switch regulator platform data for Roth */
470 static struct platform_device *fixed_reg_devs_roth[] = {
471         ADD_FIXED_REG(fan_5v0),
472         ADD_FIXED_REG(vdd_hdmi_5v0),
473         ADD_FIXED_REG(lcd_bl),
474         ADD_FIXED_REG(ts_3v3),
475         ADD_FIXED_REG(com_3v3),
476         ADD_FIXED_REG(sd_3v3),
477         ADD_FIXED_REG(com_1v8),
478 };
479
480 int __init roth_palmas_regulator_init(void)
481 {
482         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
483         u32 pmc_ctrl;
484         int i;
485
486         /* TPS65913: Normal state of INT request line is LOW.
487          * configure the power management controller to trigger PMU
488          * interrupts when HIGH.
489          */
490         pmc_ctrl = readl(pmc + PMC_CTRL);
491         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
492         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
493                 pmic_platform.reg_data[i] = roth_reg_data[i];
494                 pmic_platform.reg_init[i] = roth_reg_init[i];
495         }
496
497         i2c_register_board_info(4, palma_device,
498                         ARRAY_SIZE(palma_device));
499         return 0;
500 }
501
502 static int ac_online(void)
503 {
504         return 1;
505 }
506
507 static struct resource roth_pda_resources[] = {
508         [0] = {
509                 .name   = "ac",
510         },
511 };
512
513 static struct pda_power_pdata roth_pda_data = {
514         .is_ac_online   = ac_online,
515 };
516
517 static struct platform_device roth_pda_power_device = {
518         .name           = "pda-power",
519         .id             = -1,
520         .resource       = roth_pda_resources,
521         .num_resources  = ARRAY_SIZE(roth_pda_resources),
522         .dev    = {
523                 .platform_data  = &roth_pda_data,
524         },
525 };
526
527 static struct tegra_suspend_platform_data roth_suspend_data = {
528         .cpu_timer      = 300,
529         .cpu_off_timer  = 300,
530         .suspend_mode   = TEGRA_SUSPEND_LP0,
531         .core_timer     = 0x157e,
532         .core_off_timer = 2000,
533         .corereq_high   = true,
534         .sysclkreq_high = true,
535         .min_residency_noncpu = 600,
536         .min_residency_crail = 1000,
537 };
538 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
539 /* board parameters for cpu dfll */
540 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
541         .sample_rate = 12500,
542
543         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
544         .cf = 10,
545         .ci = 0,
546         .cg = 2,
547
548         .droop_cut_value = 0xF,
549         .droop_restore_ramp = 0x0,
550         .scale_out_ramp = 0x0,
551 };
552 #endif
553
554 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
555 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
556 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
557 static inline void fill_reg_map(void)
558 {
559         int i;
560         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
561                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
562                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
563         }
564 }
565
566 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
567 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
568         .dfll_clk_name = "dfll_cpu",
569         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
570         .u.pmu_i2c = {
571                 .fs_rate = 400000,
572                 .slave_addr = 0x86,
573                 .reg = 0x00,
574         },
575         .vdd_map = pmu_cpu_vdd_map,
576         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
577
578         .cfg_param = &roth_cl_dvfs_param,
579 };
580
581 static int __init roth_cl_dvfs_init(void)
582 {
583         fill_reg_map();
584         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
585         platform_device_register(&tegra_cl_dvfs_device);
586
587         return 0;
588 }
589 #endif
590
591 static struct regulator_bulk_data roth_gps_regulator_supply[] = {
592         [0] = {
593                 .supply = "vdd_gps_3v3",
594         },
595         [1] = {
596                 .supply = "vdd_gps_1v8",
597         },
598 };
599
600 static struct regulator_userspace_consumer_data roth_gps_regulator_pdata = {
601         .num_supplies   = ARRAY_SIZE(roth_gps_regulator_supply),
602         .supplies       = roth_gps_regulator_supply,
603 };
604
605 static struct platform_device roth_gps_regulator_device = {
606         .name   = "reg-userspace-consumer",
607         .id     = 2,
608         .dev    = {
609                         .platform_data = &roth_gps_regulator_pdata,
610         },
611 };
612
613 static struct regulator_bulk_data roth_bt_regulator_supply[] = {
614         [0] = {
615                 .supply = "vdd_bt_3v3",
616         },
617         [1] = {
618                 .supply = "vddio_bt_1v8",
619         },
620 };
621
622 static struct regulator_userspace_consumer_data roth_bt_regulator_pdata = {
623         .num_supplies   = ARRAY_SIZE(roth_bt_regulator_supply),
624         .supplies       = roth_bt_regulator_supply,
625 };
626
627 static struct platform_device roth_bt_regulator_device = {
628         .name   = "reg-userspace-consumer",
629         .id     = 1,
630         .dev    = {
631                         .platform_data = &roth_bt_regulator_pdata,
632         },
633 };
634
635 static int __init roth_fixed_regulator_init(void)
636 {
637         if (!machine_is_roth())
638                 return 0;
639
640         return platform_add_devices(fixed_reg_devs_roth,
641                                 ARRAY_SIZE(fixed_reg_devs_roth));
642 }
643 subsys_initcall_sync(roth_fixed_regulator_init);
644
645 int __init roth_regulator_init(void)
646 {
647         struct board_info board_info;
648 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
649         roth_cl_dvfs_init();
650 #endif
651         tegra_get_board_info(&board_info);
652         roth_palmas_regulator_init();
653
654         i2c_register_board_info(4, tps51632_boardinfo, 1);
655         platform_device_register(&roth_pda_power_device);
656         platform_device_register(&roth_bt_regulator_device);
657         platform_device_register(&roth_gps_regulator_device);
658         return 0;
659 }
660
661 int __init roth_suspend_init(void)
662 {
663         tegra_init_suspend(&roth_suspend_data);
664         return 0;
665 }
666
667 int __init roth_edp_init(void)
668 {
669 #ifdef CONFIG_TEGRA_EDP_LIMITS
670         unsigned int regulator_mA;
671
672         regulator_mA = get_maximum_cpu_current_supported();
673         if (!regulator_mA)
674                 regulator_mA = 15000;
675
676         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
677
678         tegra_init_cpu_edp_limits(regulator_mA);
679 #endif
680         return 0;
681 }
682
683 static struct soctherm_platform_data roth_soctherm_data = {
684         .soctherm_clk_rate = 136000000,
685         .tsensor_clk_rate = 500000,
686         .sensor_data = {
687                 [TSENSE_CPU0] = {
688                         .enable = true,
689                         .therm_a = 570,
690                         .therm_b = -744,
691                         .tall = 16300,
692                         .tiddq = 1,
693                         .ten_count = 1,
694                         .tsample = 163,
695                         .pdiv = 10,
696                 },
697                 [TSENSE_CPU1] = {
698                         .enable = true,
699                         .therm_a = 570,
700                         .therm_b = -744,
701                         .tall = 16300,
702                         .tiddq = 1,
703                         .ten_count = 1,
704                         .tsample = 163,
705                         .pdiv = 10,
706                 },
707                 [TSENSE_CPU2] = {
708                         .enable = true,
709                         .therm_a = 570,
710                         .therm_b = -744,
711                         .tall = 16300,
712                         .tiddq = 1,
713                         .ten_count = 1,
714                         .tsample = 163,
715                         .pdiv = 10,
716                 },
717                 [TSENSE_CPU3] = {
718                         .enable = true,
719                         .therm_a = 570,
720                         .therm_b = -744,
721                         .tall = 16300,
722                         .tiddq = 1,
723                         .ten_count = 1,
724                         .tsample = 163,
725                         .pdiv = 10,
726                 },
727                 [TSENSE_MEM0] = {
728                         .enable = true,
729                         .therm_a = 570,
730                         .therm_b = -744,
731                         .tall = 16300,
732                         .tiddq = 1,
733                         .ten_count = 1,
734                         .tsample = 163,
735                         .pdiv = 10,
736                 },
737                 [TSENSE_MEM1] = {
738                         .enable = true,
739                         .therm_a = 570,
740                         .therm_b = -744,
741                         .tall = 16300,
742                         .tiddq = 1,
743                         .ten_count = 1,
744                         .tsample = 163,
745                         .pdiv = 10,
746                 },
747                 [TSENSE_GPU] = {
748                         .enable = true,
749                         .therm_a = 570,
750                         .therm_b = -744,
751                         .tall = 16300,
752                         .tiddq = 1,
753                         .ten_count = 1,
754                         .tsample = 163,
755                         .pdiv = 10,
756                 },
757                 [TSENSE_PLLX] = {
758                         .enable = true,
759                         .therm_a = 570,
760                         .therm_b = -744,
761                         .tall = 16300,
762                         .tiddq = 1,
763                         .ten_count = 1,
764                         .tsample = 163,
765                         .pdiv = 10,
766                 },
767         },
768 };
769
770 int __init roth_soctherm_init(void)
771 {
772         return tegra11_soctherm_init(&roth_soctherm_data);
773 }