ARM: Tegra: Roth: Enable all 3 NCT72 therm sensors
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/gpio.h>
31 #include <linux/regulator/userspace-consumer.h>
32
33 #include <asm/mach-types.h>
34
35 #include <mach/iomap.h>
36 #include <mach/irqs.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "cpu-tegra.h"
41 #include "pm.h"
42 #include "tegra-board-id.h"
43 #include "board.h"
44 #include "gpio-names.h"
45 #include "board-roth.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49
50 #define PMC_CTRL                0x0
51 #define PMC_CTRL_INTR_LOW       (1 << 17)
52
53 /* TPS51632 DC-DC converter */
54 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
55         REGULATOR_SUPPLY("vdd_cpu", NULL),
56 };
57
58 static struct regulator_init_data tps51632_init_data = {
59         .constraints = {                                                \
60                 .min_uV = 500000,                                       \
61                 .max_uV = 1520000,                                      \
62                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
63                                         REGULATOR_MODE_STANDBY),        \
64                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
65                                         REGULATOR_CHANGE_STATUS |       \
66                                         REGULATOR_CHANGE_VOLTAGE),      \
67                 .always_on = 1,                                         \
68                 .boot_on =  1,                                          \
69                 .apply_uV = 0,                                          \
70         },                                                              \
71         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
72                 .consumer_supplies = tps51632_dcdc_supply,              \
73 };
74
75 static struct tps51632_regulator_platform_data tps51632_pdata = {
76         .reg_init_data = &tps51632_init_data,           \
77         .enable_pwm = false,                            \
78         .max_voltage_uV = 1520000,                      \
79         .base_voltage_uV = 500000,                      \
80         .slew_rate_uv_per_us = 6000,                    \
81 };
82
83 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
84         {
85                 I2C_BOARD_INFO("tps51632", 0x43),
86                 .platform_data  = &tps51632_pdata,
87         },
88 };
89
90 /************************ Palmas based regulator ****************/
91 static struct regulator_consumer_supply palmas_smps12_supply[] = {
92         REGULATOR_SUPPLY("vddio_ddr0", NULL),
93         REGULATOR_SUPPLY("vddio_ddr1", NULL),
94 };
95
96 static struct regulator_consumer_supply palmas_smps3_supply[] = {
97         REGULATOR_SUPPLY("avdd_osc", NULL),
98         REGULATOR_SUPPLY("vddio_sys", NULL),
99         REGULATOR_SUPPLY("vddio_gmi", NULL),
100         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
101         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
102         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
103         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
104         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
105         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
106         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
107         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
108         REGULATOR_SUPPLY("vddio_audio", NULL),
109         REGULATOR_SUPPLY("pwrdet_audio", NULL),
110         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
111         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
112         REGULATOR_SUPPLY("vddio_uart", NULL),
113         REGULATOR_SUPPLY("pwrdet_uart", NULL),
114         REGULATOR_SUPPLY("dbvdd", NULL),
115         REGULATOR_SUPPLY("dvdd_lcd", NULL),
116 };
117
118 static struct regulator_consumer_supply palmas_smps45_supply[] = {
119         REGULATOR_SUPPLY("vdd_core", NULL),
120 };
121
122 #define palmas_smps457_supply palmas_smps45_supply
123
124 static struct regulator_consumer_supply palmas_smps8_supply[] = {
125         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
126         REGULATOR_SUPPLY("avdd_pllx", NULL),
127         REGULATOR_SUPPLY("avdd_pllm", NULL),
128         REGULATOR_SUPPLY("avdd_pllu", NULL),
129         REGULATOR_SUPPLY("avdd_plle", NULL),
130         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
131         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
132         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
133         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
134         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
135         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
136         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
137 };
138
139 static struct regulator_consumer_supply palmas_smps9_supply[] = {
140         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
141 };
142
143 static struct regulator_consumer_supply palmas_smps10_supply[] = {
144         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
145         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
146         REGULATOR_SUPPLY("vdd_5v0", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
150         REGULATOR_SUPPLY("avdd_lcd", NULL),
151         REGULATOR_SUPPLY("vci_2v8", NULL),
152 };
153
154 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
155         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
156         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
157         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
158         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
162         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
163         REGULATOR_SUPPLY("vdd", "0-004c"),
164         REGULATOR_SUPPLY("vdd", "1-004c"),
165         REGULATOR_SUPPLY("vdd", "1-004d"),
166 };
167
168 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
169         REGULATOR_SUPPLY("vdd_rtc", NULL),
170 };
171
172 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
173         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
174         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
175 };
176
177 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
178         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
179         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
180         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
181         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
182         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
183         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
184 };
185
186 static struct regulator_consumer_supply palmas_regen1_supply[] = {
187         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
188         REGULATOR_SUPPLY("vdd", "4-004c"),
189         REGULATOR_SUPPLY("vdd", "0-004d"),
190 };
191
192 static struct regulator_consumer_supply palmas_regen2_supply[] = {
193         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
194 };
195
196 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
197         _boot_on, _apply_uv)                                            \
198         static struct regulator_init_data reg_idata_##_name = {         \
199                 .constraints = {                                        \
200                         .name = palmas_rails(_name),                    \
201                         .min_uV = (_minmv)*1000,                        \
202                         .max_uV = (_maxmv)*1000,                        \
203                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
204                                         REGULATOR_MODE_STANDBY),        \
205                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
206                                         REGULATOR_CHANGE_STATUS |       \
207                                         REGULATOR_CHANGE_VOLTAGE),      \
208                         .always_on = _always_on,                        \
209                         .boot_on = _boot_on,                            \
210                         .apply_uV = _apply_uv,                          \
211                 },                                                      \
212                 .num_consumer_supplies =                                \
213                         ARRAY_SIZE(palmas_##_name##_supply),            \
214                 .consumer_supplies = palmas_##_name##_supply,           \
215                 .supply_regulator = _supply_reg,                        \
216         }
217
218 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
219 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
220 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
221 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0);
222 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 1, 1, 1);
223 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0);
224 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
225 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
226 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1);
227 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
228 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
229 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
230 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
231 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
232 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
233
234 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
235 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
236         PALMAS_REG_PDATA(smps12),
237         NULL,
238         PALMAS_REG_PDATA(smps3),
239         PALMAS_REG_PDATA(smps45),
240         PALMAS_REG_PDATA(smps457),
241         NULL,
242         NULL,
243         PALMAS_REG_PDATA(smps8),
244         PALMAS_REG_PDATA(smps9),
245         PALMAS_REG_PDATA(smps10),
246         NULL,   /* LDO1 */
247         PALMAS_REG_PDATA(ldo2),
248         PALMAS_REG_PDATA(ldo3),
249         NULL,
250         NULL,
251         PALMAS_REG_PDATA(ldo6),
252         NULL,
253         PALMAS_REG_PDATA(ldo8),
254         PALMAS_REG_PDATA(ldo9),
255         NULL,
256         PALMAS_REG_PDATA(ldousb),
257         PALMAS_REG_PDATA(regen1),
258         PALMAS_REG_PDATA(regen2),
259         NULL,
260         NULL,
261         NULL,
262 };
263
264 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
265                 _tstep, _vsel)                                          \
266         static struct palmas_reg_init reg_init_data_##_name = {         \
267                 .warm_reset = _warm_reset,                              \
268                 .roof_floor =   _roof_floor,                            \
269                 .mode_sleep = _mode_sleep,                              \
270                 .tstep = _tstep,                                        \
271                 .vsel = _vsel,                                          \
272         }
273
274 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
275 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
276 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
277 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
278 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
279 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
280 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
281 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
282 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
283 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
284 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
285 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
286 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
287 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
288 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
289 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
291 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
295 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
300
301 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
302 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
303         PALMAS_REG_INIT_DATA(smps12),
304         PALMAS_REG_INIT_DATA(smps123),
305         PALMAS_REG_INIT_DATA(smps3),
306         PALMAS_REG_INIT_DATA(smps45),
307         PALMAS_REG_INIT_DATA(smps457),
308         PALMAS_REG_INIT_DATA(smps6),
309         PALMAS_REG_INIT_DATA(smps7),
310         PALMAS_REG_INIT_DATA(smps8),
311         PALMAS_REG_INIT_DATA(smps9),
312         PALMAS_REG_INIT_DATA(smps10),
313         PALMAS_REG_INIT_DATA(ldo1),
314         PALMAS_REG_INIT_DATA(ldo2),
315         PALMAS_REG_INIT_DATA(ldo3),
316         PALMAS_REG_INIT_DATA(ldo4),
317         PALMAS_REG_INIT_DATA(ldo5),
318         PALMAS_REG_INIT_DATA(ldo6),
319         PALMAS_REG_INIT_DATA(ldo7),
320         PALMAS_REG_INIT_DATA(ldo8),
321         PALMAS_REG_INIT_DATA(ldo9),
322         PALMAS_REG_INIT_DATA(ldoln),
323         PALMAS_REG_INIT_DATA(ldousb),
324         PALMAS_REG_INIT_DATA(regen1),
325         PALMAS_REG_INIT_DATA(regen2),
326         PALMAS_REG_INIT_DATA(regen3),
327         PALMAS_REG_INIT_DATA(sysen1),
328         PALMAS_REG_INIT_DATA(sysen2),
329 };
330
331 static struct palmas_pmic_platform_data pmic_platform = {
332         .enable_ldo8_tracking = true,
333         .disabe_ldo8_tracking_suspend = true,
334 };
335
336 static struct palmas_platform_data palmas_pdata = {
337         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
338         .irq_base = PALMAS_TEGRA_IRQ_BASE,
339         .pmic_pdata = &pmic_platform,
340         .mux_from_pdata = true,
341         .pad1 = 0,
342         .pad2 = 0,
343         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
344         .use_power_off = true,
345 };
346
347 static struct i2c_board_info palma_device[] = {
348         {
349                 I2C_BOARD_INFO("tps65913", 0x58),
350                 .irq            = INT_EXTERNAL_PMU,
351                 .platform_data  = &palmas_pdata,
352         },
353 };
354
355 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
356         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
357 };
358
359 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
360         REGULATOR_SUPPLY("fan_5v0", NULL),
361 };
362
363 /* LCD_BL_EN GMI_AD10 */
364 static struct regulator_consumer_supply fixed_reg_lcd_bl_supply[] = {
365         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
366 };
367
368 /* Touch 3v3 GMI_AD13 */
369 static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
370         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
371         REGULATOR_SUPPLY("vdd_display", NULL),
372 };
373
374 /* VDD_3V3_COM controled by Wifi */
375 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
376         REGULATOR_SUPPLY("vdd_wl_pa", "bcm4329_wlan.1"),
377         REGULATOR_SUPPLY("vdd_bt_3v3", "reg-userspace-consumer.1"),
378         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
379 };
380
381 /* VDD_1v8_COM controled by Wifi */
382 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
383         REGULATOR_SUPPLY("vddio", "bcm4329_wlan.1"),
384         REGULATOR_SUPPLY("vddio_bt_1v8", "reg-userspace-consumer.1"),
385         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
386 };
387
388 /* vdd_3v3_sd PH0 */
389 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
390         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
391 };
392
393 /* Macro for defining fixed regulator sub device data */
394 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
395 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
396         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
397         static struct regulator_init_data ri_data_##_var =              \
398         {                                                               \
399                 .supply_regulator = _in_supply,                         \
400                 .num_consumer_supplies =                                \
401                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
402                 .consumer_supplies = fixed_reg_##_name##_supply,        \
403                 .constraints = {                                        \
404                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
405                                         REGULATOR_MODE_STANDBY),        \
406                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
407                                         REGULATOR_CHANGE_STATUS |       \
408                                         REGULATOR_CHANGE_VOLTAGE),      \
409                         .always_on = _always_on,                        \
410                         .boot_on = _boot_on,                            \
411                 },                                                      \
412         };                                                              \
413         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
414         {                                                               \
415                 .supply_name = FIXED_SUPPLY(_name),                     \
416                 .microvolts = _millivolts * 1000,                       \
417                 .gpio = _gpio_nr,                                       \
418                 .gpio_is_open_drain = _open_drain,                      \
419                 .enable_high = _active_high,                            \
420                 .enabled_at_boot = _boot_state,                         \
421                 .init_data = &ri_data_##_var,                           \
422         };                                                              \
423         static struct platform_device fixed_reg_##_var##_dev = {        \
424                 .name = "reg-fixed-voltage",                            \
425                 .id = _id,                                              \
426                 .dev = {                                                \
427                         .platform_data = &fixed_reg_##_var##_pdata,     \
428                 },                                                      \
429         }
430
431 FIXED_REG(0,    fan_5v0,        fan_5v0,
432         palmas_rails(smps10),   0,      0,
433         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
434
435 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
436         palmas_rails(smps10),   0,      0,
437         TEGRA_GPIO_PK1, false,  true,   0,      5000);
438
439 FIXED_REG(2,    lcd_bl, lcd_bl,
440         NULL,   0,      0,
441         TEGRA_GPIO_PH2, false,  true,   0,      5000);
442
443 FIXED_REG(3,    ts_3v3, ts_3v3,
444         palmas_rails(regen1),   0,      0,
445         TEGRA_GPIO_PH5, false,  true,   0,      3300);
446
447 FIXED_REG(4,    com_3v3,        com_3v3,
448         palmas_rails(regen1),   0,      0,
449         TEGRA_GPIO_PX7, false,  true,   0,      3300);
450
451 FIXED_REG(5,    sd_3v3, sd_3v3,
452         palmas_rails(regen1),   0,      0,
453         TEGRA_GPIO_PH0, false,  true,   0,      3300);
454
455 FIXED_REG(6,    com_1v8,        com_1v8,
456         palmas_rails(smps3),    0,      0,
457         TEGRA_GPIO_PX1, false,  true,   0,      1800);
458
459 /*
460  * Creating the fixed regulator device tables
461  */
462
463 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
464
465 #define ROTH_COMMON_FIXED_REG           \
466         ADD_FIXED_REG(usb1_vbus),               \
467         ADD_FIXED_REG(usb3_vbus),               \
468         ADD_FIXED_REG(vdd_hdmi_5v0),
469
470 #define E1612_FIXED_REG                         \
471         ADD_FIXED_REG(avdd_usb_hdmi),           \
472         ADD_FIXED_REG(en_1v8_cam),              \
473         ADD_FIXED_REG(vpp_fuse),                \
474
475 #define ROTH_FIXED_REG                          \
476         ADD_FIXED_REG(en_1v8_cam_roth),
477
478 /* Gpio switch regulator platform data for Roth */
479 static struct platform_device *fixed_reg_devs_roth[] = {
480         ADD_FIXED_REG(fan_5v0),
481         ADD_FIXED_REG(vdd_hdmi_5v0),
482         ADD_FIXED_REG(lcd_bl),
483         ADD_FIXED_REG(ts_3v3),
484         ADD_FIXED_REG(com_3v3),
485         ADD_FIXED_REG(sd_3v3),
486         ADD_FIXED_REG(com_1v8),
487 };
488
489 int __init roth_palmas_regulator_init(void)
490 {
491         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
492         u32 pmc_ctrl;
493         int i;
494
495         /* TPS65913: Normal state of INT request line is LOW.
496          * configure the power management controller to trigger PMU
497          * interrupts when HIGH.
498          */
499         pmc_ctrl = readl(pmc + PMC_CTRL);
500         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
501         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
502                 pmic_platform.reg_data[i] = roth_reg_data[i];
503                 pmic_platform.reg_init[i] = roth_reg_init[i];
504         }
505
506         i2c_register_board_info(4, palma_device,
507                         ARRAY_SIZE(palma_device));
508         return 0;
509 }
510
511 static int ac_online(void)
512 {
513         return 1;
514 }
515
516 static struct resource roth_pda_resources[] = {
517         [0] = {
518                 .name   = "ac",
519         },
520 };
521
522 static struct pda_power_pdata roth_pda_data = {
523         .is_ac_online   = ac_online,
524 };
525
526 static struct platform_device roth_pda_power_device = {
527         .name           = "pda-power",
528         .id             = -1,
529         .resource       = roth_pda_resources,
530         .num_resources  = ARRAY_SIZE(roth_pda_resources),
531         .dev    = {
532                 .platform_data  = &roth_pda_data,
533         },
534 };
535
536 static struct tegra_suspend_platform_data roth_suspend_data = {
537         .cpu_timer      = 300,
538         .cpu_off_timer  = 300,
539         .suspend_mode   = TEGRA_SUSPEND_NONE,
540         .core_timer     = 0x157e,
541         .core_off_timer = 2000,
542         .corereq_high   = true,
543         .sysclkreq_high = true,
544         .min_residency_noncpu = 600,
545         .min_residency_crail = 1000,
546 };
547 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
548 /* board parameters for cpu dfll */
549 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
550         .sample_rate = 12500,
551
552         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
553         .cf = 10,
554         .ci = 0,
555         .cg = 2,
556
557         .droop_cut_value = 0xF,
558         .droop_restore_ramp = 0x0,
559         .scale_out_ramp = 0x0,
560 };
561 #endif
562
563 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
564 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
565 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
566 static inline void fill_reg_map(void)
567 {
568         int i;
569         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
570                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
571                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
572         }
573 }
574
575 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
576 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
577         .dfll_clk_name = "dfll_cpu",
578         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
579         .u.pmu_i2c = {
580                 .fs_rate = 400000,
581                 .slave_addr = 0x86,
582                 .reg = 0x00,
583         },
584         .vdd_map = pmu_cpu_vdd_map,
585         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
586
587         .cfg_param = &roth_cl_dvfs_param,
588 };
589
590 static int __init roth_cl_dvfs_init(void)
591 {
592         fill_reg_map();
593         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
594         platform_device_register(&tegra_cl_dvfs_device);
595
596         return 0;
597 }
598 #endif
599
600 static struct regulator_bulk_data roth_gps_regulator_supply[] = {
601         [0] = {
602                 .supply = "vdd_gps_3v3",
603         },
604         [1] = {
605                 .supply = "vdd_gps_1v8",
606         },
607 };
608
609 static struct regulator_userspace_consumer_data roth_gps_regulator_pdata = {
610         .num_supplies   = ARRAY_SIZE(roth_gps_regulator_supply),
611         .supplies       = roth_gps_regulator_supply,
612 };
613
614 static struct platform_device roth_gps_regulator_device = {
615         .name   = "reg-userspace-consumer",
616         .id     = 2,
617         .dev    = {
618                         .platform_data = &roth_gps_regulator_pdata,
619         },
620 };
621
622 static struct regulator_bulk_data roth_bt_regulator_supply[] = {
623         [0] = {
624                 .supply = "vdd_bt_3v3",
625         },
626         [1] = {
627                 .supply = "vddio_bt_1v8",
628         },
629 };
630
631 static struct regulator_userspace_consumer_data roth_bt_regulator_pdata = {
632         .num_supplies   = ARRAY_SIZE(roth_bt_regulator_supply),
633         .supplies       = roth_bt_regulator_supply,
634 };
635
636 static struct platform_device roth_bt_regulator_device = {
637         .name   = "reg-userspace-consumer",
638         .id     = 1,
639         .dev    = {
640                         .platform_data = &roth_bt_regulator_pdata,
641         },
642 };
643
644 static int __init roth_fixed_regulator_init(void)
645 {
646         if (!machine_is_roth())
647                 return 0;
648
649         return platform_add_devices(fixed_reg_devs_roth,
650                                 ARRAY_SIZE(fixed_reg_devs_roth));
651 }
652 subsys_initcall_sync(roth_fixed_regulator_init);
653
654 int __init roth_regulator_init(void)
655 {
656         struct board_info board_info;
657 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
658         roth_cl_dvfs_init();
659 #endif
660         tegra_get_board_info(&board_info);
661         roth_palmas_regulator_init();
662
663         i2c_register_board_info(4, tps51632_boardinfo, 1);
664         platform_device_register(&roth_pda_power_device);
665         platform_device_register(&roth_bt_regulator_device);
666         platform_device_register(&roth_gps_regulator_device);
667         return 0;
668 }
669
670 int __init roth_suspend_init(void)
671 {
672         tegra_init_suspend(&roth_suspend_data);
673         return 0;
674 }
675
676 int __init roth_edp_init(void)
677 {
678 #ifdef CONFIG_TEGRA_EDP_LIMITS
679         unsigned int regulator_mA;
680
681         regulator_mA = get_maximum_cpu_current_supported();
682         if (!regulator_mA)
683                 regulator_mA = 15000;
684
685         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
686
687         tegra_init_cpu_edp_limits(regulator_mA);
688 #endif
689         return 0;
690 }
691
692 static struct soctherm_platform_data roth_soctherm_data = {
693         .soctherm_clk_rate = 136000000,
694         .tsensor_clk_rate = 500000,
695         .sensor_data = {
696                 [TSENSE_CPU0] = {
697                         .enable = true,
698                         .therm_a = 570,
699                         .therm_b = -744,
700                         .tall = 16300,
701                         .tiddq = 1,
702                         .ten_count = 1,
703                         .tsample = 163,
704                         .pdiv = 10,
705                 },
706                 [TSENSE_CPU1] = {
707                         .enable = true,
708                         .therm_a = 570,
709                         .therm_b = -744,
710                         .tall = 16300,
711                         .tiddq = 1,
712                         .ten_count = 1,
713                         .tsample = 163,
714                         .pdiv = 10,
715                 },
716                 [TSENSE_CPU2] = {
717                         .enable = true,
718                         .therm_a = 570,
719                         .therm_b = -744,
720                         .tall = 16300,
721                         .tiddq = 1,
722                         .ten_count = 1,
723                         .tsample = 163,
724                         .pdiv = 10,
725                 },
726                 [TSENSE_CPU3] = {
727                         .enable = true,
728                         .therm_a = 570,
729                         .therm_b = -744,
730                         .tall = 16300,
731                         .tiddq = 1,
732                         .ten_count = 1,
733                         .tsample = 163,
734                         .pdiv = 10,
735                 },
736                 [TSENSE_MEM0] = {
737                         .enable = true,
738                         .therm_a = 570,
739                         .therm_b = -744,
740                         .tall = 16300,
741                         .tiddq = 1,
742                         .ten_count = 1,
743                         .tsample = 163,
744                         .pdiv = 10,
745                 },
746                 [TSENSE_MEM1] = {
747                         .enable = true,
748                         .therm_a = 570,
749                         .therm_b = -744,
750                         .tall = 16300,
751                         .tiddq = 1,
752                         .ten_count = 1,
753                         .tsample = 163,
754                         .pdiv = 10,
755                 },
756                 [TSENSE_GPU] = {
757                         .enable = true,
758                         .therm_a = 570,
759                         .therm_b = -744,
760                         .tall = 16300,
761                         .tiddq = 1,
762                         .ten_count = 1,
763                         .tsample = 163,
764                         .pdiv = 10,
765                 },
766                 [TSENSE_PLLX] = {
767                         .enable = true,
768                         .therm_a = 570,
769                         .therm_b = -744,
770                         .tall = 16300,
771                         .tiddq = 1,
772                         .ten_count = 1,
773                         .tsample = 163,
774                         .pdiv = 10,
775                 },
776         },
777 };
778
779 int __init roth_soctherm_init(void)
780 {
781         return tegra11_soctherm_init(&roth_soctherm_data);
782 }