ARM: Tegra: Roth: Fix Display
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/gpio.h>
31 #include <linux/regulator/userspace-consumer.h>
32
33 #include <asm/mach-types.h>
34
35 #include <mach/iomap.h>
36 #include <mach/irqs.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "cpu-tegra.h"
41 #include "pm.h"
42 #include "tegra-board-id.h"
43 #include "board.h"
44 #include "gpio-names.h"
45 #include "board-roth.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49
50 #define PMC_CTRL                0x0
51 #define PMC_CTRL_INTR_LOW       (1 << 17)
52
53 /* TPS51632 DC-DC converter */
54 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
55         REGULATOR_SUPPLY("vdd_cpu", NULL),
56 };
57
58 static struct regulator_init_data tps51632_init_data = {
59         .constraints = {                                                \
60                 .min_uV = 500000,                                       \
61                 .max_uV = 1520000,                                      \
62                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
63                                         REGULATOR_MODE_STANDBY),        \
64                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
65                                         REGULATOR_CHANGE_STATUS |       \
66                                         REGULATOR_CHANGE_VOLTAGE),      \
67                 .always_on = 1,                                         \
68                 .boot_on =  1,                                          \
69                 .apply_uV = 0,                                          \
70         },                                                              \
71         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
72                 .consumer_supplies = tps51632_dcdc_supply,              \
73 };
74
75 static struct tps51632_regulator_platform_data tps51632_pdata = {
76         .reg_init_data = &tps51632_init_data,           \
77         .enable_pwm = false,                            \
78         .max_voltage_uV = 1520000,                      \
79         .base_voltage_uV = 500000,                      \
80         .slew_rate_uv_per_us = 6000,                    \
81 };
82
83 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
84         {
85                 I2C_BOARD_INFO("tps51632", 0x43),
86                 .platform_data  = &tps51632_pdata,
87         },
88 };
89
90 /************************ Palmas based regulator ****************/
91 static struct regulator_consumer_supply palmas_smps12_supply[] = {
92         REGULATOR_SUPPLY("vddio_ddr0", NULL),
93         REGULATOR_SUPPLY("vddio_ddr1", NULL),
94 };
95
96 static struct regulator_consumer_supply palmas_smps3_supply[] = {
97         REGULATOR_SUPPLY("avdd_osc", NULL),
98         REGULATOR_SUPPLY("vddio_sys", NULL),
99         REGULATOR_SUPPLY("vddio_gmi", NULL),
100         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
101         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
102         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
103         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
104         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
105         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
106         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
107         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
108         REGULATOR_SUPPLY("vddio_audio", NULL),
109         REGULATOR_SUPPLY("pwrdet_audio", NULL),
110         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
111         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
112         REGULATOR_SUPPLY("vddio_uart", NULL),
113         REGULATOR_SUPPLY("pwrdet_uart", NULL),
114         REGULATOR_SUPPLY("dbvdd", NULL),
115         REGULATOR_SUPPLY("dvdd_lcd", NULL),
116 };
117
118 static struct regulator_consumer_supply palmas_smps45_supply[] = {
119         REGULATOR_SUPPLY("vdd_core", NULL),
120 };
121
122 #define palmas_smps457_supply palmas_smps45_supply
123
124 static struct regulator_consumer_supply palmas_smps8_supply[] = {
125         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
126         REGULATOR_SUPPLY("avdd_pllx", NULL),
127         REGULATOR_SUPPLY("avdd_pllm", NULL),
128         REGULATOR_SUPPLY("avdd_pllu", NULL),
129         REGULATOR_SUPPLY("avdd_plle", NULL),
130         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
131         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
132         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
133         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
134         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
135         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
136         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
137 };
138
139 static struct regulator_consumer_supply palmas_smps9_supply[] = {
140         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
141 };
142
143 static struct regulator_consumer_supply palmas_smps10_supply[] = {
144         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
145         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
146         REGULATOR_SUPPLY("vdd_5v0", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
150         REGULATOR_SUPPLY("avdd_lcd", NULL),
151         REGULATOR_SUPPLY("vci_2v8", NULL),
152 };
153
154 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
155         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
156         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
157         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
158         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
162         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
163 };
164
165 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
166         REGULATOR_SUPPLY("vdd_rtc", NULL),
167 };
168
169 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
170         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
171         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
172 };
173
174 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
175         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
176         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
177         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
178         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
179         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
180         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
181 };
182
183 static struct regulator_consumer_supply palmas_regen1_supply[] = {
184         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
185         REGULATOR_SUPPLY("vdd", "4-004c"),
186         REGULATOR_SUPPLY("vdd", "0-004c"),
187         REGULATOR_SUPPLY("vdd", "0-004d"),
188 };
189
190 static struct regulator_consumer_supply palmas_regen2_supply[] = {
191         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
192 };
193
194 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
195         _boot_on, _apply_uv)                                            \
196         static struct regulator_init_data reg_idata_##_name = {         \
197                 .constraints = {                                        \
198                         .name = palmas_rails(_name),                    \
199                         .min_uV = (_minmv)*1000,                        \
200                         .max_uV = (_maxmv)*1000,                        \
201                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
202                                         REGULATOR_MODE_STANDBY),        \
203                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
204                                         REGULATOR_CHANGE_STATUS |       \
205                                         REGULATOR_CHANGE_VOLTAGE),      \
206                         .always_on = _always_on,                        \
207                         .boot_on = _boot_on,                            \
208                         .apply_uV = _apply_uv,                          \
209                 },                                                      \
210                 .num_consumer_supplies =                                \
211                         ARRAY_SIZE(palmas_##_name##_supply),            \
212                 .consumer_supplies = palmas_##_name##_supply,           \
213                 .supply_regulator = _supply_reg,                        \
214         }
215
216 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
217 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
218 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
219 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0);
220 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 0, 1, 1);
221 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0);
222 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
223 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
224 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 0, 0, 1);
225 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
226 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
227 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
228 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
229 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
230 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
231
232 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
233 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
234         PALMAS_REG_PDATA(smps12),
235         NULL,
236         PALMAS_REG_PDATA(smps3),
237         PALMAS_REG_PDATA(smps45),
238         PALMAS_REG_PDATA(smps457),
239         NULL,
240         NULL,
241         PALMAS_REG_PDATA(smps8),
242         PALMAS_REG_PDATA(smps9),
243         PALMAS_REG_PDATA(smps10),
244         NULL,   /* LDO1 */
245         PALMAS_REG_PDATA(ldo2),
246         PALMAS_REG_PDATA(ldo3),
247         NULL,
248         NULL,
249         PALMAS_REG_PDATA(ldo6),
250         NULL,
251         PALMAS_REG_PDATA(ldo8),
252         PALMAS_REG_PDATA(ldo9),
253         NULL,
254         PALMAS_REG_PDATA(ldousb),
255         PALMAS_REG_PDATA(regen1),
256         PALMAS_REG_PDATA(regen2),
257         NULL,
258         NULL,
259         NULL,
260 };
261
262 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
263                 _tstep, _vsel)                                          \
264         static struct palmas_reg_init reg_init_data_##_name = {         \
265                 .warm_reset = _warm_reset,                              \
266                 .roof_floor =   _roof_floor,                            \
267                 .mode_sleep = _mode_sleep,                              \
268                 .tstep = _tstep,                                        \
269                 .vsel = _vsel,                                          \
270         }
271
272 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
273 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
274 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
275 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
276 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
277 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
278 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
279 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
280 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
281 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
282 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
283 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
284 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
285 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
286 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
287 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
288 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
289 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
291 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
295 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
298
299 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
300 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
301         PALMAS_REG_INIT_DATA(smps12),
302         PALMAS_REG_INIT_DATA(smps123),
303         PALMAS_REG_INIT_DATA(smps3),
304         PALMAS_REG_INIT_DATA(smps45),
305         PALMAS_REG_INIT_DATA(smps457),
306         PALMAS_REG_INIT_DATA(smps6),
307         PALMAS_REG_INIT_DATA(smps7),
308         PALMAS_REG_INIT_DATA(smps8),
309         PALMAS_REG_INIT_DATA(smps9),
310         PALMAS_REG_INIT_DATA(smps10),
311         PALMAS_REG_INIT_DATA(ldo1),
312         PALMAS_REG_INIT_DATA(ldo2),
313         PALMAS_REG_INIT_DATA(ldo3),
314         PALMAS_REG_INIT_DATA(ldo4),
315         PALMAS_REG_INIT_DATA(ldo5),
316         PALMAS_REG_INIT_DATA(ldo6),
317         PALMAS_REG_INIT_DATA(ldo7),
318         PALMAS_REG_INIT_DATA(ldo8),
319         PALMAS_REG_INIT_DATA(ldo9),
320         PALMAS_REG_INIT_DATA(ldoln),
321         PALMAS_REG_INIT_DATA(ldousb),
322         PALMAS_REG_INIT_DATA(regen1),
323         PALMAS_REG_INIT_DATA(regen2),
324         PALMAS_REG_INIT_DATA(regen3),
325         PALMAS_REG_INIT_DATA(sysen1),
326         PALMAS_REG_INIT_DATA(sysen2),
327 };
328
329 static struct palmas_pmic_platform_data pmic_platform = {
330         .enable_ldo8_tracking = true,
331         .disabe_ldo8_tracking_suspend = true,
332 };
333
334 static struct palmas_platform_data palmas_pdata = {
335         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
336         .irq_base = PALMAS_TEGRA_IRQ_BASE,
337         .pmic_pdata = &pmic_platform,
338         .mux_from_pdata = true,
339         .pad1 = 0,
340         .pad2 = 0,
341         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
342         .use_power_off = true,
343 };
344
345 static struct i2c_board_info palma_device[] = {
346         {
347                 I2C_BOARD_INFO("tps65913", 0x58),
348                 .irq            = INT_EXTERNAL_PMU,
349                 .platform_data  = &palmas_pdata,
350         },
351 };
352
353 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
354         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
355 };
356
357 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
358         REGULATOR_SUPPLY("fan_5v0", NULL),
359 };
360
361 /* LCD_BL_EN GMI_AD10 */
362 static struct regulator_consumer_supply fixed_reg_lcd_bl_supply[] = {
363         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
364 };
365
366 /* Touch 3v3 GMI_AD13 */
367 static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
368         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
369         REGULATOR_SUPPLY("vdd_display", NULL),
370 };
371
372 /* VDD_3V3_COM controled by Wifi */
373 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
374         REGULATOR_SUPPLY("vdd_wl_pa", "bcm4329_wlan.1"),
375         REGULATOR_SUPPLY("vdd_bt_3v3", "reg-userspace-consumer.1"),
376         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
377 };
378
379 /* VDD_1v8_COM controled by Wifi */
380 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
381         REGULATOR_SUPPLY("vddio", "bcm4329_wlan.1"),
382         REGULATOR_SUPPLY("vddio_bt_1v8", "reg-userspace-consumer.1"),
383         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
384 };
385
386 /* vdd_3v3_sd PH0 */
387 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
388         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
389 };
390
391 /* Macro for defining fixed regulator sub device data */
392 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
393 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
394         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
395         static struct regulator_init_data ri_data_##_var =              \
396         {                                                               \
397                 .supply_regulator = _in_supply,                         \
398                 .num_consumer_supplies =                                \
399                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
400                 .consumer_supplies = fixed_reg_##_name##_supply,        \
401                 .constraints = {                                        \
402                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
403                                         REGULATOR_MODE_STANDBY),        \
404                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
405                                         REGULATOR_CHANGE_STATUS |       \
406                                         REGULATOR_CHANGE_VOLTAGE),      \
407                         .always_on = _always_on,                        \
408                         .boot_on = _boot_on,                            \
409                 },                                                      \
410         };                                                              \
411         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
412         {                                                               \
413                 .supply_name = FIXED_SUPPLY(_name),                     \
414                 .microvolts = _millivolts * 1000,                       \
415                 .gpio = _gpio_nr,                                       \
416                 .gpio_is_open_drain = _open_drain,                      \
417                 .enable_high = _active_high,                            \
418                 .enabled_at_boot = _boot_state,                         \
419                 .init_data = &ri_data_##_var,                           \
420         };                                                              \
421         static struct platform_device fixed_reg_##_var##_dev = {        \
422                 .name = "reg-fixed-voltage",                            \
423                 .id = _id,                                              \
424                 .dev = {                                                \
425                         .platform_data = &fixed_reg_##_var##_pdata,     \
426                 },                                                      \
427         }
428
429 FIXED_REG(0,    fan_5v0,        fan_5v0,
430         palmas_rails(smps10),   0,      0,
431         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
432
433 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
434         palmas_rails(smps10),   0,      0,
435         TEGRA_GPIO_PK1, false,  true,   0,      5000);
436
437 FIXED_REG(2,    lcd_bl, lcd_bl,
438         NULL,   0,      0,
439         TEGRA_GPIO_PH2, false,  true,   0,      5000);
440
441 FIXED_REG(3,    ts_3v3, ts_3v3,
442         palmas_rails(regen1),   0,      0,
443         TEGRA_GPIO_PH5, false,  true,   0,      3300);
444
445 FIXED_REG(4,    com_3v3,        com_3v3,
446         palmas_rails(regen1),   0,      0,
447         TEGRA_GPIO_PX7, false,  true,   0,      3300);
448
449 FIXED_REG(5,    sd_3v3, sd_3v3,
450         palmas_rails(regen1),   0,      0,
451         TEGRA_GPIO_PH0, false,  true,   0,      3300);
452
453 FIXED_REG(6,    com_1v8,        com_1v8,
454         palmas_rails(smps3),    0,      0,
455         TEGRA_GPIO_PX1, false,  true,   0,      1800);
456
457 /*
458  * Creating the fixed regulator device tables
459  */
460
461 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
462
463 #define ROTH_COMMON_FIXED_REG           \
464         ADD_FIXED_REG(usb1_vbus),               \
465         ADD_FIXED_REG(usb3_vbus),               \
466         ADD_FIXED_REG(vdd_hdmi_5v0),
467
468 #define E1612_FIXED_REG                         \
469         ADD_FIXED_REG(avdd_usb_hdmi),           \
470         ADD_FIXED_REG(en_1v8_cam),              \
471         ADD_FIXED_REG(vpp_fuse),                \
472
473 #define ROTH_FIXED_REG                          \
474         ADD_FIXED_REG(en_1v8_cam_roth),
475
476 /* Gpio switch regulator platform data for Roth */
477 static struct platform_device *fixed_reg_devs_roth[] = {
478         ADD_FIXED_REG(fan_5v0),
479         ADD_FIXED_REG(vdd_hdmi_5v0),
480         ADD_FIXED_REG(lcd_bl),
481         ADD_FIXED_REG(ts_3v3),
482         ADD_FIXED_REG(com_3v3),
483         ADD_FIXED_REG(sd_3v3),
484         ADD_FIXED_REG(com_1v8),
485 };
486
487 int __init roth_palmas_regulator_init(void)
488 {
489         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
490         u32 pmc_ctrl;
491         int i;
492
493         /* TPS65913: Normal state of INT request line is LOW.
494          * configure the power management controller to trigger PMU
495          * interrupts when HIGH.
496          */
497         pmc_ctrl = readl(pmc + PMC_CTRL);
498         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
499         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
500                 pmic_platform.reg_data[i] = roth_reg_data[i];
501                 pmic_platform.reg_init[i] = roth_reg_init[i];
502         }
503
504         i2c_register_board_info(4, palma_device,
505                         ARRAY_SIZE(palma_device));
506         return 0;
507 }
508
509 static int ac_online(void)
510 {
511         return 1;
512 }
513
514 static struct resource roth_pda_resources[] = {
515         [0] = {
516                 .name   = "ac",
517         },
518 };
519
520 static struct pda_power_pdata roth_pda_data = {
521         .is_ac_online   = ac_online,
522 };
523
524 static struct platform_device roth_pda_power_device = {
525         .name           = "pda-power",
526         .id             = -1,
527         .resource       = roth_pda_resources,
528         .num_resources  = ARRAY_SIZE(roth_pda_resources),
529         .dev    = {
530                 .platform_data  = &roth_pda_data,
531         },
532 };
533
534 static struct tegra_suspend_platform_data roth_suspend_data = {
535         .cpu_timer      = 300,
536         .cpu_off_timer  = 300,
537         .suspend_mode   = TEGRA_SUSPEND_LP0,
538         .core_timer     = 0x157e,
539         .core_off_timer = 2000,
540         .corereq_high   = true,
541         .sysclkreq_high = true,
542         .min_residency_noncpu = 600,
543         .min_residency_crail = 1000,
544 };
545 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
546 /* board parameters for cpu dfll */
547 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
548         .sample_rate = 12500,
549
550         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
551         .cf = 10,
552         .ci = 0,
553         .cg = 2,
554
555         .droop_cut_value = 0xF,
556         .droop_restore_ramp = 0x0,
557         .scale_out_ramp = 0x0,
558 };
559 #endif
560
561 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
562 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
563 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
564 static inline void fill_reg_map(void)
565 {
566         int i;
567         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
568                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
569                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
570         }
571 }
572
573 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
574 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
575         .dfll_clk_name = "dfll_cpu",
576         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
577         .u.pmu_i2c = {
578                 .fs_rate = 400000,
579                 .slave_addr = 0x86,
580                 .reg = 0x00,
581         },
582         .vdd_map = pmu_cpu_vdd_map,
583         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
584
585         .cfg_param = &roth_cl_dvfs_param,
586 };
587
588 static int __init roth_cl_dvfs_init(void)
589 {
590         fill_reg_map();
591         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
592         platform_device_register(&tegra_cl_dvfs_device);
593
594         return 0;
595 }
596 #endif
597
598 static struct regulator_bulk_data roth_gps_regulator_supply[] = {
599         [0] = {
600                 .supply = "vdd_gps_3v3",
601         },
602         [1] = {
603                 .supply = "vdd_gps_1v8",
604         },
605 };
606
607 static struct regulator_userspace_consumer_data roth_gps_regulator_pdata = {
608         .num_supplies   = ARRAY_SIZE(roth_gps_regulator_supply),
609         .supplies       = roth_gps_regulator_supply,
610 };
611
612 static struct platform_device roth_gps_regulator_device = {
613         .name   = "reg-userspace-consumer",
614         .id     = 2,
615         .dev    = {
616                         .platform_data = &roth_gps_regulator_pdata,
617         },
618 };
619
620 static struct regulator_bulk_data roth_bt_regulator_supply[] = {
621         [0] = {
622                 .supply = "vdd_bt_3v3",
623         },
624         [1] = {
625                 .supply = "vddio_bt_1v8",
626         },
627 };
628
629 static struct regulator_userspace_consumer_data roth_bt_regulator_pdata = {
630         .num_supplies   = ARRAY_SIZE(roth_bt_regulator_supply),
631         .supplies       = roth_bt_regulator_supply,
632 };
633
634 static struct platform_device roth_bt_regulator_device = {
635         .name   = "reg-userspace-consumer",
636         .id     = 1,
637         .dev    = {
638                         .platform_data = &roth_bt_regulator_pdata,
639         },
640 };
641
642 static int __init roth_fixed_regulator_init(void)
643 {
644         if (!machine_is_roth())
645                 return 0;
646
647         return platform_add_devices(fixed_reg_devs_roth,
648                                 ARRAY_SIZE(fixed_reg_devs_roth));
649 }
650 subsys_initcall_sync(roth_fixed_regulator_init);
651
652 int __init roth_regulator_init(void)
653 {
654         struct board_info board_info;
655 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
656         roth_cl_dvfs_init();
657 #endif
658         tegra_get_board_info(&board_info);
659         roth_palmas_regulator_init();
660
661         i2c_register_board_info(4, tps51632_boardinfo, 1);
662         platform_device_register(&roth_pda_power_device);
663         platform_device_register(&roth_bt_regulator_device);
664         platform_device_register(&roth_gps_regulator_device);
665         return 0;
666 }
667
668 int __init roth_suspend_init(void)
669 {
670         tegra_init_suspend(&roth_suspend_data);
671         return 0;
672 }
673
674 int __init roth_edp_init(void)
675 {
676 #ifdef CONFIG_TEGRA_EDP_LIMITS
677         unsigned int regulator_mA;
678
679         regulator_mA = get_maximum_cpu_current_supported();
680         if (!regulator_mA)
681                 regulator_mA = 15000;
682
683         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
684
685         tegra_init_cpu_edp_limits(regulator_mA);
686 #endif
687         return 0;
688 }
689
690 static struct soctherm_platform_data roth_soctherm_data = {
691         .soctherm_clk_rate = 136000000,
692         .tsensor_clk_rate = 500000,
693         .sensor_data = {
694                 [TSENSE_CPU0] = {
695                         .enable = true,
696                         .therm_a = 570,
697                         .therm_b = -744,
698                         .tall = 16300,
699                         .tiddq = 1,
700                         .ten_count = 1,
701                         .tsample = 163,
702                         .pdiv = 10,
703                 },
704                 [TSENSE_CPU1] = {
705                         .enable = true,
706                         .therm_a = 570,
707                         .therm_b = -744,
708                         .tall = 16300,
709                         .tiddq = 1,
710                         .ten_count = 1,
711                         .tsample = 163,
712                         .pdiv = 10,
713                 },
714                 [TSENSE_CPU2] = {
715                         .enable = true,
716                         .therm_a = 570,
717                         .therm_b = -744,
718                         .tall = 16300,
719                         .tiddq = 1,
720                         .ten_count = 1,
721                         .tsample = 163,
722                         .pdiv = 10,
723                 },
724                 [TSENSE_CPU3] = {
725                         .enable = true,
726                         .therm_a = 570,
727                         .therm_b = -744,
728                         .tall = 16300,
729                         .tiddq = 1,
730                         .ten_count = 1,
731                         .tsample = 163,
732                         .pdiv = 10,
733                 },
734                 [TSENSE_MEM0] = {
735                         .enable = true,
736                         .therm_a = 570,
737                         .therm_b = -744,
738                         .tall = 16300,
739                         .tiddq = 1,
740                         .ten_count = 1,
741                         .tsample = 163,
742                         .pdiv = 10,
743                 },
744                 [TSENSE_MEM1] = {
745                         .enable = true,
746                         .therm_a = 570,
747                         .therm_b = -744,
748                         .tall = 16300,
749                         .tiddq = 1,
750                         .ten_count = 1,
751                         .tsample = 163,
752                         .pdiv = 10,
753                 },
754                 [TSENSE_GPU] = {
755                         .enable = true,
756                         .therm_a = 570,
757                         .therm_b = -744,
758                         .tall = 16300,
759                         .tiddq = 1,
760                         .ten_count = 1,
761                         .tsample = 163,
762                         .pdiv = 10,
763                 },
764                 [TSENSE_PLLX] = {
765                         .enable = true,
766                         .therm_a = 570,
767                         .therm_b = -744,
768                         .tall = 16300,
769                         .tiddq = 1,
770                         .ten_count = 1,
771                         .tsample = 163,
772                         .pdiv = 10,
773                 },
774         },
775 };
776
777 int __init roth_soctherm_init(void)
778 {
779         return tegra11_soctherm_init(&roth_soctherm_data);
780 }