f02a7bb51f9846d272c1b5fc49913db8c5e890bb
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (c) 2012 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/power/bq2419x-charger.h>
31 #include <linux/max17048_battery.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/userspace-consumer.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40 #include <mach/hardware.h>
41
42 #include "cpu-tegra.h"
43 #include "pm.h"
44 #include "tegra-board-id.h"
45 #include "board-pmu-defines.h"
46 #include "board.h"
47 #include "board-common.h"
48 #include "gpio-names.h"
49 #include "board-roth.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53 #include "iomap.h"
54 #include "tegra3_tsensor.h"
55
56 #define PMC_CTRL                0x0
57 #define PMC_CTRL_INTR_LOW       (1 << 17)
58
59 /* TPS51632 DC-DC converter */
60 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
61         REGULATOR_SUPPLY("vdd_cpu", NULL),
62 };
63
64 static struct regulator_init_data tps51632_init_data = {
65         .constraints = {                                                \
66                 .min_uV = 500000,                                       \
67                 .max_uV = 1520000,                                      \
68                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
69                                         REGULATOR_MODE_STANDBY),        \
70                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
71                                         REGULATOR_CHANGE_STATUS |       \
72                                         REGULATOR_CHANGE_VOLTAGE),      \
73                 .always_on = 1,                                         \
74                 .boot_on =  1,                                          \
75                 .apply_uV = 0,                                          \
76         },                                                              \
77         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
78                 .consumer_supplies = tps51632_dcdc_supply,              \
79 };
80
81 static struct tps51632_regulator_platform_data tps51632_pdata = {
82         .reg_init_data = &tps51632_init_data,
83         .enable_pwm_dvfs = false,
84         .max_voltage_uV = 1520000,
85         .base_voltage_uV = 500000,
86 /*      .slew_rate_uv_per_us = 6000, */
87 };
88
89 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
90         {
91                 I2C_BOARD_INFO("tps51632", 0x43),
92                 .platform_data  = &tps51632_pdata,
93         },
94 };
95
96 /* BQ2419X VBUS regulator */
97 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
98         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
99 };
100
101 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
102         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
103 };
104
105 static struct bq2419x_vbus_platform_data bq2419x_vbus_pdata = {
106         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
107         .consumer_supplies = bq2419x_vbus_supply,
108 };
109
110 struct bq2419x_charger_platform_data bq2419x_charger_pdata = {
111         .use_usb = 1,
112         .use_mains = 1,
113         .max_charge_current_mA = 3000,
114         .charging_term_current_mA = 100,
115         .consumer_supplies = bq2419x_batt_supply,
116         .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
117         .wdt_timeout    = 40,
118         .rtc_alarm_time = 3600,
119         .chg_restart_time = 1800,
120 };
121
122 struct bq2419x_platform_data bq2419x_pdata = {
123         .vbus_pdata = &bq2419x_vbus_pdata,
124         .bcharger_pdata = &bq2419x_charger_pdata,
125 };
126
127 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
128         {
129                 I2C_BOARD_INFO("bq2419x", 0x6b),
130                 .platform_data  = &bq2419x_pdata,
131         },
132 };
133
134 struct max17048_battery_model max17048_mdata __initdata = {
135         .rcomp          = 105,
136         .soccheck_A     = 240,
137         .soccheck_B     = 242,
138         .bits           = 19,
139         .alert_threshold = 0x00,
140         .one_percent_alerts = 0x40,
141         .alert_on_reset = 0x40,
142         .rcomp_seg      = 0x0080,
143         .hibernate      = 0x3080,
144         .vreset         = 0x3c96,
145         .valert         = 0xD4AA,
146         .ocvtest        = 55728,
147         .data_tbl = {
148                 0xA9, 0x90, 0xB1, 0x60, 0xB5, 0xC0, 0xB7, 0x80,
149                 0xBA, 0xF0, 0xBB, 0xA0, 0xBB, 0xE0, 0xBC, 0x50,
150                 0xBC, 0xC0, 0xBD, 0x30, 0xBE, 0xD0, 0xC0, 0x90,
151                 0xC1, 0xD0, 0xC6, 0x70, 0xCA, 0xD0, 0xCF, 0xB0,
152                 0x0A, 0xF0, 0x0D, 0xE0, 0x0B, 0x30, 0x01, 0x90,
153                 0x53, 0xB0, 0x78, 0xD0, 0x77, 0xB0, 0x7C, 0xF0,
154                 0x7A, 0x70, 0x13, 0xE0, 0x13, 0x90, 0x1F, 0x30,
155                 0x19, 0x00, 0x12, 0x10, 0x10, 0xB0, 0x10, 0xB0,
156         },
157 };
158
159 struct max17048_platform_data max17048_pdata = {
160         .model_data = &max17048_mdata,
161 };
162
163 static struct i2c_board_info __initdata max17048_boardinfo[] = {
164         {
165                 I2C_BOARD_INFO("max17048", 0x36),
166                 .platform_data  = &max17048_pdata,
167         },
168 };
169
170
171 /************************ Palmas based regulator ****************/
172 static struct regulator_consumer_supply palmas_smps12_supply[] = {
173         REGULATOR_SUPPLY("vddio_ddr0", NULL),
174         REGULATOR_SUPPLY("vddio_ddr1", NULL),
175 };
176
177 static struct regulator_consumer_supply palmas_smps3_supply[] = {
178         REGULATOR_SUPPLY("avdd_osc", NULL),
179         REGULATOR_SUPPLY("vddio_sys", NULL),
180         REGULATOR_SUPPLY("vddio_gmi", NULL),
181         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
182         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
183         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
184         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
185         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
186         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
187         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
188         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
189         REGULATOR_SUPPLY("vddio_audio", NULL),
190         REGULATOR_SUPPLY("pwrdet_audio", NULL),
191         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
192         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
193         REGULATOR_SUPPLY("vddio_uart", NULL),
194         REGULATOR_SUPPLY("pwrdet_uart", NULL),
195         REGULATOR_SUPPLY("pwrdet_nand", NULL),
196         REGULATOR_SUPPLY("pwrdet_bb", NULL),
197         REGULATOR_SUPPLY("pwrdet_cam", NULL),
198         REGULATOR_SUPPLY("dbvdd", NULL),
199         REGULATOR_SUPPLY("vlogic", "0-0068"),
200 };
201
202 static struct regulator_consumer_supply palmas_smps45_supply[] = {
203         REGULATOR_SUPPLY("vdd_core", NULL),
204 };
205
206 #define palmas_smps457_supply palmas_smps45_supply
207
208 static struct regulator_consumer_supply palmas_smps8_supply[] = {
209         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
210         REGULATOR_SUPPLY("avdd_pllx", NULL),
211         REGULATOR_SUPPLY("avdd_pllm", NULL),
212         REGULATOR_SUPPLY("avdd_pllu", NULL),
213         REGULATOR_SUPPLY("avdd_plle", NULL),
214         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
215         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
216         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
217         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
218         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
219         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
220 };
221
222 static struct regulator_consumer_supply palmas_smps9_supply[] = {
223         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
224 };
225
226 static struct regulator_consumer_supply palmas_smps10_supply[] = {
227         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
228         REGULATOR_SUPPLY("vdd_5v0", NULL),
229 };
230
231 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
232         REGULATOR_SUPPLY("avdd_lcd", NULL),
233         REGULATOR_SUPPLY("vci_2v8", NULL),
234 };
235
236 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
237         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
238         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
239         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
240         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
241 };
242
243 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
244         REGULATOR_SUPPLY("vpp_fuse", NULL),
245 };
246
247 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
248         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
249 };
250
251 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
252         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
253         REGULATOR_SUPPLY("vdd", "0-004c"),
254         REGULATOR_SUPPLY("vdd", "1-004c"),
255         REGULATOR_SUPPLY("vdd", "1-004d"),
256         REGULATOR_SUPPLY("vdd", "0-0068"),
257 };
258
259 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
260         REGULATOR_SUPPLY("vdd_rtc", NULL),
261 };
262
263 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
264         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
265         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
266 };
267
268 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
269         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
270         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
271         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
272         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
273         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
274         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
275         REGULATOR_SUPPLY("pwrdet_hv", NULL),
276 };
277
278 static struct regulator_consumer_supply palmas_regen1_supply[] = {
279         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
280         REGULATOR_SUPPLY("vdd", "4-004c"),
281         REGULATOR_SUPPLY("vdd", "0-004d"),
282         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
283 };
284
285 static struct regulator_consumer_supply palmas_regen2_supply[] = {
286         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
287 };
288
289 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0, NORMAL);
290 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0, NORMAL);
291 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0, NORMAL);
292 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0, NORMAL);
293 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 1, 1, 1, NORMAL);
294 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0, NORMAL);
295 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0, 0);
296 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1, 0);
297 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1, 0);
298 PALMAS_PDATA_INIT(ldo4, 1800,  1800, NULL, 0, 0, 1, 0);
299 PALMAS_PDATA_INIT(ldo5, 1200,  1200, NULL, 0, 0, 1, 0);
300 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1, 0);
301 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1, 0);
302 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1, 0);
303 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1, 0);
304 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0, 0);
305 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0, 0);
306
307 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
308 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
309         PALMAS_REG_PDATA(smps12),
310         NULL,
311         PALMAS_REG_PDATA(smps3),
312         PALMAS_REG_PDATA(smps45),
313         PALMAS_REG_PDATA(smps457),
314         NULL,
315         NULL,
316         PALMAS_REG_PDATA(smps8),
317         PALMAS_REG_PDATA(smps9),
318         PALMAS_REG_PDATA(smps10),
319         NULL,   /* LDO1 */
320         PALMAS_REG_PDATA(ldo2),
321         PALMAS_REG_PDATA(ldo3),
322         PALMAS_REG_PDATA(ldo4),
323         PALMAS_REG_PDATA(ldo5),
324         PALMAS_REG_PDATA(ldo6),
325         NULL,
326         PALMAS_REG_PDATA(ldo8),
327         PALMAS_REG_PDATA(ldo9),
328         NULL,
329         NULL,
330         NULL,
331         NULL,
332         NULL,
333         NULL,
334         PALMAS_REG_PDATA(ldousb),
335         PALMAS_REG_PDATA(regen1),
336         PALMAS_REG_PDATA(regen2),
337         NULL,
338         NULL,
339         NULL,
340 };
341
342 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
343                 _vsel)                                                  \
344         static struct palmas_reg_init reg_init_data_##_name = {         \
345                 .warm_reset = _warm_reset,                              \
346                 .roof_floor =   _roof_floor,                            \
347                 .mode_sleep = _mode_sleep,                              \
348                 .vsel = _vsel,                                          \
349         }
350
351 PALMAS_REG_INIT(smps12, 0, 0, 0, 0);
352 PALMAS_REG_INIT(smps123, 0, 0, 0, 0);
353 PALMAS_REG_INIT(smps3, 0, 0, 0, 0);
354 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0);
355 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0);
356 PALMAS_REG_INIT(smps6, 0, 0, 0, 0);
357 PALMAS_REG_INIT(smps7, 0, 0, 0, 0);
358 PALMAS_REG_INIT(smps8, 0, 0, 0, 0);
359 PALMAS_REG_INIT(smps9, 0, 0, 0, 0);
360 PALMAS_REG_INIT(smps10, 0, 0, 0, 0);
361 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0);
362 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0);
363 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0);
364 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0);
365 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0);
366 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0);
367 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0);
368 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0);
369 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0);
370 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0);
371 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0);
372 PALMAS_REG_INIT(regen1, 0, 0, 0, 0);
373 PALMAS_REG_INIT(regen2, 0, 0, 0, 0);
374 PALMAS_REG_INIT(regen3, 0, 0, 0, 0);
375 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0);
376 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0);
377
378 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
379 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
380         PALMAS_REG_INIT_DATA(smps12),
381         PALMAS_REG_INIT_DATA(smps123),
382         PALMAS_REG_INIT_DATA(smps3),
383         PALMAS_REG_INIT_DATA(smps45),
384         PALMAS_REG_INIT_DATA(smps457),
385         PALMAS_REG_INIT_DATA(smps6),
386         PALMAS_REG_INIT_DATA(smps7),
387         PALMAS_REG_INIT_DATA(smps8),
388         PALMAS_REG_INIT_DATA(smps9),
389         PALMAS_REG_INIT_DATA(smps10),
390         PALMAS_REG_INIT_DATA(ldo1),
391         PALMAS_REG_INIT_DATA(ldo2),
392         PALMAS_REG_INIT_DATA(ldo3),
393         PALMAS_REG_INIT_DATA(ldo4),
394         PALMAS_REG_INIT_DATA(ldo5),
395         PALMAS_REG_INIT_DATA(ldo6),
396         PALMAS_REG_INIT_DATA(ldo7),
397         PALMAS_REG_INIT_DATA(ldo8),
398         PALMAS_REG_INIT_DATA(ldo9),
399         NULL,
400         NULL,
401         NULL,
402         NULL,
403         NULL,
404         PALMAS_REG_INIT_DATA(ldoln),
405         PALMAS_REG_INIT_DATA(ldousb),
406         PALMAS_REG_INIT_DATA(regen1),
407         PALMAS_REG_INIT_DATA(regen2),
408         PALMAS_REG_INIT_DATA(regen3),
409         PALMAS_REG_INIT_DATA(sysen1),
410         PALMAS_REG_INIT_DATA(sysen2),
411 };
412
413 static struct palmas_pmic_platform_data pmic_platform = {
414 };
415
416 static struct palmas_pinctrl_config palmas_pincfg[] = {
417         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
418         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
419         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
420         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
421         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
422         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
423         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
424         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
425         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
426         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
427 };
428
429 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
430         .pincfg = palmas_pincfg,
431         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
432         .dvfs1_enable = true,
433         .dvfs2_enable = false,
434 };
435
436 static struct palmas_platform_data palmas_pdata = {
437         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
438         .irq_base = PALMAS_TEGRA_IRQ_BASE,
439         .pmic_pdata = &pmic_platform,
440         .use_power_off = true,
441         .pinctrl_pdata = &palmas_pinctrl_pdata,
442 };
443
444 static struct i2c_board_info palma_device[] = {
445         {
446                 I2C_BOARD_INFO("tps65913", 0x58),
447                 .irq            = INT_EXTERNAL_PMU,
448                 .platform_data  = &palmas_pdata,
449         },
450 };
451
452 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
453         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
454 };
455
456 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
457         REGULATOR_SUPPLY("fan_5v0", NULL),
458 };
459
460 /* LCD_BL_EN GMI_AD10 */
461 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
462         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
463 };
464
465 /* VDD_3V3_COM controled by Wifi */
466 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
467         REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
468         REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
469         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
470 };
471
472 /* VDD_1v8_COM controled by Wifi */
473 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
474         REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
475         REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
476         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
477 };
478
479 /* vdd_3v3_sd PH0 */
480 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
481         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
482 };
483
484 /* EN_3V3_TS From TEGRA_GPIO_PH5 */
485 static struct regulator_consumer_supply fixed_reg_avdd_ts_supply[] = {
486         REGULATOR_SUPPLY("avdd", "spi3.2"),
487 };
488
489 /* EN_1V8_TS From TEGRA_GPIO_PK3 */
490 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
491         REGULATOR_SUPPLY("dvdd", "spi3.2"),
492 };
493
494 /* EN_1V8_TS From TEGRA_GPIO_PU4 */
495 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_supply[] = {
496         REGULATOR_SUPPLY("dvdd_lcd", NULL),
497 };
498 /* Macro for defining fixed regulator sub device data */
499 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
500 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
501         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
502         static struct regulator_init_data ri_data_##_var =              \
503         {                                                               \
504                 .supply_regulator = _in_supply,                         \
505                 .num_consumer_supplies =                                \
506                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
507                 .consumer_supplies = fixed_reg_##_name##_supply,        \
508                 .constraints = {                                        \
509                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
510                                         REGULATOR_MODE_STANDBY),        \
511                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
512                                         REGULATOR_CHANGE_STATUS |       \
513                                         REGULATOR_CHANGE_VOLTAGE),      \
514                         .always_on = _always_on,                        \
515                         .boot_on = _boot_on,                            \
516                 },                                                      \
517         };                                                              \
518         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
519         {                                                               \
520                 .supply_name = FIXED_SUPPLY(_name),                     \
521                 .microvolts = _millivolts * 1000,                       \
522                 .gpio = _gpio_nr,                                       \
523                 .gpio_is_open_drain = _open_drain,                      \
524                 .enable_high = _active_high,                            \
525                 .enabled_at_boot = _boot_state,                         \
526                 .init_data = &ri_data_##_var,                           \
527         };                                                              \
528         static struct platform_device fixed_reg_##_var##_dev = {        \
529                 .name = "reg-fixed-voltage",                            \
530                 .id = _id,                                              \
531                 .dev = {                                                \
532                         .platform_data = &fixed_reg_##_var##_pdata,     \
533                 },                                                      \
534         }
535
536 FIXED_REG(0,    fan_5v0,        fan_5v0,
537         palmas_rails(smps10),   0,      0,
538         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
539
540 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
541         palmas_rails(smps10),   0,      0,
542         TEGRA_GPIO_PK1, false,  true,   0,      5000);
543
544 FIXED_REG(2,    lcd_bl_en,      lcd_bl_en,
545         NULL,   0,      0,
546         TEGRA_GPIO_PH2, false,  true,   1,      5000);
547
548 FIXED_REG(3,    avdd_ts,        avdd_ts,
549         palmas_rails(regen1),   0,      0,
550         TEGRA_GPIO_PH5, false,  true,   0,      3300);
551
552 FIXED_REG(4,    dvdd_ts,        dvdd_ts,
553         palmas_rails(smps3),    0,      0,
554         TEGRA_GPIO_PK3, false,  true,   0,      1800);
555
556 FIXED_REG(5,    com_3v3,        com_3v3,
557         palmas_rails(regen1),   0,      0,
558         TEGRA_GPIO_PX7, false,  true,   0,      3300);
559
560 FIXED_REG(6,    sd_3v3, sd_3v3,
561         palmas_rails(regen1),   0,      0,
562         TEGRA_GPIO_PH0, false,  true,   0,      3300);
563
564 FIXED_REG(7,    com_1v8,        com_1v8,
565         palmas_rails(smps3),    0,      0,
566         TEGRA_GPIO_PX1, false,  true,   0,      1800);
567
568 FIXED_REG(8,    dvdd_lcd,       dvdd_lcd,
569         palmas_rails(smps3),    0,      0,
570         TEGRA_GPIO_PU4, false,  true,   1,      1800);
571
572 /*
573  * Creating the fixed regulator device tables
574  */
575
576 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
577
578 #define ROTH_COMMON_FIXED_REG           \
579         ADD_FIXED_REG(usb1_vbus),               \
580         ADD_FIXED_REG(usb3_vbus),               \
581         ADD_FIXED_REG(vdd_hdmi_5v0),
582
583 #define E1612_FIXED_REG                         \
584         ADD_FIXED_REG(avdd_usb_hdmi),           \
585         ADD_FIXED_REG(en_1v8_cam),              \
586         ADD_FIXED_REG(vpp_fuse),                \
587
588 #define ROTH_FIXED_REG                          \
589         ADD_FIXED_REG(en_1v8_cam_roth),
590
591 /* Gpio switch regulator platform data for Roth */
592 static struct platform_device *fixed_reg_devs_roth[] = {
593         ADD_FIXED_REG(fan_5v0),
594         ADD_FIXED_REG(vdd_hdmi_5v0),
595         ADD_FIXED_REG(lcd_bl_en),
596         ADD_FIXED_REG(avdd_ts),
597         ADD_FIXED_REG(dvdd_ts),
598         ADD_FIXED_REG(com_3v3),
599         ADD_FIXED_REG(sd_3v3),
600         ADD_FIXED_REG(com_1v8),
601         ADD_FIXED_REG(dvdd_lcd),
602 };
603
604 int __init roth_palmas_regulator_init(void)
605 {
606         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
607         u32 pmc_ctrl;
608         int i;
609
610         /* TPS65913: Normal state of INT request line is LOW.
611          * configure the power management controller to trigger PMU
612          * interrupts when HIGH.
613          */
614         pmc_ctrl = readl(pmc + PMC_CTRL);
615         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
616
617         /* Tracking configuration */
618         reg_init_data_ldo8.config_flags =
619                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
620                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
621
622         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
623                 pmic_platform.reg_data[i] = roth_reg_data[i];
624                 pmic_platform.reg_init[i] = roth_reg_init[i];
625         }
626
627         i2c_register_board_info(4, palma_device,
628                         ARRAY_SIZE(palma_device));
629         return 0;
630 }
631
632 static int ac_online(void)
633 {
634         return 1;
635 }
636
637 static struct resource roth_pda_resources[] = {
638         [0] = {
639                 .name   = "ac",
640         },
641 };
642
643 static struct pda_power_pdata roth_pda_data = {
644         .is_ac_online   = ac_online,
645 };
646
647 static struct platform_device roth_pda_power_device = {
648         .name           = "pda-power",
649         .id             = -1,
650         .resource       = roth_pda_resources,
651         .num_resources  = ARRAY_SIZE(roth_pda_resources),
652         .dev    = {
653                 .platform_data  = &roth_pda_data,
654         },
655 };
656
657 static struct tegra_suspend_platform_data roth_suspend_data = {
658         .cpu_timer      = 500,
659         .cpu_off_timer  = 300,
660         .suspend_mode   = TEGRA_SUSPEND_LP0,
661         .core_timer     = 0x157e,
662         .core_off_timer = 2000,
663         .corereq_high   = true,
664         .sysclkreq_high = true,
665         .cpu_lp2_min_residency = 1000,
666         .min_residency_crail = 20000,
667 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
668         .lp1_lowvolt_support = false,
669         .i2c_base_addr = 0,
670         .pmuslave_addr = 0,
671         .core_reg_addr = 0,
672         .lp1_core_volt_low_cold = 0,
673         .lp1_core_volt_low = 0,
674         .lp1_core_volt_high = 0,
675 #endif
676 };
677 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
678 /* board parameters for cpu dfll */
679 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
680         .sample_rate = 12500,
681
682         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
683         .cf = 10,
684         .ci = 0,
685         .cg = 2,
686
687         .droop_cut_value = 0xF,
688         .droop_restore_ramp = 0x0,
689         .scale_out_ramp = 0x0,
690 };
691 #endif
692
693 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
694 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
695 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
696 static inline void fill_reg_map(void)
697 {
698         int i;
699         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
700                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
701                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
702         }
703 }
704
705 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
706 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
707         .dfll_clk_name = "dfll_cpu",
708         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
709         .u.pmu_i2c = {
710                 .fs_rate = 400000,
711                 .slave_addr = 0x86,
712                 .reg = 0x00,
713         },
714         .vdd_map = pmu_cpu_vdd_map,
715         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
716
717         .cfg_param = &roth_cl_dvfs_param,
718 };
719
720 static int __init roth_cl_dvfs_init(void)
721 {
722         fill_reg_map();
723         if (tegra_revision < TEGRA_REVISION_A02)
724                 roth_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
725         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
726         platform_device_register(&tegra_cl_dvfs_device);
727
728         return 0;
729 }
730 #endif
731
732 static int __init roth_fixed_regulator_init(void)
733 {
734         if (!machine_is_roth())
735                 return 0;
736
737         return platform_add_devices(fixed_reg_devs_roth,
738                                 ARRAY_SIZE(fixed_reg_devs_roth));
739 }
740 subsys_initcall_sync(roth_fixed_regulator_init);
741
742 int __init roth_regulator_init(void)
743 {
744 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
745         roth_cl_dvfs_init();
746 #endif
747         roth_palmas_regulator_init();
748
749         i2c_register_board_info(4, tps51632_boardinfo, 1);
750         i2c_register_board_info(0, max17048_boardinfo, 1);
751         i2c_register_board_info(0, bq2419x_boardinfo, 1);
752         platform_device_register(&roth_pda_power_device);
753         return 0;
754 }
755
756 int __init roth_suspend_init(void)
757 {
758         tegra_init_suspend(&roth_suspend_data);
759         return 0;
760 }
761
762 int __init roth_edp_init(void)
763 {
764         unsigned int regulator_mA;
765
766         regulator_mA = get_maximum_cpu_current_supported();
767         if (!regulator_mA)
768                 regulator_mA = 15000;
769
770         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
771         tegra_init_cpu_edp_limits(regulator_mA);
772
773         regulator_mA = get_maximum_core_current_supported();
774         if (!regulator_mA)
775                 regulator_mA = 4000;
776
777         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
778         tegra_init_core_edp_limits(regulator_mA);
779
780         return 0;
781 }
782
783 static struct tegra_tsensor_pmu_data tpdata_palmas = {
784         .reset_tegra = 1,
785         .pmu_16bit_ops = 0,
786         .controller_type = 0,
787         .pmu_i2c_addr = 0x58,
788         .i2c_controller_id = 4,
789         .poweroff_reg_addr = 0xa0,
790         .poweroff_reg_data = 0x0,
791 };
792
793 static struct soctherm_platform_data roth_soctherm_data = {
794         .therm = {
795                 [THERM_CPU] = {
796                         .zone_enable = true,
797                         .passive_delay = 1000,
798                         .hotspot_offset = 6000,
799                         .num_trips = 0, /* Disables the trips config below */
800                         /*
801                          * Following .trips config retained for compatibility
802                          * with dalmore/pluto and later enablement when needed
803                          */
804                         .trips = {
805                                 {
806                                         .cdev_type = "tegra-balanced",
807                                         .trip_temp = 90000,
808                                         .trip_type = THERMAL_TRIP_PASSIVE,
809                                         .upper = THERMAL_NO_LIMIT,
810                                         .lower = THERMAL_NO_LIMIT,
811                                 },
812                                 {
813                                         .cdev_type = "tegra-heavy",
814                                         .trip_temp = 100000,
815                                         .trip_type = THERMAL_TRIP_HOT,
816                                         .upper = THERMAL_NO_LIMIT,
817                                         .lower = THERMAL_NO_LIMIT,
818                                 },
819                                 {
820                                         .cdev_type = "tegra-shutdown",
821                                         .trip_temp = 102000,
822                                         .trip_type = THERMAL_TRIP_CRITICAL,
823                                         .upper = THERMAL_NO_LIMIT,
824                                         .lower = THERMAL_NO_LIMIT,
825                                 },
826                         },
827                 },
828                 [THERM_GPU] = {
829                         .zone_enable = true,
830                         .passive_delay = 1000,
831                         .hotspot_offset = 6000,
832                         .num_trips = 0, /* Disables the trips config below */
833                         /*
834                          * Following .trips config retained for compatibility
835                          * with dalmore/pluto and later enablement when needed
836                          */
837                         .trips = {
838                                 {
839                                         .cdev_type = "tegra-balanced",
840                                         .trip_temp = 90000,
841                                         .trip_type = THERMAL_TRIP_PASSIVE,
842                                         .upper = THERMAL_NO_LIMIT,
843                                         .lower = THERMAL_NO_LIMIT,
844                                 },
845                                 {
846                                         .cdev_type = "tegra-heavy",
847                                         .trip_temp = 100000,
848                                         .trip_type = THERMAL_TRIP_HOT,
849                                         .upper = THERMAL_NO_LIMIT,
850                                         .lower = THERMAL_NO_LIMIT,
851                                 },
852                                 {
853                                         .cdev_type = "tegra-shutdown",
854                                         .trip_temp = 102000,
855                                         .trip_type = THERMAL_TRIP_CRITICAL,
856                                         .upper = THERMAL_NO_LIMIT,
857                                         .lower = THERMAL_NO_LIMIT,
858                                 },
859                         },
860                 },
861                 [THERM_PLL] = {
862                         .zone_enable = true,
863                 },
864         },
865         .throttle = {
866                 [THROTTLE_HEAVY] = {
867                         .devs = {
868                                 [THROTTLE_DEV_CPU] = {
869                                         .enable = 1,
870                                 },
871                         },
872                 },
873         },
874         .tshut_pmu_trip_data = &tpdata_palmas,
875 };
876
877 int __init roth_soctherm_init(void)
878 {
879         tegra_add_vc_trips(roth_soctherm_data.therm[THERM_CPU].trips,
880                         &roth_soctherm_data.therm[THERM_CPU].num_trips);
881
882         return tegra11_soctherm_init(&roth_soctherm_data);
883 }