arm: tegra: Move all tj dependent thermals from nct to soc_therm
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/mfd/bq2419x.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33
34 #include <asm/mach-types.h>
35
36 #include <mach/irqs.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "cpu-tegra.h"
41 #include "pm.h"
42 #include "tegra-board-id.h"
43 #include "board.h"
44 #include "gpio-names.h"
45 #include "board-roth.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49 #include "iomap.h"
50
51 #define PMC_CTRL                0x0
52 #define PMC_CTRL_INTR_LOW       (1 << 17)
53
54 /* TPS51632 DC-DC converter */
55 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
56         REGULATOR_SUPPLY("vdd_cpu", NULL),
57 };
58
59 static struct regulator_init_data tps51632_init_data = {
60         .constraints = {                                                \
61                 .min_uV = 500000,                                       \
62                 .max_uV = 1520000,                                      \
63                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
64                                         REGULATOR_MODE_STANDBY),        \
65                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
66                                         REGULATOR_CHANGE_STATUS |       \
67                                         REGULATOR_CHANGE_VOLTAGE),      \
68                 .always_on = 1,                                         \
69                 .boot_on =  1,                                          \
70                 .apply_uV = 0,                                          \
71         },                                                              \
72         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
73                 .consumer_supplies = tps51632_dcdc_supply,              \
74 };
75
76 static struct tps51632_regulator_platform_data tps51632_pdata = {
77         .reg_init_data = &tps51632_init_data,           \
78         .enable_pwm = false,                            \
79         .max_voltage_uV = 1520000,                      \
80         .base_voltage_uV = 500000,                      \
81         .slew_rate_uv_per_us = 6000,                    \
82 };
83
84 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
85         {
86                 I2C_BOARD_INFO("tps51632", 0x43),
87                 .platform_data  = &tps51632_pdata,
88         },
89 };
90
91
92 /* BQ2419X VBUS regulator */
93 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
94         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
95 };
96 static struct regulator_init_data bq2419x_init_data = {
97         .constraints = {
98                 .name = "bq2419x_vbus",
99                 .min_uV = 0,
100                 .max_uV = 5000000,
101                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
102                                         REGULATOR_MODE_STANDBY),
103                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
104                                         REGULATOR_CHANGE_STATUS |
105                                         REGULATOR_CHANGE_VOLTAGE),
106         },
107         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
108         .consumer_supplies = bq2419x_vbus_supply,
109 };
110
111 static struct bq2419x_regulator_platform_data bq2419x_reg_pdata = {
112         .reg_init_data = &bq2419x_init_data,
113         .gpio_otg_iusb = TEGRA_GPIO_PI4,
114 };
115
116 struct bq2419x_charger_platform_data bq2419x_charger_pdata = {
117         .usb_in_current_limit = 400,
118         .ac_in_current_limit = 1000,
119         .use_usb = 1,
120         .gpio_interrupt = TEGRA_GPIO_PJ0,
121         .gpio_status = TEGRA_GPIO_PK0,
122 };
123
124 struct bq2419x_platform_data bq2419x_pdata = {
125         .reg_pdata = &bq2419x_reg_pdata,
126         .bcharger_pdata = &bq2419x_charger_pdata,
127         .disable_watchdog = true,
128 };
129
130 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
131         {
132                 I2C_BOARD_INFO("bq2419x", 0x6b),
133                 .platform_data  = &bq2419x_pdata,
134         },
135 };
136
137 /************************ Palmas based regulator ****************/
138 static struct regulator_consumer_supply palmas_smps12_supply[] = {
139         REGULATOR_SUPPLY("vddio_ddr0", NULL),
140         REGULATOR_SUPPLY("vddio_ddr1", NULL),
141 };
142
143 static struct regulator_consumer_supply palmas_smps3_supply[] = {
144         REGULATOR_SUPPLY("avdd_osc", NULL),
145         REGULATOR_SUPPLY("vddio_sys", NULL),
146         REGULATOR_SUPPLY("vddio_gmi", NULL),
147         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
148         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
149         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
150         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
151         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
152         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
153         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
154         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
155         REGULATOR_SUPPLY("vddio_audio", NULL),
156         REGULATOR_SUPPLY("pwrdet_audio", NULL),
157         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
158         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
159         REGULATOR_SUPPLY("vddio_uart", NULL),
160         REGULATOR_SUPPLY("pwrdet_uart", NULL),
161         REGULATOR_SUPPLY("dbvdd", NULL),
162         REGULATOR_SUPPLY("dvdd_lcd", NULL),
163         REGULATOR_SUPPLY("vlogic", "0-0068"),
164 };
165
166 static struct regulator_consumer_supply palmas_smps45_supply[] = {
167         REGULATOR_SUPPLY("vdd_core", NULL),
168 };
169
170 #define palmas_smps457_supply palmas_smps45_supply
171
172 static struct regulator_consumer_supply palmas_smps8_supply[] = {
173         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
174         REGULATOR_SUPPLY("avdd_pllx", NULL),
175         REGULATOR_SUPPLY("avdd_pllm", NULL),
176         REGULATOR_SUPPLY("avdd_pllu", NULL),
177         REGULATOR_SUPPLY("avdd_plle", NULL),
178         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
179         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
180         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
181         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
182         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
183         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
184         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
185 };
186
187 static struct regulator_consumer_supply palmas_smps9_supply[] = {
188         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
189 };
190
191 static struct regulator_consumer_supply palmas_smps10_supply[] = {
192         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
193         REGULATOR_SUPPLY("vdd_5v0", NULL),
194 };
195
196 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
197         REGULATOR_SUPPLY("avdd_lcd", NULL),
198         REGULATOR_SUPPLY("vci_2v8", NULL),
199 };
200
201 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
202         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
203         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
204         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
205         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
206 };
207
208 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
209         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
210         REGULATOR_SUPPLY("vdd", "0-004c"),
211         REGULATOR_SUPPLY("vdd", "1-004c"),
212         REGULATOR_SUPPLY("vdd", "1-004d"),
213         REGULATOR_SUPPLY("vdd", "0-0068"),
214 };
215
216 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
217         REGULATOR_SUPPLY("vdd_rtc", NULL),
218 };
219
220 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
221         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
222         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
223 };
224
225 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
226         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
227         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
228         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
229         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
230         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
231         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
232 };
233
234 static struct regulator_consumer_supply palmas_regen1_supply[] = {
235         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
236         REGULATOR_SUPPLY("vdd", "4-004c"),
237         REGULATOR_SUPPLY("vdd", "0-004d"),
238         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
239 };
240
241 static struct regulator_consumer_supply palmas_regen2_supply[] = {
242         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
243 };
244
245 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
246         _boot_on, _apply_uv)                                            \
247         static struct regulator_init_data reg_idata_##_name = {         \
248                 .constraints = {                                        \
249                         .name = palmas_rails(_name),                    \
250                         .min_uV = (_minmv)*1000,                        \
251                         .max_uV = (_maxmv)*1000,                        \
252                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
253                                         REGULATOR_MODE_STANDBY),        \
254                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
255                                         REGULATOR_CHANGE_STATUS |       \
256                                         REGULATOR_CHANGE_VOLTAGE),      \
257                         .always_on = _always_on,                        \
258                         .boot_on = _boot_on,                            \
259                         .apply_uV = _apply_uv,                          \
260                 },                                                      \
261                 .num_consumer_supplies =                                \
262                         ARRAY_SIZE(palmas_##_name##_supply),            \
263                 .consumer_supplies = palmas_##_name##_supply,           \
264                 .supply_regulator = _supply_reg,                        \
265         }
266
267 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
268 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
269 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
270 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0);
271 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 1, 1, 1);
272 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0);
273 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
274 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
275 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1);
276 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
277 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
278 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
279 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
280 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
281 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
282
283 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
284 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
285         PALMAS_REG_PDATA(smps12),
286         NULL,
287         PALMAS_REG_PDATA(smps3),
288         PALMAS_REG_PDATA(smps45),
289         PALMAS_REG_PDATA(smps457),
290         NULL,
291         NULL,
292         PALMAS_REG_PDATA(smps8),
293         PALMAS_REG_PDATA(smps9),
294         PALMAS_REG_PDATA(smps10),
295         NULL,   /* LDO1 */
296         PALMAS_REG_PDATA(ldo2),
297         PALMAS_REG_PDATA(ldo3),
298         NULL,
299         NULL,
300         PALMAS_REG_PDATA(ldo6),
301         NULL,
302         PALMAS_REG_PDATA(ldo8),
303         PALMAS_REG_PDATA(ldo9),
304         NULL,
305         PALMAS_REG_PDATA(ldousb),
306         PALMAS_REG_PDATA(regen1),
307         PALMAS_REG_PDATA(regen2),
308         NULL,
309         NULL,
310         NULL,
311 };
312
313 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
314                 _tstep, _vsel)                                          \
315         static struct palmas_reg_init reg_init_data_##_name = {         \
316                 .warm_reset = _warm_reset,                              \
317                 .roof_floor =   _roof_floor,                            \
318                 .mode_sleep = _mode_sleep,                              \
319                 .tstep = _tstep,                                        \
320                 .vsel = _vsel,                                          \
321         }
322
323 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
324 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
325 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
326 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
327 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
328 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
329 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
330 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
331 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
332 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
333 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
334 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
335 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
336 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
337 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
338 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
339 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
340 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
341 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
342 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
343 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
344 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
345 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
346 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
347 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
348 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
349
350 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
351 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
352         PALMAS_REG_INIT_DATA(smps12),
353         PALMAS_REG_INIT_DATA(smps123),
354         PALMAS_REG_INIT_DATA(smps3),
355         PALMAS_REG_INIT_DATA(smps45),
356         PALMAS_REG_INIT_DATA(smps457),
357         PALMAS_REG_INIT_DATA(smps6),
358         PALMAS_REG_INIT_DATA(smps7),
359         PALMAS_REG_INIT_DATA(smps8),
360         PALMAS_REG_INIT_DATA(smps9),
361         PALMAS_REG_INIT_DATA(smps10),
362         PALMAS_REG_INIT_DATA(ldo1),
363         PALMAS_REG_INIT_DATA(ldo2),
364         PALMAS_REG_INIT_DATA(ldo3),
365         PALMAS_REG_INIT_DATA(ldo4),
366         PALMAS_REG_INIT_DATA(ldo5),
367         PALMAS_REG_INIT_DATA(ldo6),
368         PALMAS_REG_INIT_DATA(ldo7),
369         PALMAS_REG_INIT_DATA(ldo8),
370         PALMAS_REG_INIT_DATA(ldo9),
371         PALMAS_REG_INIT_DATA(ldoln),
372         PALMAS_REG_INIT_DATA(ldousb),
373         PALMAS_REG_INIT_DATA(regen1),
374         PALMAS_REG_INIT_DATA(regen2),
375         PALMAS_REG_INIT_DATA(regen3),
376         PALMAS_REG_INIT_DATA(sysen1),
377         PALMAS_REG_INIT_DATA(sysen2),
378 };
379
380 static struct palmas_pmic_platform_data pmic_platform = {
381         .enable_ldo8_tracking = true,
382         .disabe_ldo8_tracking_suspend = true,
383 };
384
385 static struct palmas_platform_data palmas_pdata = {
386         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
387         .irq_base = PALMAS_TEGRA_IRQ_BASE,
388         .pmic_pdata = &pmic_platform,
389         .mux_from_pdata = true,
390         .pad1 = 0,
391         .pad2 = 0,
392         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
393         .use_power_off = true,
394 };
395
396 static struct i2c_board_info palma_device[] = {
397         {
398                 I2C_BOARD_INFO("tps65913", 0x58),
399                 .irq            = INT_EXTERNAL_PMU,
400                 .platform_data  = &palmas_pdata,
401         },
402 };
403
404 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
405         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
406 };
407
408 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
409         REGULATOR_SUPPLY("fan_5v0", NULL),
410 };
411
412 /* LCD_BL_EN GMI_AD10 */
413 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
414         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
415 };
416
417 /* Touch 3v3 GMI_AD13 */
418 static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
419         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
420         REGULATOR_SUPPLY("vdd_display", NULL),
421 };
422
423 /* VDD_3V3_COM controled by Wifi */
424 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
425         REGULATOR_SUPPLY("vdd_wl_pa", "bcm4329_wlan.1"),
426         REGULATOR_SUPPLY("vdd_bt_3v3", "bluedroid_pm.0"),
427         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
428 };
429
430 /* VDD_1v8_COM controled by Wifi */
431 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
432         REGULATOR_SUPPLY("vddio", "bcm4329_wlan.1"),
433         REGULATOR_SUPPLY("vddio_bt_1v8", "bluedroid_pm.0"),
434         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
435 };
436
437 /* vdd_3v3_sd PH0 */
438 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
439         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
440 };
441
442 /* Macro for defining fixed regulator sub device data */
443 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
444 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
445         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
446         static struct regulator_init_data ri_data_##_var =              \
447         {                                                               \
448                 .supply_regulator = _in_supply,                         \
449                 .num_consumer_supplies =                                \
450                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
451                 .consumer_supplies = fixed_reg_##_name##_supply,        \
452                 .constraints = {                                        \
453                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
454                                         REGULATOR_MODE_STANDBY),        \
455                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
456                                         REGULATOR_CHANGE_STATUS |       \
457                                         REGULATOR_CHANGE_VOLTAGE),      \
458                         .always_on = _always_on,                        \
459                         .boot_on = _boot_on,                            \
460                 },                                                      \
461         };                                                              \
462         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
463         {                                                               \
464                 .supply_name = FIXED_SUPPLY(_name),                     \
465                 .microvolts = _millivolts * 1000,                       \
466                 .gpio = _gpio_nr,                                       \
467                 .gpio_is_open_drain = _open_drain,                      \
468                 .enable_high = _active_high,                            \
469                 .enabled_at_boot = _boot_state,                         \
470                 .init_data = &ri_data_##_var,                           \
471         };                                                              \
472         static struct platform_device fixed_reg_##_var##_dev = {        \
473                 .name = "reg-fixed-voltage",                            \
474                 .id = _id,                                              \
475                 .dev = {                                                \
476                         .platform_data = &fixed_reg_##_var##_pdata,     \
477                 },                                                      \
478         }
479
480 FIXED_REG(0,    fan_5v0,        fan_5v0,
481         palmas_rails(smps10),   0,      0,
482         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
483
484 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
485         palmas_rails(smps10),   0,      0,
486         TEGRA_GPIO_PK1, false,  true,   0,      5000);
487
488 FIXED_REG(2,    lcd_bl_en,      lcd_bl_en,
489         NULL,   0,      0,
490         TEGRA_GPIO_PH2, false,  true,   0,      5000);
491
492 FIXED_REG(3,    ts_3v3, ts_3v3,
493         palmas_rails(regen1),   0,      0,
494         TEGRA_GPIO_PH5, false,  true,   0,      3300);
495
496 FIXED_REG(4,    com_3v3,        com_3v3,
497         palmas_rails(regen1),   0,      0,
498         TEGRA_GPIO_PX7, false,  true,   0,      3300);
499
500 FIXED_REG(5,    sd_3v3, sd_3v3,
501         palmas_rails(regen1),   0,      0,
502         TEGRA_GPIO_PH0, false,  true,   0,      3300);
503
504 FIXED_REG(6,    com_1v8,        com_1v8,
505         palmas_rails(smps3),    0,      0,
506         TEGRA_GPIO_PX1, false,  true,   0,      1800);
507
508 /*
509  * Creating the fixed regulator device tables
510  */
511
512 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
513
514 #define ROTH_COMMON_FIXED_REG           \
515         ADD_FIXED_REG(usb1_vbus),               \
516         ADD_FIXED_REG(usb3_vbus),               \
517         ADD_FIXED_REG(vdd_hdmi_5v0),
518
519 #define E1612_FIXED_REG                         \
520         ADD_FIXED_REG(avdd_usb_hdmi),           \
521         ADD_FIXED_REG(en_1v8_cam),              \
522         ADD_FIXED_REG(vpp_fuse),                \
523
524 #define ROTH_FIXED_REG                          \
525         ADD_FIXED_REG(en_1v8_cam_roth),
526
527 /* Gpio switch regulator platform data for Roth */
528 static struct platform_device *fixed_reg_devs_roth[] = {
529         ADD_FIXED_REG(fan_5v0),
530         ADD_FIXED_REG(vdd_hdmi_5v0),
531         ADD_FIXED_REG(lcd_bl_en),
532         ADD_FIXED_REG(ts_3v3),
533         ADD_FIXED_REG(com_3v3),
534         ADD_FIXED_REG(sd_3v3),
535         ADD_FIXED_REG(com_1v8),
536 };
537
538 int __init roth_palmas_regulator_init(void)
539 {
540         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
541         u32 pmc_ctrl;
542         int i;
543
544         /* TPS65913: Normal state of INT request line is LOW.
545          * configure the power management controller to trigger PMU
546          * interrupts when HIGH.
547          */
548         pmc_ctrl = readl(pmc + PMC_CTRL);
549         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
550         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
551                 pmic_platform.reg_data[i] = roth_reg_data[i];
552                 pmic_platform.reg_init[i] = roth_reg_init[i];
553         }
554
555         i2c_register_board_info(4, palma_device,
556                         ARRAY_SIZE(palma_device));
557         return 0;
558 }
559
560 static int ac_online(void)
561 {
562         return 1;
563 }
564
565 static struct resource roth_pda_resources[] = {
566         [0] = {
567                 .name   = "ac",
568         },
569 };
570
571 static struct pda_power_pdata roth_pda_data = {
572         .is_ac_online   = ac_online,
573 };
574
575 static struct platform_device roth_pda_power_device = {
576         .name           = "pda-power",
577         .id             = -1,
578         .resource       = roth_pda_resources,
579         .num_resources  = ARRAY_SIZE(roth_pda_resources),
580         .dev    = {
581                 .platform_data  = &roth_pda_data,
582         },
583 };
584
585 static struct tegra_suspend_platform_data roth_suspend_data = {
586         .cpu_timer      = 300,
587         .cpu_off_timer  = 300,
588         .suspend_mode   = TEGRA_SUSPEND_LP0,
589         .core_timer     = 0x157e,
590         .core_off_timer = 2000,
591         .corereq_high   = true,
592         .sysclkreq_high = true,
593         .cpu_lp2_min_residency = 1000,
594         .min_residency_noncpu = 2000,
595         .min_residency_crail = 8000,
596 };
597 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
598 /* board parameters for cpu dfll */
599 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
600         .sample_rate = 12500,
601
602         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
603         .cf = 10,
604         .ci = 0,
605         .cg = 2,
606
607         .droop_cut_value = 0xF,
608         .droop_restore_ramp = 0x0,
609         .scale_out_ramp = 0x0,
610 };
611 #endif
612
613 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
614 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
615 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
616 static inline void fill_reg_map(void)
617 {
618         int i;
619         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
620                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
621                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
622         }
623 }
624
625 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
626 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
627         .dfll_clk_name = "dfll_cpu",
628         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
629         .u.pmu_i2c = {
630                 .fs_rate = 400000,
631                 .slave_addr = 0x86,
632                 .reg = 0x00,
633         },
634         .vdd_map = pmu_cpu_vdd_map,
635         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
636
637         .cfg_param = &roth_cl_dvfs_param,
638 };
639
640 static int __init roth_cl_dvfs_init(void)
641 {
642         fill_reg_map();
643         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
644         platform_device_register(&tegra_cl_dvfs_device);
645
646         return 0;
647 }
648 #endif
649
650 static int __init roth_fixed_regulator_init(void)
651 {
652         if (!machine_is_roth())
653                 return 0;
654
655         return platform_add_devices(fixed_reg_devs_roth,
656                                 ARRAY_SIZE(fixed_reg_devs_roth));
657 }
658 subsys_initcall_sync(roth_fixed_regulator_init);
659
660 int __init roth_regulator_init(void)
661 {
662         struct board_info board_info;
663 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
664         roth_cl_dvfs_init();
665 #endif
666         tegra_get_board_info(&board_info);
667         roth_palmas_regulator_init();
668
669         i2c_register_board_info(4, tps51632_boardinfo, 1);
670         i2c_register_board_info(0, bq2419x_boardinfo, 1);
671         platform_device_register(&roth_pda_power_device);
672         return 0;
673 }
674
675 int __init roth_suspend_init(void)
676 {
677         tegra_init_suspend(&roth_suspend_data);
678         return 0;
679 }
680
681 int __init roth_edp_init(void)
682 {
683         unsigned int regulator_mA;
684
685         regulator_mA = get_maximum_cpu_current_supported();
686         if (!regulator_mA)
687                 regulator_mA = 15000;
688
689         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
690         tegra_init_cpu_edp_limits(regulator_mA);
691
692         regulator_mA = get_maximum_core_current_supported();
693         if (!regulator_mA)
694                 regulator_mA = 4000;
695
696         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
697         tegra_init_core_edp_limits(regulator_mA);
698
699         return 0;
700 }
701
702 static struct soctherm_platform_data roth_soctherm_data = {
703         .therm = {
704                 [THERM_CPU] = {
705                         .zone_enable = true,
706                         .passive_delay = 1000,
707                         .num_trips = 3,
708                         .trips = {
709                                 {
710                                         .cdev_type = "tegra-balanced",
711                                         .trip_temp = 84000,
712                                         .trip_type = THERMAL_TRIP_PASSIVE,
713                                         .upper = THERMAL_NO_LIMIT,
714                                         .lower = THERMAL_NO_LIMIT,
715                                 },
716                                 {
717                                         .cdev_type = "tegra-heavy",
718                                         .trip_temp = 94000,
719                                         .trip_type = THERMAL_TRIP_HOT,
720                                         .upper = THERMAL_NO_LIMIT,
721                                         .lower = THERMAL_NO_LIMIT,
722                                 },
723                                 {
724                                         .cdev_type = "tegra-shutdown",
725                                         .trip_temp = 104000,
726                                         .trip_type = THERMAL_TRIP_CRITICAL,
727                                         .upper = THERMAL_NO_LIMIT,
728                                         .lower = THERMAL_NO_LIMIT,
729                                 },
730                         },
731                 },
732                 [THERM_GPU] = {
733                         .zone_enable = true,
734                 },
735                 [THERM_PLL] = {
736                         .zone_enable = true,
737                 },
738         },
739         .throttle = {
740                 [THROTTLE_HEAVY] = {
741                         .devs = {
742                                 [THROTTLE_DEV_CPU] = {
743                                         .enable = 1,
744                                 },
745                         },
746                 },
747         },
748 };
749
750 int __init roth_soctherm_init(void)
751 {
752         return tegra11_soctherm_init(&roth_soctherm_data);
753 }