ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/power/power_supply_extcon.h>
30 #include <linux/regulator/tps51632-regulator.h>
31 #include <linux/power/bq2419x-charger.h>
32 #include <linux/max17048_battery.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/userspace-consumer.h>
35 #include <linux/tegra-soc.h>
36
37 #include <asm/mach-types.h>
38
39 #include <mach/irqs.h>
40 #include <mach/edp.h>
41 #include <mach/gpio-tegra.h>
42
43 #include "cpu-tegra.h"
44 #include "pm.h"
45 #include "tegra-board-id.h"
46 #include "board-pmu-defines.h"
47 #include "board.h"
48 #include "gpio-names.h"
49 #include "board-roth.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53 #include "iomap.h"
54 #include "tegra3_tsensor.h"
55 #include "battery-ini-model-data.h"
56
57 #define PMC_CTRL                0x0
58 #define PMC_CTRL_INTR_LOW       (1 << 17)
59
60 /* TPS51632 DC-DC converter */
61 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
62         REGULATOR_SUPPLY("vdd_cpu", NULL),
63 };
64
65 static struct regulator_init_data tps51632_init_data = {
66         .constraints = {                                                \
67                 .min_uV = 500000,                                       \
68                 .max_uV = 1520000,                                      \
69                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
70                                         REGULATOR_MODE_STANDBY),        \
71                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
72                                         REGULATOR_CHANGE_STATUS |       \
73                                         REGULATOR_CHANGE_VOLTAGE),      \
74                 .always_on = 1,                                         \
75                 .boot_on =  1,                                          \
76                 .apply_uV = 0,                                          \
77         },                                                              \
78         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
79                 .consumer_supplies = tps51632_dcdc_supply,              \
80 };
81
82 static struct tps51632_regulator_platform_data tps51632_pdata = {
83         .reg_init_data = &tps51632_init_data,
84         .enable_pwm_dvfs = false,
85         .max_voltage_uV = 1520000,
86         .base_voltage_uV = 500000,
87 /*      .slew_rate_uv_per_us = 6000, */
88 };
89
90 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
91         {
92                 I2C_BOARD_INFO("tps51632", 0x43),
93                 .platform_data  = &tps51632_pdata,
94         },
95 };
96
97 /* BQ2419X VBUS regulator */
98 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
99         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
100         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
101 };
102
103 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
104         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
105 };
106
107 static struct bq2419x_vbus_platform_data bq2419x_vbus_pdata = {
108         .gpio_otg_iusb = TEGRA_GPIO_PI4,
109         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
110         .consumer_supplies = bq2419x_vbus_supply,
111 };
112
113 struct bq2419x_charger_platform_data bq2419x_charger_pdata = {
114         .max_charge_current_mA = 3000,
115         .charging_term_current_mA = 100,
116         .consumer_supplies = bq2419x_batt_supply,
117         .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
118         .wdt_timeout    = 40,
119         .rtc_alarm_time = 3600,
120         .chg_restart_time = 1800,
121 };
122
123 struct bq2419x_platform_data bq2419x_pdata = {
124         .vbus_pdata = &bq2419x_vbus_pdata,
125         .bcharger_pdata = &bq2419x_charger_pdata,
126 };
127
128 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
129         {
130                 I2C_BOARD_INFO("bq2419x", 0x6b),
131                 .platform_data  = &bq2419x_pdata,
132         },
133 };
134
135 static struct max17048_platform_data max17048_pdata;
136
137 static struct i2c_board_info __initdata max17048_boardinfo[] = {
138         {
139                 I2C_BOARD_INFO("max17048", 0x36),
140                 .platform_data  = &max17048_pdata,
141         },
142 };
143
144 static struct power_supply_extcon_plat_data psy_extcon_pdata = {
145         .extcon_name = "tegra-udc",
146 };
147
148 static struct platform_device psy_extcon_device = {
149         .name = "power-supply-extcon",
150         .id = -1,
151         .dev = {
152                 .platform_data = &psy_extcon_pdata,
153         },
154 };
155
156 /************************ Palmas based regulator ****************/
157 static struct regulator_consumer_supply palmas_smps12_supply[] = {
158         REGULATOR_SUPPLY("vddio_ddr0", NULL),
159         REGULATOR_SUPPLY("vddio_ddr1", NULL),
160 };
161
162 static struct regulator_consumer_supply palmas_smps3_supply[] = {
163         REGULATOR_SUPPLY("avdd_osc", NULL),
164         REGULATOR_SUPPLY("vddio_sys", NULL),
165         REGULATOR_SUPPLY("vddio_gmi", NULL),
166         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
167         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
168         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
169         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
170         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
171         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
172         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
173         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
174         REGULATOR_SUPPLY("vddio_audio", NULL),
175         REGULATOR_SUPPLY("pwrdet_audio", NULL),
176         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
177         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
178         REGULATOR_SUPPLY("vddio_uart", NULL),
179         REGULATOR_SUPPLY("pwrdet_uart", NULL),
180         REGULATOR_SUPPLY("pwrdet_nand", NULL),
181         REGULATOR_SUPPLY("pwrdet_bb", NULL),
182         REGULATOR_SUPPLY("pwrdet_cam", NULL),
183         REGULATOR_SUPPLY("dbvdd", NULL),
184         REGULATOR_SUPPLY("vlogic", "0-0068"),
185 };
186
187 static struct regulator_consumer_supply palmas_smps45_supply[] = {
188         REGULATOR_SUPPLY("vdd_core", NULL),
189 };
190
191 #define palmas_smps457_supply palmas_smps45_supply
192
193 static struct regulator_consumer_supply palmas_smps8_supply[] = {
194         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
195         REGULATOR_SUPPLY("avdd_pllx", NULL),
196         REGULATOR_SUPPLY("avdd_pllm", NULL),
197         REGULATOR_SUPPLY("avdd_pllu", NULL),
198         REGULATOR_SUPPLY("avdd_plle", NULL),
199         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
200         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
201         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
202         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
203         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
204         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
205 };
206
207 static struct regulator_consumer_supply palmas_smps9_supply[] = {
208         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
209 };
210
211 static struct regulator_consumer_supply palmas_smps10_out2_supply[] = {
212         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
213         REGULATOR_SUPPLY("vdd_5v0", NULL),
214 };
215
216 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
217         REGULATOR_SUPPLY("avdd_lcd", NULL),
218         REGULATOR_SUPPLY("vci_2v8", NULL),
219 };
220
221 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
222         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
223         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
224         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
225         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
226 };
227
228 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
229         REGULATOR_SUPPLY("vpp_fuse", NULL),
230 };
231
232 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
233         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
234 };
235
236 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
237         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
238         REGULATOR_SUPPLY("vdd", "0-004c"),
239         REGULATOR_SUPPLY("vdd", "1-004c"),
240         REGULATOR_SUPPLY("vdd", "1-004d"),
241         REGULATOR_SUPPLY("vdd", "0-0068"),
242 };
243
244 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
245         REGULATOR_SUPPLY("vdd_rtc", NULL),
246 };
247
248 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
249         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
250         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
251 };
252
253 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
254         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
255         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
256         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
257         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
258         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
259         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
260         REGULATOR_SUPPLY("pwrdet_hv", NULL),
261 };
262
263 static struct regulator_consumer_supply palmas_regen1_supply[] = {
264         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
265         REGULATOR_SUPPLY("vdd", "4-004c"),
266         REGULATOR_SUPPLY("vdd", "0-004d"),
267         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
268 };
269
270 static struct regulator_consumer_supply palmas_regen2_supply[] = {
271         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
272 };
273
274 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0, NORMAL);
275 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0, NORMAL);
276 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0, NORMAL);
277 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0, NORMAL);
278 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 1, 1, 1, NORMAL);
279 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0, NORMAL);
280 PALMAS_PDATA_INIT(smps10_out2, 5000,  5000, NULL, 0, 0, 0, 0);
281 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1, 0);
282 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1, 0);
283 PALMAS_PDATA_INIT(ldo4, 1800,  1800, NULL, 0, 0, 1, 0);
284 PALMAS_PDATA_INIT(ldo5, 1200,  1200, NULL, 0, 0, 1, 0);
285 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1, 0);
286 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1, 0);
287 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1, 0);
288 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1, 0);
289 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0, 0);
290 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0, 0);
291
292 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
293 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
294         PALMAS_REG_PDATA(smps12),
295         NULL,
296         PALMAS_REG_PDATA(smps3),
297         PALMAS_REG_PDATA(smps45),
298         PALMAS_REG_PDATA(smps457),
299         NULL,
300         NULL,
301         PALMAS_REG_PDATA(smps8),
302         PALMAS_REG_PDATA(smps9),
303         PALMAS_REG_PDATA(smps10_out2),
304         NULL,
305         NULL,   /* LDO1 */
306         PALMAS_REG_PDATA(ldo2),
307         PALMAS_REG_PDATA(ldo3),
308         PALMAS_REG_PDATA(ldo4),
309         PALMAS_REG_PDATA(ldo5),
310         PALMAS_REG_PDATA(ldo6),
311         NULL,
312         PALMAS_REG_PDATA(ldo8),
313         PALMAS_REG_PDATA(ldo9),
314         NULL,
315         NULL,
316         NULL,
317         NULL,
318         NULL,
319         NULL,
320         PALMAS_REG_PDATA(ldousb),
321         PALMAS_REG_PDATA(regen1),
322         PALMAS_REG_PDATA(regen2),
323         NULL,
324         NULL,
325         NULL,
326 };
327
328 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
329                 _vsel)                                                  \
330         static struct palmas_reg_init reg_init_data_##_name = {         \
331                 .warm_reset = _warm_reset,                              \
332                 .roof_floor =   _roof_floor,                            \
333                 .mode_sleep = _mode_sleep,                              \
334                 .vsel = _vsel,                                          \
335         }
336
337 PALMAS_REG_INIT(smps12, 0, 0, 0, 0);
338 PALMAS_REG_INIT(smps123, 0, 0, 0, 0);
339 PALMAS_REG_INIT(smps3, 0, 0, 0, 0);
340 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0);
341 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0);
342 PALMAS_REG_INIT(smps6, 0, 0, 0, 0);
343 PALMAS_REG_INIT(smps7, 0, 0, 0, 0);
344 PALMAS_REG_INIT(smps8, 0, 0, 0, 0);
345 PALMAS_REG_INIT(smps9, 0, 0, 0, 0);
346 PALMAS_REG_INIT(smps10_out2, 0, 0, 0, 0);
347 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0);
348 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0);
349 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0);
350 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0);
351 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0);
352 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0);
353 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0);
354 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0);
355 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0);
356 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0);
357 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0);
358 PALMAS_REG_INIT(regen1, 0, 0, 0, 0);
359 PALMAS_REG_INIT(regen2, 0, 0, 0, 0);
360 PALMAS_REG_INIT(regen3, 0, 0, 0, 0);
361 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0);
362 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0);
363
364 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
365 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
366         PALMAS_REG_INIT_DATA(smps12),
367         PALMAS_REG_INIT_DATA(smps123),
368         PALMAS_REG_INIT_DATA(smps3),
369         PALMAS_REG_INIT_DATA(smps45),
370         PALMAS_REG_INIT_DATA(smps457),
371         PALMAS_REG_INIT_DATA(smps6),
372         PALMAS_REG_INIT_DATA(smps7),
373         PALMAS_REG_INIT_DATA(smps8),
374         PALMAS_REG_INIT_DATA(smps9),
375         PALMAS_REG_INIT_DATA(smps10_out2),
376         NULL,
377         PALMAS_REG_INIT_DATA(ldo1),
378         PALMAS_REG_INIT_DATA(ldo2),
379         PALMAS_REG_INIT_DATA(ldo3),
380         PALMAS_REG_INIT_DATA(ldo4),
381         PALMAS_REG_INIT_DATA(ldo5),
382         PALMAS_REG_INIT_DATA(ldo6),
383         PALMAS_REG_INIT_DATA(ldo7),
384         PALMAS_REG_INIT_DATA(ldo8),
385         PALMAS_REG_INIT_DATA(ldo9),
386         NULL,
387         NULL,
388         NULL,
389         NULL,
390         NULL,
391         PALMAS_REG_INIT_DATA(ldoln),
392         PALMAS_REG_INIT_DATA(ldousb),
393         PALMAS_REG_INIT_DATA(regen1),
394         PALMAS_REG_INIT_DATA(regen2),
395         PALMAS_REG_INIT_DATA(regen3),
396         PALMAS_REG_INIT_DATA(sysen1),
397         PALMAS_REG_INIT_DATA(sysen2),
398 };
399
400 static struct palmas_pmic_platform_data pmic_platform = {
401 };
402
403 static struct palmas_pinctrl_config palmas_pincfg[] = {
404         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
405         PALMAS_PINMUX("vac", "vac", NULL, NULL),
406         PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
407         PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
408         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
409         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
410         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
411         PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
412         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
413         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
414 };
415
416 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
417         .pincfg = palmas_pincfg,
418         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
419         .dvfs1_enable = true,
420         .dvfs2_enable = false,
421 };
422
423 static struct palmas_platform_data palmas_pdata = {
424         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
425         .irq_base = PALMAS_TEGRA_IRQ_BASE,
426         .pmic_pdata = &pmic_platform,
427         .pinctrl_pdata = &palmas_pinctrl_pdata,
428 };
429
430 static struct i2c_board_info palma_device[] = {
431         {
432                 I2C_BOARD_INFO("tps65913", 0x58),
433                 .irq            = INT_EXTERNAL_PMU,
434                 .platform_data  = &palmas_pdata,
435         },
436 };
437
438 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
439         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
440 };
441
442 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
443         REGULATOR_SUPPLY("fan_5v0", NULL),
444 };
445
446 /* LCD_BL_EN GMI_AD10 */
447 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
448         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
449 };
450
451 /* VDD_3V3_COM controled by Wifi */
452 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
453         REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
454         REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
455         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
456 };
457
458 /* VDD_1v8_COM controled by Wifi */
459 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
460         REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
461         REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
462         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
463 };
464
465 /* vdd_3v3_sd PH0 */
466 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
467         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
468 };
469
470 /* EN_3V3_TS From TEGRA_GPIO_PH5 */
471 static struct regulator_consumer_supply fixed_reg_avdd_ts_supply[] = {
472         REGULATOR_SUPPLY("avdd", "spi3.2"),
473 };
474
475 /* EN_1V8_TS From TEGRA_GPIO_PK3 */
476 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
477         REGULATOR_SUPPLY("dvdd", "spi3.2"),
478 };
479
480 /* EN_1V8_TS From TEGRA_GPIO_PU4 */
481 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_supply[] = {
482         REGULATOR_SUPPLY("dvdd_lcd", NULL),
483 };
484 /* Macro for defining fixed regulator sub device data */
485 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
486 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
487         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
488         static struct regulator_init_data ri_data_##_var =              \
489         {                                                               \
490                 .supply_regulator = _in_supply,                         \
491                 .num_consumer_supplies =                                \
492                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
493                 .consumer_supplies = fixed_reg_##_name##_supply,        \
494                 .constraints = {                                        \
495                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
496                                         REGULATOR_MODE_STANDBY),        \
497                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
498                                         REGULATOR_CHANGE_STATUS |       \
499                                         REGULATOR_CHANGE_VOLTAGE),      \
500                         .always_on = _always_on,                        \
501                         .boot_on = _boot_on,                            \
502                 },                                                      \
503         };                                                              \
504         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
505         {                                                               \
506                 .supply_name = FIXED_SUPPLY(_name),                     \
507                 .microvolts = _millivolts * 1000,                       \
508                 .gpio = _gpio_nr,                                       \
509                 .gpio_is_open_drain = _open_drain,                      \
510                 .enable_high = _active_high,                            \
511                 .enabled_at_boot = _boot_state,                         \
512                 .init_data = &ri_data_##_var,                           \
513         };                                                              \
514         static struct platform_device fixed_reg_##_var##_dev = {        \
515                 .name = "reg-fixed-voltage",                            \
516                 .id = _id,                                              \
517                 .dev = {                                                \
518                         .platform_data = &fixed_reg_##_var##_pdata,     \
519                 },                                                      \
520         }
521
522 FIXED_REG(0,    fan_5v0,        fan_5v0,
523         palmas_rails(smps10_out2),      0,      0,
524         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
525
526 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
527         palmas_rails(smps10_out2),      0,      0,
528         TEGRA_GPIO_PK1, false,  true,   0,      5000);
529
530 FIXED_REG(2,    lcd_bl_en,      lcd_bl_en,
531         NULL,   0,      0,
532         TEGRA_GPIO_PH2, false,  true,   1,      5000);
533
534 FIXED_REG(3,    avdd_ts,        avdd_ts,
535         palmas_rails(regen1),   0,      0,
536         TEGRA_GPIO_PH5, false,  true,   0,      3300);
537
538 FIXED_REG(4,    dvdd_ts,        dvdd_ts,
539         palmas_rails(smps3),    0,      0,
540         TEGRA_GPIO_PK3, false,  true,   0,      1800);
541
542 FIXED_REG(5,    com_3v3,        com_3v3,
543         palmas_rails(regen1),   0,      0,
544         TEGRA_GPIO_PX7, false,  true,   0,      3300);
545
546 FIXED_REG(6,    sd_3v3, sd_3v3,
547         palmas_rails(regen1),   0,      0,
548         TEGRA_GPIO_PH0, false,  true,   0,      3300);
549
550 FIXED_REG(7,    com_1v8,        com_1v8,
551         palmas_rails(smps3),    0,      0,
552         TEGRA_GPIO_PX1, false,  true,   0,      1800);
553
554 FIXED_REG(8,    dvdd_lcd,       dvdd_lcd,
555         palmas_rails(smps3),    0,      0,
556         TEGRA_GPIO_PU4, false,  true,   1,      1800);
557
558 /*
559  * Creating the fixed regulator device tables
560  */
561
562 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
563
564 #define ROTH_COMMON_FIXED_REG           \
565         ADD_FIXED_REG(usb1_vbus),               \
566         ADD_FIXED_REG(usb3_vbus),               \
567         ADD_FIXED_REG(vdd_hdmi_5v0),
568
569 #define E1612_FIXED_REG                         \
570         ADD_FIXED_REG(avdd_usb_hdmi),           \
571         ADD_FIXED_REG(en_1v8_cam),              \
572         ADD_FIXED_REG(vpp_fuse),                \
573
574 #define ROTH_FIXED_REG                          \
575         ADD_FIXED_REG(en_1v8_cam_roth),
576
577 /* Gpio switch regulator platform data for Roth */
578 static struct platform_device *fixed_reg_devs_roth[] = {
579         ADD_FIXED_REG(fan_5v0),
580         ADD_FIXED_REG(vdd_hdmi_5v0),
581         ADD_FIXED_REG(lcd_bl_en),
582         ADD_FIXED_REG(avdd_ts),
583         ADD_FIXED_REG(dvdd_ts),
584         ADD_FIXED_REG(com_3v3),
585         ADD_FIXED_REG(sd_3v3),
586         ADD_FIXED_REG(com_1v8),
587         ADD_FIXED_REG(dvdd_lcd),
588 };
589
590 int __init roth_palmas_regulator_init(void)
591 {
592         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
593         u32 pmc_ctrl;
594         int i;
595
596         /* TPS65913: Normal state of INT request line is LOW.
597          * configure the power management controller to trigger PMU
598          * interrupts when HIGH.
599          */
600         pmc_ctrl = readl(pmc + PMC_CTRL);
601         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
602
603         /* Tracking configuration */
604         reg_init_data_ldo8.config_flags =
605                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
606                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
607
608         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
609                 pmic_platform.reg_data[i] = roth_reg_data[i];
610                 pmic_platform.reg_init[i] = roth_reg_init[i];
611         }
612
613         i2c_register_board_info(4, palma_device,
614                         ARRAY_SIZE(palma_device));
615         return 0;
616 }
617
618 static int ac_online(void)
619 {
620         return 1;
621 }
622
623 static struct resource roth_pda_resources[] = {
624         [0] = {
625                 .name   = "ac",
626         },
627 };
628
629 static struct pda_power_pdata roth_pda_data = {
630         .is_ac_online   = ac_online,
631 };
632
633 static struct platform_device roth_pda_power_device = {
634         .name           = "pda-power",
635         .id             = -1,
636         .resource       = roth_pda_resources,
637         .num_resources  = ARRAY_SIZE(roth_pda_resources),
638         .dev    = {
639                 .platform_data  = &roth_pda_data,
640         },
641 };
642
643 static struct tegra_suspend_platform_data roth_suspend_data = {
644         .cpu_timer      = 500,
645         .cpu_off_timer  = 300,
646         .suspend_mode   = TEGRA_SUSPEND_LP0,
647         .core_timer     = 0x157e,
648         .core_off_timer = 2000,
649         .corereq_high   = true,
650         .sysclkreq_high = true,
651         .cpu_lp2_min_residency = 1000,
652         .min_residency_crail = 20000,
653 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
654         .lp1_lowvolt_support = false,
655         .i2c_base_addr = 0,
656         .pmuslave_addr = 0,
657         .core_reg_addr = 0,
658         .lp1_core_volt_low_cold = 0,
659         .lp1_core_volt_low = 0,
660         .lp1_core_volt_high = 0,
661 #endif
662 };
663 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
664 /* board parameters for cpu dfll */
665 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
666         .sample_rate = 12500,
667
668         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
669         .cf = 10,
670         .ci = 0,
671         .cg = 2,
672
673         .droop_cut_value = 0xF,
674         .droop_restore_ramp = 0x0,
675         .scale_out_ramp = 0x0,
676 };
677 #endif
678
679 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
680 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
681 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
682 static inline void fill_reg_map(void)
683 {
684         int i;
685         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
686                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
687                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
688         }
689 }
690
691 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
692 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
693         .dfll_clk_name = "dfll_cpu",
694         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
695         .u.pmu_i2c = {
696                 .fs_rate = 400000,
697                 .slave_addr = 0x86,
698                 .reg = 0x00,
699         },
700         .vdd_map = pmu_cpu_vdd_map,
701         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
702
703         .cfg_param = &roth_cl_dvfs_param,
704 };
705
706 static int __init roth_cl_dvfs_init(void)
707 {
708         fill_reg_map();
709         if (tegra_revision < TEGRA_REVISION_A02)
710                 roth_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
711         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
712         platform_device_register(&tegra_cl_dvfs_device);
713
714         return 0;
715 }
716 #endif
717
718 static int __init roth_fixed_regulator_init(void)
719 {
720         if (!machine_is_roth())
721                 return 0;
722
723         return platform_add_devices(fixed_reg_devs_roth,
724                                 ARRAY_SIZE(fixed_reg_devs_roth));
725 }
726 subsys_initcall_sync(roth_fixed_regulator_init);
727
728 int __init roth_regulator_init(void)
729 {
730         struct board_info board_info;
731 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
732         roth_cl_dvfs_init();
733 #endif
734         tegra_get_board_info(&board_info);
735
736         if (board_info.board_id == BOARD_P2560)
737                 max17048_pdata.model_data = &max17048_mdata_p2560;
738         else
739                 max17048_pdata.model_data = &max17048_mdata_p2454;
740
741         roth_palmas_regulator_init();
742
743         bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
744         i2c_register_board_info(4, tps51632_boardinfo, 1);
745         i2c_register_board_info(0, max17048_boardinfo, 1);
746         i2c_register_board_info(0, bq2419x_boardinfo, 1);
747         platform_device_register(&psy_extcon_device);
748         platform_device_register(&roth_pda_power_device);
749         return 0;
750 }
751
752 int __init roth_suspend_init(void)
753 {
754         tegra_init_suspend(&roth_suspend_data);
755         return 0;
756 }
757
758 int __init roth_edp_init(void)
759 {
760         unsigned int regulator_mA;
761
762         regulator_mA = get_maximum_cpu_current_supported();
763         if (!regulator_mA)
764                 regulator_mA = 15000;
765
766         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
767         tegra_init_cpu_edp_limits(regulator_mA);
768
769         regulator_mA = get_maximum_core_current_supported();
770         if (!regulator_mA)
771                 regulator_mA = 4000;
772
773         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
774         tegra_init_core_edp_limits(regulator_mA);
775
776         return 0;
777 }
778
779 static struct tegra_tsensor_pmu_data tpdata_palmas = {
780         .reset_tegra = 1,
781         .pmu_16bit_ops = 0,
782         .controller_type = 0,
783         .pmu_i2c_addr = 0x58,
784         .i2c_controller_id = 4,
785         .poweroff_reg_addr = 0xa0,
786         .poweroff_reg_data = 0x0,
787 };
788
789 static struct soctherm_platform_data roth_soctherm_data = {
790         .therm = {
791                 [THERM_CPU] = {
792                         .zone_enable = true,
793                         .passive_delay = 1000,
794                         .hotspot_offset = 6000,
795                         .num_trips = 0, /* Disables the trips config below */
796                         /*
797                          * Following .trips config retained for compatibility
798                          * with dalmore/pluto and later enablement when needed
799                          */
800                         .trips = {
801                                 {
802                                         .cdev_type = "tegra-balanced",
803                                         .trip_temp = 90000,
804                                         .trip_type = THERMAL_TRIP_PASSIVE,
805                                         .upper = THERMAL_NO_LIMIT,
806                                         .lower = THERMAL_NO_LIMIT,
807                                 },
808                                 {
809                                         .cdev_type = "tegra-heavy",
810                                         .trip_temp = 100000,
811                                         .trip_type = THERMAL_TRIP_HOT,
812                                         .upper = THERMAL_NO_LIMIT,
813                                         .lower = THERMAL_NO_LIMIT,
814                                 },
815                                 {
816                                         .cdev_type = "tegra-shutdown",
817                                         .trip_temp = 102000,
818                                         .trip_type = THERMAL_TRIP_CRITICAL,
819                                         .upper = THERMAL_NO_LIMIT,
820                                         .lower = THERMAL_NO_LIMIT,
821                                 },
822                         },
823                 },
824                 [THERM_GPU] = {
825                         .zone_enable = true,
826                         .passive_delay = 1000,
827                         .hotspot_offset = 6000,
828                         .num_trips = 0, /* Disables the trips config below */
829                         /*
830                          * Following .trips config retained for compatibility
831                          * with dalmore/pluto and later enablement when needed
832                          */
833                         .trips = {
834                                 {
835                                         .cdev_type = "tegra-balanced",
836                                         .trip_temp = 90000,
837                                         .trip_type = THERMAL_TRIP_PASSIVE,
838                                         .upper = THERMAL_NO_LIMIT,
839                                         .lower = THERMAL_NO_LIMIT,
840                                 },
841                                 {
842                                         .cdev_type = "tegra-heavy",
843                                         .trip_temp = 100000,
844                                         .trip_type = THERMAL_TRIP_HOT,
845                                         .upper = THERMAL_NO_LIMIT,
846                                         .lower = THERMAL_NO_LIMIT,
847                                 },
848                                 {
849                                         .cdev_type = "tegra-shutdown",
850                                         .trip_temp = 102000,
851                                         .trip_type = THERMAL_TRIP_CRITICAL,
852                                         .upper = THERMAL_NO_LIMIT,
853                                         .lower = THERMAL_NO_LIMIT,
854                                 },
855                         },
856                 },
857                 [THERM_PLL] = {
858                         .zone_enable = true,
859                 },
860         },
861         .throttle = {
862                 [THROTTLE_HEAVY] = {
863                         .priority = 100,
864                         .devs = {
865                                 [THROTTLE_DEV_CPU] = {
866                                         .enable = true,
867                                         .depth = 80,
868                                 },
869                                 [THROTTLE_DEV_GPU] = {
870                                         .enable = true,
871                                         .depth = 80,
872                                 },
873                         },
874                 },
875         },
876         .tshut_pmu_trip_data = &tpdata_palmas,
877 };
878
879 int __init roth_soctherm_init(void)
880 {
881         return tegra11_soctherm_init(&roth_soctherm_data);
882 }