2fe289c8d439d2b3b1f3aa5dc07c9242eece7a91
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/gpio.h>
31 #include <linux/regulator/userspace-consumer.h>
32
33 #include <asm/mach-types.h>
34
35 #include <mach/iomap.h>
36 #include <mach/irqs.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "cpu-tegra.h"
41 #include "pm.h"
42 #include "tegra-board-id.h"
43 #include "board.h"
44 #include "gpio-names.h"
45 #include "board-roth.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49
50 #define PMC_CTRL                0x0
51 #define PMC_CTRL_INTR_LOW       (1 << 17)
52
53 /* TPS51632 DC-DC converter */
54 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
55         REGULATOR_SUPPLY("vdd_cpu", NULL),
56 };
57
58 static struct regulator_init_data tps51632_init_data = {
59         .constraints = {                                                \
60                 .min_uV = 500000,                                       \
61                 .max_uV = 1520000,                                      \
62                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
63                                         REGULATOR_MODE_STANDBY),        \
64                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
65                                         REGULATOR_CHANGE_STATUS |       \
66                                         REGULATOR_CHANGE_VOLTAGE),      \
67                 .always_on = 1,                                         \
68                 .boot_on =  1,                                          \
69                 .apply_uV = 0,                                          \
70         },                                                              \
71         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
72                 .consumer_supplies = tps51632_dcdc_supply,              \
73 };
74
75 static struct tps51632_regulator_platform_data tps51632_pdata = {
76         .reg_init_data = &tps51632_init_data,           \
77         .enable_pwm = false,                            \
78         .max_voltage_uV = 1520000,                      \
79         .base_voltage_uV = 500000,                      \
80         .slew_rate_uv_per_us = 6000,                    \
81 };
82
83 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
84         {
85                 I2C_BOARD_INFO("tps51632", 0x43),
86                 .platform_data  = &tps51632_pdata,
87         },
88 };
89
90 /************************ Palmas based regulator ****************/
91 static struct regulator_consumer_supply palmas_smps12_supply[] = {
92         REGULATOR_SUPPLY("vddio_ddr0", NULL),
93         REGULATOR_SUPPLY("vddio_ddr1", NULL),
94 };
95
96 static struct regulator_consumer_supply palmas_smps3_supply[] = {
97         REGULATOR_SUPPLY("avdd_osc", NULL),
98         REGULATOR_SUPPLY("vddio_sys", NULL),
99         REGULATOR_SUPPLY("vddio_gmi", NULL),
100         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
101         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
102         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
103         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
104         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
105         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
106         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
107         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
108         REGULATOR_SUPPLY("vddio_audio", NULL),
109         REGULATOR_SUPPLY("pwrdet_audio", NULL),
110         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
111         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
112         REGULATOR_SUPPLY("vddio_uart", NULL),
113         REGULATOR_SUPPLY("pwrdet_uart", NULL),
114         REGULATOR_SUPPLY("dbvdd", NULL),
115         REGULATOR_SUPPLY("dvdd_lcd", NULL),
116 };
117
118 static struct regulator_consumer_supply palmas_smps45_supply[] = {
119         REGULATOR_SUPPLY("vdd_core", NULL),
120 };
121
122 #define palmas_smps457_supply palmas_smps45_supply
123
124 static struct regulator_consumer_supply palmas_smps8_supply[] = {
125         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
126         REGULATOR_SUPPLY("avdd_pllx", NULL),
127         REGULATOR_SUPPLY("avdd_pllm", NULL),
128         REGULATOR_SUPPLY("avdd_pllu", NULL),
129         REGULATOR_SUPPLY("avdd_plle", NULL),
130         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
131         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
132         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
133         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
134         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
135         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
136         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
137 };
138
139 static struct regulator_consumer_supply palmas_smps9_supply[] = {
140         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
141 };
142
143 static struct regulator_consumer_supply palmas_smps10_supply[] = {
144         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
145         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
146         REGULATOR_SUPPLY("vdd_5v0", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
150         REGULATOR_SUPPLY("avdd_lcd", NULL),
151         REGULATOR_SUPPLY("vci_2v8", NULL),
152 };
153
154 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
155         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
156         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
157         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
158         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
162         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
163         REGULATOR_SUPPLY("vdd", "0-004c"),
164         REGULATOR_SUPPLY("vdd", "1-004c"),
165         REGULATOR_SUPPLY("vdd", "1-004d"),
166 };
167
168 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
169         REGULATOR_SUPPLY("vdd_rtc", NULL),
170 };
171
172 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
173         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
174         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
175 };
176
177 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
178         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
179         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
180         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
181         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
182         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
183         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
184 };
185
186 static struct regulator_consumer_supply palmas_regen1_supply[] = {
187         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
188         REGULATOR_SUPPLY("vdd", "4-004c"),
189         REGULATOR_SUPPLY("vdd", "0-004d"),
190         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
191 };
192
193 static struct regulator_consumer_supply palmas_regen2_supply[] = {
194         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
195 };
196
197 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
198         _boot_on, _apply_uv)                                            \
199         static struct regulator_init_data reg_idata_##_name = {         \
200                 .constraints = {                                        \
201                         .name = palmas_rails(_name),                    \
202                         .min_uV = (_minmv)*1000,                        \
203                         .max_uV = (_maxmv)*1000,                        \
204                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
205                                         REGULATOR_MODE_STANDBY),        \
206                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
207                                         REGULATOR_CHANGE_STATUS |       \
208                                         REGULATOR_CHANGE_VOLTAGE),      \
209                         .always_on = _always_on,                        \
210                         .boot_on = _boot_on,                            \
211                         .apply_uV = _apply_uv,                          \
212                 },                                                      \
213                 .num_consumer_supplies =                                \
214                         ARRAY_SIZE(palmas_##_name##_supply),            \
215                 .consumer_supplies = palmas_##_name##_supply,           \
216                 .supply_regulator = _supply_reg,                        \
217         }
218
219 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
220 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
221 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
222 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0);
223 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 1, 1, 1);
224 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0);
225 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
226 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
227 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1);
228 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
229 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
230 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
231 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
232 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
233 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
234
235 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
236 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
237         PALMAS_REG_PDATA(smps12),
238         NULL,
239         PALMAS_REG_PDATA(smps3),
240         PALMAS_REG_PDATA(smps45),
241         PALMAS_REG_PDATA(smps457),
242         NULL,
243         NULL,
244         PALMAS_REG_PDATA(smps8),
245         PALMAS_REG_PDATA(smps9),
246         PALMAS_REG_PDATA(smps10),
247         NULL,   /* LDO1 */
248         PALMAS_REG_PDATA(ldo2),
249         PALMAS_REG_PDATA(ldo3),
250         NULL,
251         NULL,
252         PALMAS_REG_PDATA(ldo6),
253         NULL,
254         PALMAS_REG_PDATA(ldo8),
255         PALMAS_REG_PDATA(ldo9),
256         NULL,
257         PALMAS_REG_PDATA(ldousb),
258         PALMAS_REG_PDATA(regen1),
259         PALMAS_REG_PDATA(regen2),
260         NULL,
261         NULL,
262         NULL,
263 };
264
265 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
266                 _tstep, _vsel)                                          \
267         static struct palmas_reg_init reg_init_data_##_name = {         \
268                 .warm_reset = _warm_reset,                              \
269                 .roof_floor =   _roof_floor,                            \
270                 .mode_sleep = _mode_sleep,                              \
271                 .tstep = _tstep,                                        \
272                 .vsel = _vsel,                                          \
273         }
274
275 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
276 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
277 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
278 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
279 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
280 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
281 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
282 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
283 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
284 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
285 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
286 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
287 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
288 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
289 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
291 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
295 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
296 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
297 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
298 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
299 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
301
302 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
303 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
304         PALMAS_REG_INIT_DATA(smps12),
305         PALMAS_REG_INIT_DATA(smps123),
306         PALMAS_REG_INIT_DATA(smps3),
307         PALMAS_REG_INIT_DATA(smps45),
308         PALMAS_REG_INIT_DATA(smps457),
309         PALMAS_REG_INIT_DATA(smps6),
310         PALMAS_REG_INIT_DATA(smps7),
311         PALMAS_REG_INIT_DATA(smps8),
312         PALMAS_REG_INIT_DATA(smps9),
313         PALMAS_REG_INIT_DATA(smps10),
314         PALMAS_REG_INIT_DATA(ldo1),
315         PALMAS_REG_INIT_DATA(ldo2),
316         PALMAS_REG_INIT_DATA(ldo3),
317         PALMAS_REG_INIT_DATA(ldo4),
318         PALMAS_REG_INIT_DATA(ldo5),
319         PALMAS_REG_INIT_DATA(ldo6),
320         PALMAS_REG_INIT_DATA(ldo7),
321         PALMAS_REG_INIT_DATA(ldo8),
322         PALMAS_REG_INIT_DATA(ldo9),
323         PALMAS_REG_INIT_DATA(ldoln),
324         PALMAS_REG_INIT_DATA(ldousb),
325         PALMAS_REG_INIT_DATA(regen1),
326         PALMAS_REG_INIT_DATA(regen2),
327         PALMAS_REG_INIT_DATA(regen3),
328         PALMAS_REG_INIT_DATA(sysen1),
329         PALMAS_REG_INIT_DATA(sysen2),
330 };
331
332 static struct palmas_pmic_platform_data pmic_platform = {
333         .enable_ldo8_tracking = true,
334         .disabe_ldo8_tracking_suspend = true,
335 };
336
337 static struct palmas_platform_data palmas_pdata = {
338         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
339         .irq_base = PALMAS_TEGRA_IRQ_BASE,
340         .pmic_pdata = &pmic_platform,
341         .mux_from_pdata = true,
342         .pad1 = 0,
343         .pad2 = 0,
344         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
345         .use_power_off = true,
346 };
347
348 static struct i2c_board_info palma_device[] = {
349         {
350                 I2C_BOARD_INFO("tps65913", 0x58),
351                 .irq            = INT_EXTERNAL_PMU,
352                 .platform_data  = &palmas_pdata,
353         },
354 };
355
356 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
357         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
358 };
359
360 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
361         REGULATOR_SUPPLY("fan_5v0", NULL),
362 };
363
364 /* LCD_BL_EN GMI_AD10 */
365 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
366         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
367 };
368
369 /* Touch 3v3 GMI_AD13 */
370 static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
371         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
372         REGULATOR_SUPPLY("vdd_display", NULL),
373 };
374
375 /* VDD_3V3_COM controled by Wifi */
376 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
377         REGULATOR_SUPPLY("vdd_wl_pa", "bcm4329_wlan.1"),
378         REGULATOR_SUPPLY("vdd_bt_3v3", "reg-userspace-consumer.1"),
379         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
380 };
381
382 /* VDD_1v8_COM controled by Wifi */
383 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
384         REGULATOR_SUPPLY("vddio", "bcm4329_wlan.1"),
385         REGULATOR_SUPPLY("vddio_bt_1v8", "reg-userspace-consumer.1"),
386         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
387 };
388
389 /* vdd_3v3_sd PH0 */
390 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
391         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
392 };
393
394 /* Macro for defining fixed regulator sub device data */
395 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
396 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
397         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
398         static struct regulator_init_data ri_data_##_var =              \
399         {                                                               \
400                 .supply_regulator = _in_supply,                         \
401                 .num_consumer_supplies =                                \
402                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
403                 .consumer_supplies = fixed_reg_##_name##_supply,        \
404                 .constraints = {                                        \
405                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
406                                         REGULATOR_MODE_STANDBY),        \
407                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
408                                         REGULATOR_CHANGE_STATUS |       \
409                                         REGULATOR_CHANGE_VOLTAGE),      \
410                         .always_on = _always_on,                        \
411                         .boot_on = _boot_on,                            \
412                 },                                                      \
413         };                                                              \
414         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
415         {                                                               \
416                 .supply_name = FIXED_SUPPLY(_name),                     \
417                 .microvolts = _millivolts * 1000,                       \
418                 .gpio = _gpio_nr,                                       \
419                 .gpio_is_open_drain = _open_drain,                      \
420                 .enable_high = _active_high,                            \
421                 .enabled_at_boot = _boot_state,                         \
422                 .init_data = &ri_data_##_var,                           \
423         };                                                              \
424         static struct platform_device fixed_reg_##_var##_dev = {        \
425                 .name = "reg-fixed-voltage",                            \
426                 .id = _id,                                              \
427                 .dev = {                                                \
428                         .platform_data = &fixed_reg_##_var##_pdata,     \
429                 },                                                      \
430         }
431
432 FIXED_REG(0,    fan_5v0,        fan_5v0,
433         palmas_rails(smps10),   0,      0,
434         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
435
436 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
437         palmas_rails(smps10),   0,      0,
438         TEGRA_GPIO_PK1, false,  true,   0,      5000);
439
440 FIXED_REG(2,    lcd_bl_en,      lcd_bl_en,
441         NULL,   0,      0,
442         TEGRA_GPIO_PH2, false,  true,   0,      5000);
443
444 FIXED_REG(3,    ts_3v3, ts_3v3,
445         palmas_rails(regen1),   0,      0,
446         TEGRA_GPIO_PH5, false,  true,   0,      3300);
447
448 FIXED_REG(4,    com_3v3,        com_3v3,
449         palmas_rails(regen1),   0,      0,
450         TEGRA_GPIO_PX7, false,  true,   0,      3300);
451
452 FIXED_REG(5,    sd_3v3, sd_3v3,
453         palmas_rails(regen1),   0,      0,
454         TEGRA_GPIO_PH0, false,  true,   0,      3300);
455
456 FIXED_REG(6,    com_1v8,        com_1v8,
457         palmas_rails(smps3),    0,      0,
458         TEGRA_GPIO_PX1, false,  true,   0,      1800);
459
460 /*
461  * Creating the fixed regulator device tables
462  */
463
464 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
465
466 #define ROTH_COMMON_FIXED_REG           \
467         ADD_FIXED_REG(usb1_vbus),               \
468         ADD_FIXED_REG(usb3_vbus),               \
469         ADD_FIXED_REG(vdd_hdmi_5v0),
470
471 #define E1612_FIXED_REG                         \
472         ADD_FIXED_REG(avdd_usb_hdmi),           \
473         ADD_FIXED_REG(en_1v8_cam),              \
474         ADD_FIXED_REG(vpp_fuse),                \
475
476 #define ROTH_FIXED_REG                          \
477         ADD_FIXED_REG(en_1v8_cam_roth),
478
479 /* Gpio switch regulator platform data for Roth */
480 static struct platform_device *fixed_reg_devs_roth[] = {
481         ADD_FIXED_REG(fan_5v0),
482         ADD_FIXED_REG(vdd_hdmi_5v0),
483         ADD_FIXED_REG(lcd_bl_en),
484         ADD_FIXED_REG(ts_3v3),
485         ADD_FIXED_REG(com_3v3),
486         ADD_FIXED_REG(sd_3v3),
487         ADD_FIXED_REG(com_1v8),
488 };
489
490 int __init roth_palmas_regulator_init(void)
491 {
492         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
493         u32 pmc_ctrl;
494         int i;
495
496         /* TPS65913: Normal state of INT request line is LOW.
497          * configure the power management controller to trigger PMU
498          * interrupts when HIGH.
499          */
500         pmc_ctrl = readl(pmc + PMC_CTRL);
501         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
502         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
503                 pmic_platform.reg_data[i] = roth_reg_data[i];
504                 pmic_platform.reg_init[i] = roth_reg_init[i];
505         }
506
507         i2c_register_board_info(4, palma_device,
508                         ARRAY_SIZE(palma_device));
509         return 0;
510 }
511
512 static int ac_online(void)
513 {
514         return 1;
515 }
516
517 static struct resource roth_pda_resources[] = {
518         [0] = {
519                 .name   = "ac",
520         },
521 };
522
523 static struct pda_power_pdata roth_pda_data = {
524         .is_ac_online   = ac_online,
525 };
526
527 static struct platform_device roth_pda_power_device = {
528         .name           = "pda-power",
529         .id             = -1,
530         .resource       = roth_pda_resources,
531         .num_resources  = ARRAY_SIZE(roth_pda_resources),
532         .dev    = {
533                 .platform_data  = &roth_pda_data,
534         },
535 };
536
537 static struct tegra_suspend_platform_data roth_suspend_data = {
538         .cpu_timer      = 300,
539         .cpu_off_timer  = 300,
540         .suspend_mode   = TEGRA_SUSPEND_LP0,
541         .core_timer     = 0x157e,
542         .core_off_timer = 2000,
543         .corereq_high   = true,
544         .sysclkreq_high = true,
545         .min_residency_noncpu = 600,
546         .min_residency_crail = 1000,
547 };
548 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
549 /* board parameters for cpu dfll */
550 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
551         .sample_rate = 12500,
552
553         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
554         .cf = 10,
555         .ci = 0,
556         .cg = 2,
557
558         .droop_cut_value = 0xF,
559         .droop_restore_ramp = 0x0,
560         .scale_out_ramp = 0x0,
561 };
562 #endif
563
564 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
565 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
566 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
567 static inline void fill_reg_map(void)
568 {
569         int i;
570         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
571                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
572                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
573         }
574 }
575
576 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
577 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
578         .dfll_clk_name = "dfll_cpu",
579         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
580         .u.pmu_i2c = {
581                 .fs_rate = 400000,
582                 .slave_addr = 0x86,
583                 .reg = 0x00,
584         },
585         .vdd_map = pmu_cpu_vdd_map,
586         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
587
588         .cfg_param = &roth_cl_dvfs_param,
589 };
590
591 static int __init roth_cl_dvfs_init(void)
592 {
593         fill_reg_map();
594         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
595         platform_device_register(&tegra_cl_dvfs_device);
596
597         return 0;
598 }
599 #endif
600
601 static struct regulator_bulk_data roth_gps_regulator_supply[] = {
602         [0] = {
603                 .supply = "vdd_gps_3v3",
604         },
605         [1] = {
606                 .supply = "vdd_gps_1v8",
607         },
608 };
609
610 static struct regulator_userspace_consumer_data roth_gps_regulator_pdata = {
611         .num_supplies   = ARRAY_SIZE(roth_gps_regulator_supply),
612         .supplies       = roth_gps_regulator_supply,
613 };
614
615 static struct platform_device roth_gps_regulator_device = {
616         .name   = "reg-userspace-consumer",
617         .id     = 2,
618         .dev    = {
619                         .platform_data = &roth_gps_regulator_pdata,
620         },
621 };
622
623 static struct regulator_bulk_data roth_bt_regulator_supply[] = {
624         [0] = {
625                 .supply = "vdd_bt_3v3",
626         },
627         [1] = {
628                 .supply = "vddio_bt_1v8",
629         },
630 };
631
632 static struct regulator_userspace_consumer_data roth_bt_regulator_pdata = {
633         .num_supplies   = ARRAY_SIZE(roth_bt_regulator_supply),
634         .supplies       = roth_bt_regulator_supply,
635 };
636
637 static struct platform_device roth_bt_regulator_device = {
638         .name   = "reg-userspace-consumer",
639         .id     = 1,
640         .dev    = {
641                         .platform_data = &roth_bt_regulator_pdata,
642         },
643 };
644
645 static int __init roth_fixed_regulator_init(void)
646 {
647         if (!machine_is_roth())
648                 return 0;
649
650         return platform_add_devices(fixed_reg_devs_roth,
651                                 ARRAY_SIZE(fixed_reg_devs_roth));
652 }
653 subsys_initcall_sync(roth_fixed_regulator_init);
654
655 int __init roth_regulator_init(void)
656 {
657         struct board_info board_info;
658 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
659         roth_cl_dvfs_init();
660 #endif
661         tegra_get_board_info(&board_info);
662         roth_palmas_regulator_init();
663
664         i2c_register_board_info(4, tps51632_boardinfo, 1);
665         platform_device_register(&roth_pda_power_device);
666         platform_device_register(&roth_bt_regulator_device);
667         platform_device_register(&roth_gps_regulator_device);
668         return 0;
669 }
670
671 int __init roth_suspend_init(void)
672 {
673         tegra_init_suspend(&roth_suspend_data);
674         return 0;
675 }
676
677 int __init roth_edp_init(void)
678 {
679 #ifdef CONFIG_TEGRA_EDP_LIMITS
680         unsigned int regulator_mA;
681
682         regulator_mA = get_maximum_cpu_current_supported();
683         if (!regulator_mA)
684                 regulator_mA = 15000;
685
686         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
687
688         tegra_init_cpu_edp_limits(regulator_mA);
689 #endif
690         return 0;
691 }
692
693 static struct soctherm_platform_data roth_soctherm_data = {
694         .soctherm_clk_rate = 136000000,
695         .tsensor_clk_rate = 500000,
696         .sensor_data = {
697                 [TSENSE_CPU0] = {
698                         .enable = true,
699                         .tall = 16300,
700                         .tiddq = 1,
701                         .ten_count = 1,
702                         .tsample = 163,
703                         .pdiv = 10,
704                 },
705                 [TSENSE_CPU1] = {
706                         .enable = true,
707                         .tall = 16300,
708                         .tiddq = 1,
709                         .ten_count = 1,
710                         .tsample = 163,
711                         .pdiv = 10,
712                 },
713                 [TSENSE_CPU2] = {
714                         .enable = true,
715                         .tall = 16300,
716                         .tiddq = 1,
717                         .ten_count = 1,
718                         .tsample = 163,
719                         .pdiv = 10,
720                 },
721                 [TSENSE_CPU3] = {
722                         .enable = true,
723                         .tall = 16300,
724                         .tiddq = 1,
725                         .ten_count = 1,
726                         .tsample = 163,
727                         .pdiv = 10,
728                 },
729                 [TSENSE_MEM0] = {
730                         .enable = true,
731                         .tall = 16300,
732                         .tiddq = 1,
733                         .ten_count = 1,
734                         .tsample = 163,
735                         .pdiv = 10,
736                 },
737                 [TSENSE_MEM1] = {
738                         .enable = true,
739                         .tall = 16300,
740                         .tiddq = 1,
741                         .ten_count = 1,
742                         .tsample = 163,
743                         .pdiv = 10,
744                 },
745                 [TSENSE_GPU] = {
746                         .enable = true,
747                         .tall = 16300,
748                         .tiddq = 1,
749                         .ten_count = 1,
750                         .tsample = 163,
751                         .pdiv = 10,
752                 },
753                 [TSENSE_PLLX] = {
754                         .enable = true,
755                         .tall = 16300,
756                         .tiddq = 1,
757                         .ten_count = 1,
758                         .tsample = 163,
759                         .pdiv = 10,
760                 },
761         },
762 };
763
764 int __init roth_soctherm_init(void)
765 {
766         return tegra11_soctherm_init(&roth_soctherm_data);
767 }