1cb3bc48ce8d06351626f30f968cf92a935e9aad
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-power.c
1 /*
2  * arch/arm/mach-tegra/board-roth-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/regulator/tps51632-regulator.h>
30 #include <linux/mfd/bq2419x.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33
34 #include <asm/mach-types.h>
35
36 #include <mach/irqs.h>
37 #include <mach/edp.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "cpu-tegra.h"
41 #include "pm.h"
42 #include "tegra-board-id.h"
43 #include "board.h"
44 #include "gpio-names.h"
45 #include "board-roth.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49 #include "iomap.h"
50 #include "tegra3_tsensor.h"
51
52 #define PMC_CTRL                0x0
53 #define PMC_CTRL_INTR_LOW       (1 << 17)
54
55 /* TPS51632 DC-DC converter */
56 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
57         REGULATOR_SUPPLY("vdd_cpu", NULL),
58 };
59
60 static struct regulator_init_data tps51632_init_data = {
61         .constraints = {                                                \
62                 .min_uV = 500000,                                       \
63                 .max_uV = 1520000,                                      \
64                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
65                                         REGULATOR_MODE_STANDBY),        \
66                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
67                                         REGULATOR_CHANGE_STATUS |       \
68                                         REGULATOR_CHANGE_VOLTAGE),      \
69                 .always_on = 1,                                         \
70                 .boot_on =  1,                                          \
71                 .apply_uV = 0,                                          \
72         },                                                              \
73         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
74                 .consumer_supplies = tps51632_dcdc_supply,              \
75 };
76
77 static struct tps51632_regulator_platform_data tps51632_pdata = {
78         .reg_init_data = &tps51632_init_data,           \
79         .enable_pwm = false,                            \
80         .max_voltage_uV = 1520000,                      \
81         .base_voltage_uV = 500000,                      \
82         .slew_rate_uv_per_us = 6000,                    \
83 };
84
85 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
86         {
87                 I2C_BOARD_INFO("tps51632", 0x43),
88                 .platform_data  = &tps51632_pdata,
89         },
90 };
91
92
93 /* BQ2419X VBUS regulator */
94 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
95         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
96 };
97 static struct regulator_init_data bq2419x_init_data = {
98         .constraints = {
99                 .name = "bq2419x_vbus",
100                 .min_uV = 0,
101                 .max_uV = 5000000,
102                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
103                                         REGULATOR_MODE_STANDBY),
104                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
105                                         REGULATOR_CHANGE_STATUS |
106                                         REGULATOR_CHANGE_VOLTAGE),
107         },
108         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
109         .consumer_supplies = bq2419x_vbus_supply,
110 };
111
112 static struct bq2419x_regulator_platform_data bq2419x_reg_pdata = {
113         .reg_init_data = &bq2419x_init_data,
114         .gpio_otg_iusb = TEGRA_GPIO_PI4,
115 };
116
117 struct bq2419x_charger_platform_data bq2419x_charger_pdata = {
118         .usb_in_current_limit = 400,
119         .ac_in_current_limit = 1000,
120         .use_usb = 1,
121         .gpio_interrupt = TEGRA_GPIO_PJ0,
122         .gpio_status = TEGRA_GPIO_PK0,
123 };
124
125 struct bq2419x_platform_data bq2419x_pdata = {
126         .reg_pdata = &bq2419x_reg_pdata,
127         .bcharger_pdata = &bq2419x_charger_pdata,
128         .disable_watchdog = true,
129 };
130
131 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
132         {
133                 I2C_BOARD_INFO("bq2419x", 0x6b),
134                 .platform_data  = &bq2419x_pdata,
135         },
136 };
137
138 /************************ Palmas based regulator ****************/
139 static struct regulator_consumer_supply palmas_smps12_supply[] = {
140         REGULATOR_SUPPLY("vddio_ddr0", NULL),
141         REGULATOR_SUPPLY("vddio_ddr1", NULL),
142 };
143
144 static struct regulator_consumer_supply palmas_smps3_supply[] = {
145         REGULATOR_SUPPLY("avdd_osc", NULL),
146         REGULATOR_SUPPLY("vddio_sys", NULL),
147         REGULATOR_SUPPLY("vddio_gmi", NULL),
148         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
149         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
150         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
151         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
152         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
153         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
154         REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"),
155         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
156         REGULATOR_SUPPLY("vddio_audio", NULL),
157         REGULATOR_SUPPLY("pwrdet_audio", NULL),
158         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
159         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
160         REGULATOR_SUPPLY("vddio_uart", NULL),
161         REGULATOR_SUPPLY("pwrdet_uart", NULL),
162         REGULATOR_SUPPLY("dbvdd", NULL),
163         REGULATOR_SUPPLY("dvdd_lcd", NULL),
164         REGULATOR_SUPPLY("vlogic", "0-0068"),
165 };
166
167 static struct regulator_consumer_supply palmas_smps45_supply[] = {
168         REGULATOR_SUPPLY("vdd_core", NULL),
169 };
170
171 #define palmas_smps457_supply palmas_smps45_supply
172
173 static struct regulator_consumer_supply palmas_smps8_supply[] = {
174         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
175         REGULATOR_SUPPLY("avdd_pllx", NULL),
176         REGULATOR_SUPPLY("avdd_pllm", NULL),
177         REGULATOR_SUPPLY("avdd_pllu", NULL),
178         REGULATOR_SUPPLY("avdd_plle", NULL),
179         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
180         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
181         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
182         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
183         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
184         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
185         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
186 };
187
188 static struct regulator_consumer_supply palmas_smps9_supply[] = {
189         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
190 };
191
192 static struct regulator_consumer_supply palmas_smps10_supply[] = {
193         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
194         REGULATOR_SUPPLY("vdd_5v0", NULL),
195 };
196
197 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
198         REGULATOR_SUPPLY("avdd_lcd", NULL),
199         REGULATOR_SUPPLY("vci_2v8", NULL),
200 };
201
202 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
203         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
204         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
205         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
206         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
207 };
208
209 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
210         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
211         REGULATOR_SUPPLY("vdd", "0-004c"),
212         REGULATOR_SUPPLY("vdd", "1-004c"),
213         REGULATOR_SUPPLY("vdd", "1-004d"),
214         REGULATOR_SUPPLY("vdd", "0-0068"),
215 };
216
217 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
218         REGULATOR_SUPPLY("vdd_rtc", NULL),
219 };
220
221 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
222         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
223         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
224 };
225
226 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
227         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
228         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
229         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
230         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
231         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
232         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
233 };
234
235 static struct regulator_consumer_supply palmas_regen1_supply[] = {
236         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
237         REGULATOR_SUPPLY("vdd", "4-004c"),
238         REGULATOR_SUPPLY("vdd", "0-004d"),
239         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
240 };
241
242 static struct regulator_consumer_supply palmas_regen2_supply[] = {
243         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
244 };
245
246 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
247         _boot_on, _apply_uv)                                            \
248         static struct regulator_init_data reg_idata_##_name = {         \
249                 .constraints = {                                        \
250                         .name = palmas_rails(_name),                    \
251                         .min_uV = (_minmv)*1000,                        \
252                         .max_uV = (_maxmv)*1000,                        \
253                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
254                                         REGULATOR_MODE_STANDBY),        \
255                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
256                                         REGULATOR_CHANGE_STATUS |       \
257                                         REGULATOR_CHANGE_VOLTAGE),      \
258                         .always_on = _always_on,                        \
259                         .boot_on = _boot_on,                            \
260                         .apply_uV = _apply_uv,                          \
261                 },                                                      \
262                 .num_consumer_supplies =                                \
263                         ARRAY_SIZE(palmas_##_name##_supply),            \
264                 .consumer_supplies = palmas_##_name##_supply,           \
265                 .supply_regulator = _supply_reg,                        \
266         }
267
268 PALMAS_PDATA_INIT(smps12, 1200,  1500, NULL, 0, 0, 0);
269 PALMAS_PDATA_INIT(smps3, 1800,  1800, NULL, 0, 0, 0);
270 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 1, 1, 0);
271 PALMAS_PDATA_INIT(smps457, 900,  1400, NULL, 1, 1, 0);
272 PALMAS_PDATA_INIT(smps8, 1050,  1050, NULL, 1, 1, 1);
273 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 0, 0, 0);
274 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
275 PALMAS_PDATA_INIT(ldo2, 2800,  2800, NULL, 0, 0, 1);
276 PALMAS_PDATA_INIT(ldo3, 1200,  1200, NULL, 1, 1, 1);
277 PALMAS_PDATA_INIT(ldo6, 2850,  2850, NULL, 0, 0, 1);
278 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
279 PALMAS_PDATA_INIT(ldo9, 1800,  3300, NULL, 0, 0, 1);
280 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
281 PALMAS_PDATA_INIT(regen1, 3300,  3300, NULL, 0, 0, 0);
282 PALMAS_PDATA_INIT(regen2, 5000,  5000, NULL, 0, 0, 0);
283
284 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
285 static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = {
286         PALMAS_REG_PDATA(smps12),
287         NULL,
288         PALMAS_REG_PDATA(smps3),
289         PALMAS_REG_PDATA(smps45),
290         PALMAS_REG_PDATA(smps457),
291         NULL,
292         NULL,
293         PALMAS_REG_PDATA(smps8),
294         PALMAS_REG_PDATA(smps9),
295         PALMAS_REG_PDATA(smps10),
296         NULL,   /* LDO1 */
297         PALMAS_REG_PDATA(ldo2),
298         PALMAS_REG_PDATA(ldo3),
299         NULL,
300         NULL,
301         PALMAS_REG_PDATA(ldo6),
302         NULL,
303         PALMAS_REG_PDATA(ldo8),
304         PALMAS_REG_PDATA(ldo9),
305         NULL,
306         PALMAS_REG_PDATA(ldousb),
307         PALMAS_REG_PDATA(regen1),
308         PALMAS_REG_PDATA(regen2),
309         NULL,
310         NULL,
311         NULL,
312 };
313
314 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
315                 _tstep, _vsel)                                          \
316         static struct palmas_reg_init reg_init_data_##_name = {         \
317                 .warm_reset = _warm_reset,                              \
318                 .roof_floor =   _roof_floor,                            \
319                 .mode_sleep = _mode_sleep,                              \
320                 .tstep = _tstep,                                        \
321                 .vsel = _vsel,                                          \
322         }
323
324 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
325 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
326 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
327 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
328 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
329 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
330 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
331 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
332 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
333 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
334 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
335 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
336 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
337 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
338 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
339 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
340 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
341 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
342 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
343 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
344 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
345 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
346 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
347 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
348 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
349 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
350
351 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
352 static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = {
353         PALMAS_REG_INIT_DATA(smps12),
354         PALMAS_REG_INIT_DATA(smps123),
355         PALMAS_REG_INIT_DATA(smps3),
356         PALMAS_REG_INIT_DATA(smps45),
357         PALMAS_REG_INIT_DATA(smps457),
358         PALMAS_REG_INIT_DATA(smps6),
359         PALMAS_REG_INIT_DATA(smps7),
360         PALMAS_REG_INIT_DATA(smps8),
361         PALMAS_REG_INIT_DATA(smps9),
362         PALMAS_REG_INIT_DATA(smps10),
363         PALMAS_REG_INIT_DATA(ldo1),
364         PALMAS_REG_INIT_DATA(ldo2),
365         PALMAS_REG_INIT_DATA(ldo3),
366         PALMAS_REG_INIT_DATA(ldo4),
367         PALMAS_REG_INIT_DATA(ldo5),
368         PALMAS_REG_INIT_DATA(ldo6),
369         PALMAS_REG_INIT_DATA(ldo7),
370         PALMAS_REG_INIT_DATA(ldo8),
371         PALMAS_REG_INIT_DATA(ldo9),
372         PALMAS_REG_INIT_DATA(ldoln),
373         PALMAS_REG_INIT_DATA(ldousb),
374         PALMAS_REG_INIT_DATA(regen1),
375         PALMAS_REG_INIT_DATA(regen2),
376         PALMAS_REG_INIT_DATA(regen3),
377         PALMAS_REG_INIT_DATA(sysen1),
378         PALMAS_REG_INIT_DATA(sysen2),
379 };
380
381 static struct palmas_pmic_platform_data pmic_platform = {
382         .enable_ldo8_tracking = true,
383         .disabe_ldo8_tracking_suspend = true,
384 };
385
386 static struct palmas_platform_data palmas_pdata = {
387         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
388         .irq_base = PALMAS_TEGRA_IRQ_BASE,
389         .pmic_pdata = &pmic_platform,
390         .mux_from_pdata = true,
391         .pad1 = 0,
392         .pad2 = 0,
393         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
394         .use_power_off = true,
395 };
396
397 static struct i2c_board_info palma_device[] = {
398         {
399                 I2C_BOARD_INFO("tps65913", 0x58),
400                 .irq            = INT_EXTERNAL_PMU,
401                 .platform_data  = &palmas_pdata,
402         },
403 };
404
405 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
406         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
407 };
408
409 static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = {
410         REGULATOR_SUPPLY("fan_5v0", NULL),
411 };
412
413 /* LCD_BL_EN GMI_AD10 */
414 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
415         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
416 };
417
418 /* Touch 3v3 GMI_AD13 */
419 static struct regulator_consumer_supply fixed_reg_ts_3v3_supply[] = {
420         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
421         REGULATOR_SUPPLY("vdd_display", NULL),
422 };
423
424 /* VDD_3V3_COM controled by Wifi */
425 static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = {
426         REGULATOR_SUPPLY("vdd_wl_pa", "bcm4329_wlan.1"),
427         REGULATOR_SUPPLY("vdd_bt_3v3", "bluedroid_pm.0"),
428         REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"),
429 };
430
431 /* VDD_1v8_COM controled by Wifi */
432 static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = {
433         REGULATOR_SUPPLY("vddio", "bcm4329_wlan.1"),
434         REGULATOR_SUPPLY("vddio_bt_1v8", "bluedroid_pm.0"),
435         REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"),
436 };
437
438 /* vdd_3v3_sd PH0 */
439 static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = {
440         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
441 };
442
443 /* Macro for defining fixed regulator sub device data */
444 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
445 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
446         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
447         static struct regulator_init_data ri_data_##_var =              \
448         {                                                               \
449                 .supply_regulator = _in_supply,                         \
450                 .num_consumer_supplies =                                \
451                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
452                 .consumer_supplies = fixed_reg_##_name##_supply,        \
453                 .constraints = {                                        \
454                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
455                                         REGULATOR_MODE_STANDBY),        \
456                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
457                                         REGULATOR_CHANGE_STATUS |       \
458                                         REGULATOR_CHANGE_VOLTAGE),      \
459                         .always_on = _always_on,                        \
460                         .boot_on = _boot_on,                            \
461                 },                                                      \
462         };                                                              \
463         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
464         {                                                               \
465                 .supply_name = FIXED_SUPPLY(_name),                     \
466                 .microvolts = _millivolts * 1000,                       \
467                 .gpio = _gpio_nr,                                       \
468                 .gpio_is_open_drain = _open_drain,                      \
469                 .enable_high = _active_high,                            \
470                 .enabled_at_boot = _boot_state,                         \
471                 .init_data = &ri_data_##_var,                           \
472         };                                                              \
473         static struct platform_device fixed_reg_##_var##_dev = {        \
474                 .name = "reg-fixed-voltage",                            \
475                 .id = _id,                                              \
476                 .dev = {                                                \
477                         .platform_data = &fixed_reg_##_var##_pdata,     \
478                 },                                                      \
479         }
480
481 FIXED_REG(0,    fan_5v0,        fan_5v0,
482         palmas_rails(smps10),   0,      0,
483         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      5000);
484
485 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
486         palmas_rails(smps10),   0,      0,
487         TEGRA_GPIO_PK1, false,  true,   0,      5000);
488
489 FIXED_REG(2,    lcd_bl_en,      lcd_bl_en,
490         NULL,   0,      0,
491         TEGRA_GPIO_PH2, false,  true,   0,      5000);
492
493 FIXED_REG(3,    ts_3v3, ts_3v3,
494         palmas_rails(regen1),   0,      0,
495         TEGRA_GPIO_PH5, false,  true,   0,      3300);
496
497 FIXED_REG(4,    com_3v3,        com_3v3,
498         palmas_rails(regen1),   0,      0,
499         TEGRA_GPIO_PX7, false,  true,   0,      3300);
500
501 FIXED_REG(5,    sd_3v3, sd_3v3,
502         palmas_rails(regen1),   0,      0,
503         TEGRA_GPIO_PH0, false,  true,   0,      3300);
504
505 FIXED_REG(6,    com_1v8,        com_1v8,
506         palmas_rails(smps3),    0,      0,
507         TEGRA_GPIO_PX1, false,  true,   0,      1800);
508
509 /*
510  * Creating the fixed regulator device tables
511  */
512
513 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
514
515 #define ROTH_COMMON_FIXED_REG           \
516         ADD_FIXED_REG(usb1_vbus),               \
517         ADD_FIXED_REG(usb3_vbus),               \
518         ADD_FIXED_REG(vdd_hdmi_5v0),
519
520 #define E1612_FIXED_REG                         \
521         ADD_FIXED_REG(avdd_usb_hdmi),           \
522         ADD_FIXED_REG(en_1v8_cam),              \
523         ADD_FIXED_REG(vpp_fuse),                \
524
525 #define ROTH_FIXED_REG                          \
526         ADD_FIXED_REG(en_1v8_cam_roth),
527
528 /* Gpio switch regulator platform data for Roth */
529 static struct platform_device *fixed_reg_devs_roth[] = {
530         ADD_FIXED_REG(fan_5v0),
531         ADD_FIXED_REG(vdd_hdmi_5v0),
532         ADD_FIXED_REG(lcd_bl_en),
533         ADD_FIXED_REG(ts_3v3),
534         ADD_FIXED_REG(com_3v3),
535         ADD_FIXED_REG(sd_3v3),
536         ADD_FIXED_REG(com_1v8),
537 };
538
539 int __init roth_palmas_regulator_init(void)
540 {
541         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
542         u32 pmc_ctrl;
543         int i;
544
545         /* TPS65913: Normal state of INT request line is LOW.
546          * configure the power management controller to trigger PMU
547          * interrupts when HIGH.
548          */
549         pmc_ctrl = readl(pmc + PMC_CTRL);
550         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
551         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
552                 pmic_platform.reg_data[i] = roth_reg_data[i];
553                 pmic_platform.reg_init[i] = roth_reg_init[i];
554         }
555
556         i2c_register_board_info(4, palma_device,
557                         ARRAY_SIZE(palma_device));
558         return 0;
559 }
560
561 static int ac_online(void)
562 {
563         return 1;
564 }
565
566 static struct resource roth_pda_resources[] = {
567         [0] = {
568                 .name   = "ac",
569         },
570 };
571
572 static struct pda_power_pdata roth_pda_data = {
573         .is_ac_online   = ac_online,
574 };
575
576 static struct platform_device roth_pda_power_device = {
577         .name           = "pda-power",
578         .id             = -1,
579         .resource       = roth_pda_resources,
580         .num_resources  = ARRAY_SIZE(roth_pda_resources),
581         .dev    = {
582                 .platform_data  = &roth_pda_data,
583         },
584 };
585
586 static struct tegra_suspend_platform_data roth_suspend_data = {
587         .cpu_timer      = 300,
588         .cpu_off_timer  = 300,
589         .suspend_mode   = TEGRA_SUSPEND_LP0,
590         .core_timer     = 0x157e,
591         .core_off_timer = 2000,
592         .corereq_high   = true,
593         .sysclkreq_high = true,
594         .cpu_lp2_min_residency = 1000,
595         .min_residency_noncpu = 2000,
596         .min_residency_crail = 8000,
597 };
598 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
599 /* board parameters for cpu dfll */
600 static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = {
601         .sample_rate = 12500,
602
603         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
604         .cf = 10,
605         .ci = 0,
606         .cg = 2,
607
608         .droop_cut_value = 0xF,
609         .droop_restore_ramp = 0x0,
610         .scale_out_ramp = 0x0,
611 };
612 #endif
613
614 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
615 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
616 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
617 static inline void fill_reg_map(void)
618 {
619         int i;
620         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
621                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
622                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
623         }
624 }
625
626 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
627 static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = {
628         .dfll_clk_name = "dfll_cpu",
629         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
630         .u.pmu_i2c = {
631                 .fs_rate = 400000,
632                 .slave_addr = 0x86,
633                 .reg = 0x00,
634         },
635         .vdd_map = pmu_cpu_vdd_map,
636         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
637
638         .cfg_param = &roth_cl_dvfs_param,
639 };
640
641 static int __init roth_cl_dvfs_init(void)
642 {
643         fill_reg_map();
644         tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data;
645         platform_device_register(&tegra_cl_dvfs_device);
646
647         return 0;
648 }
649 #endif
650
651 static int __init roth_fixed_regulator_init(void)
652 {
653         if (!machine_is_roth())
654                 return 0;
655
656         return platform_add_devices(fixed_reg_devs_roth,
657                                 ARRAY_SIZE(fixed_reg_devs_roth));
658 }
659 subsys_initcall_sync(roth_fixed_regulator_init);
660
661 int __init roth_regulator_init(void)
662 {
663         struct board_info board_info;
664 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
665         roth_cl_dvfs_init();
666 #endif
667         tegra_get_board_info(&board_info);
668         roth_palmas_regulator_init();
669
670         i2c_register_board_info(4, tps51632_boardinfo, 1);
671         i2c_register_board_info(0, bq2419x_boardinfo, 1);
672         platform_device_register(&roth_pda_power_device);
673         return 0;
674 }
675
676 int __init roth_suspend_init(void)
677 {
678         tegra_init_suspend(&roth_suspend_data);
679         return 0;
680 }
681
682 int __init roth_edp_init(void)
683 {
684         unsigned int regulator_mA;
685
686         regulator_mA = get_maximum_cpu_current_supported();
687         if (!regulator_mA)
688                 regulator_mA = 15000;
689
690         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
691         tegra_init_cpu_edp_limits(regulator_mA);
692
693         regulator_mA = get_maximum_core_current_supported();
694         if (!regulator_mA)
695                 regulator_mA = 4000;
696
697         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
698         tegra_init_core_edp_limits(regulator_mA);
699
700         return 0;
701 }
702
703 static struct tegra_tsensor_pmu_data tpdata_palmas = {
704         .reset_tegra = 1,
705         .pmu_16bit_ops = 0,
706         .controller_type = 0,
707         .pmu_i2c_addr = 0x58,
708         .i2c_controller_id = 4,
709         .poweroff_reg_addr = 0xa0,
710         .poweroff_reg_data = 0x0,
711 };
712
713 static struct soctherm_platform_data roth_soctherm_data = {
714         .therm = {
715                 [THERM_CPU] = {
716                         .zone_enable = true,
717                         .passive_delay = 1000,
718                         .num_trips = 0, /* Disables the trips config below */
719                         /*
720                          * Following .trips config retained for compatibility
721                          * with dalmore/pluto and later enablement when needed
722                          */
723                         .trips = {
724                                 {
725                                         .cdev_type = "tegra-balanced",
726                                         .trip_temp = 84000,
727                                         .trip_type = THERMAL_TRIP_PASSIVE,
728                                         .upper = THERMAL_NO_LIMIT,
729                                         .lower = THERMAL_NO_LIMIT,
730                                 },
731                                 {
732                                         .cdev_type = "tegra-heavy",
733                                         .trip_temp = 94000,
734                                         .trip_type = THERMAL_TRIP_HOT,
735                                         .upper = THERMAL_NO_LIMIT,
736                                         .lower = THERMAL_NO_LIMIT,
737                                 },
738                                 {
739                                         .cdev_type = "tegra-shutdown",
740                                         .trip_temp = 104000,
741                                         .trip_type = THERMAL_TRIP_CRITICAL,
742                                         .upper = THERMAL_NO_LIMIT,
743                                         .lower = THERMAL_NO_LIMIT,
744                                 },
745                         },
746                 },
747                 [THERM_GPU] = {
748                         .zone_enable = true,
749                 },
750                 [THERM_PLL] = {
751                         .zone_enable = true,
752                 },
753         },
754         .throttle = {
755                 [THROTTLE_HEAVY] = {
756                         .devs = {
757                                 [THROTTLE_DEV_CPU] = {
758                                         .enable = 1,
759                                 },
760                         },
761                 },
762         },
763         .tshut_pmu_trip_data = &tpdata_palmas,
764 };
765
766 int __init roth_soctherm_init(void)
767 {
768         return tegra11_soctherm_init(&roth_soctherm_data);
769 }