ARM: DT: Add DT entry for PWMs and Backlight
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-panel.c
1 /*
2  * arch/arm/mach-tegra/board-roth-panel.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31
32 #include <mach/irqs.h>
33 #include <mach/dc.h>
34 #include <mach/pinmux.h>
35 #include <mach/pinmux-t11.h>
36 #include <asm/mach-types.h>
37
38 #include "board.h"
39 #include "board-panel.h"
40 #include "devices.h"
41 #include "gpio-names.h"
42 #include "iomap.h"
43 #include "tegra11_host1x_devices.h"
44
45 struct platform_device * __init roth_host1x_init(void)
46 {
47         struct platform_device *pdev = NULL;
48
49 #ifdef CONFIG_TEGRA_GRHOST
50         if (!of_have_populated_dt())
51                 pdev = tegra11_register_host1x_devices();
52         else
53                 pdev = to_platform_device(bus_find_device_by_name(
54                         &platform_bus_type, NULL, "host1x"));
55 #endif
56         return pdev;
57 }
58
59 #define IS_EXTERNAL_PWM         1
60
61 #define DSI_PANEL_RESET         1
62
63 #define DSI_PANEL_RST_GPIO      TEGRA_GPIO_PH3
64 #define DSI_PANEL_BL_PWM        TEGRA_GPIO_PH1
65
66 #define DSI_PANEL_CE            0
67
68 #define DC_CTRL_MODE    TEGRA_DC_OUT_CONTINUOUS_MODE
69
70 /* HDMI Hotplug detection pin */
71 #define roth_hdmi_hpd   TEGRA_GPIO_PN7
72
73 static bool reg_requested;
74 static bool gpio_requested;
75
76 static struct regulator *vdd_lcd_s_1v8;
77 static struct regulator *vdd_lcd_bl;
78 static struct regulator *vdd_lcd_bl_en;
79 static struct regulator *avdd_lcd_3v0_2v8;
80
81 static struct regulator *roth_hdmi_reg;
82 static struct regulator *roth_hdmi_pll;
83 static struct regulator *roth_hdmi_vddio;
84
85 #ifdef CONFIG_TEGRA_DC_CMU
86 static struct tegra_dc_cmu roth_cmu = {
87         /* lut1 maps sRGB to linear space. */
88         {
89                 0,    1,    2,    4,    5,    6,    7,    9,
90                 10,   11,   12,   14,   15,   16,   18,   20,
91                 21,   23,   25,   27,   29,   31,   33,   35,
92                 37,   40,   42,   45,   48,   50,   53,   56,
93                 59,   62,   66,   69,   72,   76,   79,   83,
94                 87,   91,   95,   99,   103,  107,  112,  116,
95                 121,  126,  131,  136,  141,  146,  151,  156,
96                 162,  168,  173,  179,  185,  191,  197,  204,
97                 210,  216,  223,  230,  237,  244,  251,  258,
98                 265,  273,  280,  288,  296,  304,  312,  320,
99                 329,  337,  346,  354,  363,  372,  381,  390,
100                 400,  409,  419,  428,  438,  448,  458,  469,
101                 479,  490,  500,  511,  522,  533,  544,  555,
102                 567,  578,  590,  602,  614,  626,  639,  651,
103                 664,  676,  689,  702,  715,  728,  742,  755,
104                 769,  783,  797,  811,  825,  840,  854,  869,
105                 884,  899,  914,  929,  945,  960,  976,  992,
106                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
107                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
108                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
109                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
110                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
111                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
112                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
113                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
114                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
115                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
116                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
117                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
118                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
119                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
120                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
121         },
122         /* csc */
123         {
124                 0x100, 0x0,   0x0,
125                 0x0,   0x100, 0x0,
126                 0x0,   0x0,   0x100,
127         },
128         /* lut2 maps linear space to sRGB*/
129         {
130                 0, 0, 1, 2, 3, 3, 4, 5,
131                 6, 6, 7, 8, 8, 9, 10, 10,
132                 11, 12, 12, 13, 13, 14, 14, 15,
133                 16, 16, 17, 17, 18, 18, 19, 19,
134                 19, 20, 20, 21, 21, 22, 22, 22,
135                 23, 23, 24, 24, 24, 25, 25, 25,
136                 26, 26, 27, 27, 27, 28, 28, 28,
137                 28, 29, 29, 29, 30, 30, 30, 31,
138                 31, 31, 31, 32, 32, 32, 33, 33,
139                 33, 33, 34, 34, 34, 35, 35, 35,
140                 35, 36, 36, 36, 36, 37, 37, 37,
141                 38, 38, 38, 38, 39, 39, 39, 39,
142                 40, 40, 40, 40, 40, 41, 41, 41,
143                 41, 42, 42, 42, 42, 43, 43, 43,
144                 43, 43, 44, 44, 44, 44, 45, 45,
145                 45, 45, 45, 46, 46, 46, 46, 46,
146                 47, 47, 47, 47, 47, 48, 48, 48,
147                 48, 48, 49, 49, 49, 49, 49, 49,
148                 50, 50, 50, 50, 50, 50, 51, 51,
149                 51, 51, 51, 51, 52, 52, 52, 52,
150                 52, 52, 53, 53, 53, 53, 53, 53,
151                 54, 54, 54, 54, 54, 54, 54, 55,
152                 55, 55, 55, 55, 55, 55, 55, 56,
153                 56, 56, 56, 56, 56, 56, 57, 57,
154                 57, 57, 57, 57, 57, 57, 58, 58,
155                 58, 58, 58, 58, 58, 58, 58, 59,
156                 59, 59, 59, 59, 59, 59, 59, 59,
157                 60, 60, 60, 60, 60, 60, 60, 60,
158                 60, 61, 61, 61, 61, 61, 61, 61,
159                 61, 61, 61, 62, 62, 62, 62, 62,
160                 62, 62, 62, 62, 62, 63, 63, 63,
161                 63, 63, 63, 63, 63, 63, 63, 63,
162                 64, 64, 64, 64, 64, 64, 64, 64,
163                 64, 64, 64, 65, 65, 65, 65, 65,
164                 65, 65, 65, 65, 65, 65, 66, 66,
165                 66, 66, 66, 66, 66, 66, 66, 66,
166                 66, 66, 67, 67, 67, 67, 67, 67,
167                 67, 67, 67, 67, 67, 67, 68, 68,
168                 68, 68, 68, 68, 68, 68, 68, 68,
169                 68, 68, 69, 69, 69, 69, 69, 69,
170                 69, 69, 69, 69, 69, 69, 70, 70,
171                 70, 70, 70, 70, 70, 70, 70, 70,
172                 70, 70, 70, 71, 71, 71, 71, 71,
173                 71, 71, 71, 71, 71, 71, 71, 71,
174                 72, 72, 72, 72, 72, 72, 72, 72,
175                 72, 72, 72, 72, 72, 73, 73, 73,
176                 73, 73, 73, 73, 73, 73, 73, 73,
177                 73, 73, 73, 74, 74, 74, 74, 74,
178                 74, 74, 74, 74, 74, 74, 74, 74,
179                 75, 75, 75, 75, 75, 75, 75, 75,
180                 75, 75, 75, 75, 75, 75, 76, 76,
181                 76, 76, 76, 76, 76, 76, 76, 76,
182                 76, 76, 76, 76, 77, 77, 77, 77,
183                 77, 77, 77, 77, 77, 77, 77, 77,
184                 77, 77, 78, 78, 78, 78, 78, 78,
185                 78, 78, 78, 78, 78, 78, 78, 78,
186                 79, 79, 79, 79, 79, 79, 79, 79,
187                 79, 79, 79, 79, 79, 79, 80, 80,
188                 80, 80, 80, 80, 80, 80, 80, 80,
189                 80, 80, 80, 80, 81, 81, 81, 81,
190                 81, 81, 81, 81, 81, 81, 81, 81,
191                 81, 81, 82, 82, 82, 82, 82, 82,
192                 82, 82, 82, 82, 82, 82, 82, 82,
193                 83, 83, 83, 83, 83, 83, 83, 83,
194                 84, 84, 85, 85, 86, 86, 87, 88,
195                 88, 89, 89, 90, 90, 91, 92, 92,
196                 93, 93, 94, 94, 95, 95, 96, 96,
197                 97, 97, 98, 98, 99, 99, 100, 100,
198                 101, 101, 102, 102, 103, 103, 104, 104,
199                 105, 105, 106, 106, 107, 107, 107, 108,
200                 108, 109, 109, 110, 110, 111, 111, 111,
201                 112, 112, 113, 113, 114, 114, 114, 115,
202                 115, 116, 116, 117, 117, 117, 118, 118,
203                 119, 119, 119, 120, 120, 121, 121, 121,
204                 122, 122, 123, 123, 123, 124, 124, 125,
205                 125, 126, 126, 126, 127, 127, 128, 128,
206                 128, 129, 129, 129, 130, 130, 131, 131,
207                 131, 132, 132, 133, 133, 133, 134, 134,
208                 135, 135, 135, 136, 136, 137, 137, 137,
209                 138, 138, 138, 139, 139, 140, 140, 140,
210                 141, 141, 142, 142, 142, 143, 143, 143,
211                 144, 144, 145, 145, 145, 146, 146, 146,
212                 147, 147, 147, 148, 148, 149, 149, 149,
213                 150, 150, 150, 151, 151, 151, 152, 152,
214                 153, 153, 153, 154, 154, 154, 155, 155,
215                 156, 156, 156, 157, 157, 157, 158, 158,
216                 159, 159, 159, 160, 160, 160, 161, 161,
217                 162, 162, 162, 163, 163, 164, 164, 164,
218                 165, 165, 166, 166, 166, 167, 167, 168,
219                 168, 168, 169, 169, 170, 170, 170, 171,
220                 171, 172, 172, 172, 173, 173, 173, 174,
221                 174, 175, 175, 175, 176, 176, 176, 177,
222                 177, 177, 178, 178, 178, 179, 179, 179,
223                 180, 180, 180, 180, 181, 181, 181, 182,
224                 182, 182, 182, 183, 183, 183, 184, 184,
225                 184, 184, 185, 185, 185, 185, 186, 186,
226                 186, 186, 187, 187, 187, 187, 188, 188,
227                 188, 188, 189, 189, 189, 190, 190, 190,
228                 190, 191, 191, 191, 191, 192, 192, 192,
229                 193, 193, 193, 193, 194, 194, 194, 195,
230                 195, 195, 195, 196, 196, 196, 197, 197,
231                 197, 198, 198, 198, 198, 199, 199, 199,
232                 200, 200, 200, 201, 201, 201, 202, 202,
233                 202, 203, 203, 204, 204, 204, 205, 205,
234                 205, 206, 206, 206, 207, 207, 208, 208,
235                 208, 209, 209, 209, 210, 210, 211, 211,
236                 211, 212, 212, 213, 213, 213, 214, 214,
237                 215, 215, 215, 216, 216, 217, 217, 217,
238                 218, 218, 218, 219, 219, 220, 220, 220,
239                 221, 221, 221, 222, 222, 222, 223, 223,
240                 223, 224, 224, 224, 225, 225, 225, 225,
241                 226, 226, 226, 226, 227, 227, 227, 227,
242                 228, 228, 228, 228, 229, 229, 229, 229,
243                 229, 230, 230, 230, 230, 231, 231, 231,
244                 231, 232, 232, 232, 233, 233, 233, 233,
245                 234, 234, 234, 235, 235, 235, 236, 236,
246                 236, 237, 237, 238, 238, 239, 239, 239,
247                 240, 240, 241, 241, 242, 242, 243, 244,
248                 244, 245, 245, 246, 247, 247, 248, 249,
249                 250, 250, 251, 252, 253, 254, 254, 255,
250         },
251 };
252 #endif
253
254 static struct resource roth_disp1_resources[] = {
255         {
256                 .name   = "irq",
257                 .start  = INT_DISPLAY_GENERAL,
258                 .end    = INT_DISPLAY_GENERAL,
259                 .flags  = IORESOURCE_IRQ,
260         },
261         {
262                 .name   = "regs",
263                 .start  = TEGRA_DISPLAY_BASE,
264                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
265                 .flags  = IORESOURCE_MEM,
266         },
267         {
268                 .name   = "fbmem",
269                 .start  = 0, /* Filled in by roth_panel_init() */
270                 .end    = 0, /* Filled in by roth_panel_init() */
271                 .flags  = IORESOURCE_MEM,
272         },
273         {
274                 .name   = "dsi_regs",
275                 .start  = TEGRA_DSI_BASE,
276                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
277                 .flags  = IORESOURCE_MEM,
278         },
279         {
280                 .name   = "mipi_cal",
281                 .start  = TEGRA_MIPI_CAL_BASE,
282                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
283                 .flags  = IORESOURCE_MEM,
284         },
285 };
286
287 static struct resource roth_disp2_resources[] = {
288         {
289                 .name   = "irq",
290                 .start  = INT_DISPLAY_B_GENERAL,
291                 .end    = INT_DISPLAY_B_GENERAL,
292                 .flags  = IORESOURCE_IRQ,
293         },
294         {
295                 .name   = "regs",
296                 .start  = TEGRA_DISPLAY2_BASE,
297                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
298                 .flags  = IORESOURCE_MEM,
299         },
300         {
301                 .name   = "fbmem",
302                 .start  = 0, /* Filled in by roth_panel_init() */
303                 .end    = 0, /* Filled in by roth_panel_init() */
304                 .flags  = IORESOURCE_MEM,
305         },
306         {
307                 .name   = "hdmi_regs",
308                 .start  = TEGRA_HDMI_BASE,
309                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
310                 .flags  = IORESOURCE_MEM,
311         },
312 };
313
314 static u8 panel_dsi_config[] = {0xe0, 0x43, 0x0, 0x80, 0x0, 0x0};
315 static u8 panel_disp_ctrl1[] = {0xb5, 0x34, 0x20, 0x40, 0x0, 0x20};
316 static u8 panel_disp_ctrl2[] = {0xb6, 0x04, 0x74, 0x0f, 0x16, 0x13};
317 static u8 panel_internal_clk[] = {0xc0, 0x01, 0x08};
318 static u8 panel_pwr_ctrl3[] = {
319         0xc3, 0x0, 0x09, 0x10, 0x02, 0x0, 0x66, 0x00, 0x13, 0x0};
320 static u8 panel_pwr_ctrl4[] = {0xc4, 0x23, 0x24, 0x12, 0x12, 0x60};
321 static u8 panel_positive_gamma_red[] = {
322         0xd0, 0x21, 0x25, 0x67, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
323 static u8 panel_negetive_gamma_red[] = {
324         0xd1, 0x31, 0x25, 0x66, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03};
325 static u8 panel_positive_gamma_green[] = {
326         0xd2, 0x41, 0x26, 0x56, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
327 static u8 panel_negetive_gamma_green[] = {
328         0xd3, 0x51, 0x26, 0x55, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03};
329 static u8 panel_positive_gamma_blue[] = {
330         0xd4, 0x41, 0x26, 0x56, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
331 static u8 panel_negetive_gamma_blue[] = {
332         0xd5, 0x51, 0x26, 0x55, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03};
333
334 #if DSI_PANEL_CE
335 static u8 panel_ce2[] = {0x71, 0x0, 0x0, 0x01, 0x01};
336 static u8 panel_ce3[] = {0x72, 0x01, 0x0e};
337 static u8 panel_ce4[] = {0x73, 0x34, 0x52, 0x0};
338 static u8 panel_ce5[] = {0x74, 0x05, 0x0, 0x06};
339 static u8 panel_ce6[] = {0x75, 0x03, 0x0, 0x07};
340 static u8 panel_ce7[] = {0x76, 0x07, 0x0, 0x06};
341 static u8 panel_ce8[] = {0x77, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f};
342 static u8 panel_ce9[] = {0x78, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
343 static u8 panel_ce10[] = {
344         0x79, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
345 static u8 panel_ce11[] = {0x7a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
346 static u8 panel_ce12[] = {0x7b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
347 static u8 panel_ce13[] = {0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
348 #endif
349
350 static struct tegra_dsi_cmd dsi_init_cmd[] = {
351         DSI_DLY_MS(20),
352         DSI_GPIO_SET(DSI_PANEL_RST_GPIO, 1),
353
354         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_dsi_config),
355
356         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl1),
357         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl2),
358
359         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal_clk),
360
361         /*  panel power control 1 */
362         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x0),
363         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl3),
364         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl4),
365
366         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_red),
367         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_red),
368         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_green),
369         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_green),
370         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_blue),
371         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_blue),
372
373         DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_ADDR_MODE, 0x0B),
374
375         /* panel OTP 2 */
376         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x0),
377
378 #if DSI_PANEL_CE
379         /* panel CE 1 */
380         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x70, 0x0),
381         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce2),
382         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce3),
383         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce4),
384         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce5),
385         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce6),
386         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce7),
387         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce8),
388         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce9),
389         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce10),
390         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce11),
391         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce12),
392         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce13),
393 #endif
394         /* panel power control 2 */
395         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x02),
396         DSI_DLY_MS(20),
397
398         /* panel power control 2 */
399         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x06),
400         DSI_DLY_MS(20),
401
402         /* panel power control 2 */
403         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x4e),
404         DSI_DLY_MS(100),
405
406         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0),
407         DSI_DLY_MS(140),
408
409         /* panel OTP 2 */
410         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x80),
411         DSI_DLY_MS(20),
412
413         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0),
414 };
415
416 static u8 panel_suspend_pwr_ctrl4[] = {0xc4, 0x0, 0x0, 0x0, 0x0, 0x0};
417
418 static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
419         DSI_DLY_MS(40),
420
421         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0),
422         DSI_DLY_MS(20),
423
424         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0),
425
426         /* panel power control 2 */
427         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x0),
428
429         /* panel power control 4 */
430         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_suspend_pwr_ctrl4),
431
432         /* panel power control 1 */
433         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x2),
434         DSI_DLY_MS(20),
435
436         /* panel power control 1 */
437         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x3),
438         DSI_DLY_MS(20),
439 };
440
441 static struct tegra_dsi_out roth_dsi = {
442         .n_data_lanes = 4,
443         .controller_vs = DSI_VS_1,
444         .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
445         .refresh_rate = 60,
446         .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
447
448         .dsi_instance = DSI_INSTANCE_0,
449
450         .panel_reset = DSI_PANEL_RESET,
451         .power_saving_suspend = true,
452         .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
453         .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
454         .video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END,
455         .dsi_init_cmd = dsi_init_cmd,
456         .n_init_cmd = ARRAY_SIZE(dsi_init_cmd),
457         .dsi_suspend_cmd = dsi_suspend_cmd,
458         .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
459 };
460
461 static int roth_dsi_regulator_get(struct device *dev)
462 {
463         int err = 0;
464
465         if (reg_requested)
466                 return 0;
467
468         avdd_lcd_3v0_2v8 = regulator_get(dev, "avdd_lcd");
469         if (IS_ERR_OR_NULL(avdd_lcd_3v0_2v8)) {
470                 pr_err("avdd_lcd regulator get failed\n");
471                 err = PTR_ERR(avdd_lcd_3v0_2v8);
472                 avdd_lcd_3v0_2v8 = NULL;
473                 goto fail;
474         }
475         vdd_lcd_s_1v8 = regulator_get(dev, "dvdd_lcd");
476         if (IS_ERR_OR_NULL(vdd_lcd_s_1v8)) {
477                 pr_err("vdd_lcd_1v8_s regulator get failed\n");
478                 err = PTR_ERR(vdd_lcd_s_1v8);
479                 vdd_lcd_s_1v8 = NULL;
480                 goto fail;
481         }
482
483         if (machine_is_dalmore()) {
484                 vdd_lcd_bl = regulator_get(dev, "vdd_lcd_bl");
485                 if (IS_ERR_OR_NULL(vdd_lcd_bl)) {
486                         pr_err("vdd_lcd_bl regulator get failed\n");
487                         err = PTR_ERR(vdd_lcd_bl);
488                         vdd_lcd_bl = NULL;
489                         goto fail;
490                 }
491         }
492
493         vdd_lcd_bl_en = regulator_get(dev, "vdd_lcd_bl_en");
494         if (IS_ERR_OR_NULL(vdd_lcd_bl_en)) {
495                 pr_err("vdd_lcd_bl_en regulator get failed\n");
496                 err = PTR_ERR(vdd_lcd_bl_en);
497                 vdd_lcd_bl_en = NULL;
498                 goto fail;
499         }
500         reg_requested = true;
501         return 0;
502 fail:
503         return err;
504 }
505
506 static int roth_dsi_gpio_get(void)
507 {
508         int err = 0;
509
510         if (gpio_requested)
511                 return 0;
512
513         err = gpio_request(DSI_PANEL_RST_GPIO, "panel rst");
514         if (err < 0) {
515                 pr_err("panel reset gpio request failed\n");
516                 goto fail;
517         }
518
519         gpio_requested = true;
520         return 0;
521 fail:
522         return err;
523 }
524
525 static struct tegra_dc_out roth_disp1_out;
526
527 static int roth_dsi_panel_enable(struct device *dev)
528 {
529         int err = 0;
530
531         err = roth_dsi_regulator_get(dev);
532         if (err < 0) {
533                 pr_err("dsi regulator get failed\n");
534                 goto fail;
535         }
536         err = roth_dsi_gpio_get();
537         if (err < 0) {
538                 pr_err("dsi gpio request failed\n");
539                 goto fail;
540         }
541
542         /* Skip panel programming if in initialized mode */
543         if (!(roth_disp1_out.flags & TEGRA_DC_OUT_INITIALIZED_MODE)) {
544                 roth_dsi.dsi_init_cmd = dsi_init_cmd;
545                 gpio_set_value(DSI_PANEL_RST_GPIO, 0);
546         } else {
547                 roth_dsi.dsi_init_cmd = dsi_init_cmd + 2;
548         }
549
550         if (vdd_lcd_s_1v8) {
551                 err = regulator_enable(vdd_lcd_s_1v8);
552                 if (err < 0) {
553                         pr_err("vdd_lcd_1v8_s regulator enable failed\n");
554                         goto fail;
555                 }
556         }
557         usleep_range(3000, 5000);
558
559         if (avdd_lcd_3v0_2v8) {
560                 err = regulator_enable(avdd_lcd_3v0_2v8);
561                 if (err < 0) {
562                         pr_err("avdd_lcd_3v0_2v8 regulator enable failed\n");
563                         goto fail;
564                 }
565                 regulator_set_voltage(avdd_lcd_3v0_2v8, 2800000, 2800000);
566         }
567         usleep_range(3000, 5000);
568
569         if (vdd_lcd_bl) {
570                 err = regulator_enable(vdd_lcd_bl);
571                 if (err < 0) {
572                         pr_err("vdd_lcd_bl regulator enable failed\n");
573                         goto fail;
574                 }
575         }
576
577         if (vdd_lcd_bl_en) {
578                 err = regulator_enable(vdd_lcd_bl_en);
579                 if (err < 0) {
580                         pr_err("vdd_lcd_bl_en regulator enable failed\n");
581                         goto fail;
582                 }
583         }
584
585         return 0;
586 fail:
587         return err;
588 }
589
590 static int roth_dsi_panel_disable(void)
591 {
592         if (vdd_lcd_bl)
593                 regulator_disable(vdd_lcd_bl);
594
595         if (vdd_lcd_bl_en)
596                 regulator_disable(vdd_lcd_bl_en);
597
598         gpio_set_value(DSI_PANEL_RST_GPIO, 0);
599         mdelay(20);
600
601         if (vdd_lcd_s_1v8)
602                 regulator_disable(vdd_lcd_s_1v8);
603
604         if (avdd_lcd_3v0_2v8)
605                 regulator_disable(avdd_lcd_3v0_2v8);
606
607         return 0;
608 }
609
610 static int roth_dsi_panel_postsuspend(void)
611 {
612         /* TODO */
613         return 0;
614 }
615
616 static struct tegra_dc_mode roth_dsi_modes[] = {
617         {
618                 .pclk = 66700000,
619                 .h_ref_to_sync = 4,
620                 .v_ref_to_sync = 1,
621                 .h_sync_width = 4,
622                 .v_sync_width = 4,
623                 .h_back_porch = 112,
624                 .v_back_porch = 12,
625                 .h_active = 720,
626                 .v_active = 1280,
627                 .h_front_porch = 12,
628                 .v_front_porch = 8,
629         },
630 };
631
632 static struct tegra_dc_sd_settings sd_settings;
633
634 static struct tegra_dc_out roth_disp1_out = {
635         .type           = TEGRA_DC_OUT_DSI,
636         .dsi            = &roth_dsi,
637
638         .flags          = DC_CTRL_MODE,
639         .sd_settings    = &sd_settings,
640
641         .modes          = roth_dsi_modes,
642         .n_modes        = ARRAY_SIZE(roth_dsi_modes),
643
644         .enable         = roth_dsi_panel_enable,
645         .disable        = roth_dsi_panel_disable,
646         .postsuspend    = roth_dsi_panel_postsuspend,
647         .width          = 62,
648         .height         = 110,
649 };
650
651 static int roth_hdmi_enable(struct device *dev)
652 {
653         int ret;
654         if (!roth_hdmi_reg) {
655                 roth_hdmi_reg = regulator_get(dev, "avdd_hdmi");
656                 if (IS_ERR_OR_NULL(roth_hdmi_reg)) {
657                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
658                         roth_hdmi_reg = NULL;
659                         return PTR_ERR(roth_hdmi_reg);
660                 }
661         }
662         ret = regulator_enable(roth_hdmi_reg);
663         if (ret < 0) {
664                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
665                 return ret;
666         }
667         if (!roth_hdmi_pll) {
668                 roth_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
669                 if (IS_ERR_OR_NULL(roth_hdmi_pll)) {
670                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
671                         roth_hdmi_pll = NULL;
672                         regulator_put(roth_hdmi_reg);
673                         roth_hdmi_reg = NULL;
674                         return PTR_ERR(roth_hdmi_pll);
675                 }
676         }
677         ret = regulator_enable(roth_hdmi_pll);
678         if (ret < 0) {
679                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
680                 return ret;
681         }
682         return 0;
683 }
684
685 static int roth_hdmi_disable(void)
686 {
687         if (roth_hdmi_reg) {
688                 regulator_disable(roth_hdmi_reg);
689                 regulator_put(roth_hdmi_reg);
690                 roth_hdmi_reg = NULL;
691         }
692
693         if (roth_hdmi_pll) {
694                 regulator_disable(roth_hdmi_pll);
695                 regulator_put(roth_hdmi_pll);
696                 roth_hdmi_pll = NULL;
697         }
698
699         return 0;
700 }
701
702 static int roth_hdmi_postsuspend(void)
703 {
704         if (roth_hdmi_vddio) {
705                 regulator_disable(roth_hdmi_vddio);
706                 regulator_put(roth_hdmi_vddio);
707                 roth_hdmi_vddio = NULL;
708         }
709         return 0;
710 }
711
712 static int roth_hdmi_hotplug_init(struct device *dev)
713 {
714         int e = 0;
715
716         if (!roth_hdmi_vddio) {
717                 roth_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
718                 if (WARN_ON(IS_ERR(roth_hdmi_vddio))) {
719                         e = PTR_ERR(roth_hdmi_vddio);
720                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %d\n",
721                                         __func__, e);
722                         roth_hdmi_vddio = NULL;
723                 } else
724                         e = regulator_enable(roth_hdmi_vddio);
725         }
726         return e;
727 }
728
729 static void roth_hdmi_hotplug_report(bool state)
730 {
731         if (state) {
732                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA,
733                                                 TEGRA_PUPD_PULL_DOWN);
734                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL,
735                                                 TEGRA_PUPD_PULL_DOWN);
736         } else {
737                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA,
738                                                 TEGRA_PUPD_NORMAL);
739                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL,
740                                                 TEGRA_PUPD_NORMAL);
741         }
742 }
743
744 static struct tegra_dc_out roth_disp2_out = {
745         .type           = TEGRA_DC_OUT_HDMI,
746         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
747         .parent_clk     = "pll_d2_out0",
748
749         .dcc_bus        = 3,
750         .hotplug_gpio   = roth_hdmi_hpd,
751
752         .max_pixclock   = KHZ2PICOS(297000),
753
754         .align          = TEGRA_DC_ALIGN_MSB,
755         .order          = TEGRA_DC_ORDER_RED_BLUE,
756
757         .enable         = roth_hdmi_enable,
758         .disable        = roth_hdmi_disable,
759         .postsuspend    = roth_hdmi_postsuspend,
760         .hotplug_init   = roth_hdmi_hotplug_init,
761         .hotplug_report = roth_hdmi_hotplug_report,
762 };
763
764 static struct tegra_fb_data roth_disp1_fb_data = {
765         .win            = 0,
766         .bits_per_pixel = 32,
767         .flags          = TEGRA_FB_FLIP_ON_PROBE,
768         .xres           = 720,
769         .yres           = 1280,
770 };
771
772 static struct tegra_dc_platform_data roth_disp1_pdata = {
773         .flags          = TEGRA_DC_FLAG_ENABLED,
774         .default_out    = &roth_disp1_out,
775         .fb             = &roth_disp1_fb_data,
776         .emc_clk_rate   = 204000000,
777 #ifdef CONFIG_TEGRA_DC_CMU
778         .cmu_enable     = 1,
779         .cmu            = &roth_cmu,
780 #endif
781 };
782
783 static struct tegra_fb_data roth_disp2_fb_data = {
784         .win            = 0,
785         .xres           = 1024,
786         .yres           = 600,
787         .bits_per_pixel = 32,
788         .flags          = TEGRA_FB_FLIP_ON_PROBE,
789 };
790
791 static struct tegra_dc_platform_data roth_disp2_pdata = {
792         .flags          = TEGRA_DC_FLAG_ENABLED,
793         .default_out    = &roth_disp2_out,
794         .fb             = &roth_disp2_fb_data,
795         .emc_clk_rate   = 300000000,
796 #ifdef CONFIG_TEGRA_DC_CMU
797         .cmu_enable     = 1,
798 #endif
799 };
800
801 static struct platform_device roth_disp2_device = {
802         .name           = "tegradc",
803         .id             = 1,
804         .resource       = roth_disp2_resources,
805         .num_resources  = ARRAY_SIZE(roth_disp2_resources),
806         .dev = {
807                 .platform_data = &roth_disp2_pdata,
808         },
809 };
810
811 static struct platform_device roth_disp1_device = {
812         .name           = "tegradc",
813         .id             = 0,
814         .resource       = roth_disp1_resources,
815         .num_resources  = ARRAY_SIZE(roth_disp1_resources),
816         .dev = {
817                 .platform_data = &roth_disp1_pdata,
818         },
819 };
820
821 static struct nvmap_platform_carveout roth_carveouts[] = {
822         [0] = {
823                 .name           = "iram",
824                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
825                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
826                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
827                 .buddy_size     = 0, /* no buddy allocation for IRAM */
828         },
829         [1] = {
830                 .name           = "generic-0",
831                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
832                 .base           = 0, /* Filled in by roth_panel_init() */
833                 .size           = 0, /* Filled in by roth_panel_init() */
834                 .buddy_size     = SZ_32K,
835         },
836         [2] = {
837                 .name           = "vpr",
838                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
839                 .base           = 0, /* Filled in by roth_panel_init() */
840                 .size           = 0, /* Filled in by roth_panel_init() */
841                 .buddy_size     = SZ_32K,
842         },
843 };
844
845 static struct nvmap_platform_data roth_nvmap_data = {
846         .carveouts      = roth_carveouts,
847         .nr_carveouts   = ARRAY_SIZE(roth_carveouts),
848 };
849
850 static struct platform_device roth_nvmap_device = {
851         .name   = "tegra-nvmap",
852         .id     = -1,
853         .dev    = {
854                 .platform_data = &roth_nvmap_data,
855         },
856 };
857
858 static int roth_disp1_bl_notify(struct device *unused, int brightness)
859 {
860         int cur_sd_brightness = atomic_read(&sd_brightness);
861
862         /* SD brightness is a percentage */
863         brightness = (brightness * cur_sd_brightness) / 255;
864
865         /* Apply any backlight response curve */
866         if (brightness > 255)
867                 pr_info("Error: Brightness > 255!\n");
868
869         return brightness;
870 }
871
872 static int roth_disp1_check_fb(struct device *dev, struct fb_info *info)
873 {
874         return info->device == &roth_disp1_device.dev;
875 }
876
877 static struct platform_pwm_backlight_data roth_disp1_bl_data = {
878         .pwm_id         = 1,
879         .max_brightness = 255,
880         .dft_brightness = 77,
881         .pwm_period_ns  = 40000,
882         .pwm_gpio       = DSI_PANEL_BL_PWM,
883         .notify         = roth_disp1_bl_notify,
884         /* Only toggle backlight on fb blank notifications for disp1 */
885         .check_fb       = roth_disp1_check_fb,
886 };
887
888 static struct platform_device __maybe_unused
889                 roth_disp1_bl_device = {
890         .name   = "pwm-backlight",
891         .id     = -1,
892         .dev    = {
893                 .platform_data = &roth_disp1_bl_data,
894         },
895 };
896
897 static struct tegra_dc_sd_settings roth_sd_settings = {
898         .enable = 0, /* disabled by default. */
899         .use_auto_pwm = false,
900         .hw_update_delay = 0,
901         .bin_width = -1,
902         .aggressiveness = 1,
903         .use_vid_luma = false,
904         .phase_in_adjustments = 0,
905         .k_limit_enable = true,
906         .k_limit = 180,
907         .sd_window_enable = false,
908         .soft_clipping_enable = true,
909         /* Low soft clipping threshold to compensate for aggressive k_limit */
910         .soft_clipping_threshold = 128,
911         .smooth_k_enable = true,
912         .smooth_k_incr = 128,
913         /* Default video coefficients */
914         .coeff = {5, 9, 2},
915         .fc = {0, 0},
916         /* Immediate backlight changes */
917         .blp = {1024, 255},
918         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
919         /* Default BL TF */
920         .bltf = {
921                         {
922                                 {57, 65, 73, 82},
923                                 {92, 103, 114, 125},
924                                 {138, 150, 164, 178},
925                                 {193, 208, 224, 241},
926                         },
927                 },
928         /* Default LUT */
929         .lut = {
930                         {
931                                 {255, 255, 255},
932                                 {199, 199, 199},
933                                 {153, 153, 153},
934                                 {116, 116, 116},
935                                 {85, 85, 85},
936                                 {59, 59, 59},
937                                 {36, 36, 36},
938                                 {17, 17, 17},
939                                 {0, 0, 0},
940                         },
941                 },
942         .sd_brightness = &sd_brightness,
943         .bl_device_name = "pwm-backlight",
944 };
945
946 static struct platform_device __maybe_unused
947                         *roth_bl_device[] __initdata = {
948         &tegra_pwfm_device,
949         &roth_disp1_bl_device,
950 };
951
952 int __init roth_panel_init(int board_id)
953 {
954         int err = 0;
955         struct resource __maybe_unused *res;
956         struct platform_device *phost1x = NULL;
957
958         sd_settings = roth_sd_settings;
959
960 #ifdef CONFIG_TEGRA_NVMAP
961         roth_carveouts[1].base = tegra_carveout_start;
962         roth_carveouts[1].size = tegra_carveout_size;
963         roth_carveouts[2].base = tegra_vpr_start;
964         roth_carveouts[2].size = tegra_vpr_size;
965
966         err = platform_device_register(&roth_nvmap_device);
967         if (err) {
968                 pr_err("nvmap device registration failed\n");
969                 return err;
970         }
971 #endif
972
973         phost1x = roth_host1x_init();
974         if (!phost1x) {
975                 pr_err("host1x devices registration failed\n");
976                 return -EINVAL;
977         }
978
979         res = platform_get_resource_byname(&roth_disp1_device,
980                                          IORESOURCE_MEM, "fbmem");
981         res->start = tegra_fb_start;
982         res->end = tegra_fb_start + tegra_fb_size - 1;
983
984         /* Copy the bootloader fb to the fb. */
985         __tegra_move_framebuffer(&roth_nvmap_device,
986                 tegra_fb_start, tegra_bootloader_fb_start,
987                         min(tegra_fb_size, tegra_bootloader_fb_size));
988
989         /*
990          * only roth supports initialized mode.
991          */
992         if (!board_id)
993                 roth_disp1_out.flags |= TEGRA_DC_OUT_INITIALIZED_MODE;
994
995         roth_disp1_device.dev.parent = &phost1x->dev;
996         err = platform_device_register(&roth_disp1_device);
997         if (err) {
998                 pr_err("disp1 device registration failed\n");
999                 return err;
1000         }
1001
1002         err = tegra_init_hdmi(&roth_disp2_device, phost1x);
1003         if (err)
1004                 return err;
1005
1006 #if IS_EXTERNAL_PWM
1007         if (!of_have_populated_dt()) {
1008                 err = platform_add_devices(roth_bl_device,
1009                                 ARRAY_SIZE(roth_bl_device));
1010                 if (err) {
1011                         pr_err("disp1 bl dev registration failed");
1012                         return err;
1013                 }
1014         }
1015 #endif
1016
1017 #ifdef CONFIG_TEGRA_NVAVP
1018         nvavp_device.dev.parent = &phost1x->dev;
1019         err = platform_device_register(&nvavp_device);
1020         if (err) {
1021                 pr_err("nvavp device registration failed\n");
1022                 return err;
1023         }
1024 #endif
1025         return err;
1026 }