134dad5ba888d2351657f102829b83f3b51bc9aa
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-panel.c
1 /*
2  * arch/arm/mach-tegra/board-roth-panel.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31
32 #include <mach/irqs.h>
33 #include <mach/dc.h>
34 #include <mach/pinmux.h>
35 #include <mach/pinmux-t11.h>
36 #include <asm/mach-types.h>
37
38 #include "board.h"
39 #include "devices.h"
40 #include "gpio-names.h"
41 #include "iomap.h"
42 #include "tegra11_host1x_devices.h"
43
44 struct platform_device * __init roth_host1x_init(void)
45 {
46         struct platform_device *pdev = NULL;
47
48 #ifdef CONFIG_TEGRA_GRHOST
49         if (!of_have_populated_dt())
50                 pdev = tegra11_register_host1x_devices();
51         else
52                 pdev = to_platform_device(bus_find_device_by_name(
53                         &platform_bus_type, NULL, "host1x"));
54 #endif
55         return pdev;
56 }
57
58 #ifdef CONFIG_TEGRA_DC
59
60 #define IS_EXTERNAL_PWM         1
61
62 #define DSI_PANEL_RESET         1
63
64 #define DSI_PANEL_RST_GPIO      TEGRA_GPIO_PH3
65 #define DSI_PANEL_BL_PWM        TEGRA_GPIO_PH1
66
67 #define DSI_PANEL_CE            0
68
69 #define DC_CTRL_MODE    TEGRA_DC_OUT_CONTINUOUS_MODE
70
71 /* HDMI Hotplug detection pin */
72 #define roth_hdmi_hpd   TEGRA_GPIO_PN7
73
74 static atomic_t sd_brightness = ATOMIC_INIT(255);
75
76 static bool reg_requested;
77 static bool gpio_requested;
78
79 static struct regulator *vdd_lcd_s_1v8;
80 static struct regulator *vdd_lcd_bl;
81 static struct regulator *vdd_lcd_bl_en;
82 static struct regulator *avdd_lcd_3v0_2v8;
83
84 static struct regulator *roth_hdmi_reg;
85 static struct regulator *roth_hdmi_pll;
86 static struct regulator *roth_hdmi_vddio;
87
88 #ifdef CONFIG_TEGRA_DC_CMU
89 static struct tegra_dc_cmu roth_cmu = {
90         /* lut1 maps sRGB to linear space. */
91         {
92                 0,    1,    2,    4,    5,    6,    7,    9,
93                 10,   11,   12,   14,   15,   16,   18,   20,
94                 21,   23,   25,   27,   29,   31,   33,   35,
95                 37,   40,   42,   45,   48,   50,   53,   56,
96                 59,   62,   66,   69,   72,   76,   79,   83,
97                 87,   91,   95,   99,   103,  107,  112,  116,
98                 121,  126,  131,  136,  141,  146,  151,  156,
99                 162,  168,  173,  179,  185,  191,  197,  204,
100                 210,  216,  223,  230,  237,  244,  251,  258,
101                 265,  273,  280,  288,  296,  304,  312,  320,
102                 329,  337,  346,  354,  363,  372,  381,  390,
103                 400,  409,  419,  428,  438,  448,  458,  469,
104                 479,  490,  500,  511,  522,  533,  544,  555,
105                 567,  578,  590,  602,  614,  626,  639,  651,
106                 664,  676,  689,  702,  715,  728,  742,  755,
107                 769,  783,  797,  811,  825,  840,  854,  869,
108                 884,  899,  914,  929,  945,  960,  976,  992,
109                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
110                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
111                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
112                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
113                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
114                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
115                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
116                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
117                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
118                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
119                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
120                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
121                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
122                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
123                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
124         },
125         /* csc */
126         {
127                 0x100, 0x0,   0x0,
128                 0x0,   0x100, 0x0,
129                 0x0,   0x0,   0x100,
130         },
131         /* lut2 maps linear space to sRGB*/
132         {
133                 0, 0, 1, 2, 3, 3, 4, 5,
134                 6, 6, 7, 8, 8, 9, 10, 10,
135                 11, 12, 12, 13, 13, 14, 14, 15,
136                 16, 16, 17, 17, 18, 18, 19, 19,
137                 19, 20, 20, 21, 21, 22, 22, 22,
138                 23, 23, 24, 24, 24, 25, 25, 25,
139                 26, 26, 27, 27, 27, 28, 28, 28,
140                 28, 29, 29, 29, 30, 30, 30, 31,
141                 31, 31, 31, 32, 32, 32, 33, 33,
142                 33, 33, 34, 34, 34, 35, 35, 35,
143                 35, 36, 36, 36, 36, 37, 37, 37,
144                 38, 38, 38, 38, 39, 39, 39, 39,
145                 40, 40, 40, 40, 40, 41, 41, 41,
146                 41, 42, 42, 42, 42, 43, 43, 43,
147                 43, 43, 44, 44, 44, 44, 45, 45,
148                 45, 45, 45, 46, 46, 46, 46, 46,
149                 47, 47, 47, 47, 47, 48, 48, 48,
150                 48, 48, 49, 49, 49, 49, 49, 49,
151                 50, 50, 50, 50, 50, 50, 51, 51,
152                 51, 51, 51, 51, 52, 52, 52, 52,
153                 52, 52, 53, 53, 53, 53, 53, 53,
154                 54, 54, 54, 54, 54, 54, 54, 55,
155                 55, 55, 55, 55, 55, 55, 55, 56,
156                 56, 56, 56, 56, 56, 56, 57, 57,
157                 57, 57, 57, 57, 57, 57, 58, 58,
158                 58, 58, 58, 58, 58, 58, 58, 59,
159                 59, 59, 59, 59, 59, 59, 59, 59,
160                 60, 60, 60, 60, 60, 60, 60, 60,
161                 60, 61, 61, 61, 61, 61, 61, 61,
162                 61, 61, 61, 62, 62, 62, 62, 62,
163                 62, 62, 62, 62, 62, 63, 63, 63,
164                 63, 63, 63, 63, 63, 63, 63, 63,
165                 64, 64, 64, 64, 64, 64, 64, 64,
166                 64, 64, 64, 65, 65, 65, 65, 65,
167                 65, 65, 65, 65, 65, 65, 66, 66,
168                 66, 66, 66, 66, 66, 66, 66, 66,
169                 66, 66, 67, 67, 67, 67, 67, 67,
170                 67, 67, 67, 67, 67, 67, 68, 68,
171                 68, 68, 68, 68, 68, 68, 68, 68,
172                 68, 68, 69, 69, 69, 69, 69, 69,
173                 69, 69, 69, 69, 69, 69, 70, 70,
174                 70, 70, 70, 70, 70, 70, 70, 70,
175                 70, 70, 70, 71, 71, 71, 71, 71,
176                 71, 71, 71, 71, 71, 71, 71, 71,
177                 72, 72, 72, 72, 72, 72, 72, 72,
178                 72, 72, 72, 72, 72, 73, 73, 73,
179                 73, 73, 73, 73, 73, 73, 73, 73,
180                 73, 73, 73, 74, 74, 74, 74, 74,
181                 74, 74, 74, 74, 74, 74, 74, 74,
182                 75, 75, 75, 75, 75, 75, 75, 75,
183                 75, 75, 75, 75, 75, 75, 76, 76,
184                 76, 76, 76, 76, 76, 76, 76, 76,
185                 76, 76, 76, 76, 77, 77, 77, 77,
186                 77, 77, 77, 77, 77, 77, 77, 77,
187                 77, 77, 78, 78, 78, 78, 78, 78,
188                 78, 78, 78, 78, 78, 78, 78, 78,
189                 79, 79, 79, 79, 79, 79, 79, 79,
190                 79, 79, 79, 79, 79, 79, 80, 80,
191                 80, 80, 80, 80, 80, 80, 80, 80,
192                 80, 80, 80, 80, 81, 81, 81, 81,
193                 81, 81, 81, 81, 81, 81, 81, 81,
194                 81, 81, 82, 82, 82, 82, 82, 82,
195                 82, 82, 82, 82, 82, 82, 82, 82,
196                 83, 83, 83, 83, 83, 83, 83, 83,
197                 84, 84, 85, 85, 86, 86, 87, 88,
198                 88, 89, 89, 90, 90, 91, 92, 92,
199                 93, 93, 94, 94, 95, 95, 96, 96,
200                 97, 97, 98, 98, 99, 99, 100, 100,
201                 101, 101, 102, 102, 103, 103, 104, 104,
202                 105, 105, 106, 106, 107, 107, 107, 108,
203                 108, 109, 109, 110, 110, 111, 111, 111,
204                 112, 112, 113, 113, 114, 114, 114, 115,
205                 115, 116, 116, 117, 117, 117, 118, 118,
206                 119, 119, 119, 120, 120, 121, 121, 121,
207                 122, 122, 123, 123, 123, 124, 124, 125,
208                 125, 126, 126, 126, 127, 127, 128, 128,
209                 128, 129, 129, 129, 130, 130, 131, 131,
210                 131, 132, 132, 133, 133, 133, 134, 134,
211                 135, 135, 135, 136, 136, 137, 137, 137,
212                 138, 138, 138, 139, 139, 140, 140, 140,
213                 141, 141, 142, 142, 142, 143, 143, 143,
214                 144, 144, 145, 145, 145, 146, 146, 146,
215                 147, 147, 147, 148, 148, 149, 149, 149,
216                 150, 150, 150, 151, 151, 151, 152, 152,
217                 153, 153, 153, 154, 154, 154, 155, 155,
218                 156, 156, 156, 157, 157, 157, 158, 158,
219                 159, 159, 159, 160, 160, 160, 161, 161,
220                 162, 162, 162, 163, 163, 164, 164, 164,
221                 165, 165, 166, 166, 166, 167, 167, 168,
222                 168, 168, 169, 169, 170, 170, 170, 171,
223                 171, 172, 172, 172, 173, 173, 173, 174,
224                 174, 175, 175, 175, 176, 176, 176, 177,
225                 177, 177, 178, 178, 178, 179, 179, 179,
226                 180, 180, 180, 180, 181, 181, 181, 182,
227                 182, 182, 182, 183, 183, 183, 184, 184,
228                 184, 184, 185, 185, 185, 185, 186, 186,
229                 186, 186, 187, 187, 187, 187, 188, 188,
230                 188, 188, 189, 189, 189, 190, 190, 190,
231                 190, 191, 191, 191, 191, 192, 192, 192,
232                 193, 193, 193, 193, 194, 194, 194, 195,
233                 195, 195, 195, 196, 196, 196, 197, 197,
234                 197, 198, 198, 198, 198, 199, 199, 199,
235                 200, 200, 200, 201, 201, 201, 202, 202,
236                 202, 203, 203, 204, 204, 204, 205, 205,
237                 205, 206, 206, 206, 207, 207, 208, 208,
238                 208, 209, 209, 209, 210, 210, 211, 211,
239                 211, 212, 212, 213, 213, 213, 214, 214,
240                 215, 215, 215, 216, 216, 217, 217, 217,
241                 218, 218, 218, 219, 219, 220, 220, 220,
242                 221, 221, 221, 222, 222, 222, 223, 223,
243                 223, 224, 224, 224, 225, 225, 225, 225,
244                 226, 226, 226, 226, 227, 227, 227, 227,
245                 228, 228, 228, 228, 229, 229, 229, 229,
246                 229, 230, 230, 230, 230, 231, 231, 231,
247                 231, 232, 232, 232, 233, 233, 233, 233,
248                 234, 234, 234, 235, 235, 235, 236, 236,
249                 236, 237, 237, 238, 238, 239, 239, 239,
250                 240, 240, 241, 241, 242, 242, 243, 244,
251                 244, 245, 245, 246, 247, 247, 248, 249,
252                 250, 250, 251, 252, 253, 254, 254, 255,
253         },
254 };
255 #endif
256
257 static struct resource roth_disp1_resources[] = {
258         {
259                 .name   = "irq",
260                 .start  = INT_DISPLAY_GENERAL,
261                 .end    = INT_DISPLAY_GENERAL,
262                 .flags  = IORESOURCE_IRQ,
263         },
264         {
265                 .name   = "regs",
266                 .start  = TEGRA_DISPLAY_BASE,
267                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
268                 .flags  = IORESOURCE_MEM,
269         },
270         {
271                 .name   = "fbmem",
272                 .start  = 0, /* Filled in by roth_panel_init() */
273                 .end    = 0, /* Filled in by roth_panel_init() */
274                 .flags  = IORESOURCE_MEM,
275         },
276         {
277                 .name   = "dsi_regs",
278                 .start  = TEGRA_DSI_BASE,
279                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
280                 .flags  = IORESOURCE_MEM,
281         },
282         {
283                 .name   = "mipi_cal",
284                 .start  = TEGRA_MIPI_CAL_BASE,
285                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
286                 .flags  = IORESOURCE_MEM,
287         },
288 };
289
290 static struct resource roth_disp2_resources[] = {
291         {
292                 .name   = "irq",
293                 .start  = INT_DISPLAY_B_GENERAL,
294                 .end    = INT_DISPLAY_B_GENERAL,
295                 .flags  = IORESOURCE_IRQ,
296         },
297         {
298                 .name   = "regs",
299                 .start  = TEGRA_DISPLAY2_BASE,
300                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
301                 .flags  = IORESOURCE_MEM,
302         },
303         {
304                 .name   = "fbmem",
305                 .start  = 0, /* Filled in by roth_panel_init() */
306                 .end    = 0, /* Filled in by roth_panel_init() */
307                 .flags  = IORESOURCE_MEM,
308         },
309         {
310                 .name   = "hdmi_regs",
311                 .start  = TEGRA_HDMI_BASE,
312                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
313                 .flags  = IORESOURCE_MEM,
314         },
315 };
316
317 static u8 panel_dsi_config[] = {0xe0, 0x43, 0x0, 0x80, 0x0, 0x0};
318 static u8 panel_disp_ctrl1[] = {0xb5, 0x34, 0x20, 0x40, 0x0, 0x20};
319 static u8 panel_disp_ctrl2[] = {0xb6, 0x04, 0x74, 0x0f, 0x16, 0x13};
320 static u8 panel_internal_clk[] = {0xc0, 0x01, 0x08};
321 static u8 panel_pwr_ctrl3[] = {
322         0xc3, 0x0, 0x09, 0x10, 0x02, 0x0, 0x66, 0x20, 0x13, 0x0};
323 static u8 panel_pwr_ctrl4[] = {0xc4, 0x23, 0x24, 0x12, 0x12, 0x60};
324 static u8 panel_positive_gamma_red[] = {
325         0xd0, 0x21, 0x25, 0x67, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
326 static u8 panel_negetive_gamma_red[] = {
327         0xd1, 0x31, 0x25, 0x66, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03};
328 static u8 panel_positive_gamma_green[] = {
329         0xd2, 0x41, 0x26, 0x56, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
330 static u8 panel_negetive_gamma_green[] = {
331         0xd3, 0x51, 0x26, 0x55, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03};
332 static u8 panel_positive_gamma_blue[] = {
333         0xd4, 0x41, 0x26, 0x56, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03};
334 static u8 panel_negetive_gamma_blue[] = {
335         0xd5, 0x51, 0x26, 0x55, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03};
336
337 #if DSI_PANEL_CE
338 static u8 panel_ce2[] = {0x71, 0x0, 0x0, 0x01, 0x01};
339 static u8 panel_ce3[] = {0x72, 0x01, 0x0e};
340 static u8 panel_ce4[] = {0x73, 0x34, 0x52, 0x0};
341 static u8 panel_ce5[] = {0x74, 0x05, 0x0, 0x06};
342 static u8 panel_ce6[] = {0x75, 0x03, 0x0, 0x07};
343 static u8 panel_ce7[] = {0x76, 0x07, 0x0, 0x06};
344 static u8 panel_ce8[] = {0x77, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f};
345 static u8 panel_ce9[] = {0x78, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
346 static u8 panel_ce10[] = {
347         0x79, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40};
348 static u8 panel_ce11[] = {0x7a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
349 static u8 panel_ce12[] = {0x7b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
350 static u8 panel_ce13[] = {0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
351 #endif
352
353 static struct tegra_dsi_cmd dsi_init_cmd[] = {
354         DSI_DLY_MS(20),
355         DSI_GPIO_SET(DSI_PANEL_RST_GPIO, 1),
356
357         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_dsi_config),
358
359         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl1),
360         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl2),
361
362         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal_clk),
363
364         /*  panel power control 1 */
365         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x0),
366         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl3),
367         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl4),
368
369         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_red),
370         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_red),
371         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_green),
372         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_green),
373         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_blue),
374         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_blue),
375
376         DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_ADDR_MODE, 0x08),
377
378         /* panel OTP 2 */
379         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x0),
380
381 #if DSI_PANEL_CE
382         /* panel CE 1 */
383         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x70, 0x0),
384         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce2),
385         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce3),
386         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce4),
387         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce5),
388         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce6),
389         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce7),
390         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce8),
391         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce9),
392         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce10),
393         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce11),
394         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce12),
395         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce13),
396 #endif
397         /* panel power control 2 */
398         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x02),
399         DSI_DLY_MS(20),
400
401         /* panel power control 2 */
402         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x06),
403         DSI_DLY_MS(20),
404
405         /* panel power control 2 */
406         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x4e),
407         DSI_DLY_MS(100),
408
409         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0),
410         DSI_DLY_MS(140),
411
412         /* panel OTP 2 */
413         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x80),
414         DSI_DLY_MS(20),
415
416         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0),
417 };
418
419 static u8 panel_suspend_pwr_ctrl4[] = {0xc4, 0x0, 0x0, 0x0, 0x0, 0x0};
420
421 static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
422         DSI_DLY_MS(40),
423
424         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0),
425         DSI_DLY_MS(20),
426
427         DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0),
428
429         /* panel power control 2 */
430         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x0),
431
432         /* panel power control 4 */
433         DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_suspend_pwr_ctrl4),
434
435         /* panel power control 1 */
436         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x2),
437         DSI_DLY_MS(20),
438
439         /* panel power control 1 */
440         DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x3),
441         DSI_DLY_MS(20),
442 };
443
444 static struct tegra_dsi_out roth_dsi = {
445         .n_data_lanes = 4,
446         .controller_vs = DSI_VS_1,
447         .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
448         .refresh_rate = 60,
449         .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
450
451         .dsi_instance = DSI_INSTANCE_0,
452
453         .panel_reset = DSI_PANEL_RESET,
454         .power_saving_suspend = true,
455         .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
456         .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
457         .video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END,
458         .dsi_init_cmd = dsi_init_cmd,
459         .n_init_cmd = ARRAY_SIZE(dsi_init_cmd),
460         .dsi_suspend_cmd = dsi_suspend_cmd,
461         .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
462 };
463
464 static int roth_dsi_regulator_get(struct device *dev)
465 {
466         int err = 0;
467
468         if (reg_requested)
469                 return 0;
470
471         avdd_lcd_3v0_2v8 = regulator_get(dev, "avdd_lcd");
472         if (IS_ERR_OR_NULL(avdd_lcd_3v0_2v8)) {
473                 pr_err("avdd_lcd regulator get failed\n");
474                 err = PTR_ERR(avdd_lcd_3v0_2v8);
475                 avdd_lcd_3v0_2v8 = NULL;
476                 goto fail;
477         }
478         vdd_lcd_s_1v8 = regulator_get(dev, "dvdd_lcd");
479         if (IS_ERR_OR_NULL(vdd_lcd_s_1v8)) {
480                 pr_err("vdd_lcd_1v8_s regulator get failed\n");
481                 err = PTR_ERR(vdd_lcd_s_1v8);
482                 vdd_lcd_s_1v8 = NULL;
483                 goto fail;
484         }
485
486         if (machine_is_dalmore()) {
487                 vdd_lcd_bl = regulator_get(dev, "vdd_lcd_bl");
488                 if (IS_ERR_OR_NULL(vdd_lcd_bl)) {
489                         pr_err("vdd_lcd_bl regulator get failed\n");
490                         err = PTR_ERR(vdd_lcd_bl);
491                         vdd_lcd_bl = NULL;
492                         goto fail;
493                 }
494         }
495
496         vdd_lcd_bl_en = regulator_get(dev, "vdd_lcd_bl_en");
497         if (IS_ERR_OR_NULL(vdd_lcd_bl_en)) {
498                 pr_err("vdd_lcd_bl_en regulator get failed\n");
499                 err = PTR_ERR(vdd_lcd_bl_en);
500                 vdd_lcd_bl_en = NULL;
501                 goto fail;
502         }
503         reg_requested = true;
504         return 0;
505 fail:
506         return err;
507 }
508
509 static int roth_dsi_gpio_get(void)
510 {
511         int err = 0;
512
513         if (gpio_requested)
514                 return 0;
515
516         err = gpio_request(DSI_PANEL_RST_GPIO, "panel rst");
517         if (err < 0) {
518                 pr_err("panel reset gpio request failed\n");
519                 goto fail;
520         }
521
522         gpio_requested = true;
523         return 0;
524 fail:
525         return err;
526 }
527
528 static struct tegra_dc_out roth_disp1_out;
529
530 static int roth_dsi_panel_enable(struct device *dev)
531 {
532         int err = 0;
533
534         err = roth_dsi_regulator_get(dev);
535         if (err < 0) {
536                 pr_err("dsi regulator get failed\n");
537                 goto fail;
538         }
539         err = roth_dsi_gpio_get();
540         if (err < 0) {
541                 pr_err("dsi gpio request failed\n");
542                 goto fail;
543         }
544
545         /* Skip panel programming if in initialized mode */
546         if (!(roth_disp1_out.flags & TEGRA_DC_OUT_INITIALIZED_MODE)) {
547                 roth_dsi.dsi_init_cmd = dsi_init_cmd;
548                 gpio_set_value(DSI_PANEL_RST_GPIO, 0);
549         } else {
550                 roth_dsi.dsi_init_cmd = dsi_init_cmd + 2;
551         }
552
553         if (vdd_lcd_s_1v8) {
554                 err = regulator_enable(vdd_lcd_s_1v8);
555                 if (err < 0) {
556                         pr_err("vdd_lcd_1v8_s regulator enable failed\n");
557                         goto fail;
558                 }
559         }
560         usleep_range(3000, 5000);
561
562         if (avdd_lcd_3v0_2v8) {
563                 err = regulator_enable(avdd_lcd_3v0_2v8);
564                 if (err < 0) {
565                         pr_err("avdd_lcd_3v0_2v8 regulator enable failed\n");
566                         goto fail;
567                 }
568                 regulator_set_voltage(avdd_lcd_3v0_2v8, 2800000, 2800000);
569         }
570         usleep_range(3000, 5000);
571
572         if (vdd_lcd_bl) {
573                 err = regulator_enable(vdd_lcd_bl);
574                 if (err < 0) {
575                         pr_err("vdd_lcd_bl regulator enable failed\n");
576                         goto fail;
577                 }
578         }
579
580         if (vdd_lcd_bl_en) {
581                 err = regulator_enable(vdd_lcd_bl_en);
582                 if (err < 0) {
583                         pr_err("vdd_lcd_bl_en regulator enable failed\n");
584                         goto fail;
585                 }
586         }
587
588         return 0;
589 fail:
590         return err;
591 }
592
593 static int roth_dsi_panel_disable(void)
594 {
595         if (vdd_lcd_bl)
596                 regulator_disable(vdd_lcd_bl);
597
598         if (vdd_lcd_bl_en)
599                 regulator_disable(vdd_lcd_bl_en);
600
601         gpio_set_value(DSI_PANEL_RST_GPIO, 0);
602         mdelay(20);
603
604         if (vdd_lcd_s_1v8)
605                 regulator_disable(vdd_lcd_s_1v8);
606
607         if (avdd_lcd_3v0_2v8)
608                 regulator_disable(avdd_lcd_3v0_2v8);
609
610         return 0;
611 }
612
613 static int roth_dsi_panel_postsuspend(void)
614 {
615         /* TODO */
616         return 0;
617 }
618
619 static struct tegra_dc_mode roth_dsi_modes[] = {
620         {
621                 .pclk = 66700000,
622                 .h_ref_to_sync = 4,
623                 .v_ref_to_sync = 1,
624                 .h_sync_width = 4,
625                 .v_sync_width = 4,
626                 .h_back_porch = 112,
627                 .v_back_porch = 7,
628                 .h_active = 720,
629                 .v_active = 1280,
630                 .h_front_porch = 12,
631                 .v_front_porch = 20,
632         },
633 };
634
635 static struct tegra_dc_sd_settings sd_settings;
636
637 static struct tegra_dc_out roth_disp1_out = {
638         .type           = TEGRA_DC_OUT_DSI,
639         .dsi            = &roth_dsi,
640
641         .flags          = DC_CTRL_MODE,
642         .sd_settings    = &sd_settings,
643
644         .modes          = roth_dsi_modes,
645         .n_modes        = ARRAY_SIZE(roth_dsi_modes),
646
647         .enable         = roth_dsi_panel_enable,
648         .disable        = roth_dsi_panel_disable,
649         .postsuspend    = roth_dsi_panel_postsuspend,
650         .width          = 62,
651         .height         = 110,
652 };
653
654 static int roth_hdmi_enable(struct device *dev)
655 {
656         int ret;
657         if (!roth_hdmi_reg) {
658                 roth_hdmi_reg = regulator_get(dev, "avdd_hdmi");
659                 if (IS_ERR_OR_NULL(roth_hdmi_reg)) {
660                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
661                         roth_hdmi_reg = NULL;
662                         return PTR_ERR(roth_hdmi_reg);
663                 }
664         }
665         ret = regulator_enable(roth_hdmi_reg);
666         if (ret < 0) {
667                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
668                 return ret;
669         }
670         if (!roth_hdmi_pll) {
671                 roth_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
672                 if (IS_ERR_OR_NULL(roth_hdmi_pll)) {
673                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
674                         roth_hdmi_pll = NULL;
675                         regulator_put(roth_hdmi_reg);
676                         roth_hdmi_reg = NULL;
677                         return PTR_ERR(roth_hdmi_pll);
678                 }
679         }
680         ret = regulator_enable(roth_hdmi_pll);
681         if (ret < 0) {
682                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
683                 return ret;
684         }
685         return 0;
686 }
687
688 static int roth_hdmi_disable(void)
689 {
690         if (roth_hdmi_reg) {
691                 regulator_disable(roth_hdmi_reg);
692                 regulator_put(roth_hdmi_reg);
693                 roth_hdmi_reg = NULL;
694         }
695
696         if (roth_hdmi_pll) {
697                 regulator_disable(roth_hdmi_pll);
698                 regulator_put(roth_hdmi_pll);
699                 roth_hdmi_pll = NULL;
700         }
701
702         return 0;
703 }
704
705 static int roth_hdmi_postsuspend(void)
706 {
707         if (roth_hdmi_vddio) {
708                 regulator_disable(roth_hdmi_vddio);
709                 regulator_put(roth_hdmi_vddio);
710                 roth_hdmi_vddio = NULL;
711         }
712         return 0;
713 }
714
715 static int roth_hdmi_hotplug_init(struct device *dev)
716 {
717         if (!roth_hdmi_vddio) {
718                 roth_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
719                 if (WARN_ON(IS_ERR(roth_hdmi_vddio))) {
720                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
721                                         __func__, PTR_ERR(roth_hdmi_vddio));
722                         roth_hdmi_vddio = NULL;
723                 } else
724                         regulator_enable(roth_hdmi_vddio);
725         }
726         return 0;
727 }
728
729 static void roth_hdmi_hotplug_report(bool state)
730 {
731         if (state) {
732                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA,
733                                                 TEGRA_PUPD_PULL_DOWN);
734                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL,
735                                                 TEGRA_PUPD_PULL_DOWN);
736         } else {
737                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA,
738                                                 TEGRA_PUPD_NORMAL);
739                 tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL,
740                                                 TEGRA_PUPD_NORMAL);
741         }
742 }
743
744 static struct tegra_dc_out roth_disp2_out = {
745         .type           = TEGRA_DC_OUT_HDMI,
746         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
747         .parent_clk     = "pll_d2_out0",
748
749         .dcc_bus        = 3,
750         .hotplug_gpio   = roth_hdmi_hpd,
751
752         .max_pixclock   = KHZ2PICOS(297000),
753
754         .align          = TEGRA_DC_ALIGN_MSB,
755         .order          = TEGRA_DC_ORDER_RED_BLUE,
756
757         .enable         = roth_hdmi_enable,
758         .disable        = roth_hdmi_disable,
759         .postsuspend    = roth_hdmi_postsuspend,
760         .hotplug_init   = roth_hdmi_hotplug_init,
761         .hotplug_report = roth_hdmi_hotplug_report,
762 };
763
764 static struct tegra_fb_data roth_disp1_fb_data = {
765         .win            = 0,
766         .bits_per_pixel = 32,
767         .flags          = TEGRA_FB_FLIP_ON_PROBE,
768         .xres           = 720,
769         .yres           = 1280,
770 };
771
772 static struct tegra_dc_platform_data roth_disp1_pdata = {
773         .flags          = TEGRA_DC_FLAG_ENABLED,
774         .default_out    = &roth_disp1_out,
775         .fb             = &roth_disp1_fb_data,
776         .emc_clk_rate   = 204000000,
777 #ifdef CONFIG_TEGRA_DC_CMU
778         .cmu_enable     = 1,
779         .cmu            = &roth_cmu,
780 #endif
781 };
782
783 static struct tegra_fb_data roth_disp2_fb_data = {
784         .win            = 0,
785         .xres           = 1024,
786         .yres           = 600,
787         .bits_per_pixel = 32,
788         .flags          = TEGRA_FB_FLIP_ON_PROBE,
789 };
790
791 static struct tegra_dc_platform_data roth_disp2_pdata = {
792         .flags          = TEGRA_DC_FLAG_ENABLED,
793         .default_out    = &roth_disp2_out,
794         .fb             = &roth_disp2_fb_data,
795         .emc_clk_rate   = 300000000,
796 #ifdef CONFIG_TEGRA_DC_CMU
797         .cmu_enable     = 1,
798 #endif
799 };
800
801 static struct platform_device roth_disp2_device = {
802         .name           = "tegradc",
803         .id             = 1,
804         .resource       = roth_disp2_resources,
805         .num_resources  = ARRAY_SIZE(roth_disp2_resources),
806         .dev = {
807                 .platform_data = &roth_disp2_pdata,
808         },
809 };
810
811 static struct platform_device roth_disp1_device = {
812         .name           = "tegradc",
813         .id             = 0,
814         .resource       = roth_disp1_resources,
815         .num_resources  = ARRAY_SIZE(roth_disp1_resources),
816         .dev = {
817                 .platform_data = &roth_disp1_pdata,
818         },
819 };
820
821 static struct nvmap_platform_carveout roth_carveouts[] = {
822         [0] = {
823                 .name           = "iram",
824                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
825                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
826                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
827                 .buddy_size     = 0, /* no buddy allocation for IRAM */
828         },
829         [1] = {
830                 .name           = "generic-0",
831                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
832                 .base           = 0, /* Filled in by roth_panel_init() */
833                 .size           = 0, /* Filled in by roth_panel_init() */
834                 .buddy_size     = SZ_32K,
835         },
836         [2] = {
837                 .name           = "vpr",
838                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
839                 .base           = 0, /* Filled in by roth_panel_init() */
840                 .size           = 0, /* Filled in by roth_panel_init() */
841                 .buddy_size     = SZ_32K,
842         },
843 };
844
845 static struct nvmap_platform_data roth_nvmap_data = {
846         .carveouts      = roth_carveouts,
847         .nr_carveouts   = ARRAY_SIZE(roth_carveouts),
848 };
849
850 static struct platform_device roth_nvmap_device = {
851         .name   = "tegra-nvmap",
852         .id     = -1,
853         .dev    = {
854                 .platform_data = &roth_nvmap_data,
855         },
856 };
857
858 static int roth_disp1_bl_notify(struct device *unused, int brightness)
859 {
860         int cur_sd_brightness = atomic_read(&sd_brightness);
861
862         /* SD brightness is a percentage */
863         brightness = (brightness * cur_sd_brightness) / 255;
864
865         /* Apply any backlight response curve */
866         if (brightness > 255)
867                 pr_info("Error: Brightness > 255!\n");
868
869         return brightness;
870 }
871
872 static int roth_disp1_check_fb(struct device *dev, struct fb_info *info)
873 {
874         return info->device == &roth_disp1_device.dev;
875 }
876
877 static struct platform_pwm_backlight_data roth_disp1_bl_data = {
878         .pwm_id         = 1,
879         .max_brightness = 255,
880         .dft_brightness = 77,
881         .pwm_period_ns  = 40000,
882         .pwm_gpio       = DSI_PANEL_BL_PWM,
883         .notify         = roth_disp1_bl_notify,
884         /* Only toggle backlight on fb blank notifications for disp1 */
885         .check_fb       = roth_disp1_check_fb,
886 };
887
888 static struct platform_device __maybe_unused
889                 roth_disp1_bl_device = {
890         .name   = "pwm-backlight",
891         .id     = -1,
892         .dev    = {
893                 .platform_data = &roth_disp1_bl_data,
894         },
895 };
896
897 static struct tegra_dc_sd_settings roth_sd_settings = {
898         .enable = 0, /* disabled by default. */
899         .use_auto_pwm = false,
900         .hw_update_delay = 0,
901         .bin_width = -1,
902         .aggressiveness = 1,
903         .use_vid_luma = false,
904         .phase_in_adjustments = 0,
905         .k_limit_enable = true,
906         .k_limit = 180,
907         .sd_window_enable = false,
908         .soft_clipping_enable = true,
909         /* Low soft clipping threshold to compensate for aggressive k_limit */
910         .soft_clipping_threshold = 128,
911         .smooth_k_enable = true,
912         .smooth_k_incr = 128,
913         /* Default video coefficients */
914         .coeff = {5, 9, 2},
915         .fc = {0, 0},
916         /* Immediate backlight changes */
917         .blp = {1024, 255},
918         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
919         /* Default BL TF */
920         .bltf = {
921                         {
922                                 {57, 65, 73, 82},
923                                 {92, 103, 114, 125},
924                                 {138, 150, 164, 178},
925                                 {193, 208, 224, 241},
926                         },
927                 },
928         /* Default LUT */
929         .lut = {
930                         {
931                                 {255, 255, 255},
932                                 {199, 199, 199},
933                                 {153, 153, 153},
934                                 {116, 116, 116},
935                                 {85, 85, 85},
936                                 {59, 59, 59},
937                                 {36, 36, 36},
938                                 {17, 17, 17},
939                                 {0, 0, 0},
940                         },
941                 },
942         .sd_brightness = &sd_brightness,
943         .bl_device_name = "pwm-backlight",
944 };
945
946 static struct platform_device __maybe_unused
947                         *roth_bl_device[] __initdata = {
948         &tegra_pwfm_device,
949         &roth_disp1_bl_device,
950 };
951
952 int __init roth_panel_init(int board_id)
953 {
954         int err = 0;
955         struct resource __maybe_unused *res;
956         struct platform_device *phost1x = NULL;
957
958         sd_settings = roth_sd_settings;
959
960 #ifdef CONFIG_TEGRA_NVMAP
961         roth_carveouts[1].base = tegra_carveout_start;
962         roth_carveouts[1].size = tegra_carveout_size;
963         roth_carveouts[2].base = tegra_vpr_start;
964         roth_carveouts[2].size = tegra_vpr_size;
965
966         err = platform_device_register(&roth_nvmap_device);
967         if (err) {
968                 pr_err("nvmap device registration failed\n");
969                 return err;
970         }
971 #endif
972
973         phost1x = roth_host1x_init();
974         if (!phost1x) {
975                 pr_err("host1x devices registration failed\n");
976                 return -EINVAL;
977         }
978
979         res = platform_get_resource_byname(&roth_disp1_device,
980                                          IORESOURCE_MEM, "fbmem");
981         res->start = tegra_fb_start;
982         res->end = tegra_fb_start + tegra_fb_size - 1;
983
984         /* Copy the bootloader fb to the fb. */
985         __tegra_move_framebuffer(&roth_nvmap_device,
986                 tegra_fb_start, tegra_bootloader_fb_start,
987                         min(tegra_fb_size, tegra_bootloader_fb_size));
988
989         res = platform_get_resource_byname(&roth_disp2_device,
990                                          IORESOURCE_MEM, "fbmem");
991         res->start = tegra_fb2_start;
992         res->end = tegra_fb2_start + tegra_fb2_size - 1;
993
994         /*
995          * only roth supports initialized mode.
996          */
997         if (!board_id)
998                 roth_disp1_out.flags |= TEGRA_DC_OUT_INITIALIZED_MODE;
999
1000         roth_disp1_device.dev.parent = &phost1x->dev;
1001         err = platform_device_register(&roth_disp1_device);
1002         if (err) {
1003                 pr_err("disp1 device registration failed\n");
1004                 return err;
1005         }
1006
1007         roth_disp2_device.dev.parent = &phost1x->dev;
1008         err = platform_device_register(&roth_disp2_device);
1009         if (err) {
1010                 pr_err("disp2 device registration failed\n");
1011                 return err;
1012         }
1013
1014 #if IS_EXTERNAL_PWM
1015         err = platform_add_devices(roth_bl_device,
1016                                 ARRAY_SIZE(roth_bl_device));
1017         if (err) {
1018                 pr_err("disp1 bl device registration failed");
1019                 return err;
1020         }
1021 #endif
1022
1023 #ifdef CONFIG_TEGRA_NVAVP
1024         nvavp_device.dev.parent = &phost1x->dev;
1025         err = platform_device_register(&nvavp_device);
1026         if (err) {
1027                 pr_err("nvavp device registration failed\n");
1028                 return err;
1029         }
1030 #endif
1031         return err;
1032 }
1033 #else
1034 int __init roth_panel_init(void)
1035 {
1036         if (roth_host1x_init())
1037                 return 0;
1038         else
1039                 return -EINVAL;
1040 }
1041 #endif