ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-roth-memory.c
1 /*
2  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_data/tegra_emc.h>
22
23 #include "board.h"
24 #include "board-roth.h"
25
26 #include "tegra11_emc.h"
27 #include "devices.h"
28
29 static struct tegra11_emc_table h5tc4g63afr_pba_table[] = {
30         {
31                 0x41,       /* Rev 4.0.3 */
32                 12750,      /* SDRAM frequency */
33                 900,       /* min voltage */
34                 "pll_p",    /* clock source id */
35                 0x4000003e, /* CLK_SOURCE_EMC */
36                 99,         /* number of burst_regs */
37                 30,         /* number of trim_regs (each channel) */
38                 11,         /* number of up_down_regs */
39                 {
40                         0x00000000, /* EMC_RC */
41                         0x00000003, /* EMC_RFC */
42                         0x00000000, /* EMC_RFC_SLR */
43                         0x00000000, /* EMC_RAS */
44                         0x00000000, /* EMC_RP */
45                         0x00000004, /* EMC_R2W */
46                         0x0000000a, /* EMC_W2R */
47                         0x00000003, /* EMC_R2P */
48                         0x0000000b, /* EMC_W2P */
49                         0x00000000, /* EMC_RD_RCD */
50                         0x00000000, /* EMC_WR_RCD */
51                         0x00000003, /* EMC_RRD */
52                         0x00000001, /* EMC_REXT */
53                         0x00000000, /* EMC_WEXT */
54                         0x00000005, /* EMC_WDV */
55                         0x0000000f, /* EMC_WDV_MASK */
56                         0x00000006, /* EMC_IBDLY */
57                         0x00010000, /* EMC_PUTERM_EXTRA */
58                         0x00000000, /* EMC_CDB_CNTL_2 */
59                         0x00000004, /* EMC_QRST */
60                         0x0000000f, /* EMC_RDV_MASK */
61                         0x00000060, /* EMC_REFRESH */
62                         0x00000000, /* EMC_BURST_REFRESH_NUM */
63                         0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
64                         0x00000002, /* EMC_PDEX2WR */
65                         0x00000002, /* EMC_PDEX2RD */
66                         0x00000001, /* EMC_PCHG2PDEN */
67                         0x00000000, /* EMC_ACT2PDEN */
68                         0x00000007, /* EMC_AR2PDEN */
69                         0x0000000f, /* EMC_RW2PDEN */
70                         0x00000005, /* EMC_TXSR */
71                         0x00000005, /* EMC_TXSRDLL */
72                         0x00000004, /* EMC_TCKE */
73                         0x00000004, /* EMC_TCKESR */
74                         0x00000004, /* EMC_TPD */
75                         0x00000004, /* EMC_TFAW */
76                         0x00000000, /* EMC_TRPAB */
77                         0x00000004, /* EMC_TCLKSTABLE */
78                         0x00000005, /* EMC_TCLKSTOP */
79                         0x00000064, /* EMC_TREFBW */
80                         0x00000005, /* EMC_QUSE_EXTRA */
81                         0x00000020, /* EMC_ODT_WRITE */
82                         0x00000000, /* EMC_ODT_READ */
83                         0x0000aa88, /* EMC_FBIO_CFG5 */
84                         0x002c00a0, /* EMC_CFG_DIG_DLL */
85                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
86                         0x00078000, /* EMC_DLL_XFORM_DQS4 */
87                         0x00078000, /* EMC_DLL_XFORM_DQS5 */
88                         0x00078000, /* EMC_DLL_XFORM_DQS6 */
89                         0x00078000, /* EMC_DLL_XFORM_DQS7 */
90                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
91                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
92                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
93                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
94                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
95                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
96                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
97                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
98                         0x001112a0, /* EMC_XM2CMDPADCTRL */
99                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
100                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
101                         0x00000000, /* EMC_XM2DQPADCTRL2 */
102                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
103                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
104                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
105                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
106                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
107                         0x00000007, /* EMC_TXDSRVTTGEN */
108                         0x02000000, /* EMC_FBIO_SPARE */
109                         0x00000802, /* EMC_CTT_TERM_CTRL */
110                         0x00000000, /* EMC_ZCAL_INTERVAL */
111                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
112                         0x000f000f, /* EMC_MRS_WAIT_CNT */
113                         0x000f000f, /* EMC_MRS_WAIT_CNT2 */
114                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
115                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
116                         0x00000000, /* EMC_CTT */
117                         0x00000000, /* EMC_CTT_DURATION */
118                         0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
119                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
120                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
121                         0x40040001, /* MC_EMEM_ARB_CFG */
122                         0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
123                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
124                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
125                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
126                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
127                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
128                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
129                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
130                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
131                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
132                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
133                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
134                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
135                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
136                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
137                         0x77e30303, /* MC_EMEM_ARB_MISC0 */
138                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
139                 },
140                 {
141                         0x00000000, /* EMC_CDB_CNTL_1 */
142                         0x00000006, /* EMC_FBIO_CFG6 */
143                         0x00000006, /* EMC_QUSE */
144                         0x00000004, /* EMC_EINPUT */
145                         0x00000004, /* EMC_EINPUT_DURATION */
146                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
147                         0x00000009, /* EMC_QSAFE */
148                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
149                         0x0000000d, /* EMC_RDV */
150                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
151                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
152                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
153                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
154                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
155                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
156                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
157                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
158                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
159                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
160                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
161                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
162                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
163                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
164                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
165                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
166                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
167                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
168                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
169                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
170                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
171                 },
172                 {
173                         0x00000000, /* EMC_CDB_CNTL_1 */
174                         0x00000006, /* EMC_FBIO_CFG6 */
175                         0x00000006, /* EMC_QUSE */
176                         0x00000004, /* EMC_EINPUT */
177                         0x00000004, /* EMC_EINPUT_DURATION */
178                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
179                         0x00000009, /* EMC_QSAFE */
180                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
181                         0x0000000d, /* EMC_RDV */
182                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
183                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
184                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
185                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
186                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
187                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
188                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
189                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
190                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
191                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
192                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
193                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
194                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
195                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
196                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
197                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
198                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
199                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
200                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
201                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
202                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
203                 },
204                 {
205                         0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
206                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
207                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
208                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
209                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
210                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
211                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
212                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
213                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
214                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
215                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
216                 },
217                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
218                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
219                 0x7324000e, /* EMC_CFG */
220                 0x80001221, /* Mode Register 0 */
221                 0x80100003, /* Mode Register 1 */
222                 0x80200008, /* Mode Register 2 */
223                 0x00000000, /* Mode Register 4 */
224                 57820,      /* expected dvfs latency (ns) */
225         },
226         {
227                 0x41,       /* Rev 4.0.3 */
228                 20400,      /* SDRAM frequency */
229                 900,       /* min voltage */
230                 "pll_p",    /* clock source id */
231                 0x40000026, /* CLK_SOURCE_EMC */
232                 99,         /* number of burst_regs */
233                 30,         /* number of trim_regs (each channel) */
234                 11,         /* number of up_down_regs */
235                 {
236                         0x00000000, /* EMC_RC */
237                         0x00000005, /* EMC_RFC */
238                         0x00000000, /* EMC_RFC_SLR */
239                         0x00000000, /* EMC_RAS */
240                         0x00000000, /* EMC_RP */
241                         0x00000004, /* EMC_R2W */
242                         0x0000000a, /* EMC_W2R */
243                         0x00000003, /* EMC_R2P */
244                         0x0000000b, /* EMC_W2P */
245                         0x00000000, /* EMC_RD_RCD */
246                         0x00000000, /* EMC_WR_RCD */
247                         0x00000003, /* EMC_RRD */
248                         0x00000001, /* EMC_REXT */
249                         0x00000000, /* EMC_WEXT */
250                         0x00000005, /* EMC_WDV */
251                         0x0000000f, /* EMC_WDV_MASK */
252                         0x00000006, /* EMC_IBDLY */
253                         0x00010000, /* EMC_PUTERM_EXTRA */
254                         0x00000000, /* EMC_CDB_CNTL_2 */
255                         0x00000004, /* EMC_QRST */
256                         0x0000000f, /* EMC_RDV_MASK */
257                         0x0000009a, /* EMC_REFRESH */
258                         0x00000000, /* EMC_BURST_REFRESH_NUM */
259                         0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
260                         0x00000002, /* EMC_PDEX2WR */
261                         0x00000002, /* EMC_PDEX2RD */
262                         0x00000001, /* EMC_PCHG2PDEN */
263                         0x00000000, /* EMC_ACT2PDEN */
264                         0x00000007, /* EMC_AR2PDEN */
265                         0x0000000f, /* EMC_RW2PDEN */
266                         0x00000006, /* EMC_TXSR */
267                         0x00000006, /* EMC_TXSRDLL */
268                         0x00000004, /* EMC_TCKE */
269                         0x00000004, /* EMC_TCKESR */
270                         0x00000004, /* EMC_TPD */
271                         0x00000004, /* EMC_TFAW */
272                         0x00000000, /* EMC_TRPAB */
273                         0x00000004, /* EMC_TCLKSTABLE */
274                         0x00000005, /* EMC_TCLKSTOP */
275                         0x000000a0, /* EMC_TREFBW */
276                         0x00000005, /* EMC_QUSE_EXTRA */
277                         0x00000020, /* EMC_ODT_WRITE */
278                         0x00000000, /* EMC_ODT_READ */
279                         0x0000aa88, /* EMC_FBIO_CFG5 */
280                         0x002c00a0, /* EMC_CFG_DIG_DLL */
281                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
282                         0x00078000, /* EMC_DLL_XFORM_DQS4 */
283                         0x00078000, /* EMC_DLL_XFORM_DQS5 */
284                         0x00078000, /* EMC_DLL_XFORM_DQS6 */
285                         0x00078000, /* EMC_DLL_XFORM_DQS7 */
286                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
287                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
288                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
289                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
290                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
291                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
292                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
293                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
294                         0x001112a0, /* EMC_XM2CMDPADCTRL */
295                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
296                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
297                         0x00000000, /* EMC_XM2DQPADCTRL2 */
298                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
299                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
300                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
301                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
302                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
303                         0x0000000b, /* EMC_TXDSRVTTGEN */
304                         0x02000000, /* EMC_FBIO_SPARE */
305                         0x00000802, /* EMC_CTT_TERM_CTRL */
306                         0x00000000, /* EMC_ZCAL_INTERVAL */
307                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
308                         0x000f000f, /* EMC_MRS_WAIT_CNT */
309                         0x000f000f, /* EMC_MRS_WAIT_CNT2 */
310                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
311                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
312                         0x00000000, /* EMC_CTT */
313                         0x00000000, /* EMC_CTT_DURATION */
314                         0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
315                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
316                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
317                         0x40020001, /* MC_EMEM_ARB_CFG */
318                         0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
319                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
320                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
321                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
322                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
323                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
324                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
325                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
326                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
327                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
328                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
329                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
330                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
331                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
332                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
333                         0x76230303, /* MC_EMEM_ARB_MISC0 */
334                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
335                 },
336                 {
337                         0x00000000, /* EMC_CDB_CNTL_1 */
338                         0x00000006, /* EMC_FBIO_CFG6 */
339                         0x00000006, /* EMC_QUSE */
340                         0x00000004, /* EMC_EINPUT */
341                         0x00000004, /* EMC_EINPUT_DURATION */
342                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
343                         0x00000009, /* EMC_QSAFE */
344                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
345                         0x0000000d, /* EMC_RDV */
346                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
347                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
348                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
349                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
350                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
351                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
352                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
353                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
354                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
355                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
356                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
357                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
358                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
359                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
360                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
361                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
362                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
363                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
364                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
365                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
366                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
367                 },
368                 {
369                         0x00000000, /* EMC_CDB_CNTL_1 */
370                         0x00000006, /* EMC_FBIO_CFG6 */
371                         0x00000006, /* EMC_QUSE */
372                         0x00000004, /* EMC_EINPUT */
373                         0x00000004, /* EMC_EINPUT_DURATION */
374                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
375                         0x00000009, /* EMC_QSAFE */
376                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
377                         0x0000000d, /* EMC_RDV */
378                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
379                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
380                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
381                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
382                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
383                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
384                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
385                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
386                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
387                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
388                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
389                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
390                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
391                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
392                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
393                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
394                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
395                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
396                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
397                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
398                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
399                 },
400                 {
401                         0x00000014, /* MC_PTSA_GRANT_DECREMENT */
402                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
403                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
404                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
405                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
406                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
407                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
408                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
409                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
410                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
411                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
412                 },
413                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
414                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
415                 0x7324000e, /* EMC_CFG */
416                 0x80001221, /* Mode Register 0 */
417                 0x80100003, /* Mode Register 1 */
418                 0x80200008, /* Mode Register 2 */
419                 0x00000000, /* Mode Register 4 */
420                 35610,      /* expected dvfs latency (ns) */
421         },
422         {
423                 0x41,       /* Rev 4.0.3 */
424                 40800,      /* SDRAM frequency */
425                 900,       /* min voltage */
426                 "pll_p",    /* clock source id */
427                 0x40000012, /* CLK_SOURCE_EMC */
428                 99,         /* number of burst_regs */
429                 30,         /* number of trim_regs (each channel) */
430                 11,         /* number of up_down_regs */
431                 {
432                         0x00000001, /* EMC_RC */
433                         0x0000000a, /* EMC_RFC */
434                         0x00000000, /* EMC_RFC_SLR */
435                         0x00000001, /* EMC_RAS */
436                         0x00000000, /* EMC_RP */
437                         0x00000004, /* EMC_R2W */
438                         0x0000000a, /* EMC_W2R */
439                         0x00000003, /* EMC_R2P */
440                         0x0000000b, /* EMC_W2P */
441                         0x00000000, /* EMC_RD_RCD */
442                         0x00000000, /* EMC_WR_RCD */
443                         0x00000003, /* EMC_RRD */
444                         0x00000001, /* EMC_REXT */
445                         0x00000000, /* EMC_WEXT */
446                         0x00000005, /* EMC_WDV */
447                         0x0000000f, /* EMC_WDV_MASK */
448                         0x00000006, /* EMC_IBDLY */
449                         0x00010000, /* EMC_PUTERM_EXTRA */
450                         0x00000000, /* EMC_CDB_CNTL_2 */
451                         0x00000004, /* EMC_QRST */
452                         0x0000000f, /* EMC_RDV_MASK */
453                         0x00000134, /* EMC_REFRESH */
454                         0x00000000, /* EMC_BURST_REFRESH_NUM */
455                         0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
456                         0x00000002, /* EMC_PDEX2WR */
457                         0x00000002, /* EMC_PDEX2RD */
458                         0x00000001, /* EMC_PCHG2PDEN */
459                         0x00000000, /* EMC_ACT2PDEN */
460                         0x00000008, /* EMC_AR2PDEN */
461                         0x0000000f, /* EMC_RW2PDEN */
462                         0x0000000c, /* EMC_TXSR */
463                         0x0000000c, /* EMC_TXSRDLL */
464                         0x00000004, /* EMC_TCKE */
465                         0x00000004, /* EMC_TCKESR */
466                         0x00000004, /* EMC_TPD */
467                         0x00000004, /* EMC_TFAW */
468                         0x00000000, /* EMC_TRPAB */
469                         0x00000004, /* EMC_TCLKSTABLE */
470                         0x00000005, /* EMC_TCLKSTOP */
471                         0x0000013f, /* EMC_TREFBW */
472                         0x00000005, /* EMC_QUSE_EXTRA */
473                         0x00000020, /* EMC_ODT_WRITE */
474                         0x00000000, /* EMC_ODT_READ */
475                         0x0000aa88, /* EMC_FBIO_CFG5 */
476                         0x002c00a0, /* EMC_CFG_DIG_DLL */
477                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
478                         0x00078000, /* EMC_DLL_XFORM_DQS4 */
479                         0x00078000, /* EMC_DLL_XFORM_DQS5 */
480                         0x00078000, /* EMC_DLL_XFORM_DQS6 */
481                         0x00078000, /* EMC_DLL_XFORM_DQS7 */
482                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
483                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
484                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
485                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
486                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
487                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
488                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
489                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
490                         0x001112a0, /* EMC_XM2CMDPADCTRL */
491                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
492                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
493                         0x00000000, /* EMC_XM2DQPADCTRL2 */
494                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
495                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
496                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
497                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
498                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
499                         0x00000015, /* EMC_TXDSRVTTGEN */
500                         0x02000000, /* EMC_FBIO_SPARE */
501                         0x00000802, /* EMC_CTT_TERM_CTRL */
502                         0x00000000, /* EMC_ZCAL_INTERVAL */
503                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
504                         0x000f000f, /* EMC_MRS_WAIT_CNT */
505                         0x000f000f, /* EMC_MRS_WAIT_CNT2 */
506                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
507                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
508                         0x00000000, /* EMC_CTT */
509                         0x00000000, /* EMC_CTT_DURATION */
510                         0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
511                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
512                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
513                         0xa0000001, /* MC_EMEM_ARB_CFG */
514                         0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
515                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
516                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
517                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
518                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
519                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
520                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
521                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
522                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
523                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
524                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
525                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
526                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
527                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
528                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
529                         0x74a30303, /* MC_EMEM_ARB_MISC0 */
530                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
531                 },
532                 {
533                         0x00000000, /* EMC_CDB_CNTL_1 */
534                         0x00000006, /* EMC_FBIO_CFG6 */
535                         0x00000006, /* EMC_QUSE */
536                         0x00000004, /* EMC_EINPUT */
537                         0x00000004, /* EMC_EINPUT_DURATION */
538                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
539                         0x00000009, /* EMC_QSAFE */
540                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
541                         0x0000000d, /* EMC_RDV */
542                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
543                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
544                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
545                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
546                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
547                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
548                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
549                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
550                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
551                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
552                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
553                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
554                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
555                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
556                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
557                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
558                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
559                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
560                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
561                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
562                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
563                 },
564                 {
565                         0x00000000, /* EMC_CDB_CNTL_1 */
566                         0x00000006, /* EMC_FBIO_CFG6 */
567                         0x00000006, /* EMC_QUSE */
568                         0x00000004, /* EMC_EINPUT */
569                         0x00000004, /* EMC_EINPUT_DURATION */
570                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
571                         0x00000009, /* EMC_QSAFE */
572                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
573                         0x0000000d, /* EMC_RDV */
574                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
575                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
576                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
577                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
578                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
579                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
580                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
581                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
582                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
583                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
584                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
585                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
586                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
587                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
588                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
589                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
590                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
591                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
592                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
593                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
594                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
595                 },
596                 {
597                         0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
598                         0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
599                         0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
600                         0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
601                         0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
602                         0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
603                         0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
604                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
605                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
606                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
607                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
608                 },
609                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
610                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
611                 0x7324000e, /* EMC_CFG */
612                 0x80001221, /* Mode Register 0 */
613                 0x80100003, /* Mode Register 1 */
614                 0x80200008, /* Mode Register 2 */
615                 0x00000000, /* Mode Register 4 */
616                 20850,      /* expected dvfs latency (ns) */
617         },
618         {
619                 0x41,       /* Rev 4.0.3 */
620                 68000,      /* SDRAM frequency */
621                 900,       /* min voltage */
622                 "pll_p",    /* clock source id */
623                 0x4000000a, /* CLK_SOURCE_EMC */
624                 99,         /* number of burst_regs */
625                 30,         /* number of trim_regs (each channel) */
626                 11,         /* number of up_down_regs */
627                 {
628                         0x00000003, /* EMC_RC */
629                         0x00000011, /* EMC_RFC */
630                         0x00000000, /* EMC_RFC_SLR */
631                         0x00000002, /* EMC_RAS */
632                         0x00000000, /* EMC_RP */
633                         0x00000004, /* EMC_R2W */
634                         0x0000000a, /* EMC_W2R */
635                         0x00000003, /* EMC_R2P */
636                         0x0000000b, /* EMC_W2P */
637                         0x00000000, /* EMC_RD_RCD */
638                         0x00000000, /* EMC_WR_RCD */
639                         0x00000003, /* EMC_RRD */
640                         0x00000001, /* EMC_REXT */
641                         0x00000000, /* EMC_WEXT */
642                         0x00000005, /* EMC_WDV */
643                         0x0000000f, /* EMC_WDV_MASK */
644                         0x00000006, /* EMC_IBDLY */
645                         0x00010000, /* EMC_PUTERM_EXTRA */
646                         0x00000000, /* EMC_CDB_CNTL_2 */
647                         0x00000004, /* EMC_QRST */
648                         0x0000000f, /* EMC_RDV_MASK */
649                         0x00000202, /* EMC_REFRESH */
650                         0x00000000, /* EMC_BURST_REFRESH_NUM */
651                         0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
652                         0x00000002, /* EMC_PDEX2WR */
653                         0x00000002, /* EMC_PDEX2RD */
654                         0x00000001, /* EMC_PCHG2PDEN */
655                         0x00000000, /* EMC_ACT2PDEN */
656                         0x0000000f, /* EMC_AR2PDEN */
657                         0x0000000f, /* EMC_RW2PDEN */
658                         0x00000013, /* EMC_TXSR */
659                         0x00000013, /* EMC_TXSRDLL */
660                         0x00000004, /* EMC_TCKE */
661                         0x00000004, /* EMC_TCKESR */
662                         0x00000004, /* EMC_TPD */
663                         0x00000004, /* EMC_TFAW */
664                         0x00000000, /* EMC_TRPAB */
665                         0x00000004, /* EMC_TCLKSTABLE */
666                         0x00000005, /* EMC_TCLKSTOP */
667                         0x00000213, /* EMC_TREFBW */
668                         0x00000005, /* EMC_QUSE_EXTRA */
669                         0x00000020, /* EMC_ODT_WRITE */
670                         0x00000000, /* EMC_ODT_READ */
671                         0x0000aa88, /* EMC_FBIO_CFG5 */
672                         0x002c00a0, /* EMC_CFG_DIG_DLL */
673                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
674                         0x00078000, /* EMC_DLL_XFORM_DQS4 */
675                         0x00078000, /* EMC_DLL_XFORM_DQS5 */
676                         0x00078000, /* EMC_DLL_XFORM_DQS6 */
677                         0x00078000, /* EMC_DLL_XFORM_DQS7 */
678                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
679                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
680                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
681                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
682                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
683                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
684                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
685                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
686                         0x001112a0, /* EMC_XM2CMDPADCTRL */
687                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
688                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
689                         0x00000000, /* EMC_XM2DQPADCTRL2 */
690                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
691                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
692                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
693                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
694                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
695                         0x00000022, /* EMC_TXDSRVTTGEN */
696                         0x02000000, /* EMC_FBIO_SPARE */
697                         0x00000802, /* EMC_CTT_TERM_CTRL */
698                         0x00000000, /* EMC_ZCAL_INTERVAL */
699                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
700                         0x000f000f, /* EMC_MRS_WAIT_CNT */
701                         0x000f000f, /* EMC_MRS_WAIT_CNT2 */
702                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
703                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
704                         0x00000000, /* EMC_CTT */
705                         0x00000000, /* EMC_CTT_DURATION */
706                         0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
707                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
708                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
709                         0x00000001, /* MC_EMEM_ARB_CFG */
710                         0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
711                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
712                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
713                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
714                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
715                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
716                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
717                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
718                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
719                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
720                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
721                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
722                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
723                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
724                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
725                         0x74230403, /* MC_EMEM_ARB_MISC0 */
726                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
727                 },
728                 {
729                         0x00000000, /* EMC_CDB_CNTL_1 */
730                         0x00000006, /* EMC_FBIO_CFG6 */
731                         0x00000006, /* EMC_QUSE */
732                         0x00000004, /* EMC_EINPUT */
733                         0x00000004, /* EMC_EINPUT_DURATION */
734                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
735                         0x00000009, /* EMC_QSAFE */
736                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
737                         0x0000000d, /* EMC_RDV */
738                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
739                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
740                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
741                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
742                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
743                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
744                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
745                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
746                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
747                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
748                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
749                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
750                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
751                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
752                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
753                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
754                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
755                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
756                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
757                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
758                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
759                 },
760                 {
761                         0x00000000, /* EMC_CDB_CNTL_1 */
762                         0x00000006, /* EMC_FBIO_CFG6 */
763                         0x00000006, /* EMC_QUSE */
764                         0x00000004, /* EMC_EINPUT */
765                         0x00000004, /* EMC_EINPUT_DURATION */
766                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
767                         0x00000009, /* EMC_QSAFE */
768                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
769                         0x0000000d, /* EMC_RDV */
770                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
771                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
772                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
773                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
774                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
775                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
776                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
777                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
778                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
779                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
780                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
781                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
782                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
783                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
784                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
785                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
786                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
787                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
788                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
789                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
790                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
791                 },
792                 {
793                         0x00000046, /* MC_PTSA_GRANT_DECREMENT */
794                         0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
795                         0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
796                         0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
797                         0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
798                         0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
799                         0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
800                         0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
801                         0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
802                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
803                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
804                 },
805                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
806                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
807                 0x7324000e, /* EMC_CFG */
808                 0x80001221, /* Mode Register 0 */
809                 0x80100003, /* Mode Register 1 */
810                 0x80200008, /* Mode Register 2 */
811                 0x00000000, /* Mode Register 4 */
812                 10720,      /* expected dvfs latency (ns) */
813         },
814         {
815                 0x41,       /* Rev 4.0.3 */
816                 102000,     /* SDRAM frequency */
817                 900,       /* min voltage */
818                 "pll_p",    /* clock source id */
819                 0x40000006, /* CLK_SOURCE_EMC */
820                 99,         /* number of burst_regs */
821                 30,         /* number of trim_regs (each channel) */
822                 11,         /* number of up_down_regs */
823                 {
824                         0x00000004, /* EMC_RC */
825                         0x0000001a, /* EMC_RFC */
826                         0x00000000, /* EMC_RFC_SLR */
827                         0x00000003, /* EMC_RAS */
828                         0x00000001, /* EMC_RP */
829                         0x00000004, /* EMC_R2W */
830                         0x0000000a, /* EMC_W2R */
831                         0x00000003, /* EMC_R2P */
832                         0x0000000b, /* EMC_W2P */
833                         0x00000001, /* EMC_RD_RCD */
834                         0x00000001, /* EMC_WR_RCD */
835                         0x00000003, /* EMC_RRD */
836                         0x00000001, /* EMC_REXT */
837                         0x00000000, /* EMC_WEXT */
838                         0x00000005, /* EMC_WDV */
839                         0x0000000f, /* EMC_WDV_MASK */
840                         0x00000006, /* EMC_IBDLY */
841                         0x00010000, /* EMC_PUTERM_EXTRA */
842                         0x00000000, /* EMC_CDB_CNTL_2 */
843                         0x00000004, /* EMC_QRST */
844                         0x0000000f, /* EMC_RDV_MASK */
845                         0x00000303, /* EMC_REFRESH */
846                         0x00000000, /* EMC_BURST_REFRESH_NUM */
847                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
848                         0x00000002, /* EMC_PDEX2WR */
849                         0x00000002, /* EMC_PDEX2RD */
850                         0x00000001, /* EMC_PCHG2PDEN */
851                         0x00000000, /* EMC_ACT2PDEN */
852                         0x00000018, /* EMC_AR2PDEN */
853                         0x0000000f, /* EMC_RW2PDEN */
854                         0x0000001c, /* EMC_TXSR */
855                         0x0000001c, /* EMC_TXSRDLL */
856                         0x00000004, /* EMC_TCKE */
857                         0x00000004, /* EMC_TCKESR */
858                         0x00000004, /* EMC_TPD */
859                         0x00000005, /* EMC_TFAW */
860                         0x00000000, /* EMC_TRPAB */
861                         0x00000004, /* EMC_TCLKSTABLE */
862                         0x00000005, /* EMC_TCLKSTOP */
863                         0x0000031c, /* EMC_TREFBW */
864                         0x00000005, /* EMC_QUSE_EXTRA */
865                         0x00000020, /* EMC_ODT_WRITE */
866                         0x00000000, /* EMC_ODT_READ */
867                         0x0000aa88, /* EMC_FBIO_CFG5 */
868                         0x002c00a0, /* EMC_CFG_DIG_DLL */
869                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
870                         0x00078000, /* EMC_DLL_XFORM_DQS4 */
871                         0x00078000, /* EMC_DLL_XFORM_DQS5 */
872                         0x00078000, /* EMC_DLL_XFORM_DQS6 */
873                         0x00078000, /* EMC_DLL_XFORM_DQS7 */
874                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
875                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
876                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
877                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
878                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
879                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
880                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
881                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
882                         0x001112a0, /* EMC_XM2CMDPADCTRL */
883                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
884                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
885                         0x00000000, /* EMC_XM2DQPADCTRL2 */
886                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
887                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
888                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
889                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
890                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
891                         0x00000033, /* EMC_TXDSRVTTGEN */
892                         0x02000000, /* EMC_FBIO_SPARE */
893                         0x00000802, /* EMC_CTT_TERM_CTRL */
894                         0x00000000, /* EMC_ZCAL_INTERVAL */
895                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
896                         0x000f000f, /* EMC_MRS_WAIT_CNT */
897                         0x000f000f, /* EMC_MRS_WAIT_CNT2 */
898                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
899                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
900                         0x00000000, /* EMC_CTT */
901                         0x00000000, /* EMC_CTT_DURATION */
902                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
903                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
904                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
905                         0x08000001, /* MC_EMEM_ARB_CFG */
906                         0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
907                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
908                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
909                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
910                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
911                         0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
912                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
913                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
914                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
915                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
916                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
917                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
918                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
919                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
920                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
921                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
922                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
923                 },
924                 {
925                         0x00000000, /* EMC_CDB_CNTL_1 */
926                         0x00000006, /* EMC_FBIO_CFG6 */
927                         0x00000006, /* EMC_QUSE */
928                         0x00000004, /* EMC_EINPUT */
929                         0x00000004, /* EMC_EINPUT_DURATION */
930                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
931                         0x00000009, /* EMC_QSAFE */
932                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
933                         0x0000000d, /* EMC_RDV */
934                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
935                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
936                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
937                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
938                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
939                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
940                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
941                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
942                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
943                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
944                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
945                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
946                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
947                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
948                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
949                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
950                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
951                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
952                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
953                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
954                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
955                 },
956                 {
957                         0x00000000, /* EMC_CDB_CNTL_1 */
958                         0x00000006, /* EMC_FBIO_CFG6 */
959                         0x00000006, /* EMC_QUSE */
960                         0x00000004, /* EMC_EINPUT */
961                         0x00000004, /* EMC_EINPUT_DURATION */
962                         0x00078000, /* EMC_DLL_XFORM_DQS0 */
963                         0x00000009, /* EMC_QSAFE */
964                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
965                         0x0000000d, /* EMC_RDV */
966                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
967                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
968                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
969                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
970                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
971                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
972                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
973                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
974                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
975                         0x00078000, /* EMC_DLL_XFORM_DQS1 */
976                         0x00078000, /* EMC_DLL_XFORM_DQS2 */
977                         0x00078000, /* EMC_DLL_XFORM_DQS3 */
978                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
979                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
980                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
981                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
982                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
983                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
984                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
985                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
986                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
987                 },
988                 {
989                         0x00000068, /* MC_PTSA_GRANT_DECREMENT */
990                         0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
991                         0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
992                         0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
993                         0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
994                         0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
995                         0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
996                         0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
997                         0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
998                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
999                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1000                 },
1001                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1002                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1003                 0x7324000e, /* EMC_CFG */
1004                 0x80001221, /* Mode Register 0 */
1005                 0x80100003, /* Mode Register 1 */
1006                 0x80200008, /* Mode Register 2 */
1007                 0x00000000, /* Mode Register 4 */
1008                 6890,       /* expected dvfs latency (ns) */
1009         },
1010         {
1011                 0x41,       /* Rev 4.0.3 */
1012                 204000,     /* SDRAM frequency */
1013                 900,       /* min voltage */
1014                 "pll_p",    /* clock source id */
1015                 0x40000002, /* CLK_SOURCE_EMC */
1016                 99,         /* number of burst_regs */
1017                 30,         /* number of trim_regs (each channel) */
1018                 11,         /* number of up_down_regs */
1019                 {
1020                         0x00000009, /* EMC_RC */
1021                         0x00000035, /* EMC_RFC */
1022                         0x00000000, /* EMC_RFC_SLR */
1023                         0x00000006, /* EMC_RAS */
1024                         0x00000002, /* EMC_RP */
1025                         0x00000004, /* EMC_R2W */
1026                         0x0000000a, /* EMC_W2R */
1027                         0x00000003, /* EMC_R2P */
1028                         0x0000000b, /* EMC_W2P */
1029                         0x00000002, /* EMC_RD_RCD */
1030                         0x00000002, /* EMC_WR_RCD */
1031                         0x00000003, /* EMC_RRD */
1032                         0x00000001, /* EMC_REXT */
1033                         0x00000000, /* EMC_WEXT */
1034                         0x00000005, /* EMC_WDV */
1035                         0x0000000f, /* EMC_WDV_MASK */
1036                         0x00000006, /* EMC_IBDLY */
1037                         0x00010000, /* EMC_PUTERM_EXTRA */
1038                         0x00000000, /* EMC_CDB_CNTL_2 */
1039                         0x00000004, /* EMC_QRST */
1040                         0x0000000f, /* EMC_RDV_MASK */
1041                         0x00000607, /* EMC_REFRESH */
1042                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1043                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
1044                         0x00000002, /* EMC_PDEX2WR */
1045                         0x00000002, /* EMC_PDEX2RD */
1046                         0x00000001, /* EMC_PCHG2PDEN */
1047                         0x00000000, /* EMC_ACT2PDEN */
1048                         0x00000032, /* EMC_AR2PDEN */
1049                         0x0000000f, /* EMC_RW2PDEN */
1050                         0x00000038, /* EMC_TXSR */
1051                         0x00000038, /* EMC_TXSRDLL */
1052                         0x00000004, /* EMC_TCKE */
1053                         0x00000004, /* EMC_TCKESR */
1054                         0x00000004, /* EMC_TPD */
1055                         0x00000009, /* EMC_TFAW */
1056                         0x00000000, /* EMC_TRPAB */
1057                         0x00000004, /* EMC_TCLKSTABLE */
1058                         0x00000005, /* EMC_TCLKSTOP */
1059                         0x00000638, /* EMC_TREFBW */
1060                         0x00000006, /* EMC_QUSE_EXTRA */
1061                         0x00000020, /* EMC_ODT_WRITE */
1062                         0x00000000, /* EMC_ODT_READ */
1063                         0x0000aa88, /* EMC_FBIO_CFG5 */
1064                         0x002c00a0, /* EMC_CFG_DIG_DLL */
1065                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1066                         0x00064000, /* EMC_DLL_XFORM_DQS4 */
1067                         0x00064000, /* EMC_DLL_XFORM_DQS5 */
1068                         0x00064000, /* EMC_DLL_XFORM_DQS6 */
1069                         0x00064000, /* EMC_DLL_XFORM_DQS7 */
1070                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1071                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1072                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1073                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1074                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1075                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1076                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1077                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1078                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1079                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1080                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
1081                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1082                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1083                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1084                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
1085                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
1086                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1087                         0x00000066, /* EMC_TXDSRVTTGEN */
1088                         0x02000000, /* EMC_FBIO_SPARE */
1089                         0x00000802, /* EMC_CTT_TERM_CTRL */
1090                         0x00020000, /* EMC_ZCAL_INTERVAL */
1091                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1092                         0x000f000f, /* EMC_MRS_WAIT_CNT */
1093                         0x000f000f, /* EMC_MRS_WAIT_CNT2 */
1094                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1095                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1096                         0x00000000, /* EMC_CTT */
1097                         0x00000000, /* EMC_CTT_DURATION */
1098                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
1099                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1100                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1101                         0x01000003, /* MC_EMEM_ARB_CFG */
1102                         0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1103                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1104                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1105                         0x00000004, /* MC_EMEM_ARB_TIMING_RC */
1106                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
1107                         0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
1108                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1109                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1110                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1111                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1112                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1113                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1114                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1115                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
1116                         0x000a0404, /* MC_EMEM_ARB_DA_COVERS */
1117                         0x73840a05, /* MC_EMEM_ARB_MISC0 */
1118                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1119                 },
1120                 {
1121                         0x00000000, /* EMC_CDB_CNTL_1 */
1122                         0x00000004, /* EMC_FBIO_CFG6 */
1123                         0x00000007, /* EMC_QUSE */
1124                         0x00000004, /* EMC_EINPUT */
1125                         0x00000004, /* EMC_EINPUT_DURATION */
1126                         0x00064000, /* EMC_DLL_XFORM_DQS0 */
1127                         0x00000009, /* EMC_QSAFE */
1128                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1129                         0x0000000d, /* EMC_RDV */
1130                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1131                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1132                         0x0007c000, /* EMC_DLL_XFORM_DQ0 */
1133                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
1134                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
1135                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
1136                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1137                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1138                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
1139                         0x00064000, /* EMC_DLL_XFORM_DQS1 */
1140                         0x00064000, /* EMC_DLL_XFORM_DQS2 */
1141                         0x00064000, /* EMC_DLL_XFORM_DQS3 */
1142                         0x0007c000, /* EMC_DLL_XFORM_DQ1 */
1143                         0x0007c000, /* EMC_DLL_XFORM_DQ2 */
1144                         0x0007c000, /* EMC_DLL_XFORM_DQ3 */
1145                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1146                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1147                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1148                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1149                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1150                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1151                 },
1152                 {
1153                         0x00000000, /* EMC_CDB_CNTL_1 */
1154                         0x00000004, /* EMC_FBIO_CFG6 */
1155                         0x00000007, /* EMC_QUSE */
1156                         0x00000004, /* EMC_EINPUT */
1157                         0x00000004, /* EMC_EINPUT_DURATION */
1158                         0x00064000, /* EMC_DLL_XFORM_DQS0 */
1159                         0x00000009, /* EMC_QSAFE */
1160                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1161                         0x0000000d, /* EMC_RDV */
1162                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1163                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1164                         0x0007c000, /* EMC_DLL_XFORM_DQ0 */
1165                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
1166                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
1167                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
1168                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1169                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1170                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
1171                         0x00064000, /* EMC_DLL_XFORM_DQS1 */
1172                         0x00064000, /* EMC_DLL_XFORM_DQS2 */
1173                         0x00064000, /* EMC_DLL_XFORM_DQS3 */
1174                         0x0007c000, /* EMC_DLL_XFORM_DQ1 */
1175                         0x0007c000, /* EMC_DLL_XFORM_DQ2 */
1176                         0x0007c000, /* EMC_DLL_XFORM_DQ3 */
1177                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1178                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1179                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1180                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1181                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1182                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1183                 },
1184                 {
1185                         0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
1186                         0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
1187                         0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
1188                         0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
1189                         0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1190                         0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
1191                         0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
1192                         0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1193                         0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
1194                         0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1195                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1196                 },
1197                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1198                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1199                 0x7320000e, /* EMC_CFG */
1200                 0x80001221, /* Mode Register 0 */
1201                 0x80100003, /* Mode Register 1 */
1202                 0x80200008, /* Mode Register 2 */
1203                 0x00000000, /* Mode Register 4 */
1204                 3420,       /* expected dvfs latency (ns) */
1205         },
1206         {
1207                 0x41,       /* Rev 4.0.3 */
1208                 312000,     /* SDRAM frequency */
1209                 1000,       /* min voltage */
1210                 "pll_c",    /* clock source id */
1211                 0x24000002, /* CLK_SOURCE_EMC */
1212                 99,         /* number of burst_regs */
1213                 30,         /* number of trim_regs (each channel) */
1214                 11,         /* number of up_down_regs */
1215                 {
1216                         0x0000000d, /* EMC_RC */
1217                         0x00000050, /* EMC_RFC */
1218                         0x00000000, /* EMC_RFC_SLR */
1219                         0x00000009, /* EMC_RAS */
1220                         0x00000003, /* EMC_RP */
1221                         0x00000004, /* EMC_R2W */
1222                         0x00000008, /* EMC_W2R */
1223                         0x00000002, /* EMC_R2P */
1224                         0x00000009, /* EMC_W2P */
1225                         0x00000003, /* EMC_RD_RCD */
1226                         0x00000003, /* EMC_WR_RCD */
1227                         0x00000002, /* EMC_RRD */
1228                         0x00000001, /* EMC_REXT */
1229                         0x00000000, /* EMC_WEXT */
1230                         0x00000004, /* EMC_WDV */
1231                         0x0000000f, /* EMC_WDV_MASK */
1232                         0x00000006, /* EMC_IBDLY */
1233                         0x00010000, /* EMC_PUTERM_EXTRA */
1234                         0x00000000, /* EMC_CDB_CNTL_2 */
1235                         0x00000004, /* EMC_QRST */
1236                         0x0000000f, /* EMC_RDV_MASK */
1237                         0x00000941, /* EMC_REFRESH */
1238                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1239                         0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */
1240                         0x00000001, /* EMC_PDEX2WR */
1241                         0x00000008, /* EMC_PDEX2RD */
1242                         0x00000001, /* EMC_PCHG2PDEN */
1243                         0x00000000, /* EMC_ACT2PDEN */
1244                         0x0000004d, /* EMC_AR2PDEN */
1245                         0x0000000e, /* EMC_RW2PDEN */
1246                         0x00000055, /* EMC_TXSR */
1247                         0x00000200, /* EMC_TXSRDLL */
1248                         0x00000004, /* EMC_TCKE */
1249                         0x00000004, /* EMC_TCKESR */
1250                         0x00000004, /* EMC_TPD */
1251                         0x0000000d, /* EMC_TFAW */
1252                         0x00000000, /* EMC_TRPAB */
1253                         0x00000004, /* EMC_TCLKSTABLE */
1254                         0x00000005, /* EMC_TCLKSTOP */
1255                         0x00000982, /* EMC_TREFBW */
1256                         0x00000000, /* EMC_QUSE_EXTRA */
1257                         0x00000020, /* EMC_ODT_WRITE */
1258                         0x00000000, /* EMC_ODT_READ */
1259                         0x00005088, /* EMC_FBIO_CFG5 */
1260                         0x002c00a0, /* EMC_CFG_DIG_DLL */
1261                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1262                         0x00030000, /* EMC_DLL_XFORM_DQS4 */
1263                         0x00030000, /* EMC_DLL_XFORM_DQS5 */
1264                         0x00030000, /* EMC_DLL_XFORM_DQS6 */
1265                         0x00030000, /* EMC_DLL_XFORM_DQS7 */
1266                         0x00020000, /* EMC_DLL_XFORM_QUSE4 */
1267                         0x00020000, /* EMC_DLL_XFORM_QUSE5 */
1268                         0x00020000, /* EMC_DLL_XFORM_QUSE6 */
1269                         0x00020000, /* EMC_DLL_XFORM_QUSE7 */
1270                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1271                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1272                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1273                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1274                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1275                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1276                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
1277                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1278                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1279                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1280                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
1281                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1282                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1283                         0x0000009c, /* EMC_TXDSRVTTGEN */
1284                         0x02000000, /* EMC_FBIO_SPARE */
1285                         0x00000802, /* EMC_CTT_TERM_CTRL */
1286                         0x00020000, /* EMC_ZCAL_INTERVAL */
1287                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1288                         0x0171000f, /* EMC_MRS_WAIT_CNT */
1289                         0x0171000f, /* EMC_MRS_WAIT_CNT2 */
1290                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1291                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1292                         0x00000000, /* EMC_CTT */
1293                         0x00000000, /* EMC_CTT_DURATION */
1294                         0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */
1295                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1296                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1297                         0x0b000004, /* MC_EMEM_ARB_CFG */
1298                         0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1299                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1300                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1301                         0x00000007, /* MC_EMEM_ARB_TIMING_RC */
1302                         0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
1303                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1304                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1305                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1306                         0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1307                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1308                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1309                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1310                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1311                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1312                         0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
1313                         0x76e50f08, /* MC_EMEM_ARB_MISC0 */
1314                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1315                 },
1316                 {
1317                         0x00000000, /* EMC_CDB_CNTL_1 */
1318                         0x00000004, /* EMC_FBIO_CFG6 */
1319                         0x00000006, /* EMC_QUSE */
1320                         0x00000005, /* EMC_EINPUT */
1321                         0x00000004, /* EMC_EINPUT_DURATION */
1322                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1323                         0x0000000b, /* EMC_QSAFE */
1324                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
1325                         0x0000000d, /* EMC_RDV */
1326                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1327                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1328                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
1329                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
1330                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
1331                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
1332                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1333                         0x00004000, /* EMC_DLL_XFORM_ADDR1 */
1334                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
1335                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1336                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1337                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1338                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
1339                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
1340                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
1341                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1342                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1343                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1344                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
1345                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
1346                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
1347                 },
1348                 {
1349                         0x00000000, /* EMC_CDB_CNTL_1 */
1350                         0x00000004, /* EMC_FBIO_CFG6 */
1351                         0x00000006, /* EMC_QUSE */
1352                         0x00000005, /* EMC_EINPUT */
1353                         0x00000004, /* EMC_EINPUT_DURATION */
1354                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1355                         0x0000000b, /* EMC_QSAFE */
1356                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
1357                         0x0000000d, /* EMC_RDV */
1358                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1359                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1360                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
1361                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
1362                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
1363                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
1364                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1365                         0x00004000, /* EMC_DLL_XFORM_ADDR1 */
1366                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
1367                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1368                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1369                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1370                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
1371                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
1372                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
1373                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1374                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1375                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1376                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
1377                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
1378                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
1379                 },
1380                 {
1381                         0x00000140, /* MC_PTSA_GRANT_DECREMENT */
1382                         0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
1383                         0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
1384                         0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
1385                         0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1386                         0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
1387                         0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
1388                         0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1389                         0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
1390                         0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1391                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1392                 },
1393                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1394                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1395                 0x5300000e, /* EMC_CFG */
1396                 0x80000321, /* Mode Register 0 */
1397                 0x80100002, /* Mode Register 1 */
1398                 0x80200000, /* Mode Register 2 */
1399                 0x00000000, /* Mode Register 4 */
1400                 2680,       /* expected dvfs latency (ns) */
1401         },
1402         {
1403                 0x41,       /* Rev 4.0.3 */
1404                 408000,     /* SDRAM frequency */
1405                 1000,       /* min voltage */
1406                 "pll_p",    /* clock source id */
1407                 0x40000000, /* CLK_SOURCE_EMC */
1408                 99,         /* number of burst_regs */
1409                 30,         /* number of trim_regs (each channel) */
1410                 11,         /* number of up_down_regs */
1411                 {
1412                         0x00000012, /* EMC_RC */
1413                         0x00000069, /* EMC_RFC */
1414                         0x00000000, /* EMC_RFC_SLR */
1415                         0x0000000c, /* EMC_RAS */
1416                         0x00000004, /* EMC_RP */
1417                         0x00000005, /* EMC_R2W */
1418                         0x00000009, /* EMC_W2R */
1419                         0x00000002, /* EMC_R2P */
1420                         0x0000000c, /* EMC_W2P */
1421                         0x00000004, /* EMC_RD_RCD */
1422                         0x00000004, /* EMC_WR_RCD */
1423                         0x00000002, /* EMC_RRD */
1424                         0x00000001, /* EMC_REXT */
1425                         0x00000000, /* EMC_WEXT */
1426                         0x00000004, /* EMC_WDV */
1427                         0x0000000f, /* EMC_WDV_MASK */
1428                         0x00000006, /* EMC_IBDLY */
1429                         0x00010000, /* EMC_PUTERM_EXTRA */
1430                         0x00000000, /* EMC_CDB_CNTL_2 */
1431                         0x00000004, /* EMC_QRST */
1432                         0x00000010, /* EMC_RDV_MASK */
1433                         0x00000c2e, /* EMC_REFRESH */
1434                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1435                         0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
1436                         0x00000001, /* EMC_PDEX2WR */
1437                         0x00000008, /* EMC_PDEX2RD */
1438                         0x00000001, /* EMC_PCHG2PDEN */
1439                         0x00000000, /* EMC_ACT2PDEN */
1440                         0x00000066, /* EMC_AR2PDEN */
1441                         0x00000011, /* EMC_RW2PDEN */
1442                         0x0000006f, /* EMC_TXSR */
1443                         0x00000200, /* EMC_TXSRDLL */
1444                         0x00000004, /* EMC_TCKE */
1445                         0x00000004, /* EMC_TCKESR */
1446                         0x00000004, /* EMC_TPD */
1447                         0x00000011, /* EMC_TFAW */
1448                         0x00000000, /* EMC_TRPAB */
1449                         0x00000004, /* EMC_TCLKSTABLE */
1450                         0x00000005, /* EMC_TCLKSTOP */
1451                         0x00000c6f, /* EMC_TREFBW */
1452                         0x00000000, /* EMC_QUSE_EXTRA */
1453                         0x00000020, /* EMC_ODT_WRITE */
1454                         0x00000000, /* EMC_ODT_READ */
1455                         0x00005088, /* EMC_FBIO_CFG5 */
1456                         0x002c0080, /* EMC_CFG_DIG_DLL */
1457                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1458                         0x00030000, /* EMC_DLL_XFORM_DQS4 */
1459                         0x00030000, /* EMC_DLL_XFORM_DQS5 */
1460                         0x00030000, /* EMC_DLL_XFORM_DQS6 */
1461                         0x00030000, /* EMC_DLL_XFORM_DQS7 */
1462                         0x00020000, /* EMC_DLL_XFORM_QUSE4 */
1463                         0x00020000, /* EMC_DLL_XFORM_QUSE5 */
1464                         0x00020000, /* EMC_DLL_XFORM_QUSE6 */
1465                         0x00020000, /* EMC_DLL_XFORM_QUSE7 */
1466                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1467                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1468                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1469                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1470                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1471                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1472                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
1473                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1474                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1475                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1476                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
1477                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1478                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1479                         0x000000cc, /* EMC_TXDSRVTTGEN */
1480                         0x02000000, /* EMC_FBIO_SPARE */
1481                         0x00000802, /* EMC_CTT_TERM_CTRL */
1482                         0x00020000, /* EMC_ZCAL_INTERVAL */
1483                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1484                         0x0158000f, /* EMC_MRS_WAIT_CNT */
1485                         0x0158000f, /* EMC_MRS_WAIT_CNT2 */
1486                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1487                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1488                         0x00000000, /* EMC_CTT */
1489                         0x00000000, /* EMC_CTT_DURATION */
1490                         0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
1491                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1492                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1493                         0x02000006, /* MC_EMEM_ARB_CFG */
1494                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1495                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1496                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1497                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
1498                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
1499                         0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
1500                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1501                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1502                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1503                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1504                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1505                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1506                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1507                         0x06040202, /* MC_EMEM_ARB_DA_TURNS */
1508                         0x000e0709, /* MC_EMEM_ARB_DA_COVERS */
1509                         0x7547130a, /* MC_EMEM_ARB_MISC0 */
1510                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1511                 },
1512                 {
1513                         0x00000000, /* EMC_CDB_CNTL_1 */
1514                         0x00000004, /* EMC_FBIO_CFG6 */
1515                         0x00000006, /* EMC_QUSE */
1516                         0x00000005, /* EMC_EINPUT */
1517                         0x00000004, /* EMC_EINPUT_DURATION */
1518                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1519                         0x0000000c, /* EMC_QSAFE */
1520                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
1521                         0x0000000e, /* EMC_RDV */
1522                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1523                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1524                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
1525                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
1526                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
1527                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1528                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1529                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1530                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
1531                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1532                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1533                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1534                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
1535                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
1536                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
1537                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1538                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1539                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1540                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1541                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1542                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1543                 },
1544                 {
1545                         0x00000000, /* EMC_CDB_CNTL_1 */
1546                         0x00000004, /* EMC_FBIO_CFG6 */
1547                         0x00000006, /* EMC_QUSE */
1548                         0x00000005, /* EMC_EINPUT */
1549                         0x00000004, /* EMC_EINPUT_DURATION */
1550                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1551                         0x0000000c, /* EMC_QSAFE */
1552                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1553                         0x0000000e, /* EMC_RDV */
1554                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1555                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1556                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
1557                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
1558                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
1559                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1560                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1561                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1562                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
1563                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1564                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1565                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1566                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
1567                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
1568                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
1569                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1570                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1571                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1572                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
1573                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
1574                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
1575                 },
1576                 {
1577                         0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
1578                         0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
1579                         0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
1580                         0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
1581                         0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1582                         0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
1583                         0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
1584                         0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1585                         0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
1586                         0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1587                         0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1588                 },
1589                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1590                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1591                 0x53000006, /* EMC_CFG */
1592                 0x80000731, /* Mode Register 0 */
1593                 0x80100002, /* Mode Register 1 */
1594                 0x80200008, /* Mode Register 2 */
1595                 0x00000000, /* Mode Register 4 */
1596                 1750,       /* expected dvfs latency (ns) */
1597         },
1598         {
1599                 0x41,       /* Rev 4.0.3 */
1600                 450000,     /* SDRAM frequency */
1601                 1100,       /* min voltage */
1602                 "pll_m",    /* clock source id */
1603                 0x00000002, /* CLK_SOURCE_EMC */
1604                 99,         /* number of burst_regs */
1605                 30,         /* number of trim_regs (each channel) */
1606                 11,         /* number of up_down_regs */
1607                 {
1608                         0x00000014, /* EMC_RC */
1609                         0x00000073, /* EMC_RFC */
1610                         0x00000000, /* EMC_RFC_SLR */
1611                         0x0000000e, /* EMC_RAS */
1612                         0x00000005, /* EMC_RP */
1613                         0x00000006, /* EMC_R2W */
1614                         0x00000009, /* EMC_W2R */
1615                         0x00000002, /* EMC_R2P */
1616                         0x0000000c, /* EMC_W2P */
1617                         0x00000005, /* EMC_RD_RCD */
1618                         0x00000005, /* EMC_WR_RCD */
1619                         0x00000002, /* EMC_RRD */
1620                         0x00000001, /* EMC_REXT */
1621                         0x00000000, /* EMC_WEXT */
1622                         0x00000004, /* EMC_WDV */
1623                         0x0000000f, /* EMC_WDV_MASK */
1624                         0x00000007, /* EMC_IBDLY */
1625                         0x00010000, /* EMC_PUTERM_EXTRA */
1626                         0x00000000, /* EMC_CDB_CNTL_2 */
1627                         0x00000005, /* EMC_QRST */
1628                         0x00000011, /* EMC_RDV_MASK */
1629                         0x00000d76, /* EMC_REFRESH */
1630                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1631                         0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
1632                         0x00000001, /* EMC_PDEX2WR */
1633                         0x00000009, /* EMC_PDEX2RD */
1634                         0x00000001, /* EMC_PCHG2PDEN */
1635                         0x00000000, /* EMC_ACT2PDEN */
1636                         0x00000071, /* EMC_AR2PDEN */
1637                         0x00000011, /* EMC_RW2PDEN */
1638                         0x0000007a, /* EMC_TXSR */
1639                         0x00000200, /* EMC_TXSRDLL */
1640                         0x00000004, /* EMC_TCKE */
1641                         0x00000004, /* EMC_TCKESR */
1642                         0x00000004, /* EMC_TPD */
1643                         0x00000012, /* EMC_TFAW */
1644                         0x00000000, /* EMC_TRPAB */
1645                         0x00000004, /* EMC_TCLKSTABLE */
1646                         0x00000005, /* EMC_TCLKSTOP */
1647                         0x00000db6, /* EMC_TREFBW */
1648                         0x00000000, /* EMC_QUSE_EXTRA */
1649                         0x00000020, /* EMC_ODT_WRITE */
1650                         0x00000000, /* EMC_ODT_READ */
1651                         0x00005088, /* EMC_FBIO_CFG5 */
1652                         0x002c0080, /* EMC_CFG_DIG_DLL */
1653                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1654                         0x00030000, /* EMC_DLL_XFORM_DQS4 */
1655                         0x00030000, /* EMC_DLL_XFORM_DQS5 */
1656                         0x00030000, /* EMC_DLL_XFORM_DQS6 */
1657                         0x00030000, /* EMC_DLL_XFORM_DQS7 */
1658                         0x00020000, /* EMC_DLL_XFORM_QUSE4 */
1659                         0x00020000, /* EMC_DLL_XFORM_QUSE5 */
1660                         0x00020000, /* EMC_DLL_XFORM_QUSE6 */
1661                         0x00020000, /* EMC_DLL_XFORM_QUSE7 */
1662                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1663                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1664                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1665                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1666                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1667                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1668                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
1669                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1670                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1671                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1672                         0x03037504, /* EMC_XM2VTTGENPADCTRL */
1673                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1674                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1675                         0x000000e1, /* EMC_TXDSRVTTGEN */
1676                         0x02000000, /* EMC_FBIO_SPARE */
1677                         0x00000802, /* EMC_CTT_TERM_CTRL */
1678                         0x00020000, /* EMC_ZCAL_INTERVAL */
1679                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1680                         0x014d000f, /* EMC_MRS_WAIT_CNT */
1681                         0x014d000f, /* EMC_MRS_WAIT_CNT2 */
1682                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1683                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1684                         0x00000000, /* EMC_CTT */
1685                         0x00000000, /* EMC_CTT_DURATION */
1686                         0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
1687                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1688                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1689                         0x0c000006, /* MC_EMEM_ARB_CFG */
1690                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1691                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1692                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1693                         0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
1694                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1695                         0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
1696                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1697                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1698                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1699                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1700                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1701                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
1702                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1703                         0x06050202, /* MC_EMEM_ARB_DA_TURNS */
1704                         0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
1705                         0x74c7150c, /* MC_EMEM_ARB_MISC0 */
1706                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1707                 },
1708                 {
1709                         0x00000000, /* EMC_CDB_CNTL_1 */
1710                         0x00000004, /* EMC_FBIO_CFG6 */
1711                         0x00000007, /* EMC_QUSE */
1712                         0x00000006, /* EMC_EINPUT */
1713                         0x00000004, /* EMC_EINPUT_DURATION */
1714                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1715                         0x0000000c, /* EMC_QSAFE */
1716                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
1717                         0x0000000f, /* EMC_RDV */
1718                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1719                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1720                         0x00034000, /* EMC_DLL_XFORM_DQ0 */
1721                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
1722                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
1723                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1724                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1725                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1726                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
1727                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1728                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1729                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1730                         0x00034000, /* EMC_DLL_XFORM_DQ1 */
1731                         0x00034000, /* EMC_DLL_XFORM_DQ2 */
1732                         0x00034000, /* EMC_DLL_XFORM_DQ3 */
1733                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1734                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1735                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1736                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
1737                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
1738                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
1739                 },
1740                 {
1741                         0x00000000, /* EMC_CDB_CNTL_1 */
1742                         0x00000004, /* EMC_FBIO_CFG6 */
1743                         0x00000007, /* EMC_QUSE */
1744                         0x00000006, /* EMC_EINPUT */
1745                         0x00000004, /* EMC_EINPUT_DURATION */
1746                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1747                         0x0000000c, /* EMC_QSAFE */
1748                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
1749                         0x0000000f, /* EMC_RDV */
1750                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1751                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1752                         0x00034000, /* EMC_DLL_XFORM_DQ0 */
1753                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
1754                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
1755                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1756                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1757                         0x00004000, /* EMC_DLL_XFORM_ADDR1 */
1758                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
1759                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1760                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1761                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1762                         0x00034000, /* EMC_DLL_XFORM_DQ1 */
1763                         0x00034000, /* EMC_DLL_XFORM_DQ2 */
1764                         0x00034000, /* EMC_DLL_XFORM_DQ3 */
1765                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1766                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1767                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1768                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
1769                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
1770                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
1771                 },
1772                 {
1773                         0x000000e6, /* MC_PTSA_GRANT_DECREMENT */
1774                         0x00100010, /* MC_LATENCY_ALLOWANCE_G2_0 */
1775                         0x00100011, /* MC_LATENCY_ALLOWANCE_G2_1 */
1776                         0x00130015, /* MC_LATENCY_ALLOWANCE_NV_0 */
1777                         0x00000015, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1778                         0x00150015, /* MC_LATENCY_ALLOWANCE_NV_2 */
1779                         0x001c0015, /* MC_LATENCY_ALLOWANCE_NV_1 */
1780                         0x0000001c, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1781                         0x001c001c, /* MC_LATENCY_ALLOWANCE_NV3 */
1782                         0x00c0005a, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1783                         0x00c000c0, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1784                 },
1785                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1786                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1787                 0x53000006, /* EMC_CFG */
1788                 0x80000741, /* Mode Register 0 */
1789                 0x80100002, /* Mode Register 1 */
1790                 0x80200008, /* Mode Register 2 */
1791                 0x00000000, /* Mode Register 4 */
1792                 1750,       /* expected dvfs latency (ns) */
1793         },
1794         {
1795                 0x41,       /* Rev 4.0.3 */
1796                 528000,     /* SDRAM frequency */
1797                 1100,       /* min voltage */
1798                 "pll_m",    /* clock source id */
1799                 0x80000000, /* CLK_SOURCE_EMC */
1800                 99,         /* number of burst_regs */
1801                 30,         /* number of trim_regs (each channel) */
1802                 11,         /* number of up_down_regs */
1803                 {
1804                         0x00000018, /* EMC_RC */
1805                         0x00000088, /* EMC_RFC */
1806                         0x00000000, /* EMC_RFC_SLR */
1807                         0x00000010, /* EMC_RAS */
1808                         0x00000006, /* EMC_RP */
1809                         0x00000006, /* EMC_R2W */
1810                         0x00000009, /* EMC_W2R */
1811                         0x00000002, /* EMC_R2P */
1812                         0x0000000d, /* EMC_W2P */
1813                         0x00000006, /* EMC_RD_RCD */
1814                         0x00000006, /* EMC_WR_RCD */
1815                         0x00000002, /* EMC_RRD */
1816                         0x00000001, /* EMC_REXT */
1817                         0x00000000, /* EMC_WEXT */
1818                         0x00000005, /* EMC_WDV */
1819                         0x0000000f, /* EMC_WDV_MASK */
1820                         0x00000009, /* EMC_IBDLY */
1821                         0x00010000, /* EMC_PUTERM_EXTRA */
1822                         0x00000000, /* EMC_CDB_CNTL_2 */
1823                         0x00000006, /* EMC_QRST */
1824                         0x00000012, /* EMC_RDV_MASK */
1825                         0x00000fd6, /* EMC_REFRESH */
1826                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1827                         0x000003f5, /* EMC_PRE_REFRESH_REQ_CNT */
1828                         0x00000002, /* EMC_PDEX2WR */
1829                         0x0000000b, /* EMC_PDEX2RD */
1830                         0x00000001, /* EMC_PCHG2PDEN */
1831                         0x00000000, /* EMC_ACT2PDEN */
1832                         0x00000084, /* EMC_AR2PDEN */
1833                         0x00000012, /* EMC_RW2PDEN */
1834                         0x0000008f, /* EMC_TXSR */
1835                         0x00000200, /* EMC_TXSRDLL */
1836                         0x00000004, /* EMC_TCKE */
1837                         0x00000004, /* EMC_TCKESR */
1838                         0x00000004, /* EMC_TPD */
1839                         0x00000016, /* EMC_TFAW */
1840                         0x00000000, /* EMC_TRPAB */
1841                         0x00000005, /* EMC_TCLKSTABLE */
1842                         0x00000006, /* EMC_TCLKSTOP */
1843                         0x00001017, /* EMC_TREFBW */
1844                         0x00000000, /* EMC_QUSE_EXTRA */
1845                         0x00000020, /* EMC_ODT_WRITE */
1846                         0x00000000, /* EMC_ODT_READ */
1847                         0x00005088, /* EMC_FBIO_CFG5 */
1848                         0xf0120091, /* EMC_CFG_DIG_DLL */
1849                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1850                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1851                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1852                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1853                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1854                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1855                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1856                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1857                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1858                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1859                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1860                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1861                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1862                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1863                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1864                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
1865                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1866                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1867                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1868                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
1869                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1870                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1871                         0x00000108, /* EMC_TXDSRVTTGEN */
1872                         0x02000000, /* EMC_FBIO_SPARE */
1873                         0x00000802, /* EMC_CTT_TERM_CTRL */
1874                         0x00020000, /* EMC_ZCAL_INTERVAL */
1875                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1876                         0x013a000f, /* EMC_MRS_WAIT_CNT */
1877                         0x013a000f, /* EMC_MRS_WAIT_CNT2 */
1878                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1879                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1880                         0x00000000, /* EMC_CTT */
1881                         0x00000000, /* EMC_CTT_DURATION */
1882                         0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
1883                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1884                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1885                         0x0f000007, /* MC_EMEM_ARB_CFG */
1886                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1887                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1888                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1889                         0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
1890                         0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
1891                         0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
1892                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1893                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1894                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1895                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1896                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1897                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
1898                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1899                         0x06050202, /* MC_EMEM_ARB_DA_TURNS */
1900                         0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
1901                         0x7428180d, /* MC_EMEM_ARB_MISC0 */
1902                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1903                 },
1904                 {
1905                         0x00000000, /* EMC_CDB_CNTL_1 */
1906                         0x00000006, /* EMC_FBIO_CFG6 */
1907                         0x00000008, /* EMC_QUSE */
1908                         0x00000007, /* EMC_EINPUT */
1909                         0x00000004, /* EMC_EINPUT_DURATION */
1910                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1911                         0x0000000c, /* EMC_QSAFE */
1912                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1913                         0x00000010, /* EMC_RDV */
1914                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1915                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1916                         0x0000000b, /* EMC_DLL_XFORM_DQ0 */
1917                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
1918                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
1919                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1920                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1921                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1922                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
1923                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1924                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1925                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1926                         0x0000000b, /* EMC_DLL_XFORM_DQ1 */
1927                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
1928                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
1929                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1930                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1931                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1932                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1933                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1934                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1935                 },
1936                 {
1937                         0x00000000, /* EMC_CDB_CNTL_1 */
1938                         0x00000006, /* EMC_FBIO_CFG6 */
1939                         0x00000008, /* EMC_QUSE */
1940                         0x00000007, /* EMC_EINPUT */
1941                         0x00000004, /* EMC_EINPUT_DURATION */
1942                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1943                         0x0000000c, /* EMC_QSAFE */
1944                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1945                         0x00000010, /* EMC_RDV */
1946                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
1947                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1948                         0x0000000b, /* EMC_DLL_XFORM_DQ0 */
1949                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
1950                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
1951                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1952                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1953                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1954                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
1955                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1956                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1957                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1958                         0x0000000b, /* EMC_DLL_XFORM_DQ1 */
1959                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
1960                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
1961                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1962                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1963                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1964                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1965                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1966                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1967                 },
1968                 {
1969                         0x0000010e, /* MC_PTSA_GRANT_DECREMENT */
1970                         0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */
1971                         0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
1972                         0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */
1973                         0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1974                         0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */
1975                         0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */
1976                         0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1977                         0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */
1978                         0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1979                         0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1980                 },
1981                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1982                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1983                 0x53000004, /* EMC_CFG */
1984                 0x80000941, /* Mode Register 0 */
1985                 0x80100002, /* Mode Register 1 */
1986                 0x80200008, /* Mode Register 2 */
1987                 0x00000000, /* Mode Register 4 */
1988                 1440,       /* expected dvfs latency (ns) */
1989         },
1990         {
1991                 0x41,       /* Rev 4.0.3 */
1992                 624000,     /* SDRAM frequency */
1993                 1100,       /* min voltage */
1994                 "pll_c",    /* clock source id */
1995                 0x24000000, /* CLK_SOURCE_EMC */
1996                 99,         /* number of burst_regs */
1997                 30,         /* number of trim_regs (each channel) */
1998                 11,         /* number of up_down_regs */
1999                 {
2000                         0x0000001c, /* EMC_RC */
2001                         0x000000a1, /* EMC_RFC */
2002                         0x00000000, /* EMC_RFC_SLR */
2003                         0x00000014, /* EMC_RAS */
2004                         0x00000007, /* EMC_RP */
2005                         0x00000007, /* EMC_R2W */
2006                         0x0000000b, /* EMC_W2R */
2007                         0x00000003, /* EMC_R2P */
2008                         0x00000010, /* EMC_W2P */
2009                         0x00000007, /* EMC_RD_RCD */
2010                         0x00000007, /* EMC_WR_RCD */
2011                         0x00000002, /* EMC_RRD */
2012                         0x00000001, /* EMC_REXT */
2013                         0x00000000, /* EMC_WEXT */
2014                         0x00000005, /* EMC_WDV */
2015                         0x0000000f, /* EMC_WDV_MASK */
2016                         0x0000000a, /* EMC_IBDLY */
2017                         0x00010000, /* EMC_PUTERM_EXTRA */
2018                         0x00000000, /* EMC_CDB_CNTL_2 */
2019                         0x00000007, /* EMC_QRST */
2020                         0x00000014, /* EMC_RDV_MASK */
2021                         0x000012c3, /* EMC_REFRESH */
2022                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2023                         0x000004b0, /* EMC_PRE_REFRESH_REQ_CNT */
2024                         0x00000002, /* EMC_PDEX2WR */
2025                         0x0000000d, /* EMC_PDEX2RD */
2026                         0x00000001, /* EMC_PCHG2PDEN */
2027                         0x00000000, /* EMC_ACT2PDEN */
2028                         0x0000009c, /* EMC_AR2PDEN */
2029                         0x00000015, /* EMC_RW2PDEN */
2030                         0x000000a9, /* EMC_TXSR */
2031                         0x00000200, /* EMC_TXSRDLL */
2032                         0x00000005, /* EMC_TCKE */
2033                         0x00000005, /* EMC_TCKESR */
2034                         0x00000005, /* EMC_TPD */
2035                         0x00000019, /* EMC_TFAW */
2036                         0x00000000, /* EMC_TRPAB */
2037                         0x00000006, /* EMC_TCLKSTABLE */
2038                         0x00000007, /* EMC_TCLKSTOP */
2039                         0x00001304, /* EMC_TREFBW */
2040                         0x00000009, /* EMC_QUSE_EXTRA */
2041                         0x00000020, /* EMC_ODT_WRITE */
2042                         0x00000000, /* EMC_ODT_READ */
2043                         0x0000ba88, /* EMC_FBIO_CFG5 */
2044                         0xf00d0191, /* EMC_CFG_DIG_DLL */
2045                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2046                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
2047                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
2048                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
2049                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
2050                         0x00020000, /* EMC_DLL_XFORM_QUSE4 */
2051                         0x00020000, /* EMC_DLL_XFORM_QUSE5 */
2052                         0x00020000, /* EMC_DLL_XFORM_QUSE6 */
2053                         0x00020000, /* EMC_DLL_XFORM_QUSE7 */
2054                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2055                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2056                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2057                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2058                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2059                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2060                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
2061                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2062                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2063                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2064                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
2065                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2066                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2067                         0x00000138, /* EMC_TXDSRVTTGEN */
2068                         0x02000000, /* EMC_FBIO_SPARE */
2069                         0x00000802, /* EMC_CTT_TERM_CTRL */
2070                         0x00020000, /* EMC_ZCAL_INTERVAL */
2071                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2072                         0x0122000f, /* EMC_MRS_WAIT_CNT */
2073                         0x0122000f, /* EMC_MRS_WAIT_CNT2 */
2074                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2075                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2076                         0x00000000, /* EMC_CTT */
2077                         0x00000000, /* EMC_CTT_DURATION */
2078                         0x80002617, /* EMC_DYN_SELF_REF_CONTROL */
2079                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2080                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2081                         0x06000009, /* MC_EMEM_ARB_CFG */
2082                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2083                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
2084                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
2085                         0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
2086                         0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
2087                         0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
2088                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2089                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2090                         0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2091                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2092                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2093                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
2094                         0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
2095                         0x07050202, /* MC_EMEM_ARB_DA_TURNS */
2096                         0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
2097                         0x736a1d10, /* MC_EMEM_ARB_MISC0 */
2098                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2099                 },
2100                 {
2101                         0x00000000, /* EMC_CDB_CNTL_1 */
2102                         0x00000006, /* EMC_FBIO_CFG6 */
2103                         0x00000009, /* EMC_QUSE */
2104                         0x00000008, /* EMC_EINPUT */
2105                         0x00000004, /* EMC_EINPUT_DURATION */
2106                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
2107                         0x0000000c, /* EMC_QSAFE */
2108                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
2109                         0x00000012, /* EMC_RDV */
2110                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2111                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2112                         0x0000000b, /* EMC_DLL_XFORM_DQ0 */
2113                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
2114                         0x00000001, /* EMC_DLL_XFORM_ADDR0 */
2115                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
2116                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2117                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2118                         0x00000001, /* EMC_DLL_XFORM_ADDR2 */
2119                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2120                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2121                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2122                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2123                         0x0000000b, /* EMC_DLL_XFORM_DQ2 */
2124                         0x0000000b, /* EMC_DLL_XFORM_DQ3 */
2125                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2126                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2127                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2128                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
2129                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
2130                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
2131                 },
2132                 {
2133                         0x00000000, /* EMC_CDB_CNTL_1 */
2134                         0x00000006, /* EMC_FBIO_CFG6 */
2135                         0x00000009, /* EMC_QUSE */
2136                         0x00000008, /* EMC_EINPUT */
2137                         0x00000004, /* EMC_EINPUT_DURATION */
2138                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
2139                         0x0000000c, /* EMC_QSAFE */
2140                         0x00020000, /* EMC_DLL_XFORM_QUSE0 */
2141                         0x00000012, /* EMC_RDV */
2142                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2143                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2144                         0x0000000b, /* EMC_DLL_XFORM_DQ0 */
2145                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
2146                         0x00000001, /* EMC_DLL_XFORM_ADDR0 */
2147                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
2148                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2149                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2150                         0x00000001, /* EMC_DLL_XFORM_ADDR2 */
2151                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2152                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2153                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2154                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2155                         0x0000000b, /* EMC_DLL_XFORM_DQ2 */
2156                         0x0000000b, /* EMC_DLL_XFORM_DQ3 */
2157                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2158                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2159                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2160                         0x00020000, /* EMC_DLL_XFORM_QUSE1 */
2161                         0x00020000, /* EMC_DLL_XFORM_QUSE2 */
2162                         0x00020000, /* EMC_DLL_XFORM_QUSE3 */
2163                 },
2164                 {
2165                         0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
2166                         0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
2167                         0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
2168                         0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
2169                         0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2170                         0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
2171                         0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
2172                         0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2173                         0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
2174                         0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2175                         0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2176                 },
2177                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2178                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2179                 0x53000000, /* EMC_CFG */
2180                 0x80000b61, /* Mode Register 0 */
2181                 0x80100002, /* Mode Register 1 */
2182                 0x80200010, /* Mode Register 2 */
2183                 0x00000000, /* Mode Register 4 */
2184                 1440,       /* expected dvfs latency (ns) */
2185         },
2186         {
2187                 0x41,       /* Rev 4.0.3 */
2188                 792000,     /* SDRAM frequency */
2189                 1100,       /* min voltage */
2190                 "pll_m",    /* clock source id */
2191                 0x80000000, /* CLK_SOURCE_EMC */
2192                 99,         /* number of burst_regs */
2193                 30,         /* number of trim_regs (each channel) */
2194                 11,         /* number of up_down_regs */
2195                 {
2196                         0x00000024, /* EMC_RC */
2197                         0x000000cc, /* EMC_RFC */
2198                         0x00000000, /* EMC_RFC_SLR */
2199                         0x00000019, /* EMC_RAS */
2200                         0x0000000a, /* EMC_RP */
2201                         0x00000008, /* EMC_R2W */
2202                         0x0000000d, /* EMC_W2R */
2203                         0x00000004, /* EMC_R2P */
2204                         0x00000013, /* EMC_W2P */
2205                         0x0000000a, /* EMC_RD_RCD */
2206                         0x0000000a, /* EMC_WR_RCD */
2207                         0x00000003, /* EMC_RRD */
2208                         0x00000001, /* EMC_REXT */
2209                         0x00000000, /* EMC_WEXT */
2210                         0x00000006, /* EMC_WDV */
2211                         0x0000000f, /* EMC_WDV_MASK */
2212                         0x0000000b, /* EMC_IBDLY */
2213                         0x00010000, /* EMC_PUTERM_EXTRA */
2214                         0x00000000, /* EMC_CDB_CNTL_2 */
2215                         0x00000008, /* EMC_QRST */
2216                         0x00000016, /* EMC_RDV_MASK */
2217                         0x000017e1, /* EMC_REFRESH */
2218                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2219                         0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
2220                         0x00000003, /* EMC_PDEX2WR */
2221                         0x00000011, /* EMC_PDEX2RD */
2222                         0x00000001, /* EMC_PCHG2PDEN */
2223                         0x00000000, /* EMC_ACT2PDEN */
2224                         0x000000c6, /* EMC_AR2PDEN */
2225                         0x00000018, /* EMC_RW2PDEN */
2226                         0x000000d6, /* EMC_TXSR */
2227                         0x00000200, /* EMC_TXSRDLL */
2228                         0x00000005, /* EMC_TCKE */
2229                         0x00000005, /* EMC_TCKESR */
2230                         0x00000005, /* EMC_TPD */
2231                         0x00000020, /* EMC_TFAW */
2232                         0x00000000, /* EMC_TRPAB */
2233                         0x00000007, /* EMC_TCLKSTABLE */
2234                         0x00000008, /* EMC_TCLKSTOP */
2235                         0x00001822, /* EMC_TREFBW */
2236                         0x00000000, /* EMC_QUSE_EXTRA */
2237                         0x80000000, /* EMC_ODT_WRITE */
2238                         0x00000000, /* EMC_ODT_READ */
2239                         0x00005088, /* EMC_FBIO_CFG5 */
2240                         0xf0070191, /* EMC_CFG_DIG_DLL */
2241                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2242                         0x00000007, /* EMC_DLL_XFORM_DQS4 */
2243                         0x00000007, /* EMC_DLL_XFORM_DQS5 */
2244                         0x00000007, /* EMC_DLL_XFORM_DQS6 */
2245                         0x00000007, /* EMC_DLL_XFORM_DQS7 */
2246                         0x00008000, /* EMC_DLL_XFORM_QUSE4 */
2247                         0x00008000, /* EMC_DLL_XFORM_QUSE5 */
2248                         0x00008000, /* EMC_DLL_XFORM_QUSE6 */
2249                         0x00008000, /* EMC_DLL_XFORM_QUSE7 */
2250                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2251                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2252                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2253                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2254                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2255                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2256                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
2257                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2258                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2259                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2260                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
2261                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2262                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2263                         0x0000018c, /* EMC_TXDSRVTTGEN */
2264                         0x02000000, /* EMC_FBIO_SPARE */
2265                         0x00000802, /* EMC_CTT_TERM_CTRL */
2266                         0x00020000, /* EMC_ZCAL_INTERVAL */
2267                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2268                         0x00f8000f, /* EMC_MRS_WAIT_CNT */
2269                         0x00f8000f, /* EMC_MRS_WAIT_CNT2 */
2270                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2271                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2272                         0x00000000, /* EMC_CTT */
2273                         0x00000000, /* EMC_CTT_DURATION */
2274                         0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
2275                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2276                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2277                         0x0e00000b, /* MC_EMEM_ARB_CFG */
2278                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2279                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
2280                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
2281                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
2282                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
2283                         0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
2284                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2285                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2286                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2287                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2288                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2289                         0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
2290                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2291                         0x08060202, /* MC_EMEM_ARB_DA_TURNS */
2292                         0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
2293                         0x734c2414, /* MC_EMEM_ARB_MISC0 */
2294                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2295                 },
2296                 {
2297                         0x00000000, /* EMC_CDB_CNTL_1 */
2298                         0x00000006, /* EMC_FBIO_CFG6 */
2299                         0x0000000a, /* EMC_QUSE */
2300                         0x00000008, /* EMC_EINPUT */
2301                         0x00000006, /* EMC_EINPUT_DURATION */
2302                         0x00000007, /* EMC_DLL_XFORM_DQS0 */
2303                         0x0000000d, /* EMC_QSAFE */
2304                         0x00008000, /* EMC_DLL_XFORM_QUSE0 */
2305                         0x00000014, /* EMC_RDV */
2306                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2307                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2308                         0x0000400a, /* EMC_DLL_XFORM_DQ0 */
2309                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
2310                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
2311                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
2312                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2313                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2314                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
2315                         0x00000007, /* EMC_DLL_XFORM_DQS1 */
2316                         0x00000007, /* EMC_DLL_XFORM_DQS2 */
2317                         0x00000007, /* EMC_DLL_XFORM_DQS3 */
2318                         0x0000400a, /* EMC_DLL_XFORM_DQ1 */
2319                         0x0000400a, /* EMC_DLL_XFORM_DQ2 */
2320                         0x0000400a, /* EMC_DLL_XFORM_DQ3 */
2321                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2322                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2323                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2324                         0x00008000, /* EMC_DLL_XFORM_QUSE1 */
2325                         0x00008000, /* EMC_DLL_XFORM_QUSE2 */
2326                         0x00008000, /* EMC_DLL_XFORM_QUSE3 */
2327                 },
2328                 {
2329                         0x00000000, /* EMC_CDB_CNTL_1 */
2330                         0x00000006, /* EMC_FBIO_CFG6 */
2331                         0x0000000a, /* EMC_QUSE */
2332                         0x00000008, /* EMC_EINPUT */
2333                         0x00000006, /* EMC_EINPUT_DURATION */
2334                         0x00000007, /* EMC_DLL_XFORM_DQS0 */
2335                         0x0000000d, /* EMC_QSAFE */
2336                         0x00008000, /* EMC_DLL_XFORM_QUSE0 */
2337                         0x00000014, /* EMC_RDV */
2338                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2339                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2340                         0x0000400a, /* EMC_DLL_XFORM_DQ0 */
2341                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
2342                         0x00004000, /* EMC_DLL_XFORM_ADDR0 */
2343                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
2344                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2345                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2346                         0x00004000, /* EMC_DLL_XFORM_ADDR2 */
2347                         0x00000007, /* EMC_DLL_XFORM_DQS1 */
2348                         0x00000007, /* EMC_DLL_XFORM_DQS2 */
2349                         0x00000007, /* EMC_DLL_XFORM_DQS3 */
2350                         0x0000400a, /* EMC_DLL_XFORM_DQ1 */
2351                         0x0000400a, /* EMC_DLL_XFORM_DQ2 */
2352                         0x0000400a, /* EMC_DLL_XFORM_DQ3 */
2353                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2354                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2355                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2356                         0x00008000, /* EMC_DLL_XFORM_QUSE1 */
2357                         0x00008000, /* EMC_DLL_XFORM_QUSE2 */
2358                         0x00008000, /* EMC_DLL_XFORM_QUSE3 */
2359                 },
2360                 {
2361                         0x00000196, /* MC_PTSA_GRANT_DECREMENT */
2362                         0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
2363                         0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
2364                         0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
2365                         0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2366                         0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
2367                         0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
2368                         0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2369                         0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
2370                         0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2371                         0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2372                 },
2373                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2374                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2375                 0x53000000, /* EMC_CFG */
2376                 0x80000d71, /* Mode Register 0 */
2377                 0x80100002, /* Mode Register 1 */
2378                 0x80200418, /* Mode Register 2 */
2379                 0x00000000, /* Mode Register 4 */
2380                 1200,       /* expected dvfs latency (ns) */
2381         },
2382         {
2383                 0x41,       /* Rev 4.0.3 */
2384                 900000,     /* SDRAM frequency */
2385                 1200,       /* min voltage */
2386                 "pll_m",    /* clock source id */
2387                 0x80000000, /* CLK_SOURCE_EMC */
2388                 99,         /* number of burst_regs */
2389                 30,         /* number of trim_regs (each channel) */
2390                 11,         /* number of up_down_regs */
2391                 {
2392                         0x0000002a, /* EMC_RC */
2393                         0x000000e8, /* EMC_RFC */
2394                         0x00000000, /* EMC_RFC_SLR */
2395                         0x0000001d, /* EMC_RAS */
2396                         0x0000000b, /* EMC_RP */
2397                         0x00000008, /* EMC_R2W */
2398                         0x0000000f, /* EMC_W2R */
2399                         0x00000005, /* EMC_R2P */
2400                         0x00000016, /* EMC_W2P */
2401                         0x0000000b, /* EMC_RD_RCD */
2402                         0x0000000b, /* EMC_WR_RCD */
2403                         0x00000004, /* EMC_RRD */
2404                         0x00000001, /* EMC_REXT */
2405                         0x00000000, /* EMC_WEXT */
2406                         0x00000007, /* EMC_WDV */
2407                         0x0000000f, /* EMC_WDV_MASK */
2408                         0x0000000d, /* EMC_IBDLY */
2409                         0x00010000, /* EMC_PUTERM_EXTRA */
2410                         0x00000000, /* EMC_CDB_CNTL_2 */
2411                         0x0000000a, /* EMC_QRST */
2412                         0x00000018, /* EMC_RDV_MASK */
2413                         0x00001b2c, /* EMC_REFRESH */
2414                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2415                         0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
2416                         0x00000004, /* EMC_PDEX2WR */
2417                         0x00000014, /* EMC_PDEX2RD */
2418                         0x00000001, /* EMC_PCHG2PDEN */
2419                         0x00000000, /* EMC_ACT2PDEN */
2420                         0x000000e0, /* EMC_AR2PDEN */
2421                         0x0000001b, /* EMC_RW2PDEN */
2422                         0x000000f3, /* EMC_TXSR */
2423                         0x00000200, /* EMC_TXSRDLL */
2424                         0x00000006, /* EMC_TCKE */
2425                         0x00000006, /* EMC_TCKESR */
2426                         0x00000006, /* EMC_TPD */
2427                         0x00000024, /* EMC_TFAW */
2428                         0x00000000, /* EMC_TRPAB */
2429                         0x00000008, /* EMC_TCLKSTABLE */
2430                         0x00000009, /* EMC_TCLKSTOP */
2431                         0x00001b6c, /* EMC_TREFBW */
2432                         0x00000000, /* EMC_QUSE_EXTRA */
2433                         0x80000000, /* EMC_ODT_WRITE */
2434                         0x00000000, /* EMC_ODT_READ */
2435                         0x00005088, /* EMC_FBIO_CFG5 */
2436                         0xf0040191, /* EMC_CFG_DIG_DLL */
2437                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2438                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
2439                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
2440                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
2441                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
2442                         0x00018000, /* EMC_DLL_XFORM_QUSE4 */
2443                         0x00018000, /* EMC_DLL_XFORM_QUSE5 */
2444                         0x00018000, /* EMC_DLL_XFORM_QUSE6 */
2445                         0x00018000, /* EMC_DLL_XFORM_QUSE7 */
2446                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2447                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2448                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2449                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2450                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2451                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2452                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
2453                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2454                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2455                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2456                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
2457                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2458                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2459                         0x000001c2, /* EMC_TXDSRVTTGEN */
2460                         0x02000000, /* EMC_FBIO_SPARE */
2461                         0x00000802, /* EMC_CTT_TERM_CTRL */
2462                         0x00020000, /* EMC_ZCAL_INTERVAL */
2463                         0x00000120, /* EMC_ZCAL_WAIT_CNT */
2464                         0x00d6000f, /* EMC_MRS_WAIT_CNT */
2465                         0x00d6000f, /* EMC_MRS_WAIT_CNT2 */
2466                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2467                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2468                         0x00000000, /* EMC_CTT */
2469                         0x00000000, /* EMC_CTT_DURATION */
2470                         0x8000367c, /* EMC_DYN_SELF_REF_CONTROL */
2471                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2472                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2473                         0x0800000d, /* MC_EMEM_ARB_CFG */
2474                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2475                         0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
2476                         0x00000006, /* MC_EMEM_ARB_TIMING_RP */
2477                         0x00000015, /* MC_EMEM_ARB_TIMING_RC */
2478                         0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
2479                         0x00000011, /* MC_EMEM_ARB_TIMING_FAW */
2480                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2481                         0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2482                         0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2483                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2484                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2485                         0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
2486                         0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
2487                         0x09060202, /* MC_EMEM_ARB_DA_TURNS */
2488                         0x001a1015, /* MC_EMEM_ARB_DA_COVERS */
2489                         0x734e2916, /* MC_EMEM_ARB_MISC0 */
2490                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2491                 },
2492                 {
2493                         0x00000000, /* EMC_CDB_CNTL_1 */
2494                         0x00000006, /* EMC_FBIO_CFG6 */
2495                         0x0000000c, /* EMC_QUSE */
2496                         0x0000000a, /* EMC_EINPUT */
2497                         0x00000006, /* EMC_EINPUT_DURATION */
2498                         0x00000009, /* EMC_DLL_XFORM_DQS0 */
2499                         0x0000000d, /* EMC_QSAFE */
2500                         0x00018000, /* EMC_DLL_XFORM_QUSE0 */
2501                         0x00000016, /* EMC_RDV */
2502                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2503                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2504                         0x0000400a, /* EMC_DLL_XFORM_DQ0 */
2505                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
2506                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2507                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
2508                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2509                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2510                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2511                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2512                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2513                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2514                         0x0000400a, /* EMC_DLL_XFORM_DQ1 */
2515                         0x0000400a, /* EMC_DLL_XFORM_DQ2 */
2516                         0x0000400a, /* EMC_DLL_XFORM_DQ3 */
2517                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2518                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2519                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2520                         0x00018000, /* EMC_DLL_XFORM_QUSE1 */
2521                         0x00018000, /* EMC_DLL_XFORM_QUSE2 */
2522                         0x00018000, /* EMC_DLL_XFORM_QUSE3 */
2523                 },
2524                 {
2525                         0x00000000, /* EMC_CDB_CNTL_1 */
2526                         0x00000006, /* EMC_FBIO_CFG6 */
2527                         0x0000000c, /* EMC_QUSE */
2528                         0x0000000a, /* EMC_EINPUT */
2529                         0x00000006, /* EMC_EINPUT_DURATION */
2530                         0x00000009, /* EMC_DLL_XFORM_DQS0 */
2531                         0x0000000d, /* EMC_QSAFE */
2532                         0x00018000, /* EMC_DLL_XFORM_QUSE0 */
2533                         0x00000016, /* EMC_RDV */
2534                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2535                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2536                         0x0000400a, /* EMC_DLL_XFORM_DQ0 */
2537                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
2538                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2539                         0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
2540                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2541                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2542                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2543                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2544                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2545                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2546                         0x0000400a, /* EMC_DLL_XFORM_DQ1 */
2547                         0x0000400a, /* EMC_DLL_XFORM_DQ2 */
2548                         0x0000400a, /* EMC_DLL_XFORM_DQ3 */
2549                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2550                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2551                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2552                         0x00018000, /* EMC_DLL_XFORM_QUSE1 */
2553                         0x00018000, /* EMC_DLL_XFORM_QUSE2 */
2554                         0x00018000, /* EMC_DLL_XFORM_QUSE3 */
2555                 },
2556                 {
2557                         0x000001cd, /* MC_PTSA_GRANT_DECREMENT */
2558                         0x00080008, /* MC_LATENCY_ALLOWANCE_G2_0 */
2559                         0x00080008, /* MC_LATENCY_ALLOWANCE_G2_1 */
2560                         0x0009000a, /* MC_LATENCY_ALLOWANCE_NV_0 */
2561                         0x0000000a, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2562                         0x000a000a, /* MC_LATENCY_ALLOWANCE_NV_2 */
2563                         0x000e000a, /* MC_LATENCY_ALLOWANCE_NV_1 */
2564                         0x0000000e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2565                         0x000e000e, /* MC_LATENCY_ALLOWANCE_NV3 */
2566                         0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2567                         0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2568                 },
2569                 0x0000004a, /* EMC_ZCAL_WAIT_CNT after clock change */
2570                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2571                 0x53000000, /* EMC_CFG */
2572                 0x80000f15, /* Mode Register 0 */
2573                 0x80100002, /* Mode Register 1 */
2574                 0x80200420, /* Mode Register 2 */
2575                 0x00000000, /* Mode Register 4 */
2576                 1200,       /* expected dvfs latency (ns) */
2577         },
2578 };
2579
2580 static struct tegra11_emc_pdata h5tc4g63afr_pba_pdata = {
2581         .description = "h5tc4g63afr_pba",
2582         .tables = h5tc4g63afr_pba_table,
2583         .num_tables = ARRAY_SIZE(h5tc4g63afr_pba_table),
2584 };
2585
2586 static struct tegra11_emc_pdata *roth_get_emc_data(void)
2587 {
2588         return &h5tc4g63afr_pba_pdata;
2589 }
2590
2591 int __init roth_emc_init(void)
2592 {
2593         tegra_emc_device.dev.platform_data = roth_get_emc_data();
2594         platform_device_register(&tegra_emc_device);
2595         tegra11_emc_init();
2596         return 0;
2597 }