arm: tegra: Move all tj dependent thermals from nct to soc_therm
[linux-3.10.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/edp.h>
27 #include <mach/irqs.h>
28 #include <linux/regulator/fixed.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/regulator/machine.h>
31 #include <linux/irq.h>
32
33 #include <asm/mach-types.h>
34
35 #include "cpu-tegra.h"
36 #include "pm.h"
37 #include "board.h"
38 #include "board-common.h"
39 #include "board-pluto.h"
40 #include "iomap.h"
41 #include "tegra_cl_dvfs.h"
42 #include "devices.h"
43 #include "tegra11_soctherm.h"
44
45 #define PMC_CTRL                0x0
46 #define PMC_CTRL_INTR_LOW       (1 << 17)
47
48 /************************ Pluto based regulator ****************/
49 static struct regulator_consumer_supply palmas_smps123_supply[] = {
50         REGULATOR_SUPPLY("vdd_cpu", NULL),
51 };
52
53 static struct regulator_consumer_supply palmas_smps45_supply[] = {
54         REGULATOR_SUPPLY("vdd_core", NULL),
55 };
56
57 static struct regulator_consumer_supply palmas_smps6_supply[] = {
58         REGULATOR_SUPPLY("vdd_core_bb", NULL),
59 };
60
61 static struct regulator_consumer_supply palmas_smps7_supply[] = {
62         REGULATOR_SUPPLY("vddio_ddr", NULL),
63         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
64         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
65         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
66 };
67
68 static struct regulator_consumer_supply palmas_smps8_supply[] = {
69         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
70         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
71         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
72         REGULATOR_SUPPLY("avdd_osc", NULL),
73         REGULATOR_SUPPLY("vddio_sys", NULL),
74         REGULATOR_SUPPLY("vddio_bb", NULL),
75         REGULATOR_SUPPLY("pwrdet_bb", NULL),
76         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
77         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
78         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
79         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
80         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
81         REGULATOR_SUPPLY("vddio_audio", NULL),
82         REGULATOR_SUPPLY("pwrdet_audio", NULL),
83         REGULATOR_SUPPLY("vddio_uart", NULL),
84         REGULATOR_SUPPLY("pwrdet_uart", NULL),
85         REGULATOR_SUPPLY("vddio_gmi", NULL),
86         REGULATOR_SUPPLY("pwrdet_nand", NULL),
87         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
88         REGULATOR_SUPPLY("pwrdet_cam", NULL),
89         REGULATOR_SUPPLY("vdd_gps", NULL),
90         REGULATOR_SUPPLY("vdd_nfc", NULL),
91         REGULATOR_SUPPLY("vlogic", "0-0069"),
92         REGULATOR_SUPPLY("vdd_dtv", NULL),
93         REGULATOR_SUPPLY("vdd_bb", NULL),
94         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
95         REGULATOR_SUPPLY("vcore_lpddr", NULL),
96         REGULATOR_SUPPLY("vddio_lpddr", NULL),
97         REGULATOR_SUPPLY("vdd_rf", NULL),
98         REGULATOR_SUPPLY("vdd_modem2", NULL),
99         REGULATOR_SUPPLY("vdd_dbg", NULL),
100         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
101         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
102         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
103         REGULATOR_SUPPLY("dvdd_audio", NULL),
104         REGULATOR_SUPPLY("avdd_audio", NULL),
105         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
106         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
107         REGULATOR_SUPPLY("dvdd", "spi3.2"),
108         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
109 };
110
111 static struct regulator_consumer_supply palmas_smps9_supply[] = {
112         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
113         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
114         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
115         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
116 };
117
118 static struct regulator_consumer_supply palmas_smps10_supply[] = {
119         REGULATOR_SUPPLY("unused_smps10", NULL),
120         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
121         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
122         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
123         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
124         REGULATOR_SUPPLY("vdd_lcd", NULL),
125 };
126
127 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
128         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
129         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
130         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
131         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
132         REGULATOR_SUPPLY("avdd_pllm", NULL),
133         REGULATOR_SUPPLY("avdd_pllu", NULL),
134         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
135         REGULATOR_SUPPLY("avdd_pllx", NULL),
136         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
137         REGULATOR_SUPPLY("avdd_plle", NULL),
138 };
139
140 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
141         REGULATOR_SUPPLY("avdd_lcd", NULL),
142 };
143
144 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
145         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
146         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
147         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
148         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
149         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
150         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
151         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
152         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
153         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
154 };
155
156 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
157         REGULATOR_SUPPLY("vdd_spare", NULL),
158 };
159
160 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
161         REGULATOR_SUPPLY("avdd_cam1", NULL),
162         REGULATOR_SUPPLY("vana", "2-0010"),
163 };
164
165 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
166         REGULATOR_SUPPLY("vdd_temp", NULL),
167         REGULATOR_SUPPLY("vdd_mb", NULL),
168         REGULATOR_SUPPLY("vin", "1-004d"),
169         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
170         REGULATOR_SUPPLY("vdd_irled", NULL),
171         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
172         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
173         REGULATOR_SUPPLY("vaux_3v3", NULL),
174         REGULATOR_SUPPLY("vdd", "0-0044"),
175         REGULATOR_SUPPLY("vdd", "0-004c"),
176         REGULATOR_SUPPLY("avdd", "spi3.2"),
177         REGULATOR_SUPPLY("vdd", "0-0069"),
178 };
179
180 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
181         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
182         REGULATOR_SUPPLY("vdd", "2-000e"),
183 };
184 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
185         REGULATOR_SUPPLY("vdd_rtc", NULL),
186 };
187 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
188         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
189         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
190 };
191 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
192         REGULATOR_SUPPLY("avdd_cam2", NULL),
193         REGULATOR_SUPPLY("vana", "2-0036"),
194 };
195
196 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
197         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
198         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
199         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
200         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
201         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
202         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
203         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
204         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
205         REGULATOR_SUPPLY("pwrdet_hv", NULL),
206         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
207
208 };
209
210 static struct regulator_consumer_supply palmas_regen1_supply[] = {
211         REGULATOR_SUPPLY("mic_ventral", NULL),
212 };
213
214 static struct regulator_consumer_supply palmas_regen2_supply[] = {
215         REGULATOR_SUPPLY("vdd_mic", NULL),
216 };
217
218 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
219         _boot_on, _apply_uv)                                            \
220         static struct regulator_init_data reg_idata_##_name = {         \
221                 .constraints = {                                        \
222                         .name = palmas_rails(_name),                    \
223                         .min_uV = (_minmv)*1000,                        \
224                         .max_uV = (_maxmv)*1000,                        \
225                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
226                                         REGULATOR_MODE_STANDBY),        \
227                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
228                                         REGULATOR_CHANGE_STATUS |       \
229                                         REGULATOR_CHANGE_VOLTAGE),      \
230                         .always_on = _always_on,                        \
231                         .boot_on = _boot_on,                            \
232                         .apply_uV = _apply_uv,                          \
233                 },                                                      \
234                 .num_consumer_supplies =                                \
235                         ARRAY_SIZE(palmas_##_name##_supply),            \
236                 .consumer_supplies = palmas_##_name##_supply,           \
237                 .supply_regulator = _supply_reg,                        \
238         }
239
240 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
241 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
242 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
243 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
244 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1);
245 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 1, 0, 1);
246 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
247 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
248 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
249 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
250 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
251 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
252 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 1, 1, 1);
253 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
254 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
255 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
256 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
257 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
258 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
259 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
260
261 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
262
263 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
264         NULL,
265         PALMAS_REG_PDATA(smps123),
266         NULL,
267         PALMAS_REG_PDATA(smps45),
268         NULL,
269         PALMAS_REG_PDATA(smps6),
270         PALMAS_REG_PDATA(smps7),
271         PALMAS_REG_PDATA(smps8),
272         PALMAS_REG_PDATA(smps9),
273         PALMAS_REG_PDATA(smps10),
274         PALMAS_REG_PDATA(ldo1),
275         PALMAS_REG_PDATA(ldo2),
276         PALMAS_REG_PDATA(ldo3),
277         PALMAS_REG_PDATA(ldo4),
278         PALMAS_REG_PDATA(ldo5),
279         PALMAS_REG_PDATA(ldo6),
280         PALMAS_REG_PDATA(ldo7),
281         PALMAS_REG_PDATA(ldo8),
282         PALMAS_REG_PDATA(ldo9),
283         PALMAS_REG_PDATA(ldoln),
284         PALMAS_REG_PDATA(ldousb),
285         PALMAS_REG_PDATA(regen1),
286         PALMAS_REG_PDATA(regen2),
287         NULL,
288         NULL,
289         NULL,
290 };
291
292 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
293                 _tstep, _vsel)                                          \
294         static struct palmas_reg_init reg_init_data_##_name = {         \
295                 .warm_reset = _warm_reset,                              \
296                 .roof_floor =   _roof_floor,                            \
297                 .mode_sleep = _mode_sleep,              \
298                 .tstep = _tstep,                        \
299                 .vsel = _vsel,          \
300         }
301
302 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
303 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
304 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
305 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
306 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
307 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
312 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
313 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
314 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
315 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
316 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
317 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
318 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
319 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
320 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
321 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
322 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
323
324 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
325 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
326         PALMAS_REG_INIT_DATA(smps12),
327         PALMAS_REG_INIT_DATA(smps123),
328         PALMAS_REG_INIT_DATA(smps3),
329         PALMAS_REG_INIT_DATA(smps45),
330         PALMAS_REG_INIT_DATA(smps457),
331         PALMAS_REG_INIT_DATA(smps6),
332         PALMAS_REG_INIT_DATA(smps7),
333         PALMAS_REG_INIT_DATA(smps8),
334         PALMAS_REG_INIT_DATA(smps9),
335         PALMAS_REG_INIT_DATA(smps10),
336         PALMAS_REG_INIT_DATA(ldo1),
337         PALMAS_REG_INIT_DATA(ldo2),
338         PALMAS_REG_INIT_DATA(ldo3),
339         PALMAS_REG_INIT_DATA(ldo4),
340         PALMAS_REG_INIT_DATA(ldo5),
341         PALMAS_REG_INIT_DATA(ldo6),
342         PALMAS_REG_INIT_DATA(ldo7),
343         PALMAS_REG_INIT_DATA(ldo8),
344         PALMAS_REG_INIT_DATA(ldo9),
345         PALMAS_REG_INIT_DATA(ldoln),
346         PALMAS_REG_INIT_DATA(ldousb),
347 };
348
349 static int ac_online(void)
350 {
351         return 1;
352 }
353
354 static struct resource pluto_pda_resources[] = {
355         [0] = {
356                 .name   = "ac",
357         },
358 };
359
360 static struct pda_power_pdata pluto_pda_data = {
361         .is_ac_online   = ac_online,
362 };
363
364 static struct platform_device pluto_pda_power_device = {
365         .name           = "pda-power",
366         .id             = -1,
367         .resource       = pluto_pda_resources,
368         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
369         .dev    = {
370                 .platform_data  = &pluto_pda_data,
371         },
372 };
373
374 /* Always ON /Battery regulator */
375 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
376                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
377                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
378                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
379                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
380                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
381 };
382
383 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
384         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
385         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
386         REGULATOR_SUPPLY("vif", "2-0010"),
387         REGULATOR_SUPPLY("vif", "2-0036"),
388         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
389 };
390
391 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
392         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
393         REGULATOR_SUPPLY("vdig", "2-0010"),
394         REGULATOR_SUPPLY("vdig", "2-0036"),
395 };
396
397 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
398         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
399         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
400         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
401 };
402
403 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
404         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
405 };
406
407 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
408         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
409 };
410
411 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
412         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
413 };
414
415 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
416         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
417 };
418
419 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
420         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
421 };
422
423 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
424         REGULATOR_SUPPLY("vpp_fuse", NULL),
425         REGULATOR_SUPPLY("v_efuse", NULL),
426 };
427
428 /* Macro for defining fixed regulator sub device data */
429 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
430 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
431         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
432         _sdelay)                                                        \
433         static struct regulator_init_data ri_data_##_var =              \
434         {                                                               \
435                 .supply_regulator = _in_supply,                         \
436                 .num_consumer_supplies =                                \
437                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
438                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
439                 .constraints = {                                        \
440                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
441                                         REGULATOR_MODE_STANDBY),        \
442                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
443                                         REGULATOR_CHANGE_STATUS |       \
444                                         REGULATOR_CHANGE_VOLTAGE),      \
445                         .always_on = _always_on,                        \
446                         .boot_on = _boot_on,                            \
447                 },                                                      \
448         };                                                              \
449         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
450         {                                                               \
451                 .supply_name = FIXED_SUPPLY(_name),                     \
452                 .microvolts = _millivolts * 1000,                       \
453                 .gpio = _gpio_nr,                                       \
454                 .gpio_is_open_drain = _open_drain,                      \
455                 .enable_high = _active_high,                            \
456                 .enabled_at_boot = _boot_state,                         \
457                 .init_data = &ri_data_##_var,                           \
458                 .startup_delay = _sdelay                                \
459         };                                                              \
460         static struct platform_device fixed_reg_en_##_var##_dev = {     \
461                 .name = "reg-fixed-voltage",                            \
462                 .id = _id,                                              \
463                 .dev = {                                                \
464                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
465                 },                                                      \
466         }
467
468 FIXED_REG(0,    battery,        battery,
469         NULL,   0,      0,
470         -1,     false, true,    0,      3300,   0);
471
472 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
473         palmas_rails(smps8),    0,      0,
474         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
475         0);
476
477 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
478         palmas_rails(smps7),    0,      0,
479         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
480         0);
481
482 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
483         palmas_rails(smps8),    0,      0,
484         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
485
486 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
487         palmas_rails(smps9),    0,      0,
488         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
489
490 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
491         palmas_rails(smps8),    0,      0,
492         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
493         0);
494
495 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
496         palmas_rails(smps9),    0,      0,
497         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
498
499 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
500         palmas_rails(smps8),    0,      0,
501         -1,     false,  true,   0,      1800,   0);
502
503 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
504         NULL,   0,      0,
505         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
506
507 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
508         palmas_rails(smps8),    0,      0,
509         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
510
511 /*
512  * Creating the fixed regulator device tables
513  */
514 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
515
516 #define E1580_COMMON_FIXED_REG                  \
517         ADD_FIXED_REG(battery),                 \
518         ADD_FIXED_REG(vdd_1v8_cam),             \
519         ADD_FIXED_REG(vdd_1v2_cam),             \
520         ADD_FIXED_REG(avdd_usb3_1v05),          \
521         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
522         ADD_FIXED_REG(vdd_lcd_1v8),             \
523         ADD_FIXED_REG(vdd_lcd_mmc),             \
524         ADD_FIXED_REG(vdd_1v8_mic),             \
525         ADD_FIXED_REG(vdd_hdmi_5v0),
526
527 #define E1580_T114_FIXED_REG                    \
528         ADD_FIXED_REG(vpp_fuse),
529
530 /* Gpio switch regulator platform data for Pluto E1580 */
531 static struct platform_device *pfixed_reg_devs[] = {
532         E1580_COMMON_FIXED_REG
533         E1580_T114_FIXED_REG
534 };
535
536 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
537 /* board parameters for cpu dfll */
538 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
539         .sample_rate = 12500,
540
541         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
542         .cf = 10,
543         .ci = 0,
544         .cg = 2,
545
546         .droop_cut_value = 0xF,
547         .droop_restore_ramp = 0x0,
548         .scale_out_ramp = 0x0,
549 };
550 #endif
551
552 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
553 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
554 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
555 static inline void fill_reg_map(void)
556 {
557         int i;
558         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
559                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
560                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
561         }
562 }
563
564 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
565 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
566         .dfll_clk_name = "dfll_cpu",
567         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
568         .u.pmu_i2c = {
569                 .fs_rate = 400000,
570                 .slave_addr = 0xb0,
571                 .reg = 0x23,
572         },
573         .vdd_map = pmu_cpu_vdd_map,
574         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
575
576         .cfg_param = &pluto_cl_dvfs_param,
577 };
578
579 static int __init pluto_cl_dvfs_init(void)
580 {
581         fill_reg_map();
582         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
583         platform_device_register(&tegra_cl_dvfs_device);
584
585         return 0;
586 }
587 #endif
588
589 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
590         {
591                 .en_pwm = false,
592         }, {
593                 .en_pwm = true,
594                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
595                 .reg_id = PALMAS_REG_SMPS6,
596                 .step_20mV = true,
597                 .base_voltage_uV = 500000,
598                 .max_voltage_uV = 1100000,
599         },
600 };
601
602 static struct palmas_pmic_platform_data pmic_platform = {
603         .enable_ldo8_tracking = true,
604         .disabe_ldo8_tracking_suspend = true,
605         .dvfs_init_data = palmas_dvfs_idata,
606         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
607 };
608
609 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
610         {
611                 .clk32k_id = PALMAS_CLOCK32KG,
612                 .enable = true,
613         }, {
614                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
615                 .enable = true,
616         },
617 };
618
619 static struct palmas_platform_data palmas_pdata = {
620         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
621         .irq_base = PALMAS_TEGRA_IRQ_BASE,
622         .pmic_pdata = &pmic_platform,
623         .mux_from_pdata = true,
624         .pad1 = 0,
625         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
626                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
627         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2,
628         .clk32k_init_data =  palmas_clk32k_idata,
629         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
630         .irq_type = IRQ_TYPE_LEVEL_HIGH,
631         .use_power_off = true,
632 };
633
634 static struct i2c_board_info palma_device[] = {
635         {
636                 I2C_BOARD_INFO("tps65913", 0x58),
637                 .irq            = INT_EXTERNAL_PMU,
638                 .platform_data  = &palmas_pdata,
639         },
640 };
641
642 int __init pluto_regulator_init(void)
643 {
644         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
645         u32 pmc_ctrl;
646         int i;
647
648 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
649         pluto_cl_dvfs_init();
650 #endif
651
652         /* TPS65913: Normal state of INT request line is LOW.
653          * configure the power management controller to trigger PMU
654          * interrupts when HIGH.
655          */
656         pmc_ctrl = readl(pmc + PMC_CTRL);
657         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
658
659         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
660                 pmic_platform.reg_data[i] = pluto_reg_data[i];
661                 pmic_platform.reg_init[i] = pluto_reg_init[i];
662         }
663
664         platform_device_register(&pluto_pda_power_device);
665         i2c_register_board_info(4, palma_device,
666                         ARRAY_SIZE(palma_device));
667         return 0;
668 }
669
670 static int __init pluto_fixed_regulator_init(void)
671 {
672         if (!machine_is_tegra_pluto())
673                 return 0;
674
675         return platform_add_devices(pfixed_reg_devs,
676                         ARRAY_SIZE(pfixed_reg_devs));
677 }
678 subsys_initcall_sync(pluto_fixed_regulator_init);
679
680 static struct tegra_suspend_platform_data pluto_suspend_data = {
681         .cpu_timer      = 300,
682         .cpu_off_timer  = 300,
683         .suspend_mode   = TEGRA_SUSPEND_LP0,
684         .core_timer     = 0x157e,
685         .core_off_timer = 2000,
686         .corereq_high   = true,
687         .sysclkreq_high = true,
688         .cpu_lp2_min_residency = 1000,
689         .min_residency_noncpu = 2000,
690         .min_residency_crail = 8000,
691 };
692
693 int __init pluto_suspend_init(void)
694 {
695         tegra_init_suspend(&pluto_suspend_data);
696         return 0;
697 }
698
699 int __init pluto_edp_init(void)
700 {
701         unsigned int regulator_mA;
702
703         regulator_mA = get_maximum_cpu_current_supported();
704         if (!regulator_mA)
705                 regulator_mA = 9000;
706
707         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
708         tegra_init_cpu_edp_limits(regulator_mA);
709
710         regulator_mA = get_maximum_core_current_supported();
711         if (!regulator_mA)
712                 regulator_mA = 4000;
713
714         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
715         tegra_init_core_edp_limits(regulator_mA);
716
717         return 0;
718 }
719
720 static struct soctherm_platform_data pluto_soctherm_data = {
721         .therm = {
722                 [THERM_CPU] = {
723                         .zone_enable = true,
724                         .passive_delay = 1000,
725                         .num_trips = 3,
726                         .trips = {
727                                 {
728                                         .cdev_type = "tegra-balanced",
729                                         .trip_temp = 84000,
730                                         .trip_type = THERMAL_TRIP_PASSIVE,
731                                         .upper = THERMAL_NO_LIMIT,
732                                         .lower = THERMAL_NO_LIMIT,
733                                 },
734                                 {
735                                         .cdev_type = "tegra-heavy",
736                                         .trip_temp = 94000,
737                                         .trip_type = THERMAL_TRIP_HOT,
738                                         .upper = THERMAL_NO_LIMIT,
739                                         .lower = THERMAL_NO_LIMIT,
740                                 },
741                                 {
742                                         .cdev_type = "tegra-shutdown",
743                                         .trip_temp = 104000,
744                                         .trip_type = THERMAL_TRIP_CRITICAL,
745                                         .upper = THERMAL_NO_LIMIT,
746                                         .lower = THERMAL_NO_LIMIT,
747                                 },
748                         },
749                 },
750                 [THERM_GPU] = {
751                         .zone_enable = true,
752                 },
753                 [THERM_PLL] = {
754                         .zone_enable = true,
755                 },
756         },
757         .throttle = {
758                 [THROTTLE_HEAVY] = {
759                         .devs = {
760                                 [THROTTLE_DEV_CPU] = {
761                                         .enable = 1,
762                                 },
763                         },
764                 },
765         },
766 };
767
768 int __init pluto_soctherm_init(void)
769 {
770         tegra_platform_edp_init(pluto_soctherm_data.therm[THERM_CPU].trips,
771                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
772         tegra_add_tj_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
773                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
774
775         return tegra11_soctherm_init(&pluto_soctherm_data);
776 }