ARM: tegra: pcie: Remove dock detect variable
[linux-3.10.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <mach/io_dpd.h>
30 #include <linux/tegra-soc.h>
31 #include <linux/regulator/fixed.h>
32 #include <linux/mfd/palmas.h>
33 #include <linux/regulator/machine.h>
34 #include <linux/irq.h>
35 #include <linux/edp.h>
36 #include <linux/edpdev.h>
37 #include <linux/platform_data/tegra_edp.h>
38 #include <linux/pid_thermal_gov.h>
39
40 #include <asm/mach-types.h>
41
42 #include "cpu-tegra.h"
43 #include "pm.h"
44 #include "board.h"
45 #include "board-common.h"
46 #include "board-pluto.h"
47 #include "board-pmu-defines.h"
48 #include "iomap.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52 #include "tegra3_tsensor.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56 #define PLUTO_4K_REWORKED       0x2
57
58 /************************ Pluto based regulator ****************/
59 static struct regulator_consumer_supply palmas_smps123_supply[] = {
60         REGULATOR_SUPPLY("vdd_cpu", NULL),
61 };
62
63 static struct regulator_consumer_supply palmas_smps45_supply[] = {
64         REGULATOR_SUPPLY("vdd_core", NULL),
65         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
66         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"),
67         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
68 };
69
70 static struct regulator_consumer_supply palmas_smps6_supply[] = {
71         REGULATOR_SUPPLY("vdd_core_bb", NULL),
72 };
73
74 static struct regulator_consumer_supply palmas_smps7_supply[] = {
75         REGULATOR_SUPPLY("vddio_ddr", NULL),
76         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
77         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
78         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
79 };
80
81 static struct regulator_consumer_supply palmas_smps8_supply[] = {
82         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
83         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
84         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
85         REGULATOR_SUPPLY("avdd_osc", NULL),
86         REGULATOR_SUPPLY("vddio_sys", NULL),
87         REGULATOR_SUPPLY("vddio_bb", NULL),
88         REGULATOR_SUPPLY("pwrdet_bb", NULL),
89         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
90         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
91         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
92         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
93         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
94         REGULATOR_SUPPLY("vddio_audio", NULL),
95         REGULATOR_SUPPLY("pwrdet_audio", NULL),
96         REGULATOR_SUPPLY("vddio_uart", NULL),
97         REGULATOR_SUPPLY("pwrdet_uart", NULL),
98         REGULATOR_SUPPLY("vddio_gmi", NULL),
99         REGULATOR_SUPPLY("pwrdet_nand", NULL),
100         REGULATOR_SUPPLY("vddio_cam", "vi"),
101         REGULATOR_SUPPLY("pwrdet_cam", NULL),
102         REGULATOR_SUPPLY("dvdd", "0-0077"),
103         REGULATOR_SUPPLY("vlogic", "0-0069"),
104         REGULATOR_SUPPLY("vid", "0-000d"),
105         REGULATOR_SUPPLY("vddio", "0-0078"),
106         REGULATOR_SUPPLY("vdd_dtv", NULL),
107         REGULATOR_SUPPLY("vdd_bb", NULL),
108         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
109         REGULATOR_SUPPLY("vcore_lpddr", NULL),
110         REGULATOR_SUPPLY("vddio_lpddr", NULL),
111         REGULATOR_SUPPLY("vdd_rf", NULL),
112         REGULATOR_SUPPLY("vdd_modem2", NULL),
113         REGULATOR_SUPPLY("vdd_dbg", NULL),
114         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
115         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
116         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
117         REGULATOR_SUPPLY("dvdd_audio", NULL),
118         REGULATOR_SUPPLY("avdd_audio", NULL),
119         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
120         REGULATOR_SUPPLY("dvdd", "spi3.2"),
121         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
122 };
123
124 static struct regulator_consumer_supply palmas_smps9_supply[] = {
125         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
126         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
127         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
128         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
129 };
130
131 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
132         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
133         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
134         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
135         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
136         REGULATOR_SUPPLY("vdd_lcd", NULL),
137 };
138
139 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
140         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
141         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
142         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
143         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
144         REGULATOR_SUPPLY("avdd_pllm", NULL),
145         REGULATOR_SUPPLY("avdd_pllu", NULL),
146         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
147         REGULATOR_SUPPLY("avdd_pllx", NULL),
148         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
149         REGULATOR_SUPPLY("avdd_plle", NULL),
150 };
151
152 static struct regulator_consumer_supply palmas_ldo1_4K_supply[] = {
153         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
154         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
155         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
156         REGULATOR_SUPPLY("avdd_pllm", NULL),
157         REGULATOR_SUPPLY("avdd_pllu", NULL),
158         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
159         REGULATOR_SUPPLY("avdd_pllx", NULL),
160         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
161         REGULATOR_SUPPLY("avdd_plle", NULL),
162 };
163
164 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
165         REGULATOR_SUPPLY("avdd_lcd", NULL),
166 };
167
168 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
169         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
170         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
171         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
172         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
173         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
174         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
175         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
176         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
177         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
178 };
179
180 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
181         REGULATOR_SUPPLY("vdd_spare", NULL),
182 };
183
184 static struct regulator_consumer_supply palmas_ldo4_4K_supply[] = {
185         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
186         REGULATOR_SUPPLY("vdd_spare", NULL),
187 };
188
189 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
190         REGULATOR_SUPPLY("avdd_cam1", NULL),
191         REGULATOR_SUPPLY("vana", "2-0010"),
192 };
193
194 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
195         REGULATOR_SUPPLY("vdd_temp", NULL),
196         REGULATOR_SUPPLY("vdd_mb", NULL),
197         REGULATOR_SUPPLY("vin", "1-004d"),
198         REGULATOR_SUPPLY("avdd", "0-0077"),
199         REGULATOR_SUPPLY("vdd_irled", NULL),
200         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
201         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
202         REGULATOR_SUPPLY("vaux_3v3", NULL),
203         REGULATOR_SUPPLY("vdd", "0-0044"),
204         REGULATOR_SUPPLY("vdd", "0-004c"),
205         REGULATOR_SUPPLY("avdd", "spi3.2"),
206         REGULATOR_SUPPLY("vdd", "0-0069"),
207         REGULATOR_SUPPLY("vdd", "0-000d"),
208         REGULATOR_SUPPLY("vdd", "0-0078"),
209 };
210
211 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
212         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
213         REGULATOR_SUPPLY("imx132_reg1", NULL),
214         REGULATOR_SUPPLY("imx091_vcm_vdd", NULL),
215         REGULATOR_SUPPLY("vdd", "2-000e"),
216 };
217 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
218         REGULATOR_SUPPLY("vdd_rtc", NULL),
219 };
220 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
221         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
222         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
223 };
224 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
225         REGULATOR_SUPPLY("avdd_cam2", NULL),
226         REGULATOR_SUPPLY("vana", "2-0036"),
227         REGULATOR_SUPPLY("vana_imx132", "2-0036"),
228 };
229
230 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
231         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
232         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
233         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
234         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
235         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
236         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
237         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
238         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
239         REGULATOR_SUPPLY("pwrdet_hv", NULL),
240         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
241
242 };
243
244 static struct regulator_consumer_supply palmas_regen1_supply[] = {
245         REGULATOR_SUPPLY("mic_ventral", NULL),
246 };
247
248 static struct regulator_consumer_supply palmas_regen2_supply[] = {
249         REGULATOR_SUPPLY("vdd_mic", NULL),
250 };
251
252 PALMAS_REGS_PDATA(smps123, 900,  1350, NULL, 0, 0, 0, NORMAL,
253                 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 2500, 0);
254 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, NORMAL,
255                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 2500, 0);
256 PALMAS_REGS_PDATA(smps6, 850,  850, NULL, 0, 0, 1, NORMAL,
257                 0, 0, 0, 0, 0);
258 PALMAS_REGS_PDATA(smps7, 1200,  1200, NULL, 0, 0, 1, NORMAL,
259                 0, 0, 0, 0, 0);
260 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
261                 0, 0, 0, 0, 0);
262 PALMAS_REGS_PDATA(smps9, 2800,  2800, NULL, 1, 0, 1, NORMAL,
263                 0, 0, 0, 0, 0);
264 PALMAS_REGS_PDATA(smps10_out1, 5000,  5000, NULL, 0, 0, 0, 0,
265                 0, 0, 0, 0, 0);
266 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1, 0,
267                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
268 PALMAS_REGS_PDATA(ldo2, 2800,  3000, NULL, 0, 0, 0, 0,
269                 0, 0, 0, 0, 0);
270 PALMAS_REGS_PDATA(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1, 0,
271                 0, 0, 0, 0, 0);
272 PALMAS_REGS_PDATA(ldo4, 1200,  1200, NULL, 0, 0, 1, 0,
273                 0, 0, 0, 0, 0);
274 PALMAS_REGS_PDATA(ldo5, 2700,  2700, NULL, 0, 0, 1, 0,
275                 0, 0, 0, 0, 0);
276 PALMAS_REGS_PDATA(ldo6, 3000,  3000, NULL, 1, 1, 1, 0,
277                 0, 0, 0, 0, 0);
278 PALMAS_REGS_PDATA(ldo7, 2800,  2800, NULL, 0, 0, 1, 0,
279                 0, 0, 0, 0, 0);
280 PALMAS_REGS_PDATA(ldo8, 900,  900, NULL, 1, 1, 1, 0,
281                 0, 0, 0, 0, 0);
282 PALMAS_REGS_PDATA(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1, 0,
283                 0, 0, 0, 0, 0);
284 PALMAS_REGS_PDATA(ldoln, 2700, 2700, NULL, 0, 0, 1, 0,
285                 0, 0, 0, 0, 0);
286 PALMAS_REGS_PDATA(ldousb, 3300,  3300, NULL, 0, 0, 1, 0,
287                 0, 0, 0, 0, 0);
288 PALMAS_REGS_PDATA(regen1, 4300,  4300, NULL, 0, 0, 0, 0,
289                 0, 0, 0, 0, 0);
290 PALMAS_REGS_PDATA(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0, 0,
291                 0, 0, 0, 0, 0);
292
293 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
294 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
295         NULL,
296         PALMAS_REG_PDATA(smps123),
297         NULL,
298         PALMAS_REG_PDATA(smps45),
299         NULL,
300         PALMAS_REG_PDATA(smps6),
301         PALMAS_REG_PDATA(smps7),
302         PALMAS_REG_PDATA(smps8),
303         PALMAS_REG_PDATA(smps9),
304         NULL,
305         PALMAS_REG_PDATA(smps10_out1),
306         PALMAS_REG_PDATA(ldo1),
307         PALMAS_REG_PDATA(ldo2),
308         PALMAS_REG_PDATA(ldo3),
309         PALMAS_REG_PDATA(ldo4),
310         PALMAS_REG_PDATA(ldo5),
311         PALMAS_REG_PDATA(ldo6),
312         PALMAS_REG_PDATA(ldo7),
313         PALMAS_REG_PDATA(ldo8),
314         PALMAS_REG_PDATA(ldo9),
315         NULL,
316         NULL,
317         NULL,
318         NULL,
319         NULL,
320         PALMAS_REG_PDATA(ldoln),
321         PALMAS_REG_PDATA(ldousb),
322         PALMAS_REG_PDATA(regen1),
323         PALMAS_REG_PDATA(regen2),
324         NULL,
325         NULL,
326         NULL,
327 };
328
329 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
330 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
331         NULL,
332         PALMAS_REG_INIT_DATA(smps123),
333         NULL,
334         PALMAS_REG_INIT_DATA(smps45),
335         NULL,
336         PALMAS_REG_INIT_DATA(smps6),
337         PALMAS_REG_INIT_DATA(smps7),
338         PALMAS_REG_INIT_DATA(smps8),
339         PALMAS_REG_INIT_DATA(smps9),
340         NULL,
341         PALMAS_REG_INIT_DATA(smps10_out1),
342         PALMAS_REG_INIT_DATA(ldo1),
343         PALMAS_REG_INIT_DATA(ldo2),
344         PALMAS_REG_INIT_DATA(ldo3),
345         PALMAS_REG_INIT_DATA(ldo4),
346         PALMAS_REG_INIT_DATA(ldo5),
347         PALMAS_REG_INIT_DATA(ldo6),
348         PALMAS_REG_INIT_DATA(ldo7),
349         PALMAS_REG_INIT_DATA(ldo8),
350         PALMAS_REG_INIT_DATA(ldo9),
351         NULL,
352         NULL,
353         NULL,
354         NULL,
355         NULL,
356         PALMAS_REG_INIT_DATA(ldoln),
357         PALMAS_REG_INIT_DATA(ldousb),
358         PALMAS_REG_INIT_DATA(regen1),
359         PALMAS_REG_INIT_DATA(regen2),
360         NULL,
361         NULL,
362         NULL,
363 };
364
365 static int ac_online(void)
366 {
367         return 1;
368 }
369
370 static struct resource pluto_pda_resources[] = {
371         [0] = {
372                 .name   = "ac",
373         },
374 };
375
376 static struct pda_power_pdata pluto_pda_data = {
377         .is_ac_online   = ac_online,
378 };
379
380 static struct platform_device pluto_pda_power_device = {
381         .name           = "pda-power",
382         .id             = -1,
383         .resource       = pluto_pda_resources,
384         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
385         .dev    = {
386                 .platform_data  = &pluto_pda_data,
387         },
388 };
389
390 /* Always ON /Battery regulator */
391 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
392                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
393                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
394                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
395                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
396                 REGULATOR_SUPPLY("vdd_sys_audio", NULL),
397                 REGULATOR_SUPPLY("vdd_vbrtr", NULL),
398 };
399
400 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
401         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
402         REGULATOR_SUPPLY("imx132_reg2", NULL),
403         REGULATOR_SUPPLY("imx091_i2c_vdd", NULL),
404         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
405         REGULATOR_SUPPLY("vif", "2-0010"),
406         REGULATOR_SUPPLY("vif", "2-0036"),
407         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
408 };
409
410 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
411         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
412         REGULATOR_SUPPLY("vdig", "2-0010"),
413         REGULATOR_SUPPLY("vdig", "2-0036"),
414 };
415
416 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
417         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
418         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
419         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
420 };
421
422 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
423         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
424 };
425
426 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
427         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
428 };
429
430 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
431         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
432 };
433
434 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
435         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
436 };
437
438 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
439         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
440 };
441
442 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
443         REGULATOR_SUPPLY("vpp_fuse", NULL),
444         REGULATOR_SUPPLY("v_efuse", NULL),
445 };
446
447 /* Macro for defining fixed regulator sub device data */
448 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
449 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
450         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
451         _sdelay)                                                        \
452         static struct regulator_init_data ri_data_##_var =              \
453         {                                                               \
454                 .supply_regulator = _in_supply,                         \
455                 .num_consumer_supplies =                                \
456                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
457                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
458                 .constraints = {                                        \
459                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
460                                         REGULATOR_MODE_STANDBY),        \
461                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
462                                         REGULATOR_CHANGE_STATUS |       \
463                                         REGULATOR_CHANGE_VOLTAGE),      \
464                         .always_on = _always_on,                        \
465                         .boot_on = _boot_on,                            \
466                 },                                                      \
467         };                                                              \
468         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
469         {                                                               \
470                 .supply_name = FIXED_SUPPLY(_name),                     \
471                 .microvolts = _millivolts * 1000,                       \
472                 .gpio = _gpio_nr,                                       \
473                 .gpio_is_open_drain = _open_drain,                      \
474                 .enable_high = _active_high,                            \
475                 .enabled_at_boot = _boot_state,                         \
476                 .init_data = &ri_data_##_var,                           \
477                 .startup_delay = _sdelay                                \
478         };                                                              \
479         static struct platform_device fixed_reg_en_##_var##_dev = {     \
480                 .name = "reg-fixed-voltage",                            \
481                 .id = _id,                                              \
482                 .dev = {                                                \
483                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
484                 },                                                      \
485         }
486
487 FIXED_REG(0,    battery,        battery,
488         NULL,   0,      0,
489         -1,     false, true,    0,      3300,   0);
490
491 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
492         palmas_rails(smps8),    0,      0,
493         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
494         0);
495
496 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
497         palmas_rails(smps7),    0,      0,
498         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
499         0);
500
501 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
502         palmas_rails(smps8),    0,      0,
503         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
504
505 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
506         palmas_rails(smps9),    0,      0,
507         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
508
509 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
510         palmas_rails(smps8),    0,      0,
511         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
512         0);
513
514 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
515         palmas_rails(smps9),    0,      0,
516         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
517
518 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
519         palmas_rails(smps8),    0,      0,
520         -1,     false,  true,   0,      1800,   0);
521
522 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
523         NULL,   0,      0,
524         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
525
526 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
527         palmas_rails(smps8),    0,      0,
528         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
529
530 /*
531  * Creating the fixed regulator device tables
532  */
533 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
534
535 #define E1580_COMMON_FIXED_REG                  \
536         ADD_FIXED_REG(battery),                 \
537         ADD_FIXED_REG(vdd_1v8_cam),             \
538         ADD_FIXED_REG(vdd_1v2_cam),             \
539         ADD_FIXED_REG(avdd_usb3_1v05),          \
540         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
541         ADD_FIXED_REG(vdd_lcd_1v8),             \
542         ADD_FIXED_REG(vdd_lcd_mmc),             \
543         ADD_FIXED_REG(vdd_1v8_mic),             \
544         ADD_FIXED_REG(vdd_hdmi_5v0),
545
546 #define E1580_T114_FIXED_REG                    \
547         ADD_FIXED_REG(vpp_fuse),
548
549 /* Gpio switch regulator platform data for Pluto E1580 */
550 static struct platform_device *pfixed_reg_devs[] = {
551         E1580_COMMON_FIXED_REG
552         E1580_T114_FIXED_REG
553 };
554
555 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
556 /* board parameters for cpu dfll */
557 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
558         .sample_rate = 11500,
559
560         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
561         .cf = 10,
562         .ci = 0,
563         .cg = 2,
564
565         .droop_cut_value = 0xF,
566         .droop_restore_ramp = 0x0,
567         .scale_out_ramp = 0x0,
568 };
569 #endif
570
571 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
572 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
573 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
574 static inline void fill_reg_map(void)
575 {
576         int i;
577         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
578                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
579                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
580         }
581 }
582
583 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
584 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
585         .dfll_clk_name = "dfll_cpu",
586         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
587         .u.pmu_i2c = {
588                 .fs_rate = 400000,
589                 .slave_addr = 0xb0,
590                 .reg = 0x23,
591         },
592         .vdd_map = pmu_cpu_vdd_map,
593         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
594         .pmu_undershoot_gb = 100,
595
596         .cfg_param = &pluto_cl_dvfs_param,
597 };
598
599 static int __init pluto_cl_dvfs_init(void)
600 {
601         fill_reg_map();
602         if (tegra_revision < TEGRA_REVISION_A02)
603                 pluto_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
604         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
605         platform_device_register(&tegra_cl_dvfs_device);
606
607         return 0;
608 }
609 #endif
610
611 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
612         {
613                 .en_pwm = false,
614         }, {
615                 .en_pwm = true,
616                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
617                 .reg_id = PALMAS_REG_SMPS6,
618                 .step_20mV = true,
619                 .base_voltage_uV = 500000,
620                 .max_voltage_uV = 1100000,
621         },
622 };
623
624 static struct palmas_pmic_platform_data pmic_platform = {
625         .dvfs_init_data = palmas_dvfs_idata,
626         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
627 };
628
629 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
630         {
631                 .clk32k_id = PALMAS_CLOCK32KG,
632                 .enable = true,
633         }, {
634                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
635                 .enable = true,
636         },
637 };
638
639 static struct palmas_pinctrl_config palmas_pincfg[] = {
640         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
641         PALMAS_PINMUX("vac", "vac", NULL, NULL),
642         PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
643         PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
644         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
645         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
646         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
647         PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
648         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
649         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
650 };
651
652 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
653         .pincfg = palmas_pincfg,
654         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
655         .dvfs1_enable = false,
656         .dvfs2_enable = true,
657 };
658
659 static struct palmas_platform_data palmas_pdata = {
660         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
661         .irq_base = PALMAS_TEGRA_IRQ_BASE,
662         .pmic_pdata = &pmic_platform,
663         .clk32k_init_data =  palmas_clk32k_idata,
664         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
665         .irq_flags = IRQ_TYPE_LEVEL_HIGH,
666         .pinctrl_pdata = &palmas_pinctrl_pdata,
667 };
668
669 static struct i2c_board_info palma_device[] = {
670         {
671                 I2C_BOARD_INFO("tps65913", 0x58),
672                 .irq            = INT_EXTERNAL_PMU,
673                 .platform_data  = &palmas_pdata,
674         },
675 };
676
677 int __init pluto_regulator_init(void)
678 {
679         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
680         u32 pmc_ctrl;
681         int i;
682
683 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
684         pluto_cl_dvfs_init();
685 #endif
686
687         /* TPS65913: Normal state of INT request line is LOW.
688          * configure the power management controller to trigger PMU
689          * interrupts when HIGH.
690          */
691         pmc_ctrl = readl(pmc + PMC_CTRL);
692         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
693
694         /* Enable full constraints */
695         regulator_has_full_constraints();
696
697         /* Tracking configuration */
698         reg_init_data_ldo8.config_flags =
699                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
700                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
701
702         if (get_power_config() & PLUTO_4K_REWORKED) {
703                 /* Account for the change of avdd_hdmi_pll from ldo1 to ldo4 */
704                 reg_idata_ldo1.consumer_supplies = palmas_ldo1_4K_supply;
705                 reg_idata_ldo1.num_consumer_supplies =
706                         ARRAY_SIZE(palmas_ldo1_4K_supply);
707                 reg_idata_ldo4.consumer_supplies = palmas_ldo4_4K_supply;
708                 reg_idata_ldo4.num_consumer_supplies =
709                         ARRAY_SIZE(palmas_ldo4_4K_supply);
710                 reg_init_data_ldo4.roof_floor = PALMAS_EXT_CONTROL_NSLEEP;
711                 reg_idata_ldo4.constraints.always_on = 1;
712                 reg_idata_ldo4.constraints.boot_on = 1;
713         }
714
715         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
716                 pmic_platform.reg_data[i] = pluto_reg_data[i];
717                 pmic_platform.reg_init[i] = pluto_reg_init[i];
718         }
719
720         platform_device_register(&pluto_pda_power_device);
721         i2c_register_board_info(4, palma_device,
722                         ARRAY_SIZE(palma_device));
723         return 0;
724 }
725
726 static int __init pluto_fixed_regulator_init(void)
727 {
728         if (!of_machine_is_compatible("nvidia,pluto"))
729                 return 0;
730
731         return platform_add_devices(pfixed_reg_devs,
732                         ARRAY_SIZE(pfixed_reg_devs));
733 }
734 subsys_initcall_sync(pluto_fixed_regulator_init);
735
736 static struct tegra_io_dpd hv_io = {
737         .name                   = "HV",
738         .io_dpd_reg_index       = 1,
739         .io_dpd_bit             = 6,
740 };
741
742 static void pluto_board_suspend(int state, enum suspend_stage stage)
743 {
744         if (stage == TEGRA_SUSPEND_BEFORE_PERIPHERAL)
745                 pluto_pinmux_suspend();
746
747         /* put HV IOs into DPD mode to save additional power */
748         if (state == TEGRA_SUSPEND_LP1 && stage == TEGRA_SUSPEND_BEFORE_CPU) {
749                 gpio_direction_input(TEGRA_GPIO_PK6);
750                 tegra_io_dpd_enable(&hv_io);
751         }
752 }
753
754 static void pluto_board_resume(int state, enum resume_stage stage)
755 {
756         /* bring HV IOs back from DPD mode, GPIO configuration
757          * will be restored by gpio driver
758          */
759         if (state == TEGRA_SUSPEND_LP1 && stage == TEGRA_RESUME_AFTER_CPU)
760                 tegra_io_dpd_disable(&hv_io);
761 }
762
763 static struct tegra_suspend_platform_data pluto_suspend_data = {
764         .cpu_timer      = 300,
765         .cpu_off_timer  = 300,
766         .suspend_mode   = TEGRA_SUSPEND_LP0,
767         .core_timer     = 0x157e,
768         .core_off_timer = 2000,
769         .corereq_high   = true,
770         .sysclkreq_high = true,
771         .cpu_lp2_min_residency = 1000,
772         .min_residency_crail = 20000,
773 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
774         .lp1_lowvolt_support = true,
775         .i2c_base_addr = TEGRA_I2C5_BASE,
776         .pmuslave_addr = 0xB0,
777         .core_reg_addr = 0x2B,
778         .lp1_core_volt_low_cold = 0x33,
779         .lp1_core_volt_low = 0x2e,
780         .lp1_core_volt_high = 0x42,
781 #endif
782         .board_suspend  = pluto_board_suspend,
783         .board_resume   = pluto_board_resume,
784 };
785
786 int __init pluto_suspend_init(void)
787 {
788         tegra_init_suspend(&pluto_suspend_data);
789         return 0;
790 }
791
792 int __init pluto_edp_init(void)
793 {
794         unsigned int regulator_mA;
795
796         regulator_mA = get_maximum_cpu_current_supported();
797         if (!regulator_mA)
798                 regulator_mA = 9000;
799
800         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
801         tegra_init_cpu_edp_limits(regulator_mA);
802
803         regulator_mA = get_maximum_core_current_supported();
804         if (!regulator_mA)
805                 regulator_mA = 4000;
806
807         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
808         tegra_init_core_edp_limits(regulator_mA);
809
810         return 0;
811 }
812
813 static struct pid_thermal_gov_params soctherm_pid_params = {
814         .max_err_temp = 9000,
815         .max_err_gain = 1000,
816
817         .gain_p = 1000,
818         .gain_d = 0,
819
820         .up_compensation = 20,
821         .down_compensation = 20,
822 };
823
824 static struct thermal_zone_params soctherm_tzp = {
825         .governor_name = "pid_thermal_gov",
826         .governor_params = &soctherm_pid_params,
827 };
828
829 static struct tegra_tsensor_pmu_data tpdata_palmas = {
830         .reset_tegra = 1,
831         .pmu_16bit_ops = 0,
832         .controller_type = 0,
833         .pmu_i2c_addr = 0x58,
834         .i2c_controller_id = 4,
835         .poweroff_reg_addr = 0xa0,
836         .poweroff_reg_data = 0x0,
837 };
838
839 static struct soctherm_platform_data pluto_soctherm_data = {
840         .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
841         .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
842         .therm = {
843                 [THERM_CPU] = {
844                         .zone_enable = true,
845                         .passive_delay = 1000,
846                         .hotspot_offset = 6000,
847                         .num_trips = 3,
848                         .trips = {
849                                 {
850                                         .cdev_type = "tegra-balanced",
851                                         .trip_temp = 90000,
852                                         .trip_type = THERMAL_TRIP_PASSIVE,
853                                         .upper = THERMAL_NO_LIMIT,
854                                         .lower = THERMAL_NO_LIMIT,
855                                 },
856                                 {
857                                         .cdev_type = "tegra-heavy",
858                                         .trip_temp = 100000,
859                                         .trip_type = THERMAL_TRIP_HOT,
860                                         .upper = THERMAL_NO_LIMIT,
861                                         .lower = THERMAL_NO_LIMIT,
862                                 },
863                                 {
864                                         .cdev_type = "tegra-shutdown",
865                                         .trip_temp = 102000,
866                                         .trip_type = THERMAL_TRIP_CRITICAL,
867                                         .upper = THERMAL_NO_LIMIT,
868                                         .lower = THERMAL_NO_LIMIT,
869                                 },
870                         },
871                         .tzp = &soctherm_tzp,
872                 },
873                 [THERM_GPU] = {
874                         .zone_enable = true,
875                         .passive_delay = 1000,
876                         .hotspot_offset = 6000,
877                         .num_trips = 3,
878                         .trips = {
879                                 {
880                                         .cdev_type = "tegra-balanced",
881                                         .trip_temp = 90000,
882                                         .trip_type = THERMAL_TRIP_PASSIVE,
883                                         .upper = THERMAL_NO_LIMIT,
884                                         .lower = THERMAL_NO_LIMIT,
885                                 },
886                                 {
887                                         .cdev_type = "tegra-heavy",
888                                         .trip_temp = 100000,
889                                         .trip_type = THERMAL_TRIP_HOT,
890                                         .upper = THERMAL_NO_LIMIT,
891                                         .lower = THERMAL_NO_LIMIT,
892                                 },
893                                 {
894                                         .cdev_type = "tegra-shutdown",
895                                         .trip_temp = 102000,
896                                         .trip_type = THERMAL_TRIP_CRITICAL,
897                                         .upper = THERMAL_NO_LIMIT,
898                                         .lower = THERMAL_NO_LIMIT,
899                                 },
900                         },
901                         .tzp = &soctherm_tzp,
902                 },
903                 [THERM_PLL] = {
904                         .zone_enable = true,
905                 },
906         },
907         .throttle = {
908                 [THROTTLE_HEAVY] = {
909                         .priority = 100,
910                         .devs = {
911                                 [THROTTLE_DEV_CPU] = {
912                                         .enable = true,
913                                         .depth = 80,
914                                 },
915                                 [THROTTLE_DEV_GPU] = {
916                                         .depth = 80,
917                                         .enable = true,
918                                 },
919                         },
920                 },
921                 [THROTTLE_OC4] = {
922                         .throt_mode = BRIEF,
923                         .polarity = 1,
924                         .intr = true,
925                         .devs = {
926                                 [THROTTLE_DEV_CPU] = {
927                                         .enable = true,
928                                         .depth = 50,
929                                 },
930                                 [THROTTLE_DEV_GPU] = {
931                                         .enable = true,
932                                         .depth = 50,
933                                 },
934                         },
935                 },
936         },
937         .tshut_pmu_trip_data = &tpdata_palmas,
938 };
939
940 int __init pluto_soctherm_init(void)
941 {
942         tegra_platform_edp_init(pluto_soctherm_data.therm[THERM_CPU].trips,
943                         &pluto_soctherm_data.therm[THERM_CPU].num_trips,
944                         6000);  /* edp temperature margin */
945         tegra_add_cpu_vmax_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
946                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
947         tegra_add_core_edp_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
948                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
949
950         return tegra11_soctherm_init(&pluto_soctherm_data);
951 }
952
953 static struct edp_manager pluto_sysedp_manager = {
954         .name = "battery",
955         .max = 14000
956 };
957
958 void __init pluto_sysedp_init(void)
959 {
960         struct edp_governor *g;
961         int r;
962
963         if (!IS_ENABLED(CONFIG_EDP_FRAMEWORK))
964                 return;
965
966         if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY)
967                 pluto_sysedp_manager.max = INT_MAX;
968
969         r = edp_register_manager(&pluto_sysedp_manager);
970         WARN_ON(r);
971         if (r)
972                 return;
973
974         /* start with priority governor */
975         g = edp_get_governor("priority");
976         WARN_ON(!g);
977         if (!g)
978                 return;
979
980         r = edp_set_governor(&pluto_sysedp_manager, g);
981         WARN_ON(r);
982 }
983
984 static unsigned int pluto_psydepl_states[] = {
985         9900, 9600, 9300, 9000, 8700, 8400, 8100, 7800,
986         7500, 7200, 6900, 6600, 6300, 6000, 5800, 5600,
987         5400, 5200, 5000, 4800, 4600, 4400, 4200, 4000,
988         3800, 3600, 3400, 3200, 3000, 2800, 2600, 2400,
989         2200, 2000, 1900, 1800, 1700, 1600, 1500, 1400,
990         1300, 1200, 1100, 1000,  900,  800,  700,  600,
991          500,  400,  300,  200,  100,    0
992 };
993
994 /* Temperature in deci-celcius */
995 static struct psy_depletion_ibat_lut pluto_ibat_lut[] = {
996         {  600,  500 },
997         {  400, 3000 },
998         {    0, 3000 },
999         { -300,    0 }
1000 };
1001
1002 static struct psy_depletion_rbat_lut pluto_rbat_lut[] = {
1003         { 100,  43600 },
1004         {  80, 104000 },
1005         {  60, 102000 },
1006         {  40, 113600 },
1007         {  20, 124000 },
1008         {   0, 150000 }
1009 };
1010
1011 static struct psy_depletion_platform_data pluto_psydepl_pdata = {
1012         .power_supply = "max170xx_battery",
1013         .states = pluto_psydepl_states,
1014         .num_states = ARRAY_SIZE(pluto_psydepl_states),
1015         .e0_index = 16,
1016         .r_const = 80000,
1017         .vsys_min = 3250000,
1018         .vcharge = 4200000,
1019         .ibat_nom = 3000,
1020         .ibat_lut = pluto_ibat_lut,
1021         .rbat_lut = pluto_rbat_lut
1022 };
1023
1024 static struct platform_device pluto_psydepl_device = {
1025         .name = "psy_depletion",
1026         .id = -1,
1027         .dev = { .platform_data = &pluto_psydepl_pdata }
1028 };
1029
1030 void __init pluto_sysedp_psydepl_init(void)
1031 {
1032         int r;
1033
1034         r = platform_device_register(&pluto_psydepl_device);
1035         WARN_ON(r);
1036 }
1037
1038 static struct tegra_sysedp_corecap pluto_sysedp_corecap[] = {
1039         {  1000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
1040         {  2000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
1041         {  3000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
1042         {  4000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
1043         {  5000, {  1000, 240000, 204000}, {  1000, 240000, 312000 } },
1044         {  6000, {  1679, 240000, 312000}, {  1679, 240000, 312000 } },
1045         {  7000, {  1843, 240000, 624000}, {  1975, 324000, 408000 } },
1046         {  8000, {  2843, 240000, 624000}, {  2306, 420000, 624000 } },
1047         {  9000, {  3843, 240000, 624000}, {  2606, 420000, 792000 } },
1048         { 10000, {  4565, 240000, 792000}, {  3398, 528000, 792000 } },
1049         { 11000, {  5565, 240000, 792000}, {  4398, 528000, 792000 } },
1050         { 12000, {  6565, 240000, 792000}, {  4277, 600000, 792000 } },
1051         { 13000, {  7565, 240000, 792000}, {  5277, 600000, 792000 } },
1052         { 14000, {  8565, 240000, 792000}, {  6277, 600000, 792000 } },
1053         { 15000, {  9565, 240000, 792000}, {  7277, 600000, 792000 } },
1054         { 16000, { 10565, 240000, 792000}, {  8277, 600000, 792000 } },
1055         { 17000, { 11565, 240000, 792000}, {  9277, 600000, 792000 } },
1056         { 18000, { 12565, 240000, 792000}, { 10277, 600000, 792000 } },
1057         { 19000, { 13565, 240000, 792000}, { 11277, 600000, 792000 } },
1058         { 20000, { 14565, 240000, 792000}, { 12277, 600000, 792000 } },
1059         { 23000, { 14565, 600000, 792000}, { 14565, 600000, 792000 } }
1060 };
1061
1062 static struct tegra_sysedp_platform_data pluto_sysedp_platdata = {
1063         .corecap = pluto_sysedp_corecap,
1064         .corecap_size = ARRAY_SIZE(pluto_sysedp_corecap),
1065         .core_gain = 130,
1066         .init_req_watts = 20000
1067 };
1068
1069 static struct platform_device pluto_sysedp_device = {
1070         .name = "tegra_sysedp",
1071         .id = -1,
1072         .dev = { .platform_data = &pluto_sysedp_platdata }
1073 };
1074
1075 void __init pluto_sysedp_core_init(void)
1076 {
1077         int r;
1078
1079         pluto_sysedp_platdata.cpufreq_lim = tegra_get_system_edp_entries(
1080                         &pluto_sysedp_platdata.cpufreq_lim_size);
1081         if (!pluto_sysedp_platdata.cpufreq_lim) {
1082                 WARN_ON(1);
1083                 return;
1084         }
1085
1086         r = platform_device_register(&pluto_sysedp_device);
1087         WARN_ON(r);
1088 }