a5a69c4ff8809cd07a43913b5ea0fe0a1b1ce34e
[linux-3.10.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25
26 #include <mach/edp.h>
27 #include <mach/irqs.h>
28 #include <linux/regulator/fixed.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/regulator/machine.h>
31 #include <linux/irq.h>
32
33 #include <asm/mach-types.h>
34
35 #include "cpu-tegra.h"
36 #include "pm.h"
37 #include "board.h"
38 #include "board-common.h"
39 #include "board-pluto.h"
40 #include "iomap.h"
41 #include "tegra_cl_dvfs.h"
42 #include "devices.h"
43 #include "tegra11_soctherm.h"
44 #include "tegra3_tsensor.h"
45
46 #define PMC_CTRL                0x0
47 #define PMC_CTRL_INTR_LOW       (1 << 17)
48
49 /************************ Pluto based regulator ****************/
50 static struct regulator_consumer_supply palmas_smps123_supply[] = {
51         REGULATOR_SUPPLY("vdd_cpu", NULL),
52 };
53
54 static struct regulator_consumer_supply palmas_smps45_supply[] = {
55         REGULATOR_SUPPLY("vdd_core", NULL),
56 };
57
58 static struct regulator_consumer_supply palmas_smps6_supply[] = {
59         REGULATOR_SUPPLY("vdd_core_bb", NULL),
60 };
61
62 static struct regulator_consumer_supply palmas_smps7_supply[] = {
63         REGULATOR_SUPPLY("vddio_ddr", NULL),
64         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
65         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
66         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
67 };
68
69 static struct regulator_consumer_supply palmas_smps8_supply[] = {
70         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
71         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
72         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
73         REGULATOR_SUPPLY("avdd_osc", NULL),
74         REGULATOR_SUPPLY("vddio_sys", NULL),
75         REGULATOR_SUPPLY("vddio_bb", NULL),
76         REGULATOR_SUPPLY("pwrdet_bb", NULL),
77         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
78         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
79         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
80         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
81         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
82         REGULATOR_SUPPLY("vddio_audio", NULL),
83         REGULATOR_SUPPLY("pwrdet_audio", NULL),
84         REGULATOR_SUPPLY("vddio_uart", NULL),
85         REGULATOR_SUPPLY("pwrdet_uart", NULL),
86         REGULATOR_SUPPLY("vddio_gmi", NULL),
87         REGULATOR_SUPPLY("pwrdet_nand", NULL),
88         REGULATOR_SUPPLY("vddio_cam", "vi"),
89         REGULATOR_SUPPLY("pwrdet_cam", NULL),
90         REGULATOR_SUPPLY("vdd_gps", NULL),
91         REGULATOR_SUPPLY("vdd_nfc", NULL),
92         REGULATOR_SUPPLY("vlogic", "0-0069"),
93         REGULATOR_SUPPLY("vdd_dtv", NULL),
94         REGULATOR_SUPPLY("vdd_bb", NULL),
95         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
96         REGULATOR_SUPPLY("vcore_lpddr", NULL),
97         REGULATOR_SUPPLY("vddio_lpddr", NULL),
98         REGULATOR_SUPPLY("vdd_rf", NULL),
99         REGULATOR_SUPPLY("vdd_modem2", NULL),
100         REGULATOR_SUPPLY("vdd_dbg", NULL),
101         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
102         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
103         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
104         REGULATOR_SUPPLY("dvdd_audio", NULL),
105         REGULATOR_SUPPLY("avdd_audio", NULL),
106         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
107         REGULATOR_SUPPLY("vdd_bt_1v8", NULL),
108         REGULATOR_SUPPLY("dvdd", "spi3.2"),
109         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
110 };
111
112 static struct regulator_consumer_supply palmas_smps9_supply[] = {
113         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
114         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
115         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
116         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
117 };
118
119 static struct regulator_consumer_supply palmas_smps10_supply[] = {
120         REGULATOR_SUPPLY("unused_smps10", NULL),
121         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
122         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
123         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
124         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
125         REGULATOR_SUPPLY("vdd_lcd", NULL),
126 };
127
128 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
129         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
130         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
131         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
132         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
133         REGULATOR_SUPPLY("avdd_pllm", NULL),
134         REGULATOR_SUPPLY("avdd_pllu", NULL),
135         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
136         REGULATOR_SUPPLY("avdd_pllx", NULL),
137         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
138         REGULATOR_SUPPLY("avdd_plle", NULL),
139 };
140
141 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
142         REGULATOR_SUPPLY("avdd_lcd", NULL),
143 };
144
145 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
146         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
147         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
148         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
149         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
150         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
151         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
152         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
153         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
154         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
155 };
156
157 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
158         REGULATOR_SUPPLY("vdd_spare", NULL),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
162         REGULATOR_SUPPLY("avdd_cam1", NULL),
163         REGULATOR_SUPPLY("vana", "2-0010"),
164 };
165
166 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
167         REGULATOR_SUPPLY("vdd_temp", NULL),
168         REGULATOR_SUPPLY("vdd_mb", NULL),
169         REGULATOR_SUPPLY("vin", "1-004d"),
170         REGULATOR_SUPPLY("vdd_nfc_3v0", NULL),
171         REGULATOR_SUPPLY("vdd_irled", NULL),
172         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
173         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
174         REGULATOR_SUPPLY("vaux_3v3", NULL),
175         REGULATOR_SUPPLY("vdd", "0-0044"),
176         REGULATOR_SUPPLY("vdd", "0-004c"),
177         REGULATOR_SUPPLY("avdd", "spi3.2"),
178         REGULATOR_SUPPLY("vdd", "0-0069"),
179 };
180
181 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
182         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
183         REGULATOR_SUPPLY("vdd", "2-000e"),
184 };
185 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
186         REGULATOR_SUPPLY("vdd_rtc", NULL),
187 };
188 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
189         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
190         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
191 };
192 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
193         REGULATOR_SUPPLY("avdd_cam2", NULL),
194         REGULATOR_SUPPLY("vana", "2-0036"),
195 };
196
197 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
198         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
199         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
200         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
201         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
202         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
203         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
204         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
205         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
206         REGULATOR_SUPPLY("pwrdet_hv", NULL),
207         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
208
209 };
210
211 static struct regulator_consumer_supply palmas_regen1_supply[] = {
212         REGULATOR_SUPPLY("mic_ventral", NULL),
213 };
214
215 static struct regulator_consumer_supply palmas_regen2_supply[] = {
216         REGULATOR_SUPPLY("vdd_mic", NULL),
217 };
218
219 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
220         _boot_on, _apply_uv)                                            \
221         static struct regulator_init_data reg_idata_##_name = {         \
222                 .constraints = {                                        \
223                         .name = palmas_rails(_name),                    \
224                         .min_uV = (_minmv)*1000,                        \
225                         .max_uV = (_maxmv)*1000,                        \
226                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
227                                         REGULATOR_MODE_STANDBY),        \
228                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
229                                         REGULATOR_CHANGE_STATUS |       \
230                                         REGULATOR_CHANGE_VOLTAGE),      \
231                         .always_on = _always_on,                        \
232                         .boot_on = _boot_on,                            \
233                         .apply_uV = _apply_uv,                          \
234                 },                                                      \
235                 .num_consumer_supplies =                                \
236                         ARRAY_SIZE(palmas_##_name##_supply),            \
237                 .consumer_supplies = palmas_##_name##_supply,           \
238                 .supply_regulator = _supply_reg,                        \
239         }
240
241 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
242 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
243 PALMAS_PDATA_INIT(smps6, 850,  850, NULL, 0, 0, 1);
244 PALMAS_PDATA_INIT(smps7, 1200,  1200, NULL, 0, 0, 1);
245 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1);
246 PALMAS_PDATA_INIT(smps9, 2800,  2800, NULL, 1, 0, 1);
247 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
248 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1);
249 PALMAS_PDATA_INIT(ldo2, 2800,  3000, NULL, 0, 0, 0);
250 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1);
251 PALMAS_PDATA_INIT(ldo4, 900,  3300, NULL, 0, 0, 0);
252 PALMAS_PDATA_INIT(ldo5, 2700,  2700, NULL, 0, 0, 1);
253 PALMAS_PDATA_INIT(ldo6, 3000,  3000, NULL, 1, 1, 1);
254 PALMAS_PDATA_INIT(ldo7, 2800,  2800, NULL, 0, 0, 1);
255 PALMAS_PDATA_INIT(ldo8, 900,  900, NULL, 1, 1, 1);
256 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
257 PALMAS_PDATA_INIT(ldoln, 2700, 2700, NULL, 0, 0, 1);
258 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
259 PALMAS_PDATA_INIT(regen1, 4300,  4300, NULL, 0, 0, 0);
260 PALMAS_PDATA_INIT(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0);
261
262 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
263
264 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
265         NULL,
266         PALMAS_REG_PDATA(smps123),
267         NULL,
268         PALMAS_REG_PDATA(smps45),
269         NULL,
270         PALMAS_REG_PDATA(smps6),
271         PALMAS_REG_PDATA(smps7),
272         PALMAS_REG_PDATA(smps8),
273         PALMAS_REG_PDATA(smps9),
274         PALMAS_REG_PDATA(smps10),
275         PALMAS_REG_PDATA(ldo1),
276         PALMAS_REG_PDATA(ldo2),
277         PALMAS_REG_PDATA(ldo3),
278         PALMAS_REG_PDATA(ldo4),
279         PALMAS_REG_PDATA(ldo5),
280         PALMAS_REG_PDATA(ldo6),
281         PALMAS_REG_PDATA(ldo7),
282         PALMAS_REG_PDATA(ldo8),
283         PALMAS_REG_PDATA(ldo9),
284         PALMAS_REG_PDATA(ldoln),
285         PALMAS_REG_PDATA(ldousb),
286         PALMAS_REG_PDATA(regen1),
287         PALMAS_REG_PDATA(regen2),
288         NULL,
289         NULL,
290         NULL,
291 };
292
293 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
294                 _tstep, _vsel)                                          \
295         static struct palmas_reg_init reg_init_data_##_name = {         \
296                 .warm_reset = _warm_reset,                              \
297                 .roof_floor =   _roof_floor,                            \
298                 .mode_sleep = _mode_sleep,              \
299                 .tstep = _tstep,                        \
300                 .vsel = _vsel,          \
301         }
302
303 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
304 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
305 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
306 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
307 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
308 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
309 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
310 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
311 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
312 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
313 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
314 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
315 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
316 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
317 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
318 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
319 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
320 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
321 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
322 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
323 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
324
325 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
326 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
327         PALMAS_REG_INIT_DATA(smps12),
328         PALMAS_REG_INIT_DATA(smps123),
329         PALMAS_REG_INIT_DATA(smps3),
330         PALMAS_REG_INIT_DATA(smps45),
331         PALMAS_REG_INIT_DATA(smps457),
332         PALMAS_REG_INIT_DATA(smps6),
333         PALMAS_REG_INIT_DATA(smps7),
334         PALMAS_REG_INIT_DATA(smps8),
335         PALMAS_REG_INIT_DATA(smps9),
336         PALMAS_REG_INIT_DATA(smps10),
337         PALMAS_REG_INIT_DATA(ldo1),
338         PALMAS_REG_INIT_DATA(ldo2),
339         PALMAS_REG_INIT_DATA(ldo3),
340         PALMAS_REG_INIT_DATA(ldo4),
341         PALMAS_REG_INIT_DATA(ldo5),
342         PALMAS_REG_INIT_DATA(ldo6),
343         PALMAS_REG_INIT_DATA(ldo7),
344         PALMAS_REG_INIT_DATA(ldo8),
345         PALMAS_REG_INIT_DATA(ldo9),
346         PALMAS_REG_INIT_DATA(ldoln),
347         PALMAS_REG_INIT_DATA(ldousb),
348 };
349
350 static int ac_online(void)
351 {
352         return 1;
353 }
354
355 static struct resource pluto_pda_resources[] = {
356         [0] = {
357                 .name   = "ac",
358         },
359 };
360
361 static struct pda_power_pdata pluto_pda_data = {
362         .is_ac_online   = ac_online,
363 };
364
365 static struct platform_device pluto_pda_power_device = {
366         .name           = "pda-power",
367         .id             = -1,
368         .resource       = pluto_pda_resources,
369         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
370         .dev    = {
371                 .platform_data  = &pluto_pda_data,
372         },
373 };
374
375 /* Always ON /Battery regulator */
376 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
377                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
378                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
379                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
380                 REGULATOR_SUPPLY("vdd_sys_gps", NULL),
381                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
382                 REGULATOR_SUPPLY("vdd_sys_audio", NULL),
383 };
384
385 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
386         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
387         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
388         REGULATOR_SUPPLY("vif", "2-0010"),
389         REGULATOR_SUPPLY("vif", "2-0036"),
390         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
391 };
392
393 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
394         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
395         REGULATOR_SUPPLY("vdig", "2-0010"),
396         REGULATOR_SUPPLY("vdig", "2-0036"),
397 };
398
399 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
400         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
401         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
402         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
403 };
404
405 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
406         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
407 };
408
409 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
410         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
411 };
412
413 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
414         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
415 };
416
417 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
418         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
419 };
420
421 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
422         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
423 };
424
425 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
426         REGULATOR_SUPPLY("vpp_fuse", NULL),
427         REGULATOR_SUPPLY("v_efuse", NULL),
428 };
429
430 /* Macro for defining fixed regulator sub device data */
431 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
432 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
433         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
434         _sdelay)                                                        \
435         static struct regulator_init_data ri_data_##_var =              \
436         {                                                               \
437                 .supply_regulator = _in_supply,                         \
438                 .num_consumer_supplies =                                \
439                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
440                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
441                 .constraints = {                                        \
442                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
443                                         REGULATOR_MODE_STANDBY),        \
444                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
445                                         REGULATOR_CHANGE_STATUS |       \
446                                         REGULATOR_CHANGE_VOLTAGE),      \
447                         .always_on = _always_on,                        \
448                         .boot_on = _boot_on,                            \
449                 },                                                      \
450         };                                                              \
451         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
452         {                                                               \
453                 .supply_name = FIXED_SUPPLY(_name),                     \
454                 .microvolts = _millivolts * 1000,                       \
455                 .gpio = _gpio_nr,                                       \
456                 .gpio_is_open_drain = _open_drain,                      \
457                 .enable_high = _active_high,                            \
458                 .enabled_at_boot = _boot_state,                         \
459                 .init_data = &ri_data_##_var,                           \
460                 .startup_delay = _sdelay                                \
461         };                                                              \
462         static struct platform_device fixed_reg_en_##_var##_dev = {     \
463                 .name = "reg-fixed-voltage",                            \
464                 .id = _id,                                              \
465                 .dev = {                                                \
466                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
467                 },                                                      \
468         }
469
470 FIXED_REG(0,    battery,        battery,
471         NULL,   0,      0,
472         -1,     false, true,    0,      3300,   0);
473
474 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
475         palmas_rails(smps8),    0,      0,
476         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
477         0);
478
479 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
480         palmas_rails(smps7),    0,      0,
481         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
482         0);
483
484 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
485         palmas_rails(smps8),    0,      0,
486         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
487
488 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
489         palmas_rails(smps9),    0,      0,
490         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
491
492 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
493         palmas_rails(smps8),    0,      0,
494         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
495         0);
496
497 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
498         palmas_rails(smps9),    0,      0,
499         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
500
501 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
502         palmas_rails(smps8),    0,      0,
503         -1,     false,  true,   0,      1800,   0);
504
505 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
506         NULL,   0,      0,
507         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
508
509 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
510         palmas_rails(smps8),    0,      0,
511         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
512
513 /*
514  * Creating the fixed regulator device tables
515  */
516 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
517
518 #define E1580_COMMON_FIXED_REG                  \
519         ADD_FIXED_REG(battery),                 \
520         ADD_FIXED_REG(vdd_1v8_cam),             \
521         ADD_FIXED_REG(vdd_1v2_cam),             \
522         ADD_FIXED_REG(avdd_usb3_1v05),          \
523         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
524         ADD_FIXED_REG(vdd_lcd_1v8),             \
525         ADD_FIXED_REG(vdd_lcd_mmc),             \
526         ADD_FIXED_REG(vdd_1v8_mic),             \
527         ADD_FIXED_REG(vdd_hdmi_5v0),
528
529 #define E1580_T114_FIXED_REG                    \
530         ADD_FIXED_REG(vpp_fuse),
531
532 /* Gpio switch regulator platform data for Pluto E1580 */
533 static struct platform_device *pfixed_reg_devs[] = {
534         E1580_COMMON_FIXED_REG
535         E1580_T114_FIXED_REG
536 };
537
538 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
539 /* board parameters for cpu dfll */
540 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
541         .sample_rate = 12500,
542
543         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
544         .cf = 10,
545         .ci = 0,
546         .cg = 2,
547
548         .droop_cut_value = 0xF,
549         .droop_restore_ramp = 0x0,
550         .scale_out_ramp = 0x0,
551 };
552 #endif
553
554 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
555 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
556 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
557 static inline void fill_reg_map(void)
558 {
559         int i;
560         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
561                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
562                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
563         }
564 }
565
566 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
567 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
568         .dfll_clk_name = "dfll_cpu",
569         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
570         .u.pmu_i2c = {
571                 .fs_rate = 400000,
572                 .slave_addr = 0xb0,
573                 .reg = 0x23,
574         },
575         .vdd_map = pmu_cpu_vdd_map,
576         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
577
578         .cfg_param = &pluto_cl_dvfs_param,
579 };
580
581 static int __init pluto_cl_dvfs_init(void)
582 {
583         fill_reg_map();
584         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
585         platform_device_register(&tegra_cl_dvfs_device);
586
587         return 0;
588 }
589 #endif
590
591 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
592         {
593                 .en_pwm = false,
594         }, {
595                 .en_pwm = true,
596                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
597                 .reg_id = PALMAS_REG_SMPS6,
598                 .step_20mV = true,
599                 .base_voltage_uV = 500000,
600                 .max_voltage_uV = 1100000,
601         },
602 };
603
604 static struct palmas_pmic_platform_data pmic_platform = {
605         .enable_ldo8_tracking = true,
606         .disabe_ldo8_tracking_suspend = true,
607         .dvfs_init_data = palmas_dvfs_idata,
608         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
609 };
610
611 struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
612         {
613                 .clk32k_id = PALMAS_CLOCK32KG,
614                 .enable = true,
615         }, {
616                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
617                 .enable = true,
618         },
619 };
620
621 static struct palmas_platform_data palmas_pdata = {
622         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
623         .irq_base = PALMAS_TEGRA_IRQ_BASE,
624         .pmic_pdata = &pmic_platform,
625         .mux_from_pdata = true,
626         .pad1 = 0,
627         .pad2 = (PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK &
628                         (1 << PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT)),
629         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2,
630         .clk32k_init_data =  palmas_clk32k_idata,
631         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
632         .irq_type = IRQ_TYPE_LEVEL_HIGH,
633         .use_power_off = true,
634 };
635
636 static struct i2c_board_info palma_device[] = {
637         {
638                 I2C_BOARD_INFO("tps65913", 0x58),
639                 .irq            = INT_EXTERNAL_PMU,
640                 .platform_data  = &palmas_pdata,
641         },
642 };
643
644 int __init pluto_regulator_init(void)
645 {
646         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
647         u32 pmc_ctrl;
648         int i;
649
650 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
651         pluto_cl_dvfs_init();
652 #endif
653
654         /* TPS65913: Normal state of INT request line is LOW.
655          * configure the power management controller to trigger PMU
656          * interrupts when HIGH.
657          */
658         pmc_ctrl = readl(pmc + PMC_CTRL);
659         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
660
661         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
662                 pmic_platform.reg_data[i] = pluto_reg_data[i];
663                 pmic_platform.reg_init[i] = pluto_reg_init[i];
664         }
665
666         platform_device_register(&pluto_pda_power_device);
667         i2c_register_board_info(4, palma_device,
668                         ARRAY_SIZE(palma_device));
669         return 0;
670 }
671
672 static int __init pluto_fixed_regulator_init(void)
673 {
674         if (!machine_is_tegra_pluto())
675                 return 0;
676
677         return platform_add_devices(pfixed_reg_devs,
678                         ARRAY_SIZE(pfixed_reg_devs));
679 }
680 subsys_initcall_sync(pluto_fixed_regulator_init);
681
682 static struct tegra_suspend_platform_data pluto_suspend_data = {
683         .cpu_timer      = 300,
684         .cpu_off_timer  = 300,
685         .suspend_mode   = TEGRA_SUSPEND_LP0,
686         .core_timer     = 0x157e,
687         .core_off_timer = 2000,
688         .corereq_high   = true,
689         .sysclkreq_high = true,
690         .cpu_lp2_min_residency = 1000,
691         .min_residency_noncpu = 2000,
692         .min_residency_crail = 8000,
693 };
694
695 int __init pluto_suspend_init(void)
696 {
697         tegra_init_suspend(&pluto_suspend_data);
698         return 0;
699 }
700
701 int __init pluto_edp_init(void)
702 {
703         unsigned int regulator_mA;
704
705         regulator_mA = get_maximum_cpu_current_supported();
706         if (!regulator_mA)
707                 regulator_mA = 9000;
708
709         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
710         tegra_init_cpu_edp_limits(regulator_mA);
711
712         regulator_mA = get_maximum_core_current_supported();
713         if (!regulator_mA)
714                 regulator_mA = 4000;
715
716         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
717         tegra_init_core_edp_limits(regulator_mA);
718
719         return 0;
720 }
721
722 static struct tegra_tsensor_pmu_data tpdata_palmas = {
723         .reset_tegra = 1,
724         .pmu_16bit_ops = 0,
725         .controller_type = 0,
726         .pmu_i2c_addr = 0x58,
727         .i2c_controller_id = 4,
728         .poweroff_reg_addr = 0xa0,
729         .poweroff_reg_data = 0x0,
730 };
731
732 static struct soctherm_platform_data pluto_soctherm_data = {
733         .therm = {
734                 [THERM_CPU] = {
735                         .zone_enable = true,
736                         .passive_delay = 1000,
737                         .num_trips = 3,
738                         .trips = {
739                                 {
740                                         .cdev_type = "tegra-balanced",
741                                         .trip_temp = 84000,
742                                         .trip_type = THERMAL_TRIP_PASSIVE,
743                                         .upper = THERMAL_NO_LIMIT,
744                                         .lower = THERMAL_NO_LIMIT,
745                                 },
746                                 {
747                                         .cdev_type = "tegra-heavy",
748                                         .trip_temp = 94000,
749                                         .trip_type = THERMAL_TRIP_HOT,
750                                         .upper = THERMAL_NO_LIMIT,
751                                         .lower = THERMAL_NO_LIMIT,
752                                 },
753                                 {
754                                         .cdev_type = "tegra-shutdown",
755                                         .trip_temp = 104000,
756                                         .trip_type = THERMAL_TRIP_CRITICAL,
757                                         .upper = THERMAL_NO_LIMIT,
758                                         .lower = THERMAL_NO_LIMIT,
759                                 },
760                         },
761                 },
762                 [THERM_GPU] = {
763                         .zone_enable = true,
764                 },
765                 [THERM_PLL] = {
766                         .zone_enable = true,
767                 },
768         },
769         .throttle = {
770                 [THROTTLE_HEAVY] = {
771                         .devs = {
772                                 [THROTTLE_DEV_CPU] = {
773                                         .enable = 1,
774                                 },
775                         },
776                 },
777         },
778         .tshut_pmu_trip_data = &tpdata_palmas,
779 };
780
781 int __init pluto_soctherm_init(void)
782 {
783         tegra_platform_edp_init(pluto_soctherm_data.therm[THERM_CPU].trips,
784                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
785         tegra_add_tj_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
786                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
787
788         return tegra11_soctherm_init(&pluto_soctherm_data);
789 }