ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-pluto-power.c
1 /*
2  * arch/arm/mach-tegra/board-pluto-power.c
3  *
4  * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26
27 #include <mach/edp.h>
28 #include <mach/irqs.h>
29 #include <mach/io_dpd.h>
30 #include <linux/tegra-soc.h>
31 #include <linux/regulator/fixed.h>
32 #include <linux/mfd/palmas.h>
33 #include <linux/regulator/machine.h>
34 #include <linux/irq.h>
35 #include <linux/pid_thermal_gov.h>
36
37 #include <asm/mach-types.h>
38
39 #include "cpu-tegra.h"
40 #include "pm.h"
41 #include "board.h"
42 #include "board-common.h"
43 #include "board-pluto.h"
44 #include "board-pmu-defines.h"
45 #include "iomap.h"
46 #include "tegra_cl_dvfs.h"
47 #include "devices.h"
48 #include "tegra11_soctherm.h"
49 #include "tegra3_tsensor.h"
50
51 #define PMC_CTRL                0x0
52 #define PMC_CTRL_INTR_LOW       (1 << 17)
53 #define PLUTO_4K_REWORKED       0x2
54
55 /************************ Pluto based regulator ****************/
56 static struct regulator_consumer_supply palmas_smps123_supply[] = {
57         REGULATOR_SUPPLY("vdd_cpu", NULL),
58 };
59
60 static struct regulator_consumer_supply palmas_smps45_supply[] = {
61         REGULATOR_SUPPLY("vdd_core", NULL),
62         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
63         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"),
64         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
65 };
66
67 static struct regulator_consumer_supply palmas_smps6_supply[] = {
68         REGULATOR_SUPPLY("vdd_core_bb", NULL),
69 };
70
71 static struct regulator_consumer_supply palmas_smps7_supply[] = {
72         REGULATOR_SUPPLY("vddio_ddr", NULL),
73         REGULATOR_SUPPLY("vddio_lpddr3", NULL),
74         REGULATOR_SUPPLY("vcore2_lpddr3", NULL),
75         REGULATOR_SUPPLY("vcore_audio_1v2", NULL),
76 };
77
78 static struct regulator_consumer_supply palmas_smps8_supply[] = {
79         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
80         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
81         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
82         REGULATOR_SUPPLY("avdd_osc", NULL),
83         REGULATOR_SUPPLY("vddio_sys", NULL),
84         REGULATOR_SUPPLY("vddio_bb", NULL),
85         REGULATOR_SUPPLY("pwrdet_bb", NULL),
86         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
87         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
88         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
89         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
90         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
91         REGULATOR_SUPPLY("vddio_audio", NULL),
92         REGULATOR_SUPPLY("pwrdet_audio", NULL),
93         REGULATOR_SUPPLY("vddio_uart", NULL),
94         REGULATOR_SUPPLY("pwrdet_uart", NULL),
95         REGULATOR_SUPPLY("vddio_gmi", NULL),
96         REGULATOR_SUPPLY("pwrdet_nand", NULL),
97         REGULATOR_SUPPLY("vddio_cam", "vi"),
98         REGULATOR_SUPPLY("pwrdet_cam", NULL),
99         REGULATOR_SUPPLY("dvdd", "0-0077"),
100         REGULATOR_SUPPLY("vlogic", "0-0069"),
101         REGULATOR_SUPPLY("vid", "0-000d"),
102         REGULATOR_SUPPLY("vddio", "0-0078"),
103         REGULATOR_SUPPLY("vdd_dtv", NULL),
104         REGULATOR_SUPPLY("vdd_bb", NULL),
105         REGULATOR_SUPPLY("vcore1_lpddr", NULL),
106         REGULATOR_SUPPLY("vcore_lpddr", NULL),
107         REGULATOR_SUPPLY("vddio_lpddr", NULL),
108         REGULATOR_SUPPLY("vdd_rf", NULL),
109         REGULATOR_SUPPLY("vdd_modem2", NULL),
110         REGULATOR_SUPPLY("vdd_dbg", NULL),
111         REGULATOR_SUPPLY("vdd_sim_1v8", NULL),
112         REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL),
113         REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL),
114         REGULATOR_SUPPLY("dvdd_audio", NULL),
115         REGULATOR_SUPPLY("avdd_audio", NULL),
116         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
117         REGULATOR_SUPPLY("dvdd", "spi3.2"),
118         REGULATOR_SUPPLY("avdd_pll_bb", NULL),
119 };
120
121 static struct regulator_consumer_supply palmas_smps9_supply[] = {
122         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
123         REGULATOR_SUPPLY("vdd_sim_mmc", NULL),
124         REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL),
125         REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL),
126 };
127
128 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
129         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
130         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
131         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
132         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
133         REGULATOR_SUPPLY("vdd_lcd", NULL),
134 };
135
136 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
137         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
138         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
139         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
140         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
141         REGULATOR_SUPPLY("avdd_pllm", NULL),
142         REGULATOR_SUPPLY("avdd_pllu", NULL),
143         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
144         REGULATOR_SUPPLY("avdd_pllx", NULL),
145         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
146         REGULATOR_SUPPLY("avdd_plle", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo1_4K_supply[] = {
150         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
151         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
152         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
153         REGULATOR_SUPPLY("avdd_pllm", NULL),
154         REGULATOR_SUPPLY("avdd_pllu", NULL),
155         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
156         REGULATOR_SUPPLY("avdd_pllx", NULL),
157         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
158         REGULATOR_SUPPLY("avdd_plle", NULL),
159 };
160
161 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
162         REGULATOR_SUPPLY("avdd_lcd", NULL),
163 };
164
165 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
166         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
167         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
168         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
169         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
170         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
171         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
172         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
173         REGULATOR_SUPPLY("vddio_hsic_bb", NULL),
174         REGULATOR_SUPPLY("vddio_hsic_modem2", NULL),
175 };
176
177 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
178         REGULATOR_SUPPLY("vdd_spare", NULL),
179 };
180
181 static struct regulator_consumer_supply palmas_ldo4_4K_supply[] = {
182         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
183         REGULATOR_SUPPLY("vdd_spare", NULL),
184 };
185
186 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
187         REGULATOR_SUPPLY("avdd_cam1", NULL),
188         REGULATOR_SUPPLY("vana", "2-0010"),
189 };
190
191 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
192         REGULATOR_SUPPLY("vdd_temp", NULL),
193         REGULATOR_SUPPLY("vdd_mb", NULL),
194         REGULATOR_SUPPLY("vin", "1-004d"),
195         REGULATOR_SUPPLY("avdd", "0-0077"),
196         REGULATOR_SUPPLY("vdd_irled", NULL),
197         REGULATOR_SUPPLY("vdd_sensor_3v0", NULL),
198         REGULATOR_SUPPLY("vdd_3v0_pm", NULL),
199         REGULATOR_SUPPLY("vaux_3v3", NULL),
200         REGULATOR_SUPPLY("vdd", "0-0044"),
201         REGULATOR_SUPPLY("vdd", "0-004c"),
202         REGULATOR_SUPPLY("avdd", "spi3.2"),
203         REGULATOR_SUPPLY("vdd", "0-0069"),
204         REGULATOR_SUPPLY("vdd", "0-000d"),
205         REGULATOR_SUPPLY("vdd", "0-0078"),
206 };
207
208 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
209         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
210         REGULATOR_SUPPLY("imx132_reg1", NULL),
211         REGULATOR_SUPPLY("imx091_vcm_vdd", NULL),
212         REGULATOR_SUPPLY("vdd", "2-000e"),
213 };
214 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
215         REGULATOR_SUPPLY("vdd_rtc", NULL),
216 };
217 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
218         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
219         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
220 };
221 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
222         REGULATOR_SUPPLY("avdd_cam2", NULL),
223         REGULATOR_SUPPLY("vana", "2-0036"),
224         REGULATOR_SUPPLY("vana_imx132", "2-0036"),
225 };
226
227 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
228         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
229         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
230         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
231         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
232         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
233         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
234         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
235         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
236         REGULATOR_SUPPLY("pwrdet_hv", NULL),
237         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
238
239 };
240
241 static struct regulator_consumer_supply palmas_regen1_supply[] = {
242         REGULATOR_SUPPLY("mic_ventral", NULL),
243 };
244
245 static struct regulator_consumer_supply palmas_regen2_supply[] = {
246         REGULATOR_SUPPLY("vdd_mic", NULL),
247 };
248
249 PALMAS_REGS_PDATA(smps123, 900,  1350, NULL, 0, 0, 0, NORMAL,
250                 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 2500, 0);
251 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, NORMAL,
252                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 2500, 0);
253 PALMAS_REGS_PDATA(smps6, 850,  850, NULL, 0, 0, 1, NORMAL,
254                 0, 0, 0, 0, 0);
255 PALMAS_REGS_PDATA(smps7, 1200,  1200, NULL, 0, 0, 1, NORMAL,
256                 0, 0, 0, 0, 0);
257 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
258                 0, 0, 0, 0, 0);
259 PALMAS_REGS_PDATA(smps9, 2800,  2800, NULL, 1, 0, 1, NORMAL,
260                 0, 0, 0, 0, 0);
261 PALMAS_REGS_PDATA(smps10_out1, 5000,  5000, NULL, 0, 0, 0, 0,
262                 0, 0, 0, 0, 0);
263 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps7), 0, 0, 1, 0,
264                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
265 PALMAS_REGS_PDATA(ldo2, 2800,  3000, NULL, 0, 0, 0, 0,
266                 0, 0, 0, 0, 0);
267 PALMAS_REGS_PDATA(ldo3, 1200,  1200, palmas_rails(smps8), 0, 1, 1, 0,
268                 0, 0, 0, 0, 0);
269 PALMAS_REGS_PDATA(ldo4, 1200,  1200, NULL, 0, 0, 1, 0,
270                 0, 0, 0, 0, 0);
271 PALMAS_REGS_PDATA(ldo5, 2700,  2700, NULL, 0, 0, 1, 0,
272                 0, 0, 0, 0, 0);
273 PALMAS_REGS_PDATA(ldo6, 3000,  3000, NULL, 1, 1, 1, 0,
274                 0, 0, 0, 0, 0);
275 PALMAS_REGS_PDATA(ldo7, 2800,  2800, NULL, 0, 0, 1, 0,
276                 0, 0, 0, 0, 0);
277 PALMAS_REGS_PDATA(ldo8, 900,  900, NULL, 1, 1, 1, 0,
278                 0, 0, 0, 0, 0);
279 PALMAS_REGS_PDATA(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1, 0,
280                 0, 0, 0, 0, 0);
281 PALMAS_REGS_PDATA(ldoln, 2700, 2700, NULL, 0, 0, 1, 0,
282                 0, 0, 0, 0, 0);
283 PALMAS_REGS_PDATA(ldousb, 3300,  3300, NULL, 0, 0, 1, 0,
284                 0, 0, 0, 0, 0);
285 PALMAS_REGS_PDATA(regen1, 4300,  4300, NULL, 0, 0, 0, 0,
286                 0, 0, 0, 0, 0);
287 PALMAS_REGS_PDATA(regen2, 4300,  4300, palmas_rails(smps8), 0, 0, 0, 0,
288                 0, 0, 0, 0, 0);
289
290 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
291 static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = {
292         NULL,
293         PALMAS_REG_PDATA(smps123),
294         NULL,
295         PALMAS_REG_PDATA(smps45),
296         NULL,
297         PALMAS_REG_PDATA(smps6),
298         PALMAS_REG_PDATA(smps7),
299         PALMAS_REG_PDATA(smps8),
300         PALMAS_REG_PDATA(smps9),
301         NULL,
302         PALMAS_REG_PDATA(smps10_out1),
303         PALMAS_REG_PDATA(ldo1),
304         PALMAS_REG_PDATA(ldo2),
305         PALMAS_REG_PDATA(ldo3),
306         PALMAS_REG_PDATA(ldo4),
307         PALMAS_REG_PDATA(ldo5),
308         PALMAS_REG_PDATA(ldo6),
309         PALMAS_REG_PDATA(ldo7),
310         PALMAS_REG_PDATA(ldo8),
311         PALMAS_REG_PDATA(ldo9),
312         NULL,
313         NULL,
314         NULL,
315         NULL,
316         NULL,
317         PALMAS_REG_PDATA(ldoln),
318         PALMAS_REG_PDATA(ldousb),
319         PALMAS_REG_PDATA(regen1),
320         PALMAS_REG_PDATA(regen2),
321         NULL,
322         NULL,
323         NULL,
324 };
325
326 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
327 static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = {
328         NULL,
329         PALMAS_REG_INIT_DATA(smps123),
330         NULL,
331         PALMAS_REG_INIT_DATA(smps45),
332         NULL,
333         PALMAS_REG_INIT_DATA(smps6),
334         PALMAS_REG_INIT_DATA(smps7),
335         PALMAS_REG_INIT_DATA(smps8),
336         PALMAS_REG_INIT_DATA(smps9),
337         NULL,
338         PALMAS_REG_INIT_DATA(smps10_out1),
339         PALMAS_REG_INIT_DATA(ldo1),
340         PALMAS_REG_INIT_DATA(ldo2),
341         PALMAS_REG_INIT_DATA(ldo3),
342         PALMAS_REG_INIT_DATA(ldo4),
343         PALMAS_REG_INIT_DATA(ldo5),
344         PALMAS_REG_INIT_DATA(ldo6),
345         PALMAS_REG_INIT_DATA(ldo7),
346         PALMAS_REG_INIT_DATA(ldo8),
347         PALMAS_REG_INIT_DATA(ldo9),
348         NULL,
349         NULL,
350         NULL,
351         NULL,
352         NULL,
353         PALMAS_REG_INIT_DATA(ldoln),
354         PALMAS_REG_INIT_DATA(ldousb),
355         PALMAS_REG_INIT_DATA(regen1),
356         PALMAS_REG_INIT_DATA(regen2),
357         NULL,
358         NULL,
359         NULL,
360 };
361
362 static int ac_online(void)
363 {
364         return 1;
365 }
366
367 static struct resource pluto_pda_resources[] = {
368         [0] = {
369                 .name   = "ac",
370         },
371 };
372
373 static struct pda_power_pdata pluto_pda_data = {
374         .is_ac_online   = ac_online,
375 };
376
377 static struct platform_device pluto_pda_power_device = {
378         .name           = "pda-power",
379         .id             = -1,
380         .resource       = pluto_pda_resources,
381         .num_resources  = ARRAY_SIZE(pluto_pda_resources),
382         .dev    = {
383                 .platform_data  = &pluto_pda_data,
384         },
385 };
386
387 /* Always ON /Battery regulator */
388 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
389                 REGULATOR_SUPPLY("vdd_sys_cam", NULL),
390                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
391                 REGULATOR_SUPPLY("vdd_sys_com", NULL),
392                 REGULATOR_SUPPLY("vdd_sys_bt", NULL),
393                 REGULATOR_SUPPLY("vdd_sys_audio", NULL),
394                 REGULATOR_SUPPLY("vdd_vbrtr", NULL),
395 };
396
397 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = {
398         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
399         REGULATOR_SUPPLY("imx132_reg2", NULL),
400         REGULATOR_SUPPLY("imx091_i2c_vdd", NULL),
401         REGULATOR_SUPPLY("vdd_1v8_cam12", NULL),
402         REGULATOR_SUPPLY("vif", "2-0010"),
403         REGULATOR_SUPPLY("vif", "2-0036"),
404         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
405 };
406
407 static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = {
408         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
409         REGULATOR_SUPPLY("vdig", "2-0010"),
410         REGULATOR_SUPPLY("vdig", "2-0036"),
411 };
412
413 static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = {
414         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
415         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
416         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
417 };
418
419 static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = {
420         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
421 };
422
423 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = {
424         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
425 };
426
427 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = {
428         REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL),
429 };
430
431 static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = {
432         REGULATOR_SUPPLY("vdd_1v8_mic", NULL),
433 };
434
435 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
436         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
437 };
438
439 static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = {
440         REGULATOR_SUPPLY("vpp_fuse", NULL),
441         REGULATOR_SUPPLY("v_efuse", NULL),
442 };
443
444 /* Macro for defining fixed regulator sub device data */
445 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
446 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
447         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
448         _sdelay)                                                        \
449         static struct regulator_init_data ri_data_##_var =              \
450         {                                                               \
451                 .supply_regulator = _in_supply,                         \
452                 .num_consumer_supplies =                                \
453                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
454                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
455                 .constraints = {                                        \
456                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
457                                         REGULATOR_MODE_STANDBY),        \
458                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
459                                         REGULATOR_CHANGE_STATUS |       \
460                                         REGULATOR_CHANGE_VOLTAGE),      \
461                         .always_on = _always_on,                        \
462                         .boot_on = _boot_on,                            \
463                 },                                                      \
464         };                                                              \
465         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
466         {                                                               \
467                 .supply_name = FIXED_SUPPLY(_name),                     \
468                 .microvolts = _millivolts * 1000,                       \
469                 .gpio = _gpio_nr,                                       \
470                 .gpio_is_open_drain = _open_drain,                      \
471                 .enable_high = _active_high,                            \
472                 .enabled_at_boot = _boot_state,                         \
473                 .init_data = &ri_data_##_var,                           \
474                 .startup_delay = _sdelay                                \
475         };                                                              \
476         static struct platform_device fixed_reg_en_##_var##_dev = {     \
477                 .name = "reg-fixed-voltage",                            \
478                 .id = _id,                                              \
479                 .dev = {                                                \
480                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
481                 },                                                      \
482         }
483
484 FIXED_REG(0,    battery,        battery,
485         NULL,   0,      0,
486         -1,     false, true,    0,      3300,   0);
487
488 FIXED_REG(1,    vdd_1v8_cam,    vdd_1v8_cam,
489         palmas_rails(smps8),    0,      0,
490         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1,  false, true,    0,      1800,
491         0);
492
493 FIXED_REG(2,    vdd_1v2_cam,    vdd_1v2_cam,
494         palmas_rails(smps7),    0,      0,
495         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,  false, true,    0,      1200,
496         0);
497
498 FIXED_REG(3,    avdd_usb3_1v05, avdd_usb3_1v05,
499         palmas_rails(smps8),    0,      0,
500         TEGRA_GPIO_PK5, false,  true,   0,      1050,   0);
501
502 FIXED_REG(4,    vdd_mmc_sdmmc3, vdd_mmc_sdmmc3,
503         palmas_rails(smps9),    0,      0,
504         TEGRA_GPIO_PK1, false,  true,   0,      3300,   0);
505
506 FIXED_REG(5,    vdd_lcd_1v8,    vdd_lcd_1v8,
507         palmas_rails(smps8),    0,      0,
508         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   0,      1800,
509         0);
510
511 FIXED_REG(6,    vdd_lcd_mmc,    vdd_lcd_mmc,
512         palmas_rails(smps9),    0,      0,
513         TEGRA_GPIO_PI4, false,  true,   0,      1800,   0);
514
515 FIXED_REG(7,    vdd_1v8_mic,    vdd_1v8_mic,
516         palmas_rails(smps8),    0,      0,
517         -1,     false,  true,   0,      1800,   0);
518
519 FIXED_REG(8,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
520         NULL,   0,      0,
521         TEGRA_GPIO_PK6, true,   true,   0,      5000,   5000);
522
523 FIXED_REG(9,    vpp_fuse,       vpp_fuse,
524         palmas_rails(smps8),    0,      0,
525         TEGRA_GPIO_PX4, false,  true,   0,      1800,   0);
526
527 /*
528  * Creating the fixed regulator device tables
529  */
530 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
531
532 #define E1580_COMMON_FIXED_REG                  \
533         ADD_FIXED_REG(battery),                 \
534         ADD_FIXED_REG(vdd_1v8_cam),             \
535         ADD_FIXED_REG(vdd_1v2_cam),             \
536         ADD_FIXED_REG(avdd_usb3_1v05),          \
537         ADD_FIXED_REG(vdd_mmc_sdmmc3),          \
538         ADD_FIXED_REG(vdd_lcd_1v8),             \
539         ADD_FIXED_REG(vdd_lcd_mmc),             \
540         ADD_FIXED_REG(vdd_1v8_mic),             \
541         ADD_FIXED_REG(vdd_hdmi_5v0),
542
543 #define E1580_T114_FIXED_REG                    \
544         ADD_FIXED_REG(vpp_fuse),
545
546 /* Gpio switch regulator platform data for Pluto E1580 */
547 static struct platform_device *pfixed_reg_devs[] = {
548         E1580_COMMON_FIXED_REG
549         E1580_T114_FIXED_REG
550 };
551
552 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
553 /* board parameters for cpu dfll */
554 static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = {
555         .sample_rate = 11500,
556
557         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
558         .cf = 10,
559         .ci = 0,
560         .cg = 2,
561
562         .droop_cut_value = 0xF,
563         .droop_restore_ramp = 0x0,
564         .scale_out_ramp = 0x0,
565 };
566 #endif
567
568 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
569 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
570 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
571 static inline void fill_reg_map(void)
572 {
573         int i;
574         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
575                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
576                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
577         }
578 }
579
580 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
581 static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = {
582         .dfll_clk_name = "dfll_cpu",
583         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
584         .u.pmu_i2c = {
585                 .fs_rate = 400000,
586                 .slave_addr = 0xb0,
587                 .reg = 0x23,
588         },
589         .vdd_map = pmu_cpu_vdd_map,
590         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
591         .pmu_undershoot_gb = 100,
592
593         .cfg_param = &pluto_cl_dvfs_param,
594 };
595
596 static int __init pluto_cl_dvfs_init(void)
597 {
598         fill_reg_map();
599         if (tegra_revision < TEGRA_REVISION_A02)
600                 pluto_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
601         tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data;
602         platform_device_register(&tegra_cl_dvfs_device);
603
604         return 0;
605 }
606 #endif
607
608 static struct palmas_dvfs_init_data palmas_dvfs_idata[] = {
609         {
610                 .en_pwm = false,
611         }, {
612                 .en_pwm = true,
613                 .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2,
614                 .reg_id = PALMAS_REG_SMPS6,
615                 .step_20mV = true,
616                 .base_voltage_uV = 500000,
617                 .max_voltage_uV = 1100000,
618         },
619 };
620
621 static struct palmas_pmic_platform_data pmic_platform = {
622         .dvfs_init_data = palmas_dvfs_idata,
623         .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata),
624 };
625
626 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
627         {
628                 .clk32k_id = PALMAS_CLOCK32KG,
629                 .enable = true,
630         }, {
631                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
632                 .enable = true,
633         },
634 };
635
636 static struct palmas_pinctrl_config palmas_pincfg[] = {
637         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
638         PALMAS_PINMUX("vac", "vac", NULL, NULL),
639         PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
640         PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
641         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
642         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
643         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
644         PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
645         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
646         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
647 };
648
649 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
650         .pincfg = palmas_pincfg,
651         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
652         .dvfs1_enable = false,
653         .dvfs2_enable = true,
654 };
655
656 static struct palmas_platform_data palmas_pdata = {
657         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
658         .irq_base = PALMAS_TEGRA_IRQ_BASE,
659         .pmic_pdata = &pmic_platform,
660         .clk32k_init_data =  palmas_clk32k_idata,
661         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
662         .irq_flags = IRQ_TYPE_LEVEL_HIGH,
663         .pinctrl_pdata = &palmas_pinctrl_pdata,
664 };
665
666 static struct i2c_board_info palma_device[] = {
667         {
668                 I2C_BOARD_INFO("tps65913", 0x58),
669                 .irq            = INT_EXTERNAL_PMU,
670                 .platform_data  = &palmas_pdata,
671         },
672 };
673
674 int __init pluto_regulator_init(void)
675 {
676         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
677         u32 pmc_ctrl;
678         int i;
679
680 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
681         pluto_cl_dvfs_init();
682 #endif
683
684         /* TPS65913: Normal state of INT request line is LOW.
685          * configure the power management controller to trigger PMU
686          * interrupts when HIGH.
687          */
688         pmc_ctrl = readl(pmc + PMC_CTRL);
689         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
690
691         /* Enable full constraints */
692         regulator_has_full_constraints();
693
694         /* Tracking configuration */
695         reg_init_data_ldo8.config_flags =
696                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
697                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
698
699         if (get_power_config() & PLUTO_4K_REWORKED) {
700                 /* Account for the change of avdd_hdmi_pll from ldo1 to ldo4 */
701                 reg_idata_ldo1.consumer_supplies = palmas_ldo1_4K_supply;
702                 reg_idata_ldo1.num_consumer_supplies =
703                         ARRAY_SIZE(palmas_ldo1_4K_supply);
704                 reg_idata_ldo4.consumer_supplies = palmas_ldo4_4K_supply;
705                 reg_idata_ldo4.num_consumer_supplies =
706                         ARRAY_SIZE(palmas_ldo4_4K_supply);
707                 reg_init_data_ldo4.roof_floor = PALMAS_EXT_CONTROL_NSLEEP;
708                 reg_idata_ldo4.constraints.always_on = 1;
709                 reg_idata_ldo4.constraints.boot_on = 1;
710         }
711
712         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
713                 pmic_platform.reg_data[i] = pluto_reg_data[i];
714                 pmic_platform.reg_init[i] = pluto_reg_init[i];
715         }
716
717         platform_device_register(&pluto_pda_power_device);
718         i2c_register_board_info(4, palma_device,
719                         ARRAY_SIZE(palma_device));
720         return 0;
721 }
722
723 static int __init pluto_fixed_regulator_init(void)
724 {
725         if (!of_machine_is_compatible("nvidia,pluto"))
726                 return 0;
727
728         return platform_add_devices(pfixed_reg_devs,
729                         ARRAY_SIZE(pfixed_reg_devs));
730 }
731 subsys_initcall_sync(pluto_fixed_regulator_init);
732
733 static struct tegra_io_dpd hv_io = {
734         .name                   = "HV",
735         .io_dpd_reg_index       = 1,
736         .io_dpd_bit             = 6,
737 };
738
739 static void pluto_board_suspend(int state, enum suspend_stage stage)
740 {
741         /* put HV IOs into DPD mode to save additional power */
742         if (state == TEGRA_SUSPEND_LP1 && stage == TEGRA_SUSPEND_BEFORE_CPU) {
743                 gpio_direction_input(TEGRA_GPIO_PK6);
744                 tegra_io_dpd_enable(&hv_io);
745         }
746 }
747
748 static void pluto_board_resume(int state, enum resume_stage stage)
749 {
750         /* bring HV IOs back from DPD mode, GPIO configuration
751          * will be restored by gpio driver
752          */
753         if (state == TEGRA_SUSPEND_LP1 && stage == TEGRA_RESUME_AFTER_CPU)
754                 tegra_io_dpd_disable(&hv_io);
755 }
756
757 static struct tegra_suspend_platform_data pluto_suspend_data = {
758         .cpu_timer      = 300,
759         .cpu_off_timer  = 300,
760         .suspend_mode   = TEGRA_SUSPEND_LP0,
761         .core_timer     = 0x157e,
762         .core_off_timer = 2000,
763         .corereq_high   = true,
764         .sysclkreq_high = true,
765         .cpu_lp2_min_residency = 1000,
766         .min_residency_crail = 20000,
767 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
768         .lp1_lowvolt_support = true,
769         .i2c_base_addr = TEGRA_I2C5_BASE,
770         .pmuslave_addr = 0xB0,
771         .core_reg_addr = 0x2B,
772         .lp1_core_volt_low_cold = 0x33,
773         .lp1_core_volt_low = 0x2e,
774         .lp1_core_volt_high = 0x42,
775 #endif
776         .board_suspend  = pluto_board_suspend,
777         .board_resume   = pluto_board_resume,
778 };
779
780 int __init pluto_suspend_init(void)
781 {
782         tegra_init_suspend(&pluto_suspend_data);
783         return 0;
784 }
785
786 int __init pluto_edp_init(void)
787 {
788         unsigned int regulator_mA;
789
790         regulator_mA = get_maximum_cpu_current_supported();
791         if (!regulator_mA)
792                 regulator_mA = 9000;
793
794         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
795         tegra_init_cpu_edp_limits(regulator_mA);
796
797         regulator_mA = get_maximum_core_current_supported();
798         if (!regulator_mA)
799                 regulator_mA = 4000;
800
801         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
802         tegra_init_core_edp_limits(regulator_mA);
803
804         return 0;
805 }
806
807 static struct pid_thermal_gov_params soctherm_pid_params = {
808         .max_err_temp = 9000,
809         .max_err_gain = 1000,
810
811         .gain_p = 1000,
812         .gain_d = 0,
813
814         .up_compensation = 20,
815         .down_compensation = 20,
816 };
817
818 static struct thermal_zone_params soctherm_tzp = {
819         .governor_name = "pid_thermal_gov",
820         .governor_params = &soctherm_pid_params,
821 };
822
823 static struct tegra_tsensor_pmu_data tpdata_palmas = {
824         .reset_tegra = 1,
825         .pmu_16bit_ops = 0,
826         .controller_type = 0,
827         .pmu_i2c_addr = 0x58,
828         .i2c_controller_id = 4,
829         .poweroff_reg_addr = 0xa0,
830         .poweroff_reg_data = 0x0,
831 };
832
833 static struct soctherm_platform_data pluto_soctherm_data = {
834         .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
835         .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
836         .therm = {
837                 [THERM_CPU] = {
838                         .zone_enable = true,
839                         .passive_delay = 1000,
840                         .hotspot_offset = 6000,
841                         .num_trips = 3,
842                         .trips = {
843                                 {
844                                         .cdev_type = "tegra-balanced",
845                                         .trip_temp = 90000,
846                                         .trip_type = THERMAL_TRIP_PASSIVE,
847                                         .upper = THERMAL_NO_LIMIT,
848                                         .lower = THERMAL_NO_LIMIT,
849                                 },
850                                 {
851                                         .cdev_type = "tegra-heavy",
852                                         .trip_temp = 100000,
853                                         .trip_type = THERMAL_TRIP_HOT,
854                                         .upper = THERMAL_NO_LIMIT,
855                                         .lower = THERMAL_NO_LIMIT,
856                                 },
857                                 {
858                                         .cdev_type = "tegra-shutdown",
859                                         .trip_temp = 102000,
860                                         .trip_type = THERMAL_TRIP_CRITICAL,
861                                         .upper = THERMAL_NO_LIMIT,
862                                         .lower = THERMAL_NO_LIMIT,
863                                 },
864                         },
865                         .tzp = &soctherm_tzp,
866                 },
867                 [THERM_GPU] = {
868                         .zone_enable = true,
869                         .passive_delay = 1000,
870                         .hotspot_offset = 6000,
871                         .num_trips = 3,
872                         .trips = {
873                                 {
874                                         .cdev_type = "tegra-balanced",
875                                         .trip_temp = 90000,
876                                         .trip_type = THERMAL_TRIP_PASSIVE,
877                                         .upper = THERMAL_NO_LIMIT,
878                                         .lower = THERMAL_NO_LIMIT,
879                                 },
880                                 {
881                                         .cdev_type = "tegra-heavy",
882                                         .trip_temp = 100000,
883                                         .trip_type = THERMAL_TRIP_HOT,
884                                         .upper = THERMAL_NO_LIMIT,
885                                         .lower = THERMAL_NO_LIMIT,
886                                 },
887                                 {
888                                         .cdev_type = "tegra-shutdown",
889                                         .trip_temp = 102000,
890                                         .trip_type = THERMAL_TRIP_CRITICAL,
891                                         .upper = THERMAL_NO_LIMIT,
892                                         .lower = THERMAL_NO_LIMIT,
893                                 },
894                         },
895                         .tzp = &soctherm_tzp,
896                 },
897                 [THERM_PLL] = {
898                         .zone_enable = true,
899                 },
900         },
901         .throttle = {
902                 [THROTTLE_HEAVY] = {
903                         .priority = 100,
904                         .devs = {
905                                 [THROTTLE_DEV_CPU] = {
906                                         .enable = true,
907                                         .depth = 80,
908                                 },
909                                 [THROTTLE_DEV_GPU] = {
910                                         .depth = 80,
911                                         .enable = true,
912                                 },
913                         },
914                 },
915                 [THROTTLE_OC4] = {
916                         .throt_mode = BRIEF,
917                         .polarity = 1,
918                         .intr = true,
919                         .devs = {
920                                 [THROTTLE_DEV_CPU] = {
921                                         .enable = true,
922                                         .depth = 50,
923                                 },
924                                 [THROTTLE_DEV_GPU] = {
925                                         .enable = true,
926                                         .depth = 50,
927                                 },
928                         },
929                 },
930         },
931         .tshut_pmu_trip_data = &tpdata_palmas,
932 };
933
934 int __init pluto_soctherm_init(void)
935 {
936         tegra_platform_edp_init(pluto_soctherm_data.therm[THERM_CPU].trips,
937                         &pluto_soctherm_data.therm[THERM_CPU].num_trips,
938                         6000);  /* edp temperature margin */
939         tegra_add_cpu_vmax_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
940                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
941         tegra_add_core_edp_trips(pluto_soctherm_data.therm[THERM_CPU].trips,
942                         &pluto_soctherm_data.therm[THERM_CPU].num_trips);
943
944         return tegra11_soctherm_init(&pluto_soctherm_data);
945 }