2 * arch/arm/mach-tegra/board-pluto-memory.c
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/platform_data/tegra_emc.h>
24 #include <linux/memblock.h>
25 #include <asm-generic/sizes.h>
28 #include "board-pluto.h"
29 #include "tegra-board-id.h"
30 #include "tegra11_emc.h"
34 static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
37 12750, /* SDRAM frequency */
38 900, /* min voltage */
39 "pll_p", /* clock source id */
40 0x4000003e, /* CLK_SOURCE_EMC */
41 99, /* number of burst_regs */
42 30, /* number of trim_regs (each channel) */
43 11, /* number of up_down_regs */
45 0x00000000, /* EMC_RC */
46 0x00000003, /* EMC_RFC */
47 0x00000000, /* EMC_RFC_SLR */
48 0x00000002, /* EMC_RAS */
49 0x00000002, /* EMC_RP */
50 0x00000006, /* EMC_R2W */
51 0x00000008, /* EMC_W2R */
52 0x00000003, /* EMC_R2P */
53 0x0000000a, /* EMC_W2P */
54 0x00000002, /* EMC_RD_RCD */
55 0x00000002, /* EMC_WR_RCD */
56 0x00000001, /* EMC_RRD */
57 0x00000001, /* EMC_REXT */
58 0x00000000, /* EMC_WEXT */
59 0x00000003, /* EMC_WDV */
60 0x0000000f, /* EMC_WDV_MASK */
61 0x00000005, /* EMC_IBDLY */
62 0x00010000, /* EMC_PUTERM_EXTRA */
63 0x00000000, /* EMC_CDB_CNTL_2 */
64 0x00000004, /* EMC_QRST */
65 0x0000000f, /* EMC_RDV_MASK */
66 0x0000002f, /* EMC_REFRESH */
67 0x00000000, /* EMC_BURST_REFRESH_NUM */
68 0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */
69 0x00000002, /* EMC_PDEX2WR */
70 0x00000002, /* EMC_PDEX2RD */
71 0x00000002, /* EMC_PCHG2PDEN */
72 0x00000000, /* EMC_ACT2PDEN */
73 0x00000001, /* EMC_AR2PDEN */
74 0x0000000c, /* EMC_RW2PDEN */
75 0x00000002, /* EMC_TXSR */
76 0x00000002, /* EMC_TXSRDLL */
77 0x00000003, /* EMC_TCKE */
78 0x00000003, /* EMC_TCKESR */
79 0x00000003, /* EMC_TPD */
80 0x00000008, /* EMC_TFAW */
81 0x00000004, /* EMC_TRPAB */
82 0x00000001, /* EMC_TCLKSTABLE */
83 0x00000003, /* EMC_TCLKSTOP */
84 0x00000036, /* EMC_TREFBW */
85 0x00000005, /* EMC_QUSE_EXTRA */
86 0x00000020, /* EMC_ODT_WRITE */
87 0x00000000, /* EMC_ODT_READ */
88 0x0001aa86, /* EMC_FBIO_CFG5 */
89 0x005800a8, /* EMC_CFG_DIG_DLL */
90 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
91 0x00048000, /* EMC_DLL_XFORM_DQS4 */
92 0x00048000, /* EMC_DLL_XFORM_DQS5 */
93 0x00048000, /* EMC_DLL_XFORM_DQS6 */
94 0x00048000, /* EMC_DLL_XFORM_DQS7 */
95 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
96 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
97 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
98 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
99 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
100 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
101 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
102 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
103 0x00010220, /* EMC_XM2CMDPADCTRL */
104 0x00000000, /* EMC_XM2CMDPADCTRL4 */
105 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
106 0x00000000, /* EMC_XM2DQPADCTRL2 */
107 0x77ffc004, /* EMC_XM2CLKPADCTRL */
108 0x81f1f008, /* EMC_XM2COMPPADCTRL */
109 0x00000000, /* EMC_XM2VTTGENPADCTRL */
110 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
111 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
112 0x00000000, /* EMC_TXDSRVTTGEN */
113 0x02000100, /* EMC_FBIO_SPARE */
114 0x00000802, /* EMC_CTT_TERM_CTRL */
115 0x00064000, /* EMC_ZCAL_INTERVAL */
116 0x0000000f, /* EMC_ZCAL_WAIT_CNT */
117 0x000f000f, /* EMC_MRS_WAIT_CNT */
118 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
119 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
120 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
121 0x00000000, /* EMC_CTT */
122 0x00000000, /* EMC_CTT_DURATION */
123 0x80000165, /* EMC_DYN_SELF_REF_CONTROL */
124 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
125 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
126 0x40040001, /* MC_EMEM_ARB_CFG */
127 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
128 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
129 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
130 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
131 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
132 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
133 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
134 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
135 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
136 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
137 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
138 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
139 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
140 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
141 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
142 0x77c30303, /* MC_EMEM_ARB_MISC0 */
143 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
146 0x00000000, /* EMC_CDB_CNTL_1 */
147 0x00000004, /* EMC_FBIO_CFG6 */
148 0x00000007, /* EMC_QUSE */
149 0x00000003, /* EMC_EINPUT */
150 0x00000005, /* EMC_EINPUT_DURATION */
151 0x00048000, /* EMC_DLL_XFORM_DQS0 */
152 0x0000000b, /* EMC_QSAFE */
153 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
154 0x0000000d, /* EMC_RDV */
155 0x00249249, /* EMC_XM2DQSPADCTRL4 */
156 0x20820800, /* EMC_XM2DQSPADCTRL3 */
157 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
158 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
159 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
160 0x00000909, /* EMC_XM2CLKPADCTRL2 */
161 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
162 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
163 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
164 0x00048000, /* EMC_DLL_XFORM_DQS1 */
165 0x00048000, /* EMC_DLL_XFORM_DQS2 */
166 0x00048000, /* EMC_DLL_XFORM_DQS3 */
167 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
168 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
169 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
170 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
171 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
172 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
173 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
174 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
175 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
178 0x00000000, /* EMC_CDB_CNTL_1 */
179 0x00000004, /* EMC_FBIO_CFG6 */
180 0x00000007, /* EMC_QUSE */
181 0x00000003, /* EMC_EINPUT */
182 0x00000005, /* EMC_EINPUT_DURATION */
183 0x00048000, /* EMC_DLL_XFORM_DQS0 */
184 0x0000000b, /* EMC_QSAFE */
185 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
186 0x0000000d, /* EMC_RDV */
187 0x00249249, /* EMC_XM2DQSPADCTRL4 */
188 0x20820800, /* EMC_XM2DQSPADCTRL3 */
189 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
190 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
191 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
192 0x00000909, /* EMC_XM2CLKPADCTRL2 */
193 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
194 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
195 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
196 0x00048000, /* EMC_DLL_XFORM_DQS1 */
197 0x00048000, /* EMC_DLL_XFORM_DQS2 */
198 0x00048000, /* EMC_DLL_XFORM_DQS3 */
199 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
200 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
201 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
202 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
203 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
204 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
205 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
206 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
207 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
210 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
211 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
212 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
213 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
214 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
215 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
216 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
217 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
218 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
219 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
220 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
222 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
223 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
224 0xf320000e, /* EMC_CFG */
225 0x00000000, /* Mode Register 0 */
226 0x00010083, /* Mode Register 1 */
227 0x00020004, /* Mode Register 2 */
228 0x000b0000, /* Mode Register 4 */
229 57820, /* expected dvfs latency (ns) */
232 0x41, /* Rev 4.0.3 */
233 20400, /* SDRAM frequency */
234 900, /* min voltage */
235 "pll_p", /* clock source id */
236 0x40000026, /* CLK_SOURCE_EMC */
237 99, /* number of burst_regs */
238 30, /* number of trim_regs (each channel) */
239 11, /* number of up_down_regs */
241 0x00000001, /* EMC_RC */
242 0x00000003, /* EMC_RFC */
243 0x00000000, /* EMC_RFC_SLR */
244 0x00000002, /* EMC_RAS */
245 0x00000002, /* EMC_RP */
246 0x00000006, /* EMC_R2W */
247 0x00000008, /* EMC_W2R */
248 0x00000003, /* EMC_R2P */
249 0x0000000a, /* EMC_W2P */
250 0x00000002, /* EMC_RD_RCD */
251 0x00000002, /* EMC_WR_RCD */
252 0x00000001, /* EMC_RRD */
253 0x00000001, /* EMC_REXT */
254 0x00000000, /* EMC_WEXT */
255 0x00000003, /* EMC_WDV */
256 0x0000000f, /* EMC_WDV_MASK */
257 0x00000005, /* EMC_IBDLY */
258 0x00010000, /* EMC_PUTERM_EXTRA */
259 0x00000000, /* EMC_CDB_CNTL_2 */
260 0x00000004, /* EMC_QRST */
261 0x0000000f, /* EMC_RDV_MASK */
262 0x0000004c, /* EMC_REFRESH */
263 0x00000000, /* EMC_BURST_REFRESH_NUM */
264 0x00000013, /* EMC_PRE_REFRESH_REQ_CNT */
265 0x00000002, /* EMC_PDEX2WR */
266 0x00000002, /* EMC_PDEX2RD */
267 0x00000002, /* EMC_PCHG2PDEN */
268 0x00000000, /* EMC_ACT2PDEN */
269 0x00000001, /* EMC_AR2PDEN */
270 0x0000000c, /* EMC_RW2PDEN */
271 0x00000003, /* EMC_TXSR */
272 0x00000003, /* EMC_TXSRDLL */
273 0x00000003, /* EMC_TCKE */
274 0x00000003, /* EMC_TCKESR */
275 0x00000003, /* EMC_TPD */
276 0x00000008, /* EMC_TFAW */
277 0x00000004, /* EMC_TRPAB */
278 0x00000001, /* EMC_TCLKSTABLE */
279 0x00000003, /* EMC_TCLKSTOP */
280 0x00000055, /* EMC_TREFBW */
281 0x00000005, /* EMC_QUSE_EXTRA */
282 0x00000020, /* EMC_ODT_WRITE */
283 0x00000000, /* EMC_ODT_READ */
284 0x0001aa86, /* EMC_FBIO_CFG5 */
285 0x005800a8, /* EMC_CFG_DIG_DLL */
286 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
287 0x00048000, /* EMC_DLL_XFORM_DQS4 */
288 0x00048000, /* EMC_DLL_XFORM_DQS5 */
289 0x00048000, /* EMC_DLL_XFORM_DQS6 */
290 0x00048000, /* EMC_DLL_XFORM_DQS7 */
291 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
292 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
293 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
294 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
295 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
296 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
297 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
298 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
299 0x00010220, /* EMC_XM2CMDPADCTRL */
300 0x00000000, /* EMC_XM2CMDPADCTRL4 */
301 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
302 0x00000000, /* EMC_XM2DQPADCTRL2 */
303 0x77ffc004, /* EMC_XM2CLKPADCTRL */
304 0x81f1f008, /* EMC_XM2COMPPADCTRL */
305 0x00000000, /* EMC_XM2VTTGENPADCTRL */
306 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
307 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
308 0x00000000, /* EMC_TXDSRVTTGEN */
309 0x02000100, /* EMC_FBIO_SPARE */
310 0x00000802, /* EMC_CTT_TERM_CTRL */
311 0x00064000, /* EMC_ZCAL_INTERVAL */
312 0x0000000f, /* EMC_ZCAL_WAIT_CNT */
313 0x000f000f, /* EMC_MRS_WAIT_CNT */
314 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
315 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
316 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
317 0x00000000, /* EMC_CTT */
318 0x00000000, /* EMC_CTT_DURATION */
319 0x8000019f, /* EMC_DYN_SELF_REF_CONTROL */
320 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
321 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
322 0x40020001, /* MC_EMEM_ARB_CFG */
323 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
324 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
325 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
326 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
327 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
328 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
329 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
330 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
331 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
332 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
333 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
334 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
335 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
336 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
337 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
338 0x74e30303, /* MC_EMEM_ARB_MISC0 */
339 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
342 0x00000000, /* EMC_CDB_CNTL_1 */
343 0x00000004, /* EMC_FBIO_CFG6 */
344 0x00000007, /* EMC_QUSE */
345 0x00000003, /* EMC_EINPUT */
346 0x00000005, /* EMC_EINPUT_DURATION */
347 0x00048000, /* EMC_DLL_XFORM_DQS0 */
348 0x0000000b, /* EMC_QSAFE */
349 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
350 0x0000000d, /* EMC_RDV */
351 0x00249249, /* EMC_XM2DQSPADCTRL4 */
352 0x20820800, /* EMC_XM2DQSPADCTRL3 */
353 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
354 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
355 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
356 0x00000909, /* EMC_XM2CLKPADCTRL2 */
357 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
358 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
359 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
360 0x00048000, /* EMC_DLL_XFORM_DQS1 */
361 0x00048000, /* EMC_DLL_XFORM_DQS2 */
362 0x00048000, /* EMC_DLL_XFORM_DQS3 */
363 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
364 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
365 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
366 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
367 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
368 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
369 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
370 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
371 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
374 0x00000000, /* EMC_CDB_CNTL_1 */
375 0x00000004, /* EMC_FBIO_CFG6 */
376 0x00000007, /* EMC_QUSE */
377 0x00000003, /* EMC_EINPUT */
378 0x00000005, /* EMC_EINPUT_DURATION */
379 0x00048000, /* EMC_DLL_XFORM_DQS0 */
380 0x0000000b, /* EMC_QSAFE */
381 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
382 0x0000000d, /* EMC_RDV */
383 0x00249249, /* EMC_XM2DQSPADCTRL4 */
384 0x20820800, /* EMC_XM2DQSPADCTRL3 */
385 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
386 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
387 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
388 0x00000909, /* EMC_XM2CLKPADCTRL2 */
389 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
390 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
391 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
392 0x00048000, /* EMC_DLL_XFORM_DQS1 */
393 0x00048000, /* EMC_DLL_XFORM_DQS2 */
394 0x00048000, /* EMC_DLL_XFORM_DQS3 */
395 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
396 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
397 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
398 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
399 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
400 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
401 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
402 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
403 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
406 0x00000014, /* MC_PTSA_GRANT_DECREMENT */
407 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
408 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
409 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
410 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
411 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
412 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
413 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
414 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
415 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
416 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
418 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
419 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
420 0xf320000e, /* EMC_CFG */
421 0x00000000, /* Mode Register 0 */
422 0x00010083, /* Mode Register 1 */
423 0x00020004, /* Mode Register 2 */
424 0x000b0000, /* Mode Register 4 */
425 35610, /* expected dvfs latency (ns) */
428 0x41, /* Rev 4.0.3 */
429 40800, /* SDRAM frequency */
430 900, /* min voltage */
431 "pll_p", /* clock source id */
432 0x40000012, /* CLK_SOURCE_EMC */
433 99, /* number of burst_regs */
434 30, /* number of trim_regs (each channel) */
435 11, /* number of up_down_regs */
437 0x00000002, /* EMC_RC */
438 0x00000005, /* EMC_RFC */
439 0x00000000, /* EMC_RFC_SLR */
440 0x00000002, /* EMC_RAS */
441 0x00000002, /* EMC_RP */
442 0x00000006, /* EMC_R2W */
443 0x00000008, /* EMC_W2R */
444 0x00000003, /* EMC_R2P */
445 0x0000000a, /* EMC_W2P */
446 0x00000002, /* EMC_RD_RCD */
447 0x00000002, /* EMC_WR_RCD */
448 0x00000001, /* EMC_RRD */
449 0x00000001, /* EMC_REXT */
450 0x00000000, /* EMC_WEXT */
451 0x00000003, /* EMC_WDV */
452 0x0000000f, /* EMC_WDV_MASK */
453 0x00000005, /* EMC_IBDLY */
454 0x00010000, /* EMC_PUTERM_EXTRA */
455 0x00000000, /* EMC_CDB_CNTL_2 */
456 0x00000004, /* EMC_QRST */
457 0x0000000f, /* EMC_RDV_MASK */
458 0x0000009a, /* EMC_REFRESH */
459 0x00000000, /* EMC_BURST_REFRESH_NUM */
460 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
461 0x00000002, /* EMC_PDEX2WR */
462 0x00000002, /* EMC_PDEX2RD */
463 0x00000002, /* EMC_PCHG2PDEN */
464 0x00000000, /* EMC_ACT2PDEN */
465 0x00000001, /* EMC_AR2PDEN */
466 0x0000000c, /* EMC_RW2PDEN */
467 0x00000006, /* EMC_TXSR */
468 0x00000006, /* EMC_TXSRDLL */
469 0x00000003, /* EMC_TCKE */
470 0x00000003, /* EMC_TCKESR */
471 0x00000003, /* EMC_TPD */
472 0x00000008, /* EMC_TFAW */
473 0x00000004, /* EMC_TRPAB */
474 0x00000001, /* EMC_TCLKSTABLE */
475 0x00000003, /* EMC_TCLKSTOP */
476 0x000000aa, /* EMC_TREFBW */
477 0x00000005, /* EMC_QUSE_EXTRA */
478 0x00000020, /* EMC_ODT_WRITE */
479 0x00000000, /* EMC_ODT_READ */
480 0x0001aa86, /* EMC_FBIO_CFG5 */
481 0x005800a8, /* EMC_CFG_DIG_DLL */
482 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
483 0x00048000, /* EMC_DLL_XFORM_DQS4 */
484 0x00048000, /* EMC_DLL_XFORM_DQS5 */
485 0x00048000, /* EMC_DLL_XFORM_DQS6 */
486 0x00048000, /* EMC_DLL_XFORM_DQS7 */
487 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
488 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
489 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
490 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
491 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
492 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
493 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
494 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
495 0x00010220, /* EMC_XM2CMDPADCTRL */
496 0x00000000, /* EMC_XM2CMDPADCTRL4 */
497 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
498 0x00000000, /* EMC_XM2DQPADCTRL2 */
499 0x77ffc004, /* EMC_XM2CLKPADCTRL */
500 0x81f1f008, /* EMC_XM2COMPPADCTRL */
501 0x00000000, /* EMC_XM2VTTGENPADCTRL */
502 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
503 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
504 0x00000000, /* EMC_TXDSRVTTGEN */
505 0x02000100, /* EMC_FBIO_SPARE */
506 0x00000802, /* EMC_CTT_TERM_CTRL */
507 0x00064000, /* EMC_ZCAL_INTERVAL */
508 0x0000000f, /* EMC_ZCAL_WAIT_CNT */
509 0x000f000f, /* EMC_MRS_WAIT_CNT */
510 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
511 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
512 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
513 0x00000000, /* EMC_CTT */
514 0x00000000, /* EMC_CTT_DURATION */
515 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
516 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
517 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
518 0xa0000001, /* MC_EMEM_ARB_CFG */
519 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
520 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
521 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
522 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
523 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
524 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
525 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
526 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
527 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
528 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
529 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
530 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
531 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
532 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
533 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
534 0x73030303, /* MC_EMEM_ARB_MISC0 */
535 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
538 0x00000000, /* EMC_CDB_CNTL_1 */
539 0x00000004, /* EMC_FBIO_CFG6 */
540 0x00000007, /* EMC_QUSE */
541 0x00000003, /* EMC_EINPUT */
542 0x00000005, /* EMC_EINPUT_DURATION */
543 0x00048000, /* EMC_DLL_XFORM_DQS0 */
544 0x0000000b, /* EMC_QSAFE */
545 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
546 0x0000000d, /* EMC_RDV */
547 0x00249249, /* EMC_XM2DQSPADCTRL4 */
548 0x20820800, /* EMC_XM2DQSPADCTRL3 */
549 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
550 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
551 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
552 0x00000909, /* EMC_XM2CLKPADCTRL2 */
553 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
554 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
555 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
556 0x00048000, /* EMC_DLL_XFORM_DQS1 */
557 0x00048000, /* EMC_DLL_XFORM_DQS2 */
558 0x00048000, /* EMC_DLL_XFORM_DQS3 */
559 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
560 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
561 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
562 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
563 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
564 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
565 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
566 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
567 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
570 0x00000000, /* EMC_CDB_CNTL_1 */
571 0x00000004, /* EMC_FBIO_CFG6 */
572 0x00000007, /* EMC_QUSE */
573 0x00000003, /* EMC_EINPUT */
574 0x00000005, /* EMC_EINPUT_DURATION */
575 0x00048000, /* EMC_DLL_XFORM_DQS0 */
576 0x0000000b, /* EMC_QSAFE */
577 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
578 0x0000000d, /* EMC_RDV */
579 0x00249249, /* EMC_XM2DQSPADCTRL4 */
580 0x20820800, /* EMC_XM2DQSPADCTRL3 */
581 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
582 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
583 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
584 0x00000909, /* EMC_XM2CLKPADCTRL2 */
585 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
586 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
587 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
588 0x00048000, /* EMC_DLL_XFORM_DQS1 */
589 0x00048000, /* EMC_DLL_XFORM_DQS2 */
590 0x00048000, /* EMC_DLL_XFORM_DQS3 */
591 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
592 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
593 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
594 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
595 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
596 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
597 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
598 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
599 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
602 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
603 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
604 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
605 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
606 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
607 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
608 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
609 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
610 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
611 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
612 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
614 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
615 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
616 0xf320000e, /* EMC_CFG */
617 0x00000000, /* Mode Register 0 */
618 0x00010083, /* Mode Register 1 */
619 0x00020004, /* Mode Register 2 */
620 0x000b0000, /* Mode Register 4 */
621 20850, /* expected dvfs latency (ns) */
624 0x41, /* Rev 4.0.3 */
625 68000, /* SDRAM frequency */
626 900, /* min voltage */
627 "pll_p", /* clock source id */
628 0x4000000a, /* CLK_SOURCE_EMC */
629 99, /* number of burst_regs */
630 30, /* number of trim_regs (each channel) */
631 11, /* number of up_down_regs */
633 0x00000004, /* EMC_RC */
634 0x00000008, /* EMC_RFC */
635 0x00000000, /* EMC_RFC_SLR */
636 0x00000002, /* EMC_RAS */
637 0x00000002, /* EMC_RP */
638 0x00000006, /* EMC_R2W */
639 0x00000008, /* EMC_W2R */
640 0x00000003, /* EMC_R2P */
641 0x0000000a, /* EMC_W2P */
642 0x00000002, /* EMC_RD_RCD */
643 0x00000002, /* EMC_WR_RCD */
644 0x00000001, /* EMC_RRD */
645 0x00000001, /* EMC_REXT */
646 0x00000000, /* EMC_WEXT */
647 0x00000003, /* EMC_WDV */
648 0x0000000f, /* EMC_WDV_MASK */
649 0x00000005, /* EMC_IBDLY */
650 0x00010000, /* EMC_PUTERM_EXTRA */
651 0x00000000, /* EMC_CDB_CNTL_2 */
652 0x00000004, /* EMC_QRST */
653 0x0000000f, /* EMC_RDV_MASK */
654 0x00000101, /* EMC_REFRESH */
655 0x00000000, /* EMC_BURST_REFRESH_NUM */
656 0x00000040, /* EMC_PRE_REFRESH_REQ_CNT */
657 0x00000002, /* EMC_PDEX2WR */
658 0x00000002, /* EMC_PDEX2RD */
659 0x00000002, /* EMC_PCHG2PDEN */
660 0x00000000, /* EMC_ACT2PDEN */
661 0x00000001, /* EMC_AR2PDEN */
662 0x0000000c, /* EMC_RW2PDEN */
663 0x0000000a, /* EMC_TXSR */
664 0x0000000a, /* EMC_TXSRDLL */
665 0x00000003, /* EMC_TCKE */
666 0x00000003, /* EMC_TCKESR */
667 0x00000003, /* EMC_TPD */
668 0x00000008, /* EMC_TFAW */
669 0x00000004, /* EMC_TRPAB */
670 0x00000001, /* EMC_TCLKSTABLE */
671 0x00000003, /* EMC_TCLKSTOP */
672 0x0000011b, /* EMC_TREFBW */
673 0x00000005, /* EMC_QUSE_EXTRA */
674 0x00000020, /* EMC_ODT_WRITE */
675 0x00000000, /* EMC_ODT_READ */
676 0x0001aa86, /* EMC_FBIO_CFG5 */
677 0x005800a8, /* EMC_CFG_DIG_DLL */
678 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
679 0x00048000, /* EMC_DLL_XFORM_DQS4 */
680 0x00048000, /* EMC_DLL_XFORM_DQS5 */
681 0x00048000, /* EMC_DLL_XFORM_DQS6 */
682 0x00048000, /* EMC_DLL_XFORM_DQS7 */
683 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
684 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
685 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
686 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
687 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
688 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
689 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
690 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
691 0x00010220, /* EMC_XM2CMDPADCTRL */
692 0x00000000, /* EMC_XM2CMDPADCTRL4 */
693 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
694 0x00000000, /* EMC_XM2DQPADCTRL2 */
695 0x77ffc004, /* EMC_XM2CLKPADCTRL */
696 0x81f1f008, /* EMC_XM2COMPPADCTRL */
697 0x00000000, /* EMC_XM2VTTGENPADCTRL */
698 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
699 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
700 0x00000000, /* EMC_TXDSRVTTGEN */
701 0x02000100, /* EMC_FBIO_SPARE */
702 0x00000802, /* EMC_CTT_TERM_CTRL */
703 0x00064000, /* EMC_ZCAL_INTERVAL */
704 0x00000019, /* EMC_ZCAL_WAIT_CNT */
705 0x000f000f, /* EMC_MRS_WAIT_CNT */
706 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
707 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
708 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
709 0x00000000, /* EMC_CTT */
710 0x00000000, /* EMC_CTT_DURATION */
711 0x80000309, /* EMC_DYN_SELF_REF_CONTROL */
712 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
713 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
714 0x00000001, /* MC_EMEM_ARB_CFG */
715 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
716 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
717 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
718 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
719 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
720 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
721 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
722 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
723 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
724 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
725 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
726 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
727 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
728 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
729 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
730 0x72630403, /* MC_EMEM_ARB_MISC0 */
731 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
734 0x00000000, /* EMC_CDB_CNTL_1 */
735 0x00000004, /* EMC_FBIO_CFG6 */
736 0x00000007, /* EMC_QUSE */
737 0x00000003, /* EMC_EINPUT */
738 0x00000005, /* EMC_EINPUT_DURATION */
739 0x00048000, /* EMC_DLL_XFORM_DQS0 */
740 0x0000000b, /* EMC_QSAFE */
741 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
742 0x0000000d, /* EMC_RDV */
743 0x00249249, /* EMC_XM2DQSPADCTRL4 */
744 0x20820800, /* EMC_XM2DQSPADCTRL3 */
745 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
746 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
747 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
748 0x00000909, /* EMC_XM2CLKPADCTRL2 */
749 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
750 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
751 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
752 0x00048000, /* EMC_DLL_XFORM_DQS1 */
753 0x00048000, /* EMC_DLL_XFORM_DQS2 */
754 0x00048000, /* EMC_DLL_XFORM_DQS3 */
755 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
756 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
757 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
758 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
759 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
760 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
761 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
762 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
763 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
766 0x00000000, /* EMC_CDB_CNTL_1 */
767 0x00000004, /* EMC_FBIO_CFG6 */
768 0x00000007, /* EMC_QUSE */
769 0x00000003, /* EMC_EINPUT */
770 0x00000005, /* EMC_EINPUT_DURATION */
771 0x00048000, /* EMC_DLL_XFORM_DQS0 */
772 0x0000000b, /* EMC_QSAFE */
773 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
774 0x0000000d, /* EMC_RDV */
775 0x00249249, /* EMC_XM2DQSPADCTRL4 */
776 0x20820800, /* EMC_XM2DQSPADCTRL3 */
777 0x0006c000, /* EMC_DLL_XFORM_DQ0 */
778 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
779 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
780 0x00000909, /* EMC_XM2CLKPADCTRL2 */
781 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
782 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
783 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
784 0x00048000, /* EMC_DLL_XFORM_DQS1 */
785 0x00048000, /* EMC_DLL_XFORM_DQS2 */
786 0x00048000, /* EMC_DLL_XFORM_DQS3 */
787 0x0006c000, /* EMC_DLL_XFORM_DQ1 */
788 0x0006c000, /* EMC_DLL_XFORM_DQ2 */
789 0x0006c000, /* EMC_DLL_XFORM_DQ3 */
790 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
791 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
792 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
793 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
794 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
795 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
798 0x00000046, /* MC_PTSA_GRANT_DECREMENT */
799 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
800 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
801 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
802 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
803 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
804 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
805 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
806 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
807 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
808 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
810 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
811 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
812 0xf320000e, /* EMC_CFG */
813 0x00000000, /* Mode Register 0 */
814 0x00010083, /* Mode Register 1 */
815 0x00020004, /* Mode Register 2 */
816 0x000b0000, /* Mode Register 4 */
817 10720, /* expected dvfs latency (ns) */
820 0x41, /* Rev 4.0.3 */
821 102000, /* SDRAM frequency */
822 900, /* min voltage */
823 "pll_p", /* clock source id */
824 0x40000006, /* CLK_SOURCE_EMC */
825 99, /* number of burst_regs */
826 30, /* number of trim_regs (each channel) */
827 11, /* number of up_down_regs */
829 0x00000006, /* EMC_RC */
830 0x0000000d, /* EMC_RFC */
831 0x00000000, /* EMC_RFC_SLR */
832 0x00000004, /* EMC_RAS */
833 0x00000002, /* EMC_RP */
834 0x00000006, /* EMC_R2W */
835 0x00000008, /* EMC_W2R */
836 0x00000003, /* EMC_R2P */
837 0x0000000a, /* EMC_W2P */
838 0x00000002, /* EMC_RD_RCD */
839 0x00000002, /* EMC_WR_RCD */
840 0x00000001, /* EMC_RRD */
841 0x00000001, /* EMC_REXT */
842 0x00000000, /* EMC_WEXT */
843 0x00000003, /* EMC_WDV */
844 0x0000000f, /* EMC_WDV_MASK */
845 0x00000005, /* EMC_IBDLY */
846 0x00010000, /* EMC_PUTERM_EXTRA */
847 0x00000000, /* EMC_CDB_CNTL_2 */
848 0x00000004, /* EMC_QRST */
849 0x0000000f, /* EMC_RDV_MASK */
850 0x00000181, /* EMC_REFRESH */
851 0x00000000, /* EMC_BURST_REFRESH_NUM */
852 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
853 0x00000002, /* EMC_PDEX2WR */
854 0x00000002, /* EMC_PDEX2RD */
855 0x00000002, /* EMC_PCHG2PDEN */
856 0x00000000, /* EMC_ACT2PDEN */
857 0x00000001, /* EMC_AR2PDEN */
858 0x0000000c, /* EMC_RW2PDEN */
859 0x0000000f, /* EMC_TXSR */
860 0x0000000f, /* EMC_TXSRDLL */
861 0x00000003, /* EMC_TCKE */
862 0x00000003, /* EMC_TCKESR */
863 0x00000003, /* EMC_TPD */
864 0x00000008, /* EMC_TFAW */
865 0x00000004, /* EMC_TRPAB */
866 0x00000001, /* EMC_TCLKSTABLE */
867 0x00000003, /* EMC_TCLKSTOP */
868 0x000001a9, /* EMC_TREFBW */
869 0x00000005, /* EMC_QUSE_EXTRA */
870 0x00000020, /* EMC_ODT_WRITE */
871 0x00000000, /* EMC_ODT_READ */
872 0x0001aa86, /* EMC_FBIO_CFG5 */
873 0x005800a8, /* EMC_CFG_DIG_DLL */
874 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
875 0x00048000, /* EMC_DLL_XFORM_DQS4 */
876 0x00048000, /* EMC_DLL_XFORM_DQS5 */
877 0x00048000, /* EMC_DLL_XFORM_DQS6 */
878 0x00048000, /* EMC_DLL_XFORM_DQS7 */
879 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
880 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
881 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
882 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
883 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
884 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
885 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
886 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
887 0x00010220, /* EMC_XM2CMDPADCTRL */
888 0x00000000, /* EMC_XM2CMDPADCTRL4 */
889 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
890 0x00000000, /* EMC_XM2DQPADCTRL2 */
891 0x77ffc004, /* EMC_XM2CLKPADCTRL */
892 0x81f1f008, /* EMC_XM2COMPPADCTRL */
893 0x00000000, /* EMC_XM2VTTGENPADCTRL */
894 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
895 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
896 0x00000000, /* EMC_TXDSRVTTGEN */
897 0x02000100, /* EMC_FBIO_SPARE */
898 0x00000802, /* EMC_CTT_TERM_CTRL */
899 0x00064000, /* EMC_ZCAL_INTERVAL */
900 0x00000025, /* EMC_ZCAL_WAIT_CNT */
901 0x000e000e, /* EMC_MRS_WAIT_CNT */
902 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
903 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
904 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
905 0x00000000, /* EMC_CTT */
906 0x00000000, /* EMC_CTT_DURATION */
907 0x8000040c, /* EMC_DYN_SELF_REF_CONTROL */
908 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
909 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
910 0x08000001, /* MC_EMEM_ARB_CFG */
911 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
912 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
913 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
914 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
915 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
916 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
917 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
918 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
919 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
920 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
921 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
922 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
923 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
924 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
925 0x00090403, /* MC_EMEM_ARB_DA_COVERS */
926 0x72430504, /* MC_EMEM_ARB_MISC0 */
927 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
930 0x00000000, /* EMC_CDB_CNTL_1 */
931 0x00000004, /* EMC_FBIO_CFG6 */
932 0x00000007, /* EMC_QUSE */
933 0x00000003, /* EMC_EINPUT */
934 0x00000005, /* EMC_EINPUT_DURATION */
935 0x00078000, /* EMC_DLL_XFORM_DQS0 */
936 0x0000000b, /* EMC_QSAFE */
937 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
938 0x0000000d, /* EMC_RDV */
939 0x00249249, /* EMC_XM2DQSPADCTRL4 */
940 0x20820800, /* EMC_XM2DQSPADCTRL3 */
941 0x000c0000, /* EMC_DLL_XFORM_DQ0 */
942 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
943 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
944 0x00000909, /* EMC_XM2CLKPADCTRL2 */
945 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
946 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
947 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
948 0x00078000, /* EMC_DLL_XFORM_DQS1 */
949 0x00078000, /* EMC_DLL_XFORM_DQS2 */
950 0x00078000, /* EMC_DLL_XFORM_DQS3 */
951 0x000c0000, /* EMC_DLL_XFORM_DQ1 */
952 0x000c0000, /* EMC_DLL_XFORM_DQ2 */
953 0x000c0000, /* EMC_DLL_XFORM_DQ3 */
954 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
955 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
956 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
957 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
958 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
959 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
962 0x00000000, /* EMC_CDB_CNTL_1 */
963 0x00000004, /* EMC_FBIO_CFG6 */
964 0x00000007, /* EMC_QUSE */
965 0x00000003, /* EMC_EINPUT */
966 0x00000005, /* EMC_EINPUT_DURATION */
967 0x00078000, /* EMC_DLL_XFORM_DQS0 */
968 0x0000000b, /* EMC_QSAFE */
969 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
970 0x0000000d, /* EMC_RDV */
971 0x00249249, /* EMC_XM2DQSPADCTRL4 */
972 0x20820800, /* EMC_XM2DQSPADCTRL3 */
973 0x000c0000, /* EMC_DLL_XFORM_DQ0 */
974 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
975 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
976 0x00000909, /* EMC_XM2CLKPADCTRL2 */
977 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
978 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
979 0x00048000, /* EMC_DLL_XFORM_ADDR2 */
980 0x00078000, /* EMC_DLL_XFORM_DQS1 */
981 0x00078000, /* EMC_DLL_XFORM_DQS2 */
982 0x00078000, /* EMC_DLL_XFORM_DQS3 */
983 0x000c0000, /* EMC_DLL_XFORM_DQ1 */
984 0x000c0000, /* EMC_DLL_XFORM_DQ2 */
985 0x000c0000, /* EMC_DLL_XFORM_DQ3 */
986 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
987 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
988 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
989 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
990 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
991 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
994 0x00000068, /* MC_PTSA_GRANT_DECREMENT */
995 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
996 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
997 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
998 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
999 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
1000 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
1001 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1002 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
1003 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1004 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1006 0x00000012, /* EMC_ZCAL_WAIT_CNT after clock change */
1007 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1008 0xf320000e, /* EMC_CFG */
1009 0x00000000, /* Mode Register 0 */
1010 0x00010083, /* Mode Register 1 */
1011 0x00020004, /* Mode Register 2 */
1012 0x000b0000, /* Mode Register 4 */
1013 6890, /* expected dvfs latency (ns) */
1016 0x41, /* Rev 4.0.3 */
1017 204000, /* SDRAM frequency */
1018 900, /* min voltage */
1019 "pll_p", /* clock source id */
1020 0x40000002, /* CLK_SOURCE_EMC */
1021 99, /* number of burst_regs */
1022 30, /* number of trim_regs (each channel) */
1023 11, /* number of up_down_regs */
1025 0x0000000c, /* EMC_RC */
1026 0x0000001a, /* EMC_RFC */
1027 0x00000000, /* EMC_RFC_SLR */
1028 0x00000008, /* EMC_RAS */
1029 0x00000003, /* EMC_RP */
1030 0x00000007, /* EMC_R2W */
1031 0x00000008, /* EMC_W2R */
1032 0x00000003, /* EMC_R2P */
1033 0x0000000a, /* EMC_W2P */
1034 0x00000003, /* EMC_RD_RCD */
1035 0x00000003, /* EMC_WR_RCD */
1036 0x00000002, /* EMC_RRD */
1037 0x00000002, /* EMC_REXT */
1038 0x00000000, /* EMC_WEXT */
1039 0x00000003, /* EMC_WDV */
1040 0x0000000f, /* EMC_WDV_MASK */
1041 0x00000006, /* EMC_IBDLY */
1042 0x00010000, /* EMC_PUTERM_EXTRA */
1043 0x00000000, /* EMC_CDB_CNTL_2 */
1044 0x00000004, /* EMC_QRST */
1045 0x00000010, /* EMC_RDV_MASK */
1046 0x00000303, /* EMC_REFRESH */
1047 0x00000000, /* EMC_BURST_REFRESH_NUM */
1048 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
1049 0x00000002, /* EMC_PDEX2WR */
1050 0x00000002, /* EMC_PDEX2RD */
1051 0x00000003, /* EMC_PCHG2PDEN */
1052 0x00000000, /* EMC_ACT2PDEN */
1053 0x00000001, /* EMC_AR2PDEN */
1054 0x0000000c, /* EMC_RW2PDEN */
1055 0x0000001d, /* EMC_TXSR */
1056 0x0000001d, /* EMC_TXSRDLL */
1057 0x00000004, /* EMC_TCKE */
1058 0x00000004, /* EMC_TCKESR */
1059 0x00000004, /* EMC_TPD */
1060 0x0000000b, /* EMC_TFAW */
1061 0x00000005, /* EMC_TRPAB */
1062 0x00000001, /* EMC_TCLKSTABLE */
1063 0x00000003, /* EMC_TCLKSTOP */
1064 0x00000351, /* EMC_TREFBW */
1065 0x00000006, /* EMC_QUSE_EXTRA */
1066 0x00000020, /* EMC_ODT_WRITE */
1067 0x00000000, /* EMC_ODT_READ */
1068 0x0001aa86, /* EMC_FBIO_CFG5 */
1069 0x005800a8, /* EMC_CFG_DIG_DLL */
1070 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1071 0x00030000, /* EMC_DLL_XFORM_DQS4 */
1072 0x00030000, /* EMC_DLL_XFORM_DQS5 */
1073 0x00030000, /* EMC_DLL_XFORM_DQS6 */
1074 0x00030000, /* EMC_DLL_XFORM_DQS7 */
1075 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1076 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1077 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1078 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1079 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1080 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1081 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1082 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1083 0x00010220, /* EMC_XM2CMDPADCTRL */
1084 0x00000000, /* EMC_XM2CMDPADCTRL4 */
1085 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
1086 0x00000000, /* EMC_XM2DQPADCTRL2 */
1087 0x77ffc004, /* EMC_XM2CLKPADCTRL */
1088 0x81f1f008, /* EMC_XM2COMPPADCTRL */
1089 0x00000000, /* EMC_XM2VTTGENPADCTRL */
1090 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1091 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1092 0x00000000, /* EMC_TXDSRVTTGEN */
1093 0x02000100, /* EMC_FBIO_SPARE */
1094 0x00000802, /* EMC_CTT_TERM_CTRL */
1095 0x00064000, /* EMC_ZCAL_INTERVAL */
1096 0x0000004a, /* EMC_ZCAL_WAIT_CNT */
1097 0x000f000f, /* EMC_MRS_WAIT_CNT */
1098 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
1099 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1100 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1101 0x00000000, /* EMC_CTT */
1102 0x00000000, /* EMC_CTT_DURATION */
1103 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
1104 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1105 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1106 0x01000003, /* MC_EMEM_ARB_CFG */
1107 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1108 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1109 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1110 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
1111 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
1112 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
1113 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1114 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1115 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1116 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1117 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1118 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
1119 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
1120 0x05050102, /* MC_EMEM_ARB_DA_TURNS */
1121 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
1122 0x71e40a07, /* MC_EMEM_ARB_MISC0 */
1123 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1126 0x00000000, /* EMC_CDB_CNTL_1 */
1127 0x00000004, /* EMC_FBIO_CFG6 */
1128 0x00000008, /* EMC_QUSE */
1129 0x00000004, /* EMC_EINPUT */
1130 0x00000005, /* EMC_EINPUT_DURATION */
1131 0x00030000, /* EMC_DLL_XFORM_DQS0 */
1132 0x0000000c, /* EMC_QSAFE */
1133 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1134 0x0000000e, /* EMC_RDV */
1135 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1136 0x20820800, /* EMC_XM2DQSPADCTRL3 */
1137 0x00058000, /* EMC_DLL_XFORM_DQ0 */
1138 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1139 0x00070000, /* EMC_DLL_XFORM_ADDR0 */
1140 0x00000909, /* EMC_XM2CLKPADCTRL2 */
1141 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1142 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1143 0x00070000, /* EMC_DLL_XFORM_ADDR2 */
1144 0x00030000, /* EMC_DLL_XFORM_DQS1 */
1145 0x00030000, /* EMC_DLL_XFORM_DQS2 */
1146 0x00030000, /* EMC_DLL_XFORM_DQS3 */
1147 0x00058000, /* EMC_DLL_XFORM_DQ1 */
1148 0x00058000, /* EMC_DLL_XFORM_DQ2 */
1149 0x00058000, /* EMC_DLL_XFORM_DQ3 */
1150 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1151 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1152 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1153 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1154 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1155 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1158 0x00000000, /* EMC_CDB_CNTL_1 */
1159 0x00000004, /* EMC_FBIO_CFG6 */
1160 0x00000008, /* EMC_QUSE */
1161 0x00000004, /* EMC_EINPUT */
1162 0x00000005, /* EMC_EINPUT_DURATION */
1163 0x00030000, /* EMC_DLL_XFORM_DQS0 */
1164 0x0000000c, /* EMC_QSAFE */
1165 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1166 0x0000000e, /* EMC_RDV */
1167 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1168 0x20820800, /* EMC_XM2DQSPADCTRL3 */
1169 0x00058000, /* EMC_DLL_XFORM_DQ0 */
1170 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1171 0x00070000, /* EMC_DLL_XFORM_ADDR0 */
1172 0x00000000, /* EMC_XM2CLKPADCTRL2 */
1173 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1174 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1175 0x00070000, /* EMC_DLL_XFORM_ADDR2 */
1176 0x00030000, /* EMC_DLL_XFORM_DQS1 */
1177 0x00030000, /* EMC_DLL_XFORM_DQS2 */
1178 0x00030000, /* EMC_DLL_XFORM_DQS3 */
1179 0x00058000, /* EMC_DLL_XFORM_DQ1 */
1180 0x00058000, /* EMC_DLL_XFORM_DQ2 */
1181 0x00058000, /* EMC_DLL_XFORM_DQ3 */
1182 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1183 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1184 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1185 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1186 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1187 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1190 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
1191 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
1192 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
1193 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
1194 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1195 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
1196 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
1197 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1198 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
1199 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1200 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1202 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */
1203 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1204 0xf320000e, /* EMC_CFG */
1205 0x00000000, /* Mode Register 0 */
1206 0x00010083, /* Mode Register 1 */
1207 0x00020004, /* Mode Register 2 */
1208 0x000b0000, /* Mode Register 4 */
1209 3420, /* expected dvfs latency (ns) */
1212 0x41, /* Rev 4.0.3 */
1213 312000, /* SDRAM frequency */
1214 1000, /* min voltage */
1215 "pll_c", /* clock source id */
1216 0x24000002, /* CLK_SOURCE_EMC */
1217 99, /* number of burst_regs */
1218 30, /* number of trim_regs (each channel) */
1219 11, /* number of up_down_regs */
1221 0x00000012, /* EMC_RC */
1222 0x00000028, /* EMC_RFC */
1223 0x00000000, /* EMC_RFC_SLR */
1224 0x0000000d, /* EMC_RAS */
1225 0x00000005, /* EMC_RP */
1226 0x00000008, /* EMC_R2W */
1227 0x00000008, /* EMC_W2R */
1228 0x00000003, /* EMC_R2P */
1229 0x0000000a, /* EMC_W2P */
1230 0x00000005, /* EMC_RD_RCD */
1231 0x00000005, /* EMC_WR_RCD */
1232 0x00000003, /* EMC_RRD */
1233 0x00000002, /* EMC_REXT */
1234 0x00000000, /* EMC_WEXT */
1235 0x00000003, /* EMC_WDV */
1236 0x00000003, /* EMC_WDV_MASK */
1237 0x00000006, /* EMC_IBDLY */
1238 0x00010000, /* EMC_PUTERM_EXTRA */
1239 0x00000000, /* EMC_CDB_CNTL_2 */
1240 0x00000004, /* EMC_QRST */
1241 0x0000000f, /* EMC_RDV_MASK */
1242 0x0000049d, /* EMC_REFRESH */
1243 0x00000000, /* EMC_BURST_REFRESH_NUM */
1244 0x00000127, /* EMC_PRE_REFRESH_REQ_CNT */
1245 0x00000002, /* EMC_PDEX2WR */
1246 0x00000002, /* EMC_PDEX2RD */
1247 0x00000005, /* EMC_PCHG2PDEN */
1248 0x00000000, /* EMC_ACT2PDEN */
1249 0x00000001, /* EMC_AR2PDEN */
1250 0x0000000c, /* EMC_RW2PDEN */
1251 0x0000002c, /* EMC_TXSR */
1252 0x0000002c, /* EMC_TXSRDLL */
1253 0x00000005, /* EMC_TCKE */
1254 0x00000005, /* EMC_TCKESR */
1255 0x00000005, /* EMC_TPD */
1256 0x00000010, /* EMC_TFAW */
1257 0x00000007, /* EMC_TRPAB */
1258 0x00000001, /* EMC_TCLKSTABLE */
1259 0x00000003, /* EMC_TCLKSTOP */
1260 0x00000514, /* EMC_TREFBW */
1261 0x00000006, /* EMC_QUSE_EXTRA */
1262 0x00000020, /* EMC_ODT_WRITE */
1263 0x00000000, /* EMC_ODT_READ */
1264 0x0001aa86, /* EMC_FBIO_CFG5 */
1265 0x005800a8, /* EMC_CFG_DIG_DLL */
1266 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1267 0x00020000, /* EMC_DLL_XFORM_DQS4 */
1268 0x00020000, /* EMC_DLL_XFORM_DQS5 */
1269 0x00020000, /* EMC_DLL_XFORM_DQS6 */
1270 0x00020000, /* EMC_DLL_XFORM_DQS7 */
1271 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1272 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1273 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1274 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1275 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1276 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1277 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1278 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1279 0x00010220, /* EMC_XM2CMDPADCTRL */
1280 0x00000000, /* EMC_XM2CMDPADCTRL4 */
1281 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
1282 0x00000000, /* EMC_XM2DQPADCTRL2 */
1283 0x77ffc004, /* EMC_XM2CLKPADCTRL */
1284 0x81f1f008, /* EMC_XM2COMPPADCTRL */
1285 0x00000000, /* EMC_XM2VTTGENPADCTRL */
1286 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1287 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1288 0x00000000, /* EMC_TXDSRVTTGEN */
1289 0x02000100, /* EMC_FBIO_SPARE */
1290 0x00000802, /* EMC_CTT_TERM_CTRL */
1291 0x00064000, /* EMC_ZCAL_INTERVAL */
1292 0x00000071, /* EMC_ZCAL_WAIT_CNT */
1293 0x000e000e, /* EMC_MRS_WAIT_CNT */
1294 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
1295 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1296 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1297 0x00000000, /* EMC_CTT */
1298 0x00000000, /* EMC_CTT_DURATION */
1299 0x80000a4c, /* EMC_DYN_SELF_REF_CONTROL */
1300 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1301 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1302 0x0b000004, /* MC_EMEM_ARB_CFG */
1303 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1304 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1305 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1306 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
1307 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
1308 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
1309 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1310 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1311 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1312 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1313 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1314 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
1315 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
1316 0x05050102, /* MC_EMEM_ARB_DA_TURNS */
1317 0x000c0709, /* MC_EMEM_ARB_DA_COVERS */
1318 0x71c50f0a, /* MC_EMEM_ARB_MISC0 */
1319 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1322 0x00000000, /* EMC_CDB_CNTL_1 */
1323 0x00000004, /* EMC_FBIO_CFG6 */
1324 0x00000009, /* EMC_QUSE */
1325 0x00000004, /* EMC_EINPUT */
1326 0x00000006, /* EMC_EINPUT_DURATION */
1327 0x00030000, /* EMC_DLL_XFORM_DQS0 */
1328 0x0000000d, /* EMC_QSAFE */
1329 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1330 0x0000000f, /* EMC_RDV */
1331 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1332 0x20820800, /* EMC_XM2DQSPADCTRL3 */
1333 0x00038000, /* EMC_DLL_XFORM_DQ0 */
1334 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1335 0x00038000, /* EMC_DLL_XFORM_ADDR0 */
1336 0x00000000, /* EMC_XM2CLKPADCTRL2 */
1337 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1338 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1339 0x00038000, /* EMC_DLL_XFORM_ADDR2 */
1340 0x00030000, /* EMC_DLL_XFORM_DQS1 */
1341 0x00030000, /* EMC_DLL_XFORM_DQS2 */
1342 0x00030000, /* EMC_DLL_XFORM_DQS3 */
1343 0x00038000, /* EMC_DLL_XFORM_DQ1 */
1344 0x00038000, /* EMC_DLL_XFORM_DQ2 */
1345 0x00038000, /* EMC_DLL_XFORM_DQ3 */
1346 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1347 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1348 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1349 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1350 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1351 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1354 0x00000000, /* EMC_CDB_CNTL_1 */
1355 0x00000004, /* EMC_FBIO_CFG6 */
1356 0x00000009, /* EMC_QUSE */
1357 0x00000004, /* EMC_EINPUT */
1358 0x00000006, /* EMC_EINPUT_DURATION */
1359 0x00030000, /* EMC_DLL_XFORM_DQS0 */
1360 0x0000000d, /* EMC_QSAFE */
1361 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1362 0x0000000f, /* EMC_RDV */
1363 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1364 0x20820800, /* EMC_XM2DQSPADCTRL3 */
1365 0x00038000, /* EMC_DLL_XFORM_DQ0 */
1366 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1367 0x00038000, /* EMC_DLL_XFORM_ADDR0 */
1368 0x00000000, /* EMC_XM2CLKPADCTRL2 */
1369 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1370 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1371 0x00038000, /* EMC_DLL_XFORM_ADDR2 */
1372 0x00030000, /* EMC_DLL_XFORM_DQS1 */
1373 0x00030000, /* EMC_DLL_XFORM_DQS2 */
1374 0x00030000, /* EMC_DLL_XFORM_DQS3 */
1375 0x00038000, /* EMC_DLL_XFORM_DQ1 */
1376 0x00038000, /* EMC_DLL_XFORM_DQ2 */
1377 0x00038000, /* EMC_DLL_XFORM_DQ3 */
1378 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1379 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1380 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1381 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1382 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1383 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1386 0x00000140, /* MC_PTSA_GRANT_DECREMENT */
1387 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
1388 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
1389 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
1390 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1391 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
1392 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
1393 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1394 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
1395 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1396 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1398 0x00000021, /* EMC_ZCAL_WAIT_CNT after clock change */
1399 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1400 0xf320000e, /* EMC_CFG */
1401 0x00000000, /* Mode Register 0 */
1402 0x00010083, /* Mode Register 1 */
1403 0x00020004, /* Mode Register 2 */
1404 0x000b0000, /* Mode Register 4 */
1405 2680, /* expected dvfs latency (ns) */
1408 0x41, /* Rev 4.0.3 */
1409 408000, /* SDRAM frequency */
1410 1000, /* min voltage */
1411 "pll_p", /* clock source id */
1412 0x40000000, /* CLK_SOURCE_EMC */
1413 99, /* number of burst_regs */
1414 30, /* number of trim_regs (each channel) */
1415 11, /* number of up_down_regs */
1417 0x00000018, /* EMC_RC */
1418 0x00000035, /* EMC_RFC */
1419 0x00000000, /* EMC_RFC_SLR */
1420 0x00000011, /* EMC_RAS */
1421 0x00000007, /* EMC_RP */
1422 0x0000000b, /* EMC_R2W */
1423 0x00000009, /* EMC_W2R */
1424 0x00000003, /* EMC_R2P */
1425 0x0000000d, /* EMC_W2P */
1426 0x00000007, /* EMC_RD_RCD */
1427 0x00000007, /* EMC_WR_RCD */
1428 0x00000004, /* EMC_RRD */
1429 0x00000002, /* EMC_REXT */
1430 0x00000000, /* EMC_WEXT */
1431 0x00000003, /* EMC_WDV */
1432 0x0000000f, /* EMC_WDV_MASK */
1433 0x00000008, /* EMC_IBDLY */
1434 0x00010000, /* EMC_PUTERM_EXTRA */
1435 0x00000000, /* EMC_CDB_CNTL_2 */
1436 0x00000005, /* EMC_QRST */
1437 0x00000013, /* EMC_RDV_MASK */
1438 0x00000607, /* EMC_REFRESH */
1439 0x00000000, /* EMC_BURST_REFRESH_NUM */
1440 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
1441 0x00000003, /* EMC_PDEX2WR */
1442 0x00000003, /* EMC_PDEX2RD */
1443 0x00000007, /* EMC_PCHG2PDEN */
1444 0x00000000, /* EMC_ACT2PDEN */
1445 0x00000001, /* EMC_AR2PDEN */
1446 0x0000000f, /* EMC_RW2PDEN */
1447 0x0000003a, /* EMC_TXSR */
1448 0x0000003a, /* EMC_TXSRDLL */
1449 0x00000007, /* EMC_TCKE */
1450 0x00000007, /* EMC_TCKESR */
1451 0x00000007, /* EMC_TPD */
1452 0x00000015, /* EMC_TFAW */
1453 0x00000009, /* EMC_TRPAB */
1454 0x00000001, /* EMC_TCLKSTABLE */
1455 0x00000003, /* EMC_TCLKSTOP */
1456 0x000006a2, /* EMC_TREFBW */
1457 0x00000008, /* EMC_QUSE_EXTRA */
1458 0x00000020, /* EMC_ODT_WRITE */
1459 0x00000000, /* EMC_ODT_READ */
1460 0x0001a886, /* EMC_FBIO_CFG5 */
1461 0x00580088, /* EMC_CFG_DIG_DLL */
1462 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1463 0x00030000, /* EMC_DLL_XFORM_DQS4 */
1464 0x00030000, /* EMC_DLL_XFORM_DQS5 */
1465 0x00030000, /* EMC_DLL_XFORM_DQS6 */
1466 0x00030000, /* EMC_DLL_XFORM_DQS7 */
1467 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1468 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1469 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1470 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1471 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1472 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1473 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1474 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1475 0x00010220, /* EMC_XM2CMDPADCTRL */
1476 0x00000000, /* EMC_XM2CMDPADCTRL4 */
1477 0x0001003d, /* EMC_XM2DQSPADCTRL2 */
1478 0x00000000, /* EMC_XM2DQPADCTRL2 */
1479 0x77ffc004, /* EMC_XM2CLKPADCTRL */
1480 0x81f1f008, /* EMC_XM2COMPPADCTRL */
1481 0x00000000, /* EMC_XM2VTTGENPADCTRL */
1482 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1483 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1484 0x00000000, /* EMC_TXDSRVTTGEN */
1485 0x02000100, /* EMC_FBIO_SPARE */
1486 0x00000802, /* EMC_CTT_TERM_CTRL */
1487 0x00064000, /* EMC_ZCAL_INTERVAL */
1488 0x00000093, /* EMC_ZCAL_WAIT_CNT */
1489 0x00110011, /* EMC_MRS_WAIT_CNT */
1490 0x00110011, /* EMC_MRS_WAIT_CNT2 */
1491 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1492 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1493 0x00000000, /* EMC_CTT */
1494 0x00000000, /* EMC_CTT_DURATION */
1495 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */
1496 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1497 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1498 0x02000006, /* MC_EMEM_ARB_CFG */
1499 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1500 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1501 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1502 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
1503 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
1504 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
1505 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1506 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1507 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1508 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1509 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1510 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
1511 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1512 0x06070102, /* MC_EMEM_ARB_DA_TURNS */
1513 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
1514 0x71c7130d, /* MC_EMEM_ARB_MISC0 */
1515 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1518 0x00000000, /* EMC_CDB_CNTL_1 */
1519 0x00000004, /* EMC_FBIO_CFG6 */
1520 0x0000000b, /* EMC_QUSE */
1521 0x00000006, /* EMC_EINPUT */
1522 0x00000006, /* EMC_EINPUT_DURATION */
1523 0x00030000, /* EMC_DLL_XFORM_DQS0 */
1524 0x0000000e, /* EMC_QSAFE */
1525 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1526 0x00000011, /* EMC_RDV */
1527 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1528 0x10410421, /* EMC_XM2DQSPADCTRL3 */
1529 0x00020000, /* EMC_DLL_XFORM_DQ0 */
1530 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1531 0x00018000, /* EMC_DLL_XFORM_ADDR0 */
1532 0x00000000, /* EMC_XM2CLKPADCTRL2 */
1533 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1534 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1535 0x00018000, /* EMC_DLL_XFORM_ADDR2 */
1536 0x00030000, /* EMC_DLL_XFORM_DQS1 */
1537 0x00030000, /* EMC_DLL_XFORM_DQS2 */
1538 0x00030000, /* EMC_DLL_XFORM_DQS3 */
1539 0x00020000, /* EMC_DLL_XFORM_DQ1 */
1540 0x00020000, /* EMC_DLL_XFORM_DQ2 */
1541 0x00020000, /* EMC_DLL_XFORM_DQ3 */
1542 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1543 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1544 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1545 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1546 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1547 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1550 0x00000000, /* EMC_CDB_CNTL_1 */
1551 0x00000004, /* EMC_FBIO_CFG6 */
1552 0x0000000b, /* EMC_QUSE */
1553 0x00000006, /* EMC_EINPUT */
1554 0x00000006, /* EMC_EINPUT_DURATION */
1555 0x00030000, /* EMC_DLL_XFORM_DQS0 */
1556 0x0000000e, /* EMC_QSAFE */
1557 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1558 0x00000011, /* EMC_RDV */
1559 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1560 0x10410421, /* EMC_XM2DQSPADCTRL3 */
1561 0x00020000, /* EMC_DLL_XFORM_DQ0 */
1562 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1563 0x00018000, /* EMC_DLL_XFORM_ADDR0 */
1564 0x00000000, /* EMC_XM2CLKPADCTRL2 */
1565 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1566 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1567 0x00018000, /* EMC_DLL_XFORM_ADDR2 */
1568 0x00030000, /* EMC_DLL_XFORM_DQS1 */
1569 0x00030000, /* EMC_DLL_XFORM_DQS2 */
1570 0x00030000, /* EMC_DLL_XFORM_DQS3 */
1571 0x00020000, /* EMC_DLL_XFORM_DQ1 */
1572 0x00020000, /* EMC_DLL_XFORM_DQ2 */
1573 0x00020000, /* EMC_DLL_XFORM_DQ3 */
1574 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1575 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1576 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1577 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1578 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1579 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1582 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
1583 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
1584 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
1585 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
1586 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1587 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
1588 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
1589 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1590 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
1591 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1592 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1594 0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */
1595 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1596 0xf3200006, /* EMC_CFG */
1597 0x00000000, /* Mode Register 0 */
1598 0x000100c3, /* Mode Register 1 */
1599 0x00020006, /* Mode Register 2 */
1600 0x000b0000, /* Mode Register 4 */
1601 1750, /* expected dvfs latency (ns) */
1604 0x41, /* Rev 4.0.3 */
1605 624000, /* SDRAM frequency */
1606 1100, /* min voltage */
1607 "pll_c", /* clock source id */
1608 0x24000000, /* CLK_SOURCE_EMC */
1609 99, /* number of burst_regs */
1610 30, /* number of trim_regs (each channel) */
1611 11, /* number of up_down_regs */
1613 0x00000025, /* EMC_RC */
1614 0x00000051, /* EMC_RFC */
1615 0x00000000, /* EMC_RFC_SLR */
1616 0x0000001a, /* EMC_RAS */
1617 0x0000000b, /* EMC_RP */
1618 0x0000000d, /* EMC_R2W */
1619 0x0000000c, /* EMC_W2R */
1620 0x00000004, /* EMC_R2P */
1621 0x00000011, /* EMC_W2P */
1622 0x0000000b, /* EMC_RD_RCD */
1623 0x0000000b, /* EMC_WR_RCD */
1624 0x00000006, /* EMC_RRD */
1625 0x00000003, /* EMC_REXT */
1626 0x00000000, /* EMC_WEXT */
1627 0x00000005, /* EMC_WDV */
1628 0x0000000f, /* EMC_WDV_MASK */
1629 0x0000000b, /* EMC_IBDLY */
1630 0x00010000, /* EMC_PUTERM_EXTRA */
1631 0x00000000, /* EMC_CDB_CNTL_2 */
1632 0x00000007, /* EMC_QRST */
1633 0x00000017, /* EMC_RDV_MASK */
1634 0x00000945, /* EMC_REFRESH */
1635 0x00000000, /* EMC_BURST_REFRESH_NUM */
1636 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
1637 0x00000004, /* EMC_PDEX2WR */
1638 0x00000004, /* EMC_PDEX2RD */
1639 0x0000000b, /* EMC_PCHG2PDEN */
1640 0x00000000, /* EMC_ACT2PDEN */
1641 0x00000001, /* EMC_AR2PDEN */
1642 0x00000014, /* EMC_RW2PDEN */
1643 0x00000058, /* EMC_TXSR */
1644 0x00000058, /* EMC_TXSRDLL */
1645 0x0000000a, /* EMC_TCKE */
1646 0x0000000a, /* EMC_TCKESR */
1647 0x0000000a, /* EMC_TPD */
1648 0x00000020, /* EMC_TFAW */
1649 0x0000000e, /* EMC_TRPAB */
1650 0x00000001, /* EMC_TCLKSTABLE */
1651 0x00000003, /* EMC_TCLKSTOP */
1652 0x00000a28, /* EMC_TREFBW */
1653 0x0000000b, /* EMC_QUSE_EXTRA */
1654 0x00000020, /* EMC_ODT_WRITE */
1655 0x00000000, /* EMC_ODT_READ */
1656 0x0001a886, /* EMC_FBIO_CFG5 */
1657 0xf00d0199, /* EMC_CFG_DIG_DLL */
1658 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1659 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1660 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1661 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1662 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1663 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1664 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1665 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1666 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1667 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1668 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1669 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1670 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1671 0x00010220, /* EMC_XM2CMDPADCTRL */
1672 0x00000000, /* EMC_XM2CMDPADCTRL4 */
1673 0x0001003d, /* EMC_XM2DQSPADCTRL2 */
1674 0x00000000, /* EMC_XM2DQPADCTRL2 */
1675 0x77ffc004, /* EMC_XM2CLKPADCTRL */
1676 0x81f1f008, /* EMC_XM2COMPPADCTRL */
1677 0x00000000, /* EMC_XM2VTTGENPADCTRL */
1678 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
1679 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1680 0x00000000, /* EMC_TXDSRVTTGEN */
1681 0x02000100, /* EMC_FBIO_SPARE */
1682 0x00000301, /* EMC_CTT_TERM_CTRL */
1683 0x00064000, /* EMC_ZCAL_INTERVAL */
1684 0x000000e1, /* EMC_ZCAL_WAIT_CNT */
1685 0x00140014, /* EMC_MRS_WAIT_CNT */
1686 0x00140014, /* EMC_MRS_WAIT_CNT2 */
1687 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1688 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1689 0x00000000, /* EMC_CTT */
1690 0x00000000, /* EMC_CTT_DURATION */
1691 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
1692 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1693 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1694 0x06000009, /* MC_EMEM_ARB_CFG */
1695 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1696 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
1697 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
1698 0x00000013, /* MC_EMEM_ARB_TIMING_RC */
1699 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
1700 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
1701 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
1702 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1703 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1704 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
1705 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1706 0x00000008, /* MC_EMEM_ARB_TIMING_R2W */
1707 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
1708 0x07080103, /* MC_EMEM_ARB_DA_TURNS */
1709 0x00160e13, /* MC_EMEM_ARB_DA_COVERS */
1710 0x71ca1d14, /* MC_EMEM_ARB_MISC0 */
1711 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1714 0x00000000, /* EMC_CDB_CNTL_1 */
1715 0x00000004, /* EMC_FBIO_CFG6 */
1716 0x0000000f, /* EMC_QUSE */
1717 0x00000009, /* EMC_EINPUT */
1718 0x00000007, /* EMC_EINPUT_DURATION */
1719 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1720 0x00000010, /* EMC_QSAFE */
1721 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1722 0x00000015, /* EMC_RDV */
1723 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1724 0x18618621, /* EMC_XM2DQSPADCTRL3 */
1725 0x00003010, /* EMC_DLL_XFORM_DQ0 */
1726 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1727 0x00000010, /* EMC_DLL_XFORM_ADDR0 */
1728 0x00000909, /* EMC_XM2CLKPADCTRL2 */
1729 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1730 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1731 0x00000010, /* EMC_DLL_XFORM_ADDR2 */
1732 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1733 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1734 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1735 0x00003010, /* EMC_DLL_XFORM_DQ1 */
1736 0x00003010, /* EMC_DLL_XFORM_DQ2 */
1737 0x00003010, /* EMC_DLL_XFORM_DQ3 */
1738 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1739 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1740 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1741 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1742 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1743 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1746 0x00000000, /* EMC_CDB_CNTL_1 */
1747 0x00000004, /* EMC_FBIO_CFG6 */
1748 0x0000000f, /* EMC_QUSE */
1749 0x00000009, /* EMC_EINPUT */
1750 0x00000007, /* EMC_EINPUT_DURATION */
1751 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1752 0x00000010, /* EMC_QSAFE */
1753 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1754 0x00000015, /* EMC_RDV */
1755 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1756 0x18618621, /* EMC_XM2DQSPADCTRL3 */
1757 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
1758 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1759 0x00000010, /* EMC_DLL_XFORM_ADDR0 */
1760 0x00000909, /* EMC_XM2CLKPADCTRL2 */
1761 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1762 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1763 0x00000010, /* EMC_DLL_XFORM_ADDR2 */
1764 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1765 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1766 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1767 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
1768 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
1769 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
1770 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1771 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1772 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1773 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1774 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1775 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1778 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
1779 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
1780 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
1781 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
1782 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1783 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
1784 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
1785 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1786 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
1787 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1788 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1790 0x0000003d, /* EMC_ZCAL_WAIT_CNT after clock change */
1791 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1792 0xf3200000, /* EMC_CFG */
1793 0x00000000, /* Mode Register 0 */
1794 0x00010003, /* Mode Register 1 */
1795 0x00020018, /* Mode Register 2 */
1796 0x000b0000, /* Mode Register 4 */
1797 1440, /* expected dvfs latency (ns) */
1800 0x41, /* Rev 4.0.3 */
1801 744000, /* SDRAM frequency */
1802 1100, /* min voltage */
1803 "pll_m", /* clock source id */
1804 0x80000000, /* CLK_SOURCE_EMC */
1805 99, /* number of burst_regs */
1806 30, /* number of trim_regs (each channel) */
1807 11, /* number of up_down_regs */
1809 0x0000002c, /* EMC_RC */
1810 0x00000061, /* EMC_RFC */
1811 0x00000000, /* EMC_RFC_SLR */
1812 0x0000001f, /* EMC_RAS */
1813 0x0000000d, /* EMC_RP */
1814 0x0000000f, /* EMC_R2W */
1815 0x0000000d, /* EMC_W2R */
1816 0x00000005, /* EMC_R2P */
1817 0x00000013, /* EMC_W2P */
1818 0x0000000d, /* EMC_RD_RCD */
1819 0x0000000d, /* EMC_WR_RCD */
1820 0x00000007, /* EMC_RRD */
1821 0x00000003, /* EMC_REXT */
1822 0x00000000, /* EMC_WEXT */
1823 0x00000005, /* EMC_WDV */
1824 0x0000000f, /* EMC_WDV_MASK */
1825 0x0000000d, /* EMC_IBDLY */
1826 0x00010000, /* EMC_PUTERM_EXTRA */
1827 0x00000000, /* EMC_CDB_CNTL_2 */
1828 0x00000009, /* EMC_QRST */
1829 0x0000001a, /* EMC_RDV_MASK */
1830 0x00000b1e, /* EMC_REFRESH */
1831 0x00000000, /* EMC_BURST_REFRESH_NUM */
1832 0x000002c7, /* EMC_PRE_REFRESH_REQ_CNT */
1833 0x00000005, /* EMC_PDEX2WR */
1834 0x00000005, /* EMC_PDEX2RD */
1835 0x0000000d, /* EMC_PCHG2PDEN */
1836 0x00000000, /* EMC_ACT2PDEN */
1837 0x00000001, /* EMC_AR2PDEN */
1838 0x00000016, /* EMC_RW2PDEN */
1839 0x00000069, /* EMC_TXSR */
1840 0x00000069, /* EMC_TXSRDLL */
1841 0x0000000c, /* EMC_TCKE */
1842 0x0000000c, /* EMC_TCKESR */
1843 0x0000000c, /* EMC_TPD */
1844 0x00000026, /* EMC_TFAW */
1845 0x00000010, /* EMC_TRPAB */
1846 0x00000001, /* EMC_TCLKSTABLE */
1847 0x00000003, /* EMC_TCLKSTOP */
1848 0x00000c21, /* EMC_TREFBW */
1849 0x0000010d, /* EMC_QUSE_EXTRA */
1850 0x00000020, /* EMC_ODT_WRITE */
1851 0x00000000, /* EMC_ODT_READ */
1852 0x0001a886, /* EMC_FBIO_CFG5 */
1853 0xf0080199, /* EMC_CFG_DIG_DLL */
1854 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1855 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1856 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1857 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1858 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1859 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1860 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1861 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1862 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1863 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1864 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1865 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1866 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1867 0x00010220, /* EMC_XM2CMDPADCTRL */
1868 0x00000000, /* EMC_XM2CMDPADCTRL4 */
1869 0x0000003d, /* EMC_XM2DQSPADCTRL2 */
1870 0x00000000, /* EMC_XM2DQPADCTRL2 */
1871 0x77ffc004, /* EMC_XM2CLKPADCTRL */
1872 0x81f1f408, /* EMC_XM2COMPPADCTRL */
1873 0x00000000, /* EMC_XM2VTTGENPADCTRL */
1874 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1875 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1876 0x00000000, /* EMC_TXDSRVTTGEN */
1877 0x02000100, /* EMC_FBIO_SPARE */
1878 0x00000301, /* EMC_CTT_TERM_CTRL */
1879 0x00064000, /* EMC_ZCAL_INTERVAL */
1880 0x0000010c, /* EMC_ZCAL_WAIT_CNT */
1881 0x00150015, /* EMC_MRS_WAIT_CNT */
1882 0x00150015, /* EMC_MRS_WAIT_CNT2 */
1883 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1884 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1885 0x00000000, /* EMC_CTT */
1886 0x00000000, /* EMC_CTT_DURATION */
1887 0x8000172f, /* EMC_DYN_SELF_REF_CONTROL */
1888 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1889 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1890 0x0300000b, /* MC_EMEM_ARB_CFG */
1891 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1892 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
1893 0x00000006, /* MC_EMEM_ARB_TIMING_RP */
1894 0x00000016, /* MC_EMEM_ARB_TIMING_RC */
1895 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
1896 0x00000012, /* MC_EMEM_ARB_TIMING_FAW */
1897 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
1898 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1899 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1900 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
1901 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1902 0x00000009, /* MC_EMEM_ARB_TIMING_R2W */
1903 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
1904 0x08090103, /* MC_EMEM_ARB_DA_TURNS */
1905 0x00191016, /* MC_EMEM_ARB_DA_COVERS */
1906 0x71cc2217, /* MC_EMEM_ARB_MISC0 */
1907 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1910 0x00000000, /* EMC_CDB_CNTL_1 */
1911 0x00000004, /* EMC_FBIO_CFG6 */
1912 0x00000012, /* EMC_QUSE */
1913 0x0000000b, /* EMC_EINPUT */
1914 0x00000007, /* EMC_EINPUT_DURATION */
1915 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1916 0x00000011, /* EMC_QSAFE */
1917 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1918 0x00000018, /* EMC_RDV */
1919 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1920 0x18618621, /* EMC_XM2DQSPADCTRL3 */
1921 0x00008007, /* EMC_DLL_XFORM_DQ0 */
1922 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
1923 0x00004009, /* EMC_DLL_XFORM_ADDR0 */
1924 0x00000707, /* EMC_XM2CLKPADCTRL2 */
1925 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1926 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1927 0x00004009, /* EMC_DLL_XFORM_ADDR2 */
1928 0x0000400a, /* EMC_DLL_XFORM_DQS1 */
1929 0x0000800a, /* EMC_DLL_XFORM_DQS2 */
1930 0x0000400a, /* EMC_DLL_XFORM_DQS3 */
1931 0x00008007, /* EMC_DLL_XFORM_DQ1 */
1932 0x00008007, /* EMC_DLL_XFORM_DQ2 */
1933 0x00008007, /* EMC_DLL_XFORM_DQ3 */
1934 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1935 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1936 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1937 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1938 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1939 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1942 0x00000000, /* EMC_CDB_CNTL_1 */
1943 0x00000004, /* EMC_FBIO_CFG6 */
1944 0x00000012, /* EMC_QUSE */
1945 0x0000000b, /* EMC_EINPUT */
1946 0x00000007, /* EMC_EINPUT_DURATION */
1947 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1948 0x00000011, /* EMC_QSAFE */
1949 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1950 0x00000018, /* EMC_RDV */
1951 0x00249249, /* EMC_XM2DQSPADCTRL4 */
1952 0x18618621, /* EMC_XM2DQSPADCTRL3 */
1953 0x00008007, /* EMC_DLL_XFORM_DQ0 */
1954 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
1955 0x00004009, /* EMC_DLL_XFORM_ADDR0 */
1956 0x00000909, /* EMC_XM2CLKPADCTRL2 */
1957 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1958 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1959 0x00004009, /* EMC_DLL_XFORM_ADDR2 */
1960 0x0000400a, /* EMC_DLL_XFORM_DQS1 */
1961 0x0000800a, /* EMC_DLL_XFORM_DQS2 */
1962 0x0000400a, /* EMC_DLL_XFORM_DQS3 */
1963 0x00008007, /* EMC_DLL_XFORM_DQ1 */
1964 0x00008007, /* EMC_DLL_XFORM_DQ2 */
1965 0x00008007, /* EMC_DLL_XFORM_DQ3 */
1966 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1967 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1968 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1969 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1970 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1971 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1974 0x0000017d, /* MC_PTSA_GRANT_DECREMENT */
1975 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
1976 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
1977 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
1978 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1979 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
1980 0x0011000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
1981 0x00000011, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1982 0x00110011, /* MC_LATENCY_ALLOWANCE_NV3 */
1983 0x00740036, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1984 0x00740074, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1986 0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
1987 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1988 0xf3200000, /* EMC_CFG */
1989 0x00000000, /* Mode Register 0 */
1990 0x00010043, /* Mode Register 1 */
1991 0x0002001a, /* Mode Register 2 */
1992 0x000b0000, /* Mode Register 4 */
1993 1200, /* expected dvfs latency (ns) */
1997 static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_table[] = {
1999 0x41, /* Rev 4.0.3 */
2000 12750, /* SDRAM frequency */
2001 900, /* min voltage */
2002 "pll_p", /* clock source id */
2003 0x4000003e, /* CLK_SOURCE_EMC */
2004 99, /* number of burst_regs */
2005 30, /* number of trim_regs (each channel) */
2006 11, /* number of up_down_regs */
2008 0x00000000, /* EMC_RC */
2009 0x00000003, /* EMC_RFC */
2010 0x00000000, /* EMC_RFC_SLR */
2011 0x00000002, /* EMC_RAS */
2012 0x00000002, /* EMC_RP */
2013 0x00000006, /* EMC_R2W */
2014 0x00000008, /* EMC_W2R */
2015 0x00000003, /* EMC_R2P */
2016 0x0000000a, /* EMC_W2P */
2017 0x00000002, /* EMC_RD_RCD */
2018 0x00000002, /* EMC_WR_RCD */
2019 0x00000001, /* EMC_RRD */
2020 0x00000001, /* EMC_REXT */
2021 0x00000000, /* EMC_WEXT */
2022 0x00000003, /* EMC_WDV */
2023 0x00000003, /* EMC_WDV_MASK */
2024 0x00000005, /* EMC_IBDLY */
2025 0x00010000, /* EMC_PUTERM_EXTRA */
2026 0x00000000, /* EMC_CDB_CNTL_2 */
2027 0x00000004, /* EMC_QRST */
2028 0x0000000d, /* EMC_RDV_MASK */
2029 0x0000002f, /* EMC_REFRESH */
2030 0x00000000, /* EMC_BURST_REFRESH_NUM */
2031 0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */
2032 0x00000002, /* EMC_PDEX2WR */
2033 0x00000002, /* EMC_PDEX2RD */
2034 0x00000002, /* EMC_PCHG2PDEN */
2035 0x00000000, /* EMC_ACT2PDEN */
2036 0x00000001, /* EMC_AR2PDEN */
2037 0x0000000c, /* EMC_RW2PDEN */
2038 0x00000002, /* EMC_TXSR */
2039 0x00000002, /* EMC_TXSRDLL */
2040 0x00000003, /* EMC_TCKE */
2041 0x00000003, /* EMC_TCKESR */
2042 0x00000003, /* EMC_TPD */
2043 0x00000008, /* EMC_TFAW */
2044 0x00000004, /* EMC_TRPAB */
2045 0x00000001, /* EMC_TCLKSTABLE */
2046 0x00000003, /* EMC_TCLKSTOP */
2047 0x00000036, /* EMC_TREFBW */
2048 0x00000005, /* EMC_QUSE_EXTRA */
2049 0x00000020, /* EMC_ODT_WRITE */
2050 0x00000000, /* EMC_ODT_READ */
2051 0x0001aa86, /* EMC_FBIO_CFG5 */
2052 0x005800a8, /* EMC_CFG_DIG_DLL */
2053 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2054 0x0007c000, /* EMC_DLL_XFORM_DQS4 */
2055 0x0007c000, /* EMC_DLL_XFORM_DQS5 */
2056 0x0007c000, /* EMC_DLL_XFORM_DQS6 */
2057 0x0007c000, /* EMC_DLL_XFORM_DQS7 */
2058 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2059 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2060 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2061 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2062 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2063 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2064 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2065 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2066 0x00010220, /* EMC_XM2CMDPADCTRL */
2067 0x00000000, /* EMC_XM2CMDPADCTRL4 */
2068 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
2069 0x00000000, /* EMC_XM2DQPADCTRL2 */
2070 0x77ffc004, /* EMC_XM2CLKPADCTRL */
2071 0x81f1f008, /* EMC_XM2COMPPADCTRL */
2072 0x00000000, /* EMC_XM2VTTGENPADCTRL */
2073 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2074 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2075 0x00000000, /* EMC_TXDSRVTTGEN */
2076 0x02000100, /* EMC_FBIO_SPARE */
2077 0x00000802, /* EMC_CTT_TERM_CTRL */
2078 0x00064000, /* EMC_ZCAL_INTERVAL */
2079 0x0000000f, /* EMC_ZCAL_WAIT_CNT */
2080 0x000f000f, /* EMC_MRS_WAIT_CNT */
2081 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
2082 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2083 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2084 0x00000000, /* EMC_CTT */
2085 0x00000000, /* EMC_CTT_DURATION */
2086 0x80000165, /* EMC_DYN_SELF_REF_CONTROL */
2087 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2088 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2089 0x40040001, /* MC_EMEM_ARB_CFG */
2090 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2091 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2092 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2093 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2094 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2095 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2096 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2097 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2098 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2099 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2100 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2101 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2102 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
2103 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
2104 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
2105 0x77c30303, /* MC_EMEM_ARB_MISC0 */
2106 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2109 0x00000000, /* EMC_CDB_CNTL_1 */
2110 0x00000006, /* EMC_FBIO_CFG6 */
2111 0x00000007, /* EMC_QUSE */
2112 0x00000004, /* EMC_EINPUT */
2113 0x00000005, /* EMC_EINPUT_DURATION */
2114 0x00030000, /* EMC_DLL_XFORM_DQS0 */
2115 0x0000000a, /* EMC_QSAFE */
2116 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2117 0x0000000d, /* EMC_RDV */
2118 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2119 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2120 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2121 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2122 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2123 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2124 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2125 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2126 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2127 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2128 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2129 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2130 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2131 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2132 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2133 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2134 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2135 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2136 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2137 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2138 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2141 0x00000000, /* EMC_CDB_CNTL_1 */
2142 0x00000006, /* EMC_FBIO_CFG6 */
2143 0x00000007, /* EMC_QUSE */
2144 0x00000004, /* EMC_EINPUT */
2145 0x00000005, /* EMC_EINPUT_DURATION */
2146 0x0007c000, /* EMC_DLL_XFORM_DQS0 */
2147 0x0000000a, /* EMC_QSAFE */
2148 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2149 0x0000000d, /* EMC_RDV */
2150 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2151 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2152 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2153 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2154 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2155 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2156 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2157 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2158 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2159 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2160 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2161 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2162 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2163 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2164 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2165 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2166 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2167 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2168 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2169 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2170 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2173 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
2174 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
2175 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
2176 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
2177 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2178 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
2179 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
2180 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2181 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
2182 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2183 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2185 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
2186 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2187 0xf320000e, /* EMC_CFG */
2188 0x00000000, /* Mode Register 0 */
2189 0x80010083, /* Mode Register 1 */
2190 0x80020004, /* Mode Register 2 */
2191 0x800b0000, /* Mode Register 4 */
2192 57820, /* expected dvfs latency (ns) */
2195 0x41, /* Rev 4.0.3 */
2196 20400, /* SDRAM frequency */
2197 900, /* min voltage */
2198 "pll_p", /* clock source id */
2199 0x40000026, /* CLK_SOURCE_EMC */
2200 99, /* number of burst_regs */
2201 30, /* number of trim_regs (each channel) */
2202 11, /* number of up_down_regs */
2204 0x00000001, /* EMC_RC */
2205 0x00000003, /* EMC_RFC */
2206 0x00000000, /* EMC_RFC_SLR */
2207 0x00000002, /* EMC_RAS */
2208 0x00000002, /* EMC_RP */
2209 0x00000006, /* EMC_R2W */
2210 0x00000008, /* EMC_W2R */
2211 0x00000003, /* EMC_R2P */
2212 0x0000000a, /* EMC_W2P */
2213 0x00000002, /* EMC_RD_RCD */
2214 0x00000002, /* EMC_WR_RCD */
2215 0x00000001, /* EMC_RRD */
2216 0x00000001, /* EMC_REXT */
2217 0x00000000, /* EMC_WEXT */
2218 0x00000003, /* EMC_WDV */
2219 0x00000003, /* EMC_WDV_MASK */
2220 0x00000005, /* EMC_IBDLY */
2221 0x00010000, /* EMC_PUTERM_EXTRA */
2222 0x00000000, /* EMC_CDB_CNTL_2 */
2223 0x00000004, /* EMC_QRST */
2224 0x0000000d, /* EMC_RDV_MASK */
2225 0x0000004c, /* EMC_REFRESH */
2226 0x00000000, /* EMC_BURST_REFRESH_NUM */
2227 0x00000013, /* EMC_PRE_REFRESH_REQ_CNT */
2228 0x00000002, /* EMC_PDEX2WR */
2229 0x00000002, /* EMC_PDEX2RD */
2230 0x00000002, /* EMC_PCHG2PDEN */
2231 0x00000000, /* EMC_ACT2PDEN */
2232 0x00000001, /* EMC_AR2PDEN */
2233 0x0000000c, /* EMC_RW2PDEN */
2234 0x00000003, /* EMC_TXSR */
2235 0x00000003, /* EMC_TXSRDLL */
2236 0x00000003, /* EMC_TCKE */
2237 0x00000003, /* EMC_TCKESR */
2238 0x00000003, /* EMC_TPD */
2239 0x00000008, /* EMC_TFAW */
2240 0x00000004, /* EMC_TRPAB */
2241 0x00000001, /* EMC_TCLKSTABLE */
2242 0x00000003, /* EMC_TCLKSTOP */
2243 0x00000055, /* EMC_TREFBW */
2244 0x00000005, /* EMC_QUSE_EXTRA */
2245 0x00000020, /* EMC_ODT_WRITE */
2246 0x00000000, /* EMC_ODT_READ */
2247 0x0001aa86, /* EMC_FBIO_CFG5 */
2248 0x005800a8, /* EMC_CFG_DIG_DLL */
2249 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2250 0x0007c000, /* EMC_DLL_XFORM_DQS4 */
2251 0x0007c000, /* EMC_DLL_XFORM_DQS5 */
2252 0x0007c000, /* EMC_DLL_XFORM_DQS6 */
2253 0x0007c000, /* EMC_DLL_XFORM_DQS7 */
2254 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2255 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2256 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2257 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2258 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2259 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2260 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2261 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2262 0x00010220, /* EMC_XM2CMDPADCTRL */
2263 0x00000000, /* EMC_XM2CMDPADCTRL4 */
2264 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
2265 0x00000000, /* EMC_XM2DQPADCTRL2 */
2266 0x77ffc004, /* EMC_XM2CLKPADCTRL */
2267 0x81f1f008, /* EMC_XM2COMPPADCTRL */
2268 0x00000000, /* EMC_XM2VTTGENPADCTRL */
2269 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2270 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2271 0x00000000, /* EMC_TXDSRVTTGEN */
2272 0x02000100, /* EMC_FBIO_SPARE */
2273 0x00000802, /* EMC_CTT_TERM_CTRL */
2274 0x00064000, /* EMC_ZCAL_INTERVAL */
2275 0x0000000f, /* EMC_ZCAL_WAIT_CNT */
2276 0x000f000f, /* EMC_MRS_WAIT_CNT */
2277 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
2278 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2279 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2280 0x00000000, /* EMC_CTT */
2281 0x00000000, /* EMC_CTT_DURATION */
2282 0x8000019f, /* EMC_DYN_SELF_REF_CONTROL */
2283 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2284 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2285 0x40020001, /* MC_EMEM_ARB_CFG */
2286 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2287 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2288 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2289 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2290 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2291 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2292 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2293 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2294 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2295 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2296 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2297 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2298 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
2299 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
2300 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
2301 0x74e30303, /* MC_EMEM_ARB_MISC0 */
2302 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2305 0x00000000, /* EMC_CDB_CNTL_1 */
2306 0x00000006, /* EMC_FBIO_CFG6 */
2307 0x00000007, /* EMC_QUSE */
2308 0x00000004, /* EMC_EINPUT */
2309 0x00000005, /* EMC_EINPUT_DURATION */
2310 0x00030000, /* EMC_DLL_XFORM_DQS0 */
2311 0x0000000a, /* EMC_QSAFE */
2312 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2313 0x0000000d, /* EMC_RDV */
2314 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2315 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2316 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2317 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2318 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2319 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2320 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2321 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2322 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2323 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2324 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2325 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2326 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2327 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2328 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2329 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2330 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2331 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2332 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2333 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2334 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2337 0x00000000, /* EMC_CDB_CNTL_1 */
2338 0x00000006, /* EMC_FBIO_CFG6 */
2339 0x00000007, /* EMC_QUSE */
2340 0x00000004, /* EMC_EINPUT */
2341 0x00000005, /* EMC_EINPUT_DURATION */
2342 0x0007c000, /* EMC_DLL_XFORM_DQS0 */
2343 0x0000000a, /* EMC_QSAFE */
2344 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2345 0x0000000d, /* EMC_RDV */
2346 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2347 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2348 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2349 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2350 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2351 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2352 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2353 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2354 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2355 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2356 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2357 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2358 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2359 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2360 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2361 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2362 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2363 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2364 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2365 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2366 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2369 0x00000014, /* MC_PTSA_GRANT_DECREMENT */
2370 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
2371 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
2372 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
2373 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2374 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
2375 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
2376 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2377 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
2378 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2379 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2381 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
2382 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2383 0xf320000e, /* EMC_CFG */
2384 0x00000000, /* Mode Register 0 */
2385 0x80010083, /* Mode Register 1 */
2386 0x80020004, /* Mode Register 2 */
2387 0x800b0000, /* Mode Register 4 */
2388 35610, /* expected dvfs latency (ns) */
2391 0x41, /* Rev 4.0.3 */
2392 40800, /* SDRAM frequency */
2393 900, /* min voltage */
2394 "pll_p", /* clock source id */
2395 0x40000012, /* CLK_SOURCE_EMC */
2396 99, /* number of burst_regs */
2397 30, /* number of trim_regs (each channel) */
2398 11, /* number of up_down_regs */
2400 0x00000002, /* EMC_RC */
2401 0x00000005, /* EMC_RFC */
2402 0x00000000, /* EMC_RFC_SLR */
2403 0x00000002, /* EMC_RAS */
2404 0x00000002, /* EMC_RP */
2405 0x00000006, /* EMC_R2W */
2406 0x00000008, /* EMC_W2R */
2407 0x00000003, /* EMC_R2P */
2408 0x0000000a, /* EMC_W2P */
2409 0x00000002, /* EMC_RD_RCD */
2410 0x00000002, /* EMC_WR_RCD */
2411 0x00000001, /* EMC_RRD */
2412 0x00000001, /* EMC_REXT */
2413 0x00000000, /* EMC_WEXT */
2414 0x00000003, /* EMC_WDV */
2415 0x00000003, /* EMC_WDV_MASK */
2416 0x00000005, /* EMC_IBDLY */
2417 0x00010000, /* EMC_PUTERM_EXTRA */
2418 0x00000000, /* EMC_CDB_CNTL_2 */
2419 0x00000004, /* EMC_QRST */
2420 0x0000000d, /* EMC_RDV_MASK */
2421 0x0000009a, /* EMC_REFRESH */
2422 0x00000000, /* EMC_BURST_REFRESH_NUM */
2423 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
2424 0x00000002, /* EMC_PDEX2WR */
2425 0x00000002, /* EMC_PDEX2RD */
2426 0x00000002, /* EMC_PCHG2PDEN */
2427 0x00000000, /* EMC_ACT2PDEN */
2428 0x00000001, /* EMC_AR2PDEN */
2429 0x0000000c, /* EMC_RW2PDEN */
2430 0x00000006, /* EMC_TXSR */
2431 0x00000006, /* EMC_TXSRDLL */
2432 0x00000003, /* EMC_TCKE */
2433 0x00000003, /* EMC_TCKESR */
2434 0x00000003, /* EMC_TPD */
2435 0x00000008, /* EMC_TFAW */
2436 0x00000004, /* EMC_TRPAB */
2437 0x00000001, /* EMC_TCLKSTABLE */
2438 0x00000003, /* EMC_TCLKSTOP */
2439 0x000000aa, /* EMC_TREFBW */
2440 0x00000005, /* EMC_QUSE_EXTRA */
2441 0x00000020, /* EMC_ODT_WRITE */
2442 0x00000000, /* EMC_ODT_READ */
2443 0x0001aa86, /* EMC_FBIO_CFG5 */
2444 0x005800a8, /* EMC_CFG_DIG_DLL */
2445 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2446 0x0007c000, /* EMC_DLL_XFORM_DQS4 */
2447 0x0007c000, /* EMC_DLL_XFORM_DQS5 */
2448 0x0007c000, /* EMC_DLL_XFORM_DQS6 */
2449 0x0007c000, /* EMC_DLL_XFORM_DQS7 */
2450 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2451 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2452 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2453 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2454 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2455 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2456 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2457 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2458 0x00010220, /* EMC_XM2CMDPADCTRL */
2459 0x00000000, /* EMC_XM2CMDPADCTRL4 */
2460 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
2461 0x00000000, /* EMC_XM2DQPADCTRL2 */
2462 0x77ffc004, /* EMC_XM2CLKPADCTRL */
2463 0x81f1f008, /* EMC_XM2COMPPADCTRL */
2464 0x00000000, /* EMC_XM2VTTGENPADCTRL */
2465 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2466 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2467 0x00000000, /* EMC_TXDSRVTTGEN */
2468 0x02000100, /* EMC_FBIO_SPARE */
2469 0x00000802, /* EMC_CTT_TERM_CTRL */
2470 0x00064000, /* EMC_ZCAL_INTERVAL */
2471 0x0000000f, /* EMC_ZCAL_WAIT_CNT */
2472 0x000f000f, /* EMC_MRS_WAIT_CNT */
2473 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
2474 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2475 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2476 0x00000000, /* EMC_CTT */
2477 0x00000000, /* EMC_CTT_DURATION */
2478 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
2479 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2480 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2481 0xa0000001, /* MC_EMEM_ARB_CFG */
2482 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2483 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2484 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2485 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2486 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2487 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2488 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2489 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2490 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2491 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2492 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2493 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2494 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
2495 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
2496 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
2497 0x73030303, /* MC_EMEM_ARB_MISC0 */
2498 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2501 0x00000000, /* EMC_CDB_CNTL_1 */
2502 0x00000006, /* EMC_FBIO_CFG6 */
2503 0x00000007, /* EMC_QUSE */
2504 0x00000004, /* EMC_EINPUT */
2505 0x00000005, /* EMC_EINPUT_DURATION */
2506 0x00030000, /* EMC_DLL_XFORM_DQS0 */
2507 0x0000000a, /* EMC_QSAFE */
2508 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2509 0x0000000d, /* EMC_RDV */
2510 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2511 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2512 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2513 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2514 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2515 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2516 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2517 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2518 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2519 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2520 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2521 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2522 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2523 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2524 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2525 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2526 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2527 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2528 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2529 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2530 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2533 0x00000000, /* EMC_CDB_CNTL_1 */
2534 0x00000006, /* EMC_FBIO_CFG6 */
2535 0x00000007, /* EMC_QUSE */
2536 0x00000004, /* EMC_EINPUT */
2537 0x00000005, /* EMC_EINPUT_DURATION */
2538 0x0007c000, /* EMC_DLL_XFORM_DQS0 */
2539 0x0000000a, /* EMC_QSAFE */
2540 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2541 0x0000000d, /* EMC_RDV */
2542 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2543 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2544 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2545 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2546 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2547 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2548 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2549 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2550 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2551 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2552 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2553 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2554 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2555 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2556 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2557 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2558 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2559 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2560 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2561 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2562 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2565 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
2566 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
2567 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
2568 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
2569 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2570 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
2571 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
2572 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2573 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
2574 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2575 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2577 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
2578 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2579 0xf320000e, /* EMC_CFG */
2580 0x00000000, /* Mode Register 0 */
2581 0x80010083, /* Mode Register 1 */
2582 0x80020004, /* Mode Register 2 */
2583 0x800b0000, /* Mode Register 4 */
2584 20850, /* expected dvfs latency (ns) */
2587 0x41, /* Rev 4.0.3 */
2588 68000, /* SDRAM frequency */
2589 900, /* min voltage */
2590 "pll_p", /* clock source id */
2591 0x4000000a, /* CLK_SOURCE_EMC */
2592 99, /* number of burst_regs */
2593 30, /* number of trim_regs (each channel) */
2594 11, /* number of up_down_regs */
2596 0x00000004, /* EMC_RC */
2597 0x00000008, /* EMC_RFC */
2598 0x00000000, /* EMC_RFC_SLR */
2599 0x00000002, /* EMC_RAS */
2600 0x00000002, /* EMC_RP */
2601 0x00000006, /* EMC_R2W */
2602 0x00000008, /* EMC_W2R */
2603 0x00000003, /* EMC_R2P */
2604 0x0000000a, /* EMC_W2P */
2605 0x00000002, /* EMC_RD_RCD */
2606 0x00000002, /* EMC_WR_RCD */
2607 0x00000001, /* EMC_RRD */
2608 0x00000001, /* EMC_REXT */
2609 0x00000000, /* EMC_WEXT */
2610 0x00000003, /* EMC_WDV */
2611 0x00000003, /* EMC_WDV_MASK */
2612 0x00000005, /* EMC_IBDLY */
2613 0x00010000, /* EMC_PUTERM_EXTRA */
2614 0x00000000, /* EMC_CDB_CNTL_2 */
2615 0x00000004, /* EMC_QRST */
2616 0x0000000d, /* EMC_RDV_MASK */
2617 0x00000101, /* EMC_REFRESH */
2618 0x00000000, /* EMC_BURST_REFRESH_NUM */
2619 0x00000040, /* EMC_PRE_REFRESH_REQ_CNT */
2620 0x00000002, /* EMC_PDEX2WR */
2621 0x00000002, /* EMC_PDEX2RD */
2622 0x00000002, /* EMC_PCHG2PDEN */
2623 0x00000000, /* EMC_ACT2PDEN */
2624 0x00000001, /* EMC_AR2PDEN */
2625 0x0000000c, /* EMC_RW2PDEN */
2626 0x0000000a, /* EMC_TXSR */
2627 0x0000000a, /* EMC_TXSRDLL */
2628 0x00000003, /* EMC_TCKE */
2629 0x00000003, /* EMC_TCKESR */
2630 0x00000003, /* EMC_TPD */
2631 0x00000008, /* EMC_TFAW */
2632 0x00000004, /* EMC_TRPAB */
2633 0x00000001, /* EMC_TCLKSTABLE */
2634 0x00000003, /* EMC_TCLKSTOP */
2635 0x0000011b, /* EMC_TREFBW */
2636 0x00000005, /* EMC_QUSE_EXTRA */
2637 0x00000020, /* EMC_ODT_WRITE */
2638 0x00000000, /* EMC_ODT_READ */
2639 0x0001aa86, /* EMC_FBIO_CFG5 */
2640 0x005800a8, /* EMC_CFG_DIG_DLL */
2641 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2642 0x0007c000, /* EMC_DLL_XFORM_DQS4 */
2643 0x0007c000, /* EMC_DLL_XFORM_DQS5 */
2644 0x0007c000, /* EMC_DLL_XFORM_DQS6 */
2645 0x0007c000, /* EMC_DLL_XFORM_DQS7 */
2646 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2647 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2648 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2649 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2650 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2651 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2652 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2653 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2654 0x00010220, /* EMC_XM2CMDPADCTRL */
2655 0x00000000, /* EMC_XM2CMDPADCTRL4 */
2656 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
2657 0x00000000, /* EMC_XM2DQPADCTRL2 */
2658 0x77ffc004, /* EMC_XM2CLKPADCTRL */
2659 0x81f1f008, /* EMC_XM2COMPPADCTRL */
2660 0x00000000, /* EMC_XM2VTTGENPADCTRL */
2661 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2662 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2663 0x00000000, /* EMC_TXDSRVTTGEN */
2664 0x02000100, /* EMC_FBIO_SPARE */
2665 0x00000802, /* EMC_CTT_TERM_CTRL */
2666 0x00064000, /* EMC_ZCAL_INTERVAL */
2667 0x00000019, /* EMC_ZCAL_WAIT_CNT */
2668 0x000f000f, /* EMC_MRS_WAIT_CNT */
2669 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
2670 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2671 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2672 0x00000000, /* EMC_CTT */
2673 0x00000000, /* EMC_CTT_DURATION */
2674 0x80000309, /* EMC_DYN_SELF_REF_CONTROL */
2675 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2676 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2677 0x00000001, /* MC_EMEM_ARB_CFG */
2678 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2679 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2680 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2681 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2682 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2683 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2684 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2685 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2686 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2687 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2688 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2689 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2690 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
2691 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
2692 0x00090402, /* MC_EMEM_ARB_DA_COVERS */
2693 0x72630403, /* MC_EMEM_ARB_MISC0 */
2694 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2697 0x00000000, /* EMC_CDB_CNTL_1 */
2698 0x00000006, /* EMC_FBIO_CFG6 */
2699 0x00000007, /* EMC_QUSE */
2700 0x00000004, /* EMC_EINPUT */
2701 0x00000005, /* EMC_EINPUT_DURATION */
2702 0x00030000, /* EMC_DLL_XFORM_DQS0 */
2703 0x0000000a, /* EMC_QSAFE */
2704 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2705 0x0000000d, /* EMC_RDV */
2706 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2707 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2708 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2709 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2710 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2711 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2712 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2713 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2714 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2715 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2716 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2717 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2718 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2719 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2720 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2721 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2722 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2723 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2724 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2725 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2726 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2729 0x00000000, /* EMC_CDB_CNTL_1 */
2730 0x00000006, /* EMC_FBIO_CFG6 */
2731 0x00000007, /* EMC_QUSE */
2732 0x00000004, /* EMC_EINPUT */
2733 0x00000005, /* EMC_EINPUT_DURATION */
2734 0x0007c000, /* EMC_DLL_XFORM_DQS0 */
2735 0x0000000a, /* EMC_QSAFE */
2736 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2737 0x0000000d, /* EMC_RDV */
2738 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2739 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2740 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2741 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2742 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2743 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2744 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2745 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2746 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2747 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2748 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2749 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2750 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2751 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2752 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2753 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2754 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2755 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2756 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2757 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2758 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2761 0x00000046, /* MC_PTSA_GRANT_DECREMENT */
2762 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
2763 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
2764 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
2765 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2766 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
2767 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
2768 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2769 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
2770 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2771 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2773 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
2774 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2775 0xf320000e, /* EMC_CFG */
2776 0x00000000, /* Mode Register 0 */
2777 0x80010083, /* Mode Register 1 */
2778 0x80020004, /* Mode Register 2 */
2779 0x800b0000, /* Mode Register 4 */
2780 10720, /* expected dvfs latency (ns) */
2783 0x41, /* Rev 4.0.3 */
2784 102000, /* SDRAM frequency */
2785 900, /* min voltage */
2786 "pll_p", /* clock source id */
2787 0x40000006, /* CLK_SOURCE_EMC */
2788 99, /* number of burst_regs */
2789 30, /* number of trim_regs (each channel) */
2790 11, /* number of up_down_regs */
2792 0x00000006, /* EMC_RC */
2793 0x0000000d, /* EMC_RFC */
2794 0x00000000, /* EMC_RFC_SLR */
2795 0x00000004, /* EMC_RAS */
2796 0x00000002, /* EMC_RP */
2797 0x00000006, /* EMC_R2W */
2798 0x00000008, /* EMC_W2R */
2799 0x00000003, /* EMC_R2P */
2800 0x0000000a, /* EMC_W2P */
2801 0x00000002, /* EMC_RD_RCD */
2802 0x00000002, /* EMC_WR_RCD */
2803 0x00000001, /* EMC_RRD */
2804 0x00000001, /* EMC_REXT */
2805 0x00000000, /* EMC_WEXT */
2806 0x00000003, /* EMC_WDV */
2807 0x00000003, /* EMC_WDV_MASK */
2808 0x00000005, /* EMC_IBDLY */
2809 0x00010000, /* EMC_PUTERM_EXTRA */
2810 0x00000000, /* EMC_CDB_CNTL_2 */
2811 0x00000004, /* EMC_QRST */
2812 0x0000000d, /* EMC_RDV_MASK */
2813 0x00000181, /* EMC_REFRESH */
2814 0x00000000, /* EMC_BURST_REFRESH_NUM */
2815 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
2816 0x00000002, /* EMC_PDEX2WR */
2817 0x00000002, /* EMC_PDEX2RD */
2818 0x00000002, /* EMC_PCHG2PDEN */
2819 0x00000000, /* EMC_ACT2PDEN */
2820 0x00000001, /* EMC_AR2PDEN */
2821 0x0000000c, /* EMC_RW2PDEN */
2822 0x0000000f, /* EMC_TXSR */
2823 0x0000000f, /* EMC_TXSRDLL */
2824 0x00000003, /* EMC_TCKE */
2825 0x00000003, /* EMC_TCKESR */
2826 0x00000003, /* EMC_TPD */
2827 0x00000008, /* EMC_TFAW */
2828 0x00000004, /* EMC_TRPAB */
2829 0x00000001, /* EMC_TCLKSTABLE */
2830 0x00000003, /* EMC_TCLKSTOP */
2831 0x000001a9, /* EMC_TREFBW */
2832 0x00000006, /* EMC_QUSE_EXTRA */
2833 0x00000020, /* EMC_ODT_WRITE */
2834 0x00000000, /* EMC_ODT_READ */
2835 0x0001aa86, /* EMC_FBIO_CFG5 */
2836 0x005800a8, /* EMC_CFG_DIG_DLL */
2837 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2838 0x0007c000, /* EMC_DLL_XFORM_DQS4 */
2839 0x0007c000, /* EMC_DLL_XFORM_DQS5 */
2840 0x0007c000, /* EMC_DLL_XFORM_DQS6 */
2841 0x0007c000, /* EMC_DLL_XFORM_DQS7 */
2842 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2843 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2844 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2845 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2846 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2847 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2848 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2849 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2850 0x00010220, /* EMC_XM2CMDPADCTRL */
2851 0x00000000, /* EMC_XM2CMDPADCTRL4 */
2852 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
2853 0x00000000, /* EMC_XM2DQPADCTRL2 */
2854 0x77ffc004, /* EMC_XM2CLKPADCTRL */
2855 0x81f1f008, /* EMC_XM2COMPPADCTRL */
2856 0x00000000, /* EMC_XM2VTTGENPADCTRL */
2857 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2858 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2859 0x00000000, /* EMC_TXDSRVTTGEN */
2860 0x02000100, /* EMC_FBIO_SPARE */
2861 0x00000802, /* EMC_CTT_TERM_CTRL */
2862 0x00064000, /* EMC_ZCAL_INTERVAL */
2863 0x00000025, /* EMC_ZCAL_WAIT_CNT */
2864 0x000f000f, /* EMC_MRS_WAIT_CNT */
2865 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
2866 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2867 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2868 0x00000000, /* EMC_CTT */
2869 0x00000000, /* EMC_CTT_DURATION */
2870 0x8000040c, /* EMC_DYN_SELF_REF_CONTROL */
2871 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2872 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2873 0x08000001, /* MC_EMEM_ARB_CFG */
2874 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2875 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2876 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2877 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
2878 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
2879 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2880 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2881 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2882 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2883 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2884 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2885 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2886 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
2887 0x05040102, /* MC_EMEM_ARB_DA_TURNS */
2888 0x00090403, /* MC_EMEM_ARB_DA_COVERS */
2889 0x72430504, /* MC_EMEM_ARB_MISC0 */
2890 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2893 0x00000000, /* EMC_CDB_CNTL_1 */
2894 0x00000006, /* EMC_FBIO_CFG6 */
2895 0x00000007, /* EMC_QUSE */
2896 0x00000004, /* EMC_EINPUT */
2897 0x00000005, /* EMC_EINPUT_DURATION */
2898 0x00030000, /* EMC_DLL_XFORM_DQS0 */
2899 0x0000000a, /* EMC_QSAFE */
2900 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2901 0x0000000d, /* EMC_RDV */
2902 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2903 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2904 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2905 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2906 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2907 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2908 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2909 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2910 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2911 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2912 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2913 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2914 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2915 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2916 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2917 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2918 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2919 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2920 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2921 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2922 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2925 0x00000000, /* EMC_CDB_CNTL_1 */
2926 0x00000006, /* EMC_FBIO_CFG6 */
2927 0x00000007, /* EMC_QUSE */
2928 0x00000004, /* EMC_EINPUT */
2929 0x00000005, /* EMC_EINPUT_DURATION */
2930 0x0007c000, /* EMC_DLL_XFORM_DQS0 */
2931 0x0000000a, /* EMC_QSAFE */
2932 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2933 0x0000000d, /* EMC_RDV */
2934 0x00208208, /* EMC_XM2DQSPADCTRL4 */
2935 0x20820800, /* EMC_XM2DQSPADCTRL3 */
2936 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
2937 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2938 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2939 0x00000000, /* EMC_XM2CLKPADCTRL2 */
2940 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2941 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2942 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */
2943 0x0007c000, /* EMC_DLL_XFORM_DQS1 */
2944 0x0007c000, /* EMC_DLL_XFORM_DQS2 */
2945 0x0007c000, /* EMC_DLL_XFORM_DQS3 */
2946 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
2947 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
2948 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
2949 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2950 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2951 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2952 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2953 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2954 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2957 0x00000068, /* MC_PTSA_GRANT_DECREMENT */
2958 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
2959 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
2960 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
2961 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2962 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
2963 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
2964 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2965 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
2966 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2967 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2969 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
2970 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2971 0xf320000e, /* EMC_CFG */
2972 0x00000000, /* Mode Register 0 */
2973 0x80010083, /* Mode Register 1 */
2974 0x80020004, /* Mode Register 2 */
2975 0x800b0000, /* Mode Register 4 */
2976 6890, /* expected dvfs latency (ns) */
2979 0x41, /* Rev 4.0.3 */
2980 204000, /* SDRAM frequency */
2981 900, /* min voltage */
2982 "pll_p", /* clock source id */
2983 0x40000002, /* CLK_SOURCE_EMC */
2984 99, /* number of burst_regs */
2985 30, /* number of trim_regs (each channel) */
2986 11, /* number of up_down_regs */
2988 0x0000000c, /* EMC_RC */
2989 0x0000001a, /* EMC_RFC */
2990 0x00000000, /* EMC_RFC_SLR */
2991 0x00000008, /* EMC_RAS */
2992 0x00000003, /* EMC_RP */
2993 0x00000007, /* EMC_R2W */
2994 0x00000008, /* EMC_W2R */
2995 0x00000003, /* EMC_R2P */
2996 0x0000000a, /* EMC_W2P */
2997 0x00000003, /* EMC_RD_RCD */
2998 0x00000003, /* EMC_WR_RCD */
2999 0x00000002, /* EMC_RRD */
3000 0x00000002, /* EMC_REXT */
3001 0x00000000, /* EMC_WEXT */
3002 0x00000003, /* EMC_WDV */
3003 0x00000003, /* EMC_WDV_MASK */
3004 0x00000006, /* EMC_IBDLY */
3005 0x00010000, /* EMC_PUTERM_EXTRA */
3006 0x00000000, /* EMC_CDB_CNTL_2 */
3007 0x00000004, /* EMC_QRST */
3008 0x0000000e, /* EMC_RDV_MASK */
3009 0x00000303, /* EMC_REFRESH */
3010 0x00000000, /* EMC_BURST_REFRESH_NUM */
3011 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
3012 0x00000002, /* EMC_PDEX2WR */
3013 0x00000002, /* EMC_PDEX2RD */
3014 0x00000003, /* EMC_PCHG2PDEN */
3015 0x00000000, /* EMC_ACT2PDEN */
3016 0x00000001, /* EMC_AR2PDEN */
3017 0x0000000c, /* EMC_RW2PDEN */
3018 0x0000001d, /* EMC_TXSR */
3019 0x0000001d, /* EMC_TXSRDLL */
3020 0x00000004, /* EMC_TCKE */
3021 0x00000004, /* EMC_TCKESR */
3022 0x00000004, /* EMC_TPD */
3023 0x0000000b, /* EMC_TFAW */
3024 0x00000005, /* EMC_TRPAB */
3025 0x00000001, /* EMC_TCLKSTABLE */
3026 0x00000003, /* EMC_TCLKSTOP */
3027 0x00000351, /* EMC_TREFBW */
3028 0x00000006, /* EMC_QUSE_EXTRA */
3029 0x00000020, /* EMC_ODT_WRITE */
3030 0x00000000, /* EMC_ODT_READ */
3031 0x0001aa86, /* EMC_FBIO_CFG5 */
3032 0x005800a8, /* EMC_CFG_DIG_DLL */
3033 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3034 0x00030000, /* EMC_DLL_XFORM_DQS4 */
3035 0x00030000, /* EMC_DLL_XFORM_DQS5 */
3036 0x00030000, /* EMC_DLL_XFORM_DQS6 */
3037 0x00030000, /* EMC_DLL_XFORM_DQS7 */
3038 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3039 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3040 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3041 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3042 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3043 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3044 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3045 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3046 0x00010220, /* EMC_XM2CMDPADCTRL */
3047 0x00000000, /* EMC_XM2CMDPADCTRL4 */
3048 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
3049 0x00000000, /* EMC_XM2DQPADCTRL2 */
3050 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3051 0x81f1f008, /* EMC_XM2COMPPADCTRL */
3052 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3053 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
3054 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3055 0x00000000, /* EMC_TXDSRVTTGEN */
3056 0x02000100, /* EMC_FBIO_SPARE */
3057 0x00000802, /* EMC_CTT_TERM_CTRL */
3058 0x00064000, /* EMC_ZCAL_INTERVAL */
3059 0x0000004a, /* EMC_ZCAL_WAIT_CNT */
3060 0x000f000f, /* EMC_MRS_WAIT_CNT */
3061 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
3062 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3063 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3064 0x00000000, /* EMC_CTT */
3065 0x00000000, /* EMC_CTT_DURATION */
3066 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
3067 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3068 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3069 0x01000003, /* MC_EMEM_ARB_CFG */
3070 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3071 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3072 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3073 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
3074 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
3075 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3076 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3077 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3078 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3079 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3080 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3081 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
3082 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
3083 0x05050102, /* MC_EMEM_ARB_DA_TURNS */
3084 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
3085 0x71e40a07, /* MC_EMEM_ARB_MISC0 */
3086 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3089 0x00000000, /* EMC_CDB_CNTL_1 */
3090 0x00000006, /* EMC_FBIO_CFG6 */
3091 0x00000007, /* EMC_QUSE */
3092 0x00000004, /* EMC_EINPUT */
3093 0x00000005, /* EMC_EINPUT_DURATION */
3094 0x00030000, /* EMC_DLL_XFORM_DQS0 */
3095 0x0000000a, /* EMC_QSAFE */
3096 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3097 0x0000000e, /* EMC_RDV */
3098 0x00208208, /* EMC_XM2DQSPADCTRL4 */
3099 0x20820800, /* EMC_XM2DQSPADCTRL3 */
3100 0x00040000, /* EMC_DLL_XFORM_DQ0 */
3101 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3102 0x00040000, /* EMC_DLL_XFORM_ADDR0 */
3103 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3104 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3105 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3106 0x00040000, /* EMC_DLL_XFORM_ADDR2 */
3107 0x00030000, /* EMC_DLL_XFORM_DQS1 */
3108 0x00030000, /* EMC_DLL_XFORM_DQS2 */
3109 0x00030000, /* EMC_DLL_XFORM_DQS3 */
3110 0x00040000, /* EMC_DLL_XFORM_DQ1 */
3111 0x00040000, /* EMC_DLL_XFORM_DQ2 */
3112 0x00040000, /* EMC_DLL_XFORM_DQ3 */
3113 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3114 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3115 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3116 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3117 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3118 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3121 0x00000000, /* EMC_CDB_CNTL_1 */
3122 0x00000006, /* EMC_FBIO_CFG6 */
3123 0x00000007, /* EMC_QUSE */
3124 0x00000004, /* EMC_EINPUT */
3125 0x00000005, /* EMC_EINPUT_DURATION */
3126 0x00030000, /* EMC_DLL_XFORM_DQS0 */
3127 0x0000000a, /* EMC_QSAFE */
3128 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3129 0x0000000e, /* EMC_RDV */
3130 0x00208208, /* EMC_XM2DQSPADCTRL4 */
3131 0x20820800, /* EMC_XM2DQSPADCTRL3 */
3132 0x00040000, /* EMC_DLL_XFORM_DQ0 */
3133 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3134 0x00040000, /* EMC_DLL_XFORM_ADDR0 */
3135 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3136 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3137 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3138 0x00040000, /* EMC_DLL_XFORM_ADDR2 */
3139 0x00030000, /* EMC_DLL_XFORM_DQS1 */
3140 0x00030000, /* EMC_DLL_XFORM_DQS2 */
3141 0x00030000, /* EMC_DLL_XFORM_DQS3 */
3142 0x00040000, /* EMC_DLL_XFORM_DQ1 */
3143 0x00040000, /* EMC_DLL_XFORM_DQ2 */
3144 0x00040000, /* EMC_DLL_XFORM_DQ3 */
3145 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3146 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3147 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3148 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3149 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3150 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3153 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
3154 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
3155 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
3156 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
3157 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3158 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
3159 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
3160 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3161 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
3162 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3163 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3165 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */
3166 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3167 0xf320000e, /* EMC_CFG */
3168 0x00000000, /* Mode Register 0 */
3169 0x80010083, /* Mode Register 1 */
3170 0x80020004, /* Mode Register 2 */
3171 0x800b0000, /* Mode Register 4 */
3172 3420, /* expected dvfs latency (ns) */
3175 0x41, /* Rev 4.0.3 */
3176 312000, /* SDRAM frequency */
3177 1000, /* min voltage */
3178 "pll_c", /* clock source id */
3179 0x24000002, /* CLK_SOURCE_EMC */
3180 99, /* number of burst_regs */
3181 30, /* number of trim_regs (each channel) */
3182 11, /* number of up_down_regs */
3184 0x00000012, /* EMC_RC */
3185 0x00000028, /* EMC_RFC */
3186 0x00000000, /* EMC_RFC_SLR */
3187 0x0000000d, /* EMC_RAS */
3188 0x00000005, /* EMC_RP */
3189 0x00000008, /* EMC_R2W */
3190 0x00000008, /* EMC_W2R */
3191 0x00000003, /* EMC_R2P */
3192 0x0000000a, /* EMC_W2P */
3193 0x00000005, /* EMC_RD_RCD */
3194 0x00000005, /* EMC_WR_RCD */
3195 0x00000003, /* EMC_RRD */
3196 0x00000002, /* EMC_REXT */
3197 0x00000000, /* EMC_WEXT */
3198 0x00000003, /* EMC_WDV */
3199 0x0000000f, /* EMC_WDV_MASK */
3200 0x00000006, /* EMC_IBDLY */
3201 0x00010000, /* EMC_PUTERM_EXTRA */
3202 0x00000000, /* EMC_CDB_CNTL_2 */
3203 0x00000004, /* EMC_QRST */
3204 0x00000011, /* EMC_RDV_MASK */
3205 0x0000049d, /* EMC_REFRESH */
3206 0x00000000, /* EMC_BURST_REFRESH_NUM */
3207 0x00000127, /* EMC_PRE_REFRESH_REQ_CNT */
3208 0x00000002, /* EMC_PDEX2WR */
3209 0x00000002, /* EMC_PDEX2RD */
3210 0x00000005, /* EMC_PCHG2PDEN */
3211 0x00000000, /* EMC_ACT2PDEN */
3212 0x00000001, /* EMC_AR2PDEN */
3213 0x0000000d, /* EMC_RW2PDEN */
3214 0x0000002c, /* EMC_TXSR */
3215 0x0000002c, /* EMC_TXSRDLL */
3216 0x00000005, /* EMC_TCKE */
3217 0x00000005, /* EMC_TCKESR */
3218 0x00000005, /* EMC_TPD */
3219 0x00000010, /* EMC_TFAW */
3220 0x00000007, /* EMC_TRPAB */
3221 0x00000001, /* EMC_TCLKSTABLE */
3222 0x00000003, /* EMC_TCLKSTOP */
3223 0x00000514, /* EMC_TREFBW */
3224 0x00000006, /* EMC_QUSE_EXTRA */
3225 0x00000020, /* EMC_ODT_WRITE */
3226 0x00000000, /* EMC_ODT_READ */
3227 0x0001aa86, /* EMC_FBIO_CFG5 */
3228 0x00580088, /* EMC_CFG_DIG_DLL */
3229 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3230 0x00020000, /* EMC_DLL_XFORM_DQS4 */
3231 0x00020000, /* EMC_DLL_XFORM_DQS5 */
3232 0x00020000, /* EMC_DLL_XFORM_DQS6 */
3233 0x00020000, /* EMC_DLL_XFORM_DQS7 */
3234 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3235 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3236 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3237 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3238 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3239 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3240 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3241 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3242 0x00010220, /* EMC_XM2CMDPADCTRL */
3243 0x00000000, /* EMC_XM2CMDPADCTRL4 */
3244 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
3245 0x00000000, /* EMC_XM2DQPADCTRL2 */
3246 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3247 0x81f1f008, /* EMC_XM2COMPPADCTRL */
3248 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3249 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
3250 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3251 0x00000000, /* EMC_TXDSRVTTGEN */
3252 0x02000100, /* EMC_FBIO_SPARE */
3253 0x00000802, /* EMC_CTT_TERM_CTRL */
3254 0x00064000, /* EMC_ZCAL_INTERVAL */
3255 0x00000071, /* EMC_ZCAL_WAIT_CNT */
3256 0x000f000f, /* EMC_MRS_WAIT_CNT */
3257 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
3258 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3259 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3260 0x00000000, /* EMC_CTT */
3261 0x00000000, /* EMC_CTT_DURATION */
3262 0x80000a4c, /* EMC_DYN_SELF_REF_CONTROL */
3263 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3264 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3265 0x0b000004, /* MC_EMEM_ARB_CFG */
3266 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3267 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3268 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3269 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3270 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3271 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
3272 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3273 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3274 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3275 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3276 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3277 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
3278 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
3279 0x05050102, /* MC_EMEM_ARB_DA_TURNS */
3280 0x000c0709, /* MC_EMEM_ARB_DA_COVERS */
3281 0x71c50f0a, /* MC_EMEM_ARB_MISC0 */
3282 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3285 0x00000000, /* EMC_CDB_CNTL_1 */
3286 0x00000004, /* EMC_FBIO_CFG6 */
3287 0x00000009, /* EMC_QUSE */
3288 0x00000004, /* EMC_EINPUT */
3289 0x00000006, /* EMC_EINPUT_DURATION */
3290 0x00020000, /* EMC_DLL_XFORM_DQS0 */
3291 0x0000000d, /* EMC_QSAFE */
3292 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3293 0x0000000f, /* EMC_RDV */
3294 0x00208208, /* EMC_XM2DQSPADCTRL4 */
3295 0x20820800, /* EMC_XM2DQSPADCTRL3 */
3296 0x00038000, /* EMC_DLL_XFORM_DQ0 */
3297 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3298 0x00024000, /* EMC_DLL_XFORM_ADDR0 */
3299 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3300 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3301 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3302 0x00024000, /* EMC_DLL_XFORM_ADDR2 */
3303 0x00020000, /* EMC_DLL_XFORM_DQS1 */
3304 0x00020000, /* EMC_DLL_XFORM_DQS2 */
3305 0x00020000, /* EMC_DLL_XFORM_DQS3 */
3306 0x00038000, /* EMC_DLL_XFORM_DQ1 */
3307 0x00038000, /* EMC_DLL_XFORM_DQ2 */
3308 0x00038000, /* EMC_DLL_XFORM_DQ3 */
3309 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3310 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3311 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3312 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3313 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3314 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3317 0x00000000, /* EMC_CDB_CNTL_1 */
3318 0x00000004, /* EMC_FBIO_CFG6 */
3319 0x00000009, /* EMC_QUSE */
3320 0x00000004, /* EMC_EINPUT */
3321 0x00000006, /* EMC_EINPUT_DURATION */
3322 0x00020000, /* EMC_DLL_XFORM_DQS0 */
3323 0x0000000d, /* EMC_QSAFE */
3324 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3325 0x0000000f, /* EMC_RDV */
3326 0x00208208, /* EMC_XM2DQSPADCTRL4 */
3327 0x20820800, /* EMC_XM2DQSPADCTRL3 */
3328 0x00038000, /* EMC_DLL_XFORM_DQ0 */
3329 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3330 0x00024000, /* EMC_DLL_XFORM_ADDR0 */
3331 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3332 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3333 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3334 0x00024000, /* EMC_DLL_XFORM_ADDR2 */
3335 0x00020000, /* EMC_DLL_XFORM_DQS1 */
3336 0x00020000, /* EMC_DLL_XFORM_DQS2 */
3337 0x00020000, /* EMC_DLL_XFORM_DQS3 */
3338 0x00038000, /* EMC_DLL_XFORM_DQ1 */
3339 0x00038000, /* EMC_DLL_XFORM_DQ2 */
3340 0x00038000, /* EMC_DLL_XFORM_DQ3 */
3341 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3342 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3343 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3344 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3345 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3346 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3349 0x00000140, /* MC_PTSA_GRANT_DECREMENT */
3350 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
3351 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
3352 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
3353 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3354 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
3355 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
3356 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3357 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
3358 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3359 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3361 0x00000021, /* EMC_ZCAL_WAIT_CNT after clock change */
3362 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3363 0xf320000e, /* EMC_CFG */
3364 0x00000000, /* Mode Register 0 */
3365 0x80010083, /* Mode Register 1 */
3366 0x80020004, /* Mode Register 2 */
3367 0x800b0000, /* Mode Register 4 */
3368 2680, /* expected dvfs latency (ns) */
3371 0x41, /* Rev 4.0.3 */
3372 408000, /* SDRAM frequency */
3373 1000, /* min voltage */
3374 "pll_p", /* clock source id */
3375 0x40000000, /* CLK_SOURCE_EMC */
3376 99, /* number of burst_regs */
3377 30, /* number of trim_regs (each channel) */
3378 11, /* number of up_down_regs */
3380 0x00000018, /* EMC_RC */
3381 0x00000035, /* EMC_RFC */
3382 0x00000000, /* EMC_RFC_SLR */
3383 0x00000011, /* EMC_RAS */
3384 0x00000007, /* EMC_RP */
3385 0x0000000a, /* EMC_R2W */
3386 0x00000009, /* EMC_W2R */
3387 0x00000003, /* EMC_R2P */
3388 0x0000000d, /* EMC_W2P */
3389 0x00000007, /* EMC_RD_RCD */
3390 0x00000007, /* EMC_WR_RCD */
3391 0x00000004, /* EMC_RRD */
3392 0x00000002, /* EMC_REXT */
3393 0x00000000, /* EMC_WEXT */
3394 0x00000003, /* EMC_WDV */
3395 0x0000000f, /* EMC_WDV_MASK */
3396 0x00000008, /* EMC_IBDLY */
3397 0x00010000, /* EMC_PUTERM_EXTRA */
3398 0x00000000, /* EMC_CDB_CNTL_2 */
3399 0x00000005, /* EMC_QRST */
3400 0x00000013, /* EMC_RDV_MASK */
3401 0x00000607, /* EMC_REFRESH */
3402 0x00000000, /* EMC_BURST_REFRESH_NUM */
3403 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
3404 0x00000003, /* EMC_PDEX2WR */
3405 0x00000003, /* EMC_PDEX2RD */
3406 0x00000007, /* EMC_PCHG2PDEN */
3407 0x00000000, /* EMC_ACT2PDEN */
3408 0x00000001, /* EMC_AR2PDEN */
3409 0x0000000f, /* EMC_RW2PDEN */
3410 0x0000003a, /* EMC_TXSR */
3411 0x0000003a, /* EMC_TXSRDLL */
3412 0x00000007, /* EMC_TCKE */
3413 0x00000007, /* EMC_TCKESR */
3414 0x00000007, /* EMC_TPD */
3415 0x00000015, /* EMC_TFAW */
3416 0x00000009, /* EMC_TRPAB */
3417 0x00000001, /* EMC_TCLKSTABLE */
3418 0x00000003, /* EMC_TCLKSTOP */
3419 0x000006a2, /* EMC_TREFBW */
3420 0x00000007, /* EMC_QUSE_EXTRA */
3421 0x00000020, /* EMC_ODT_WRITE */
3422 0x00000000, /* EMC_ODT_READ */
3423 0x0001a886, /* EMC_FBIO_CFG5 */
3424 0x00580088, /* EMC_CFG_DIG_DLL */
3425 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3426 0x00020000, /* EMC_DLL_XFORM_DQS4 */
3427 0x00020000, /* EMC_DLL_XFORM_DQS5 */
3428 0x00020000, /* EMC_DLL_XFORM_DQS6 */
3429 0x00020000, /* EMC_DLL_XFORM_DQS7 */
3430 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3431 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3432 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3433 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3434 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3435 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3436 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3437 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3438 0x00010220, /* EMC_XM2CMDPADCTRL */
3439 0x00000000, /* EMC_XM2CMDPADCTRL4 */
3440 0x0001003d, /* EMC_XM2DQSPADCTRL2 */
3441 0x00000000, /* EMC_XM2DQPADCTRL2 */
3442 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3443 0xa1f1f409, /* EMC_XM2COMPPADCTRL */
3444 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3445 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
3446 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3447 0x00000000, /* EMC_TXDSRVTTGEN */
3448 0x02000100, /* EMC_FBIO_SPARE */
3449 0x00000802, /* EMC_CTT_TERM_CTRL */
3450 0x00064000, /* EMC_ZCAL_INTERVAL */
3451 0x00000093, /* EMC_ZCAL_WAIT_CNT */
3452 0x00110011, /* EMC_MRS_WAIT_CNT */
3453 0x00110011, /* EMC_MRS_WAIT_CNT2 */
3454 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3455 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3456 0x00000000, /* EMC_CTT */
3457 0x00000000, /* EMC_CTT_DURATION */
3458 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */
3459 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3460 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3461 0x02000006, /* MC_EMEM_ARB_CFG */
3462 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3463 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
3464 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
3465 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
3466 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
3467 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
3468 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3469 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3470 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3471 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3472 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3473 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
3474 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3475 0x06060102, /* MC_EMEM_ARB_DA_TURNS */
3476 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
3477 0x71c7130d, /* MC_EMEM_ARB_MISC0 */
3478 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3481 0x00000000, /* EMC_CDB_CNTL_1 */
3482 0x00000006, /* EMC_FBIO_CFG6 */
3483 0x0000000a, /* EMC_QUSE */
3484 0x00000006, /* EMC_EINPUT */
3485 0x00000006, /* EMC_EINPUT_DURATION */
3486 0x00020000, /* EMC_DLL_XFORM_DQS0 */
3487 0x0000000e, /* EMC_QSAFE */
3488 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3489 0x00000011, /* EMC_RDV */
3490 0x00249249, /* EMC_XM2DQSPADCTRL4 */
3491 0x14514521, /* EMC_XM2DQSPADCTRL3 */
3492 0x00020000, /* EMC_DLL_XFORM_DQ0 */
3493 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3494 0x00008000, /* EMC_DLL_XFORM_ADDR0 */
3495 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3496 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3497 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3498 0x00008000, /* EMC_DLL_XFORM_ADDR2 */
3499 0x00020000, /* EMC_DLL_XFORM_DQS1 */
3500 0x00020000, /* EMC_DLL_XFORM_DQS2 */
3501 0x00020000, /* EMC_DLL_XFORM_DQS3 */
3502 0x00020000, /* EMC_DLL_XFORM_DQ1 */
3503 0x00020000, /* EMC_DLL_XFORM_DQ2 */
3504 0x00020000, /* EMC_DLL_XFORM_DQ3 */
3505 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3506 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3507 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3508 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3509 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3510 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3513 0x00000000, /* EMC_CDB_CNTL_1 */
3514 0x00000006, /* EMC_FBIO_CFG6 */
3515 0x0000000a, /* EMC_QUSE */
3516 0x00000006, /* EMC_EINPUT */
3517 0x00000006, /* EMC_EINPUT_DURATION */
3518 0x00020000, /* EMC_DLL_XFORM_DQS0 */
3519 0x0000000e, /* EMC_QSAFE */
3520 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3521 0x00000011, /* EMC_RDV */
3522 0x00249249, /* EMC_XM2DQSPADCTRL4 */
3523 0x14514521, /* EMC_XM2DQSPADCTRL3 */
3524 0x00020000, /* EMC_DLL_XFORM_DQ0 */
3525 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3526 0x00008000, /* EMC_DLL_XFORM_ADDR0 */
3527 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3528 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3529 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3530 0x00008000, /* EMC_DLL_XFORM_ADDR2 */
3531 0x00020000, /* EMC_DLL_XFORM_DQS1 */
3532 0x00020000, /* EMC_DLL_XFORM_DQS2 */
3533 0x00020000, /* EMC_DLL_XFORM_DQS3 */
3534 0x00020000, /* EMC_DLL_XFORM_DQ1 */
3535 0x00020000, /* EMC_DLL_XFORM_DQ2 */
3536 0x00020000, /* EMC_DLL_XFORM_DQ3 */
3537 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3538 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3539 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3540 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3541 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3542 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3545 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
3546 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
3547 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
3548 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
3549 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3550 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
3551 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
3552 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3553 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
3554 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3555 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3557 0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */
3558 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3559 0xf3200006, /* EMC_CFG */
3560 0x00000000, /* Mode Register 0 */
3561 0x800100c3, /* Mode Register 1 */
3562 0x80020006, /* Mode Register 2 */
3563 0x800b0000, /* Mode Register 4 */
3564 1750, /* expected dvfs latency (ns) */
3567 0x41, /* Rev 4.0.3 */
3568 624000, /* SDRAM frequency */
3569 1100, /* min voltage */
3570 "pll_c", /* clock source id */
3571 0x24000000, /* CLK_SOURCE_EMC */
3572 99, /* number of burst_regs */
3573 30, /* number of trim_regs (each channel) */
3574 11, /* number of up_down_regs */
3576 0x00000025, /* EMC_RC */
3577 0x00000051, /* EMC_RFC */
3578 0x00000000, /* EMC_RFC_SLR */
3579 0x0000001a, /* EMC_RAS */
3580 0x0000000b, /* EMC_RP */
3581 0x0000000c, /* EMC_R2W */
3582 0x0000000c, /* EMC_W2R */
3583 0x00000004, /* EMC_R2P */
3584 0x00000011, /* EMC_W2P */
3585 0x0000000b, /* EMC_RD_RCD */
3586 0x0000000b, /* EMC_WR_RCD */
3587 0x00000006, /* EMC_RRD */
3588 0x00000003, /* EMC_REXT */
3589 0x00000000, /* EMC_WEXT */
3590 0x00000005, /* EMC_WDV */
3591 0x0000000f, /* EMC_WDV_MASK */
3592 0x0000000b, /* EMC_IBDLY */
3593 0x00010000, /* EMC_PUTERM_EXTRA */
3594 0x00000000, /* EMC_CDB_CNTL_2 */
3595 0x00000007, /* EMC_QRST */
3596 0x00000017, /* EMC_RDV_MASK */
3597 0x00000945, /* EMC_REFRESH */
3598 0x00000000, /* EMC_BURST_REFRESH_NUM */
3599 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
3600 0x00000004, /* EMC_PDEX2WR */
3601 0x00000004, /* EMC_PDEX2RD */
3602 0x0000000b, /* EMC_PCHG2PDEN */
3603 0x00000000, /* EMC_ACT2PDEN */
3604 0x00000001, /* EMC_AR2PDEN */
3605 0x00000014, /* EMC_RW2PDEN */
3606 0x00000058, /* EMC_TXSR */
3607 0x00000058, /* EMC_TXSRDLL */
3608 0x0000000a, /* EMC_TCKE */
3609 0x0000000a, /* EMC_TCKESR */
3610 0x0000000a, /* EMC_TPD */
3611 0x00000020, /* EMC_TFAW */
3612 0x0000000e, /* EMC_TRPAB */
3613 0x00000001, /* EMC_TCLKSTABLE */
3614 0x00000003, /* EMC_TCLKSTOP */
3615 0x00000a28, /* EMC_TREFBW */
3616 0x0000000b, /* EMC_QUSE_EXTRA */
3617 0x00000020, /* EMC_ODT_WRITE */
3618 0x00000000, /* EMC_ODT_READ */
3619 0x0001a886, /* EMC_FBIO_CFG5 */
3620 0xf00d0199, /* EMC_CFG_DIG_DLL */
3621 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3622 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
3623 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
3624 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
3625 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
3626 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3627 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3628 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3629 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3630 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3631 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3632 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3633 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3634 0x00010220, /* EMC_XM2CMDPADCTRL */
3635 0x00000000, /* EMC_XM2CMDPADCTRL4 */
3636 0x0001003d, /* EMC_XM2DQSPADCTRL2 */
3637 0x00000000, /* EMC_XM2DQPADCTRL2 */
3638 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3639 0x81f1f008, /* EMC_XM2COMPPADCTRL */
3640 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3641 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
3642 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3643 0x00000000, /* EMC_TXDSRVTTGEN */
3644 0x02000100, /* EMC_FBIO_SPARE */
3645 0x00000802, /* EMC_CTT_TERM_CTRL */
3646 0x00064000, /* EMC_ZCAL_INTERVAL */
3647 0x000000e1, /* EMC_ZCAL_WAIT_CNT */
3648 0x00130013, /* EMC_MRS_WAIT_CNT */
3649 0x00130013, /* EMC_MRS_WAIT_CNT2 */
3650 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3651 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3652 0x00000000, /* EMC_CTT */
3653 0x00000000, /* EMC_CTT_DURATION */
3654 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
3655 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3656 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3657 0x06000009, /* MC_EMEM_ARB_CFG */
3658 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3659 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3660 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3661 0x00000013, /* MC_EMEM_ARB_TIMING_RC */
3662 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3663 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
3664 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
3665 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3666 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3667 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
3668 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3669 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
3670 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
3671 0x07070103, /* MC_EMEM_ARB_DA_TURNS */
3672 0x00160e13, /* MC_EMEM_ARB_DA_COVERS */
3673 0x71ca1d14, /* MC_EMEM_ARB_MISC0 */
3674 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3677 0x00000000, /* EMC_CDB_CNTL_1 */
3678 0x00000004, /* EMC_FBIO_CFG6 */
3679 0x0000000f, /* EMC_QUSE */
3680 0x00000009, /* EMC_EINPUT */
3681 0x00000007, /* EMC_EINPUT_DURATION */
3682 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
3683 0x00000010, /* EMC_QSAFE */
3684 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3685 0x00000015, /* EMC_RDV */
3686 0x00249249, /* EMC_XM2DQSPADCTRL4 */
3687 0x18618621, /* EMC_XM2DQSPADCTRL3 */
3688 0x00000009, /* EMC_DLL_XFORM_DQ0 */
3689 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3690 0x0000c000, /* EMC_DLL_XFORM_ADDR0 */
3691 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3692 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3693 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3694 0x0000c000, /* EMC_DLL_XFORM_ADDR2 */
3695 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
3696 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
3697 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
3698 0x00000008, /* EMC_DLL_XFORM_DQ1 */
3699 0x00000009, /* EMC_DLL_XFORM_DQ2 */
3700 0x00000008, /* EMC_DLL_XFORM_DQ3 */
3701 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3702 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3703 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3704 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3705 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3706 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3709 0x00000000, /* EMC_CDB_CNTL_1 */
3710 0x00000004, /* EMC_FBIO_CFG6 */
3711 0x0000000f, /* EMC_QUSE */
3712 0x00000009, /* EMC_EINPUT */
3713 0x00000007, /* EMC_EINPUT_DURATION */
3714 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
3715 0x00000010, /* EMC_QSAFE */
3716 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3717 0x00000015, /* EMC_RDV */
3718 0x00249249, /* EMC_XM2DQSPADCTRL4 */
3719 0x18618621, /* EMC_XM2DQSPADCTRL3 */
3720 0x00000009, /* EMC_DLL_XFORM_DQ0 */
3721 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3722 0x0000c000, /* EMC_DLL_XFORM_ADDR0 */
3723 0x00000000, /* EMC_XM2CLKPADCTRL2 */
3724 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3725 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3726 0x0000c000, /* EMC_DLL_XFORM_ADDR2 */
3727 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
3728 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
3729 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
3730 0x00000008, /* EMC_DLL_XFORM_DQ1 */
3731 0x00000009, /* EMC_DLL_XFORM_DQ2 */
3732 0x00000008, /* EMC_DLL_XFORM_DQ3 */
3733 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3734 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3735 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3736 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3737 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3738 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3741 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
3742 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
3743 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
3744 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
3745 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3746 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
3747 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
3748 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3749 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
3750 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3751 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3753 0x0000003d, /* EMC_ZCAL_WAIT_CNT after clock change */
3754 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3755 0xf3200000, /* EMC_CFG */
3756 0x00000000, /* Mode Register 0 */
3757 0x80010003, /* Mode Register 1 */
3758 0x80020018, /* Mode Register 2 */
3759 0x800b0000, /* Mode Register 4 */
3760 1440, /* expected dvfs latency (ns) */
3763 0x41, /* Rev 4.0.3 */
3764 792000, /* SDRAM frequency */
3765 1100, /* min voltage */
3766 "pll_m", /* clock source id */
3767 0x80000000, /* CLK_SOURCE_EMC */
3768 99, /* number of burst_regs */
3769 30, /* number of trim_regs (each channel) */
3770 11, /* number of up_down_regs */
3772 0x0000002f, /* EMC_RC */
3773 0x00000066, /* EMC_RFC */
3774 0x00000000, /* EMC_RFC_SLR */
3775 0x00000021, /* EMC_RAS */
3776 0x0000000e, /* EMC_RP */
3777 0x0000000f, /* EMC_R2W */
3778 0x0000000d, /* EMC_W2R */
3779 0x00000005, /* EMC_R2P */
3780 0x00000013, /* EMC_W2P */
3781 0x0000000e, /* EMC_RD_RCD */
3782 0x0000000e, /* EMC_WR_RCD */
3783 0x00000007, /* EMC_RRD */
3784 0x00000003, /* EMC_REXT */
3785 0x00000000, /* EMC_WEXT */
3786 0x00000005, /* EMC_WDV */
3787 0x0000000f, /* EMC_WDV_MASK */
3788 0x0000000e, /* EMC_IBDLY */
3789 0x00010000, /* EMC_PUTERM_EXTRA */
3790 0x00000000, /* EMC_CDB_CNTL_2 */
3791 0x00000009, /* EMC_QRST */
3792 0x0000001a, /* EMC_RDV_MASK */
3793 0x00000bd0, /* EMC_REFRESH */
3794 0x00000000, /* EMC_BURST_REFRESH_NUM */
3795 0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */
3796 0x00000005, /* EMC_PDEX2WR */
3797 0x00000005, /* EMC_PDEX2RD */
3798 0x0000000e, /* EMC_PCHG2PDEN */
3799 0x00000000, /* EMC_ACT2PDEN */
3800 0x00000001, /* EMC_AR2PDEN */
3801 0x00000017, /* EMC_RW2PDEN */
3802 0x0000006f, /* EMC_TXSR */
3803 0x0000006f, /* EMC_TXSRDLL */
3804 0x0000000c, /* EMC_TCKE */
3805 0x0000000c, /* EMC_TCKESR */
3806 0x0000000c, /* EMC_TPD */
3807 0x00000028, /* EMC_TFAW */
3808 0x00000011, /* EMC_TRPAB */
3809 0x00000001, /* EMC_TCLKSTABLE */
3810 0x00000003, /* EMC_TCLKSTOP */
3811 0x00000cdf, /* EMC_TREFBW */
3812 0x0000000d, /* EMC_QUSE_EXTRA */
3813 0x00000020, /* EMC_ODT_WRITE */
3814 0x00000000, /* EMC_ODT_READ */
3815 0x0001aa86, /* EMC_FBIO_CFG5 */
3816 0xf0070199, /* EMC_CFG_DIG_DLL */
3817 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3818 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
3819 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
3820 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
3821 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
3822 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3823 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3824 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3825 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3826 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3827 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3828 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3829 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3830 0x00010220, /* EMC_XM2CMDPADCTRL */
3831 0x00000000, /* EMC_XM2CMDPADCTRL4 */
3832 0x0000003d, /* EMC_XM2DQSPADCTRL2 */
3833 0x00000000, /* EMC_XM2DQPADCTRL2 */
3834 0x77ffc004, /* EMC_XM2CLKPADCTRL */
3835 0x81f1f408, /* EMC_XM2COMPPADCTRL */
3836 0x00000000, /* EMC_XM2VTTGENPADCTRL */
3837 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
3838 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3839 0x00000000, /* EMC_TXDSRVTTGEN */
3840 0x02000100, /* EMC_FBIO_SPARE */
3841 0x00000802, /* EMC_CTT_TERM_CTRL */
3842 0x00064000, /* EMC_ZCAL_INTERVAL */
3843 0x0000011e, /* EMC_ZCAL_WAIT_CNT */
3844 0x00150015, /* EMC_MRS_WAIT_CNT */
3845 0x00150015, /* EMC_MRS_WAIT_CNT2 */
3846 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3847 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3848 0x00000000, /* EMC_CTT */
3849 0x00000000, /* EMC_CTT_DURATION */
3850 0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */
3851 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3852 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3853 0x0e00000b, /* MC_EMEM_ARB_CFG */
3854 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3855 0x00000006, /* MC_EMEM_ARB_TIMING_RCD */
3856 0x00000007, /* MC_EMEM_ARB_TIMING_RP */
3857 0x00000018, /* MC_EMEM_ARB_TIMING_RC */
3858 0x0000000f, /* MC_EMEM_ARB_TIMING_RAS */
3859 0x00000013, /* MC_EMEM_ARB_TIMING_FAW */
3860 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */
3861 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3862 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3863 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
3864 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3865 0x00000009, /* MC_EMEM_ARB_TIMING_R2W */
3866 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3867 0x08090103, /* MC_EMEM_ARB_DA_TURNS */
3868 0x001a1118, /* MC_EMEM_ARB_DA_COVERS */
3869 0x71ac2419, /* MC_EMEM_ARB_MISC0 */
3870 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3873 0x00000000, /* EMC_CDB_CNTL_1 */
3874 0x00000006, /* EMC_FBIO_CFG6 */
3875 0x00000011, /* EMC_QUSE */
3876 0x0000000b, /* EMC_EINPUT */
3877 0x00000007, /* EMC_EINPUT_DURATION */
3878 0x0000000c, /* EMC_DLL_XFORM_DQS0 */
3879 0x00000011, /* EMC_QSAFE */
3880 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3881 0x00000018, /* EMC_RDV */
3882 0x00249249, /* EMC_XM2DQSPADCTRL4 */
3883 0x20820800, /* EMC_XM2DQSPADCTRL3 */
3884 0x0000000d, /* EMC_DLL_XFORM_DQ0 */
3885 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3886 0x00000010, /* EMC_DLL_XFORM_ADDR0 */
3887 0x00000808, /* EMC_XM2CLKPADCTRL2 */
3888 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3889 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3890 0x0000000f, /* EMC_DLL_XFORM_ADDR2 */
3891 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
3892 0x00000009, /* EMC_DLL_XFORM_DQS2 */
3893 0x0000000b, /* EMC_DLL_XFORM_DQS3 */
3894 0x0000000d, /* EMC_DLL_XFORM_DQ1 */
3895 0x0000000d, /* EMC_DLL_XFORM_DQ2 */
3896 0x0000000d, /* EMC_DLL_XFORM_DQ3 */
3897 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3898 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3899 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3900 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3901 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3902 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3905 0x00000000, /* EMC_CDB_CNTL_1 */
3906 0x00000006, /* EMC_FBIO_CFG6 */
3907 0x00000011, /* EMC_QUSE */
3908 0x0000000b, /* EMC_EINPUT */
3909 0x00000007, /* EMC_EINPUT_DURATION */
3910 0x0000000c, /* EMC_DLL_XFORM_DQS0 */
3911 0x00000011, /* EMC_QSAFE */
3912 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3913 0x00000018, /* EMC_RDV */
3914 0x00249249, /* EMC_XM2DQSPADCTRL4 */
3915 0x20820800, /* EMC_XM2DQSPADCTRL3 */
3916 0x0000000d, /* EMC_DLL_XFORM_DQ0 */
3917 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3918 0x00000010, /* EMC_DLL_XFORM_ADDR0 */
3919 0x00000808, /* EMC_XM2CLKPADCTRL2 */
3920 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3921 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3922 0x0000000f, /* EMC_DLL_XFORM_ADDR2 */
3923 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
3924 0x00000009, /* EMC_DLL_XFORM_DQS2 */
3925 0x0000000b, /* EMC_DLL_XFORM_DQS3 */
3926 0x0000000d, /* EMC_DLL_XFORM_DQ1 */
3927 0x0000000d, /* EMC_DLL_XFORM_DQ2 */
3928 0x0000000d, /* EMC_DLL_XFORM_DQ3 */
3929 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3930 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3931 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3932 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3933 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3934 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3937 0x00000196, /* MC_PTSA_GRANT_DECREMENT */
3938 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
3939 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
3940 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
3941 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3942 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
3943 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
3944 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3945 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
3946 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3947 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3949 0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */
3950 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3951 0xf3200000, /* EMC_CFG */
3952 0x00000000, /* Mode Register 0 */
3953 0x80010043, /* Mode Register 1 */
3954 0x8002001a, /* Mode Register 2 */
3955 0x800b0000, /* Mode Register 4 */
3956 1200, /* expected dvfs latency (ns) */
3960 static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_table[] = {
3963 204000, /* SDRAM frequency */
3964 1000, /* min voltage */
3965 "pll_p", /* clock source id */
3966 0x40000002, /* CLK_SOURCE_EMC */
3967 99, /* number of burst_regs */
3968 30, /* number of trim_regs (each channel) */
3969 11, /* number of up_down_regs */
3971 0x0000000c, /* EMC_RC */
3972 0x0000001a, /* EMC_RFC */
3973 0x00000000, /* EMC_RFC_SLR */
3974 0x00000008, /* EMC_RAS */
3975 0x00000003, /* EMC_RP */
3976 0x00000007, /* EMC_R2W */
3977 0x00000008, /* EMC_W2R */
3978 0x00000003, /* EMC_R2P */
3979 0x0000000a, /* EMC_W2P */
3980 0x00000003, /* EMC_RD_RCD */
3981 0x00000003, /* EMC_WR_RCD */
3982 0x00000002, /* EMC_RRD */
3983 0x00000002, /* EMC_REXT */
3984 0x00000000, /* EMC_WEXT */
3985 0x00000003, /* EMC_WDV */
3986 0x00000003, /* EMC_WDV_MASK */
3987 0x00000006, /* EMC_IBDLY */
3988 0x00010000, /* EMC_PUTERM_EXTRA */
3989 0x00000000, /* EMC_CDB_CNTL_2 */
3990 0x00000004, /* EMC_QRST */
3991 0x0000000e, /* EMC_RDV_MASK */
3992 0x00000303, /* EMC_REFRESH */
3993 0x00000000, /* EMC_BURST_REFRESH_NUM */
3994 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
3995 0x00000002, /* EMC_PDEX2WR */
3996 0x00000002, /* EMC_PDEX2RD */
3997 0x00000003, /* EMC_PCHG2PDEN */
3998 0x00000000, /* EMC_ACT2PDEN */
3999 0x00000001, /* EMC_AR2PDEN */
4000 0x0000000c, /* EMC_RW2PDEN */
4001 0x0000001d, /* EMC_TXSR */
4002 0x0000001d, /* EMC_TXSRDLL */
4003 0x00000004, /* EMC_TCKE */
4004 0x00000004, /* EMC_TCKESR */
4005 0x00000004, /* EMC_TPD */
4006 0x0000000b, /* EMC_TFAW */
4007 0x00000005, /* EMC_TRPAB */
4008 0x00000001, /* EMC_TCLKSTABLE */
4009 0x00000003, /* EMC_TCLKSTOP */
4010 0x00000351, /* EMC_TREFBW */
4011 0x00000006, /* EMC_QUSE_EXTRA */
4012 0x00000020, /* EMC_ODT_WRITE */
4013 0x00000000, /* EMC_ODT_READ */
4014 0x0001aa86, /* EMC_FBIO_CFG5 */
4015 0x005800a8, /* EMC_CFG_DIG_DLL */
4016 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4017 0x00030000, /* EMC_DLL_XFORM_DQS4 */
4018 0x00030000, /* EMC_DLL_XFORM_DQS5 */
4019 0x00030000, /* EMC_DLL_XFORM_DQS6 */
4020 0x00030000, /* EMC_DLL_XFORM_DQS7 */
4021 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
4022 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
4023 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
4024 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
4025 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4026 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4027 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4028 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4029 0x00010220, /* EMC_XM2CMDPADCTRL */
4030 0x00000000, /* EMC_XM2CMDPADCTRL4 */
4031 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */
4032 0x00000000, /* EMC_XM2DQPADCTRL2 */
4033 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4034 0x81f1f008, /* EMC_XM2COMPPADCTRL */
4035 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4036 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
4037 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
4038 0x00000000, /* EMC_TXDSRVTTGEN */
4039 0x02000100, /* EMC_FBIO_SPARE */
4040 0x00000802, /* EMC_CTT_TERM_CTRL */
4041 0x00064000, /* EMC_ZCAL_INTERVAL */
4042 0x0000004a, /* EMC_ZCAL_WAIT_CNT */
4043 0x000f000f, /* EMC_MRS_WAIT_CNT */
4044 0x000f000f, /* EMC_MRS_WAIT_CNT2 */
4045 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
4046 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
4047 0x00000000, /* EMC_CTT */
4048 0x00000000, /* EMC_CTT_DURATION */
4049 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
4050 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
4051 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
4052 0x01000003, /* MC_EMEM_ARB_CFG */
4053 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4054 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
4055 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
4056 0x00000006, /* MC_EMEM_ARB_TIMING_RC */
4057 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
4058 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
4059 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
4060 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4061 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4062 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
4063 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
4064 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
4065 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
4066 0x05050102, /* MC_EMEM_ARB_DA_TURNS */
4067 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
4068 0x71e40a07, /* MC_EMEM_ARB_MISC0 */
4069 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4072 0x00000000, /* EMC_CDB_CNTL_1 */
4073 0x00000006, /* EMC_FBIO_CFG6 */
4074 0x00000007, /* EMC_QUSE */
4075 0x00000004, /* EMC_EINPUT */
4076 0x00000005, /* EMC_EINPUT_DURATION */
4077 0x00030000, /* EMC_DLL_XFORM_DQS0 */
4078 0x0000000a, /* EMC_QSAFE */
4079 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4080 0x0000000e, /* EMC_RDV */
4081 0x00208208, /* EMC_XM2DQSPADCTRL4 */
4082 0x20820800, /* EMC_XM2DQSPADCTRL3 */
4083 0x00040000, /* EMC_DLL_XFORM_DQ0 */
4084 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4085 0x00040000, /* EMC_DLL_XFORM_ADDR0 */
4086 0x00000000, /* EMC_XM2CLKPADCTRL2 */
4087 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4088 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
4089 0x00040000, /* EMC_DLL_XFORM_ADDR2 */
4090 0x00030000, /* EMC_DLL_XFORM_DQS1 */
4091 0x00030000, /* EMC_DLL_XFORM_DQS2 */
4092 0x00030000, /* EMC_DLL_XFORM_DQS3 */
4093 0x00040000, /* EMC_DLL_XFORM_DQ1 */
4094 0x00040000, /* EMC_DLL_XFORM_DQ2 */
4095 0x00040000, /* EMC_DLL_XFORM_DQ3 */
4096 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4097 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4098 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4099 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4100 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4101 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4104 0x00000000, /* EMC_CDB_CNTL_1 */
4105 0x00000006, /* EMC_FBIO_CFG6 */
4106 0x00000007, /* EMC_QUSE */
4107 0x00000004, /* EMC_EINPUT */
4108 0x00000005, /* EMC_EINPUT_DURATION */
4109 0x00030000, /* EMC_DLL_XFORM_DQS0 */
4110 0x0000000a, /* EMC_QSAFE */
4111 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4112 0x0000000e, /* EMC_RDV */
4113 0x00208208, /* EMC_XM2DQSPADCTRL4 */
4114 0x20820800, /* EMC_XM2DQSPADCTRL3 */
4115 0x00040000, /* EMC_DLL_XFORM_DQ0 */
4116 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
4117 0x00040000, /* EMC_DLL_XFORM_ADDR0 */
4118 0x00000000, /* EMC_XM2CLKPADCTRL2 */
4119 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4120 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
4121 0x00040000, /* EMC_DLL_XFORM_ADDR2 */
4122 0x00030000, /* EMC_DLL_XFORM_DQS1 */
4123 0x00030000, /* EMC_DLL_XFORM_DQS2 */
4124 0x00030000, /* EMC_DLL_XFORM_DQS3 */
4125 0x00040000, /* EMC_DLL_XFORM_DQ1 */
4126 0x00040000, /* EMC_DLL_XFORM_DQ2 */
4127 0x00040000, /* EMC_DLL_XFORM_DQ3 */
4128 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4129 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4130 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4131 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4132 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4133 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4136 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
4137 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
4138 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
4139 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
4140 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
4141 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
4142 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
4143 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
4144 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
4145 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
4146 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
4148 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */
4149 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4150 0xf320000e, /* EMC_CFG */
4151 0x00000000, /* Mode Register 0 */
4152 0x80010083, /* Mode Register 1 */
4153 0x80020004, /* Mode Register 2 */
4154 0x800b0000, /* Mode Register 4 */
4158 504000, /* SDRAM frequency */
4159 1100, /* min voltage */
4160 "pll_m", /* clock source id */
4161 0x80000000, /* CLK_SOURCE_EMC */
4162 99, /* number of burst_regs */
4163 30, /* number of trim_regs (each channel) */
4164 11, /* number of up_down_regs */
4166 0x0000001e, /* EMC_RC */
4167 0x00000041, /* EMC_RFC */
4168 0x00000000, /* EMC_RFC_SLR */
4169 0x00000015, /* EMC_RAS */
4170 0x00000009, /* EMC_RP */
4171 0x0000000b, /* EMC_R2W */
4172 0x00000009, /* EMC_W2R */
4173 0x00000003, /* EMC_R2P */
4174 0x0000000d, /* EMC_W2P */
4175 0x00000009, /* EMC_RD_RCD */
4176 0x00000009, /* EMC_WR_RCD */
4177 0x00000005, /* EMC_RRD */
4178 0x00000003, /* EMC_REXT */
4179 0x00000000, /* EMC_WEXT */
4180 0x00000003, /* EMC_WDV */
4181 0x00000003, /* EMC_WDV_MASK */
4182 0x00000008, /* EMC_IBDLY */
4183 0x00010000, /* EMC_PUTERM_EXTRA */
4184 0x00000000, /* EMC_CDB_CNTL_2 */
4185 0x00000005, /* EMC_QRST */
4186 0x00000012, /* EMC_RDV_MASK */
4187 0x00000775, /* EMC_REFRESH */
4188 0x00000000, /* EMC_BURST_REFRESH_NUM */
4189 0x000001dd, /* EMC_PRE_REFRESH_REQ_CNT */
4190 0x00000003, /* EMC_PDEX2WR */
4191 0x00000003, /* EMC_PDEX2RD */
4192 0x00000009, /* EMC_PCHG2PDEN */
4193 0x00000000, /* EMC_ACT2PDEN */
4194 0x00000001, /* EMC_AR2PDEN */
4195 0x00000011, /* EMC_RW2PDEN */
4196 0x00000047, /* EMC_TXSR */
4197 0x00000047, /* EMC_TXSRDLL */
4198 0x00000008, /* EMC_TCKE */
4199 0x00000008, /* EMC_TCKESR */
4200 0x00000008, /* EMC_TPD */
4201 0x0000001a, /* EMC_TFAW */
4202 0x0000000b, /* EMC_TRPAB */
4203 0x00000001, /* EMC_TCLKSTABLE */
4204 0x00000003, /* EMC_TCLKSTOP */
4205 0x00000836, /* EMC_TREFBW */
4206 0x00000007, /* EMC_QUSE_EXTRA */
4207 0x00000020, /* EMC_ODT_WRITE */
4208 0x00000000, /* EMC_ODT_READ */
4209 0x0001aa86, /* EMC_FBIO_CFG5 */
4210 0xf0140099, /* EMC_CFG_DIG_DLL */
4211 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
4212 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
4213 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
4214 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
4215 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
4216 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
4217 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
4218 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
4219 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
4220 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
4221 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
4222 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
4223 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
4224 0x00010220, /* EMC_XM2CMDPADCTRL */
4225 0x00000000, /* EMC_XM2CMDPADCTRL4 */
4226 0x0003023d, /* EMC_XM2DQSPADCTRL2 */
4227 0x00000000, /* EMC_XM2DQPADCTRL2 */
4228 0x77ffc004, /* EMC_XM2CLKPADCTRL */
4229 0x81f1f008, /* EMC_XM2COMPPADCTRL */
4230 0x00000000, /* EMC_XM2VTTGENPADCTRL */
4231 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
4232 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
4233 0x00000000, /* EMC_TXDSRVTTGEN */
4234 0x02000100, /* EMC_FBIO_SPARE */
4235 0x00000802, /* EMC_CTT_TERM_CTRL */
4236 0x00064000, /* EMC_ZCAL_INTERVAL */
4237 0x000000b6, /* EMC_ZCAL_WAIT_CNT */
4238 0x00110011, /* EMC_MRS_WAIT_CNT */
4239 0x00110011, /* EMC_MRS_WAIT_CNT2 */
4240 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
4241 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
4242 0x00000000, /* EMC_CTT */
4243 0x00000000, /* EMC_CTT_DURATION */
4244 0x80001004, /* EMC_DYN_SELF_REF_CONTROL */
4245 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
4246 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
4247 0x09000007, /* MC_EMEM_ARB_CFG */
4248 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
4249 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
4250 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
4251 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
4252 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
4253 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
4254 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
4255 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
4256 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
4257 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
4258 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
4259 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
4260 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
4261 0x06070103, /* MC_EMEM_ARB_DA_TURNS */
4262 0x00120b0f, /* MC_EMEM_ARB_DA_COVERS */
4263 0x71c81710, /* MC_EMEM_ARB_MISC0 */
4264 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
4267 0x00000000, /* EMC_CDB_CNTL_1 */
4268 0x00000006, /* EMC_FBIO_CFG6 */
4269 0x0000000b, /* EMC_QUSE */
4270 0x00000006, /* EMC_EINPUT */
4271 0x00000007, /* EMC_EINPUT_DURATION */
4272 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
4273 0x0000000f, /* EMC_QSAFE */
4274 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4275 0x00000012, /* EMC_RDV */
4276 0x007df7df, /* EMC_XM2DQSPADCTRL4 */
4277 0x20820800, /* EMC_XM2DQSPADCTRL3 */
4278 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
4279 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
4280 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
4281 0x00000000, /* EMC_XM2CLKPADCTRL2 */
4282 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4283 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
4284 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
4285 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
4286 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
4287 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
4288 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
4289 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
4290 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
4291 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4292 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4293 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4294 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4295 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4296 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4299 0x00000000, /* EMC_CDB_CNTL_1 */
4300 0x00000006, /* EMC_FBIO_CFG6 */
4301 0x0000000b, /* EMC_QUSE */
4302 0x00000006, /* EMC_EINPUT */
4303 0x00000007, /* EMC_EINPUT_DURATION */
4304 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
4305 0x0000000f, /* EMC_QSAFE */
4306 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
4307 0x00000012, /* EMC_RDV */
4308 0x007df7df, /* EMC_XM2DQSPADCTRL4 */
4309 0x20820800, /* EMC_XM2DQSPADCTRL3 */
4310 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
4311 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
4312 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
4313 0x00000000, /* EMC_XM2CLKPADCTRL2 */
4314 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
4315 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
4316 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
4317 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
4318 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
4319 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
4320 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
4321 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
4322 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
4323 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
4324 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
4325 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
4326 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
4327 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
4328 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
4331 0x00000102, /* MC_PTSA_GRANT_DECREMENT */
4332 0x000e000e, /* MC_LATENCY_ALLOWANCE_G2_0 */
4333 0x000e000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
4334 0x00110013, /* MC_LATENCY_ALLOWANCE_NV_0 */
4335 0x00000013, /* MC_LATENCY_ALLOWANCE_NV2_0 */
4336 0x00130013, /* MC_LATENCY_ALLOWANCE_NV_2 */
4337 0x00190013, /* MC_LATENCY_ALLOWANCE_NV_1 */
4338 0x00000019, /* MC_LATENCY_ALLOWANCE_NV2_1 */
4339 0x00190019, /* MC_LATENCY_ALLOWANCE_NV3 */
4340 0x00ab0050, /* MC_LATENCY_ALLOWANCE_EPP_0 */
4341 0x00ab00ab, /* MC_LATENCY_ALLOWANCE_EPP_1 */
4343 0x00000032, /* EMC_ZCAL_WAIT_CNT after clock change */
4344 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
4345 0xf3200006, /* EMC_CFG */
4346 0x00000000, /* Mode Register 0 */
4347 0x800100c3, /* Mode Register 1 */
4348 0x80020006, /* Mode Register 2 */
4349 0x800b0000, /* Mode Register 4 */
4353 static struct tegra11_emc_pdata e1580_no_dram_pdata = {
4354 .description = "e1580_h9ccnnn8ktmlbr_ntm",
4355 .tables = e1580_h9ccnnn8ktmlbr_ntm_table,
4356 .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_table),
4359 static struct tegra11_emc_pdata e1580_A01P_AP40_pdata = {
4360 .description = "e1580_h9ccnnn8ktmlbr_ntm_AP40",
4361 .tables = e1580_h9ccnnn8ktmlbr_ntm_AP40_table,
4362 .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_AP40_table),
4365 static struct tegra11_emc_pdata e1580_A01P_AP40_2gb_pdata = {
4366 .description = "e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb",
4367 .tables = e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table,
4368 .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table),
4371 static struct tegra11_emc_pdata *pluto_get_emc_data(void)
4373 struct board_info board_info;
4376 tegra_get_board_info(&board_info);
4378 /* Load AP40 Table */
4379 if (board_info.board_id == BOARD_E1580 && tegra_sku_id == 0x6) {
4380 /* Get the memory size */
4381 mem = memblock_phys_mem_size();
4383 /* Table for 2 GB memory */
4384 return &e1580_A01P_AP40_2gb_pdata;
4386 return &e1580_A01P_AP40_pdata;
4389 /* Default Pluto Table */
4390 if (board_info.board_id == BOARD_E1580 ||
4391 board_info.board_id == BOARD_E1575 ||
4392 board_info.board_id == BOARD_E1577)
4393 return &e1580_no_dram_pdata;
4398 int __init pluto_emc_init(void)
4400 tegra_emc_device.dev.platform_data = pluto_get_emc_data();
4401 platform_device_register(&tegra_emc_device);