2 * arch/arm/mach-tegra/board-pismo-power.c
4 * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/as3720.h>
29 #include <linux/gpio.h>
30 #include <linux/regulator/userspace-consumer.h>
32 #include <asm/mach-types.h>
34 #include <mach/irqs.h>
36 #include <mach/gpio-tegra.h>
38 #include "cpu-tegra.h"
40 #include "tegra-board-id.h"
42 #include "gpio-names.h"
43 #include "board-common.h"
44 #include "board-pismo.h"
45 #include "tegra_cl_dvfs.h"
47 #include "tegra11_soctherm.h"
51 #define PMC_CTRL_INTR_LOW (1 << 17)
53 static struct regulator_consumer_supply as3720_ldo0_supply[] = {
54 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
55 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
56 REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
57 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
58 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
61 static struct regulator_consumer_supply as3720_ldo1_supply[] = {
62 REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
63 REGULATOR_SUPPLY("pwrdet_cam", NULL),
66 static struct regulator_consumer_supply as3720_ldo2_supply[] = {
67 REGULATOR_SUPPLY("vpp_fuse", NULL),
70 static struct regulator_consumer_supply as3720_ldo3_supply[] = {
71 REGULATOR_SUPPLY("vdd_rtc", NULL),
74 static struct regulator_consumer_supply as3720_ldo5_supply[] = {
75 REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
76 REGULATOR_SUPPLY("vdd_als", NULL),
77 REGULATOR_SUPPLY("vdd", "0-004c"),
78 REGULATOR_SUPPLY("vdd", "0-0069"),
81 static struct regulator_consumer_supply as3720_ldo6_supply[] = {
82 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
83 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
86 static struct regulator_consumer_supply as3720_ldo8_supply[] = {
87 REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
90 static struct regulator_consumer_supply as3720_sd0_supply[] = {
91 REGULATOR_SUPPLY("vdd_cpu", NULL),
94 static struct regulator_consumer_supply as3720_sd1_supply[] = {
95 REGULATOR_SUPPLY("vdd_core", NULL),
98 static struct regulator_consumer_supply as3720_sd2_supply[] = {
99 REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
100 REGULATOR_SUPPLY("vcore_emmc", NULL),
101 REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
102 REGULATOR_SUPPLY("vdd_af_cam1", NULL),
105 static struct regulator_consumer_supply as3720_sd3_supply[] = {
106 REGULATOR_SUPPLY("vdd_emmc", NULL),
107 REGULATOR_SUPPLY("vddio_sys", NULL),
108 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
109 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
110 REGULATOR_SUPPLY("vddio_bb", NULL),
111 REGULATOR_SUPPLY("pwrdet_bb", NULL),
112 REGULATOR_SUPPLY("vddio_uart", NULL),
113 REGULATOR_SUPPLY("pwrdet_uart", NULL),
114 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
115 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
116 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
117 REGULATOR_SUPPLY("avdd_osc", NULL),
118 REGULATOR_SUPPLY("vddio_gmi", NULL),
119 REGULATOR_SUPPLY("pwrdet_nand", NULL),
120 REGULATOR_SUPPLY("vddio_audio", NULL),
121 REGULATOR_SUPPLY("pwrdet_audio", NULL),
122 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
123 REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
124 REGULATOR_SUPPLY("pwrdet_mipi", NULL),
125 REGULATOR_SUPPLY("vddio_bt_1v8", NULL),
126 REGULATOR_SUPPLY("vddio_wifi_1v8", NULL),
127 REGULATOR_SUPPLY("vdd_gps_1v8", NULL),
130 static struct regulator_consumer_supply as3720_sd4_supply[] = {
131 REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
132 REGULATOR_SUPPLY("avdd_plle", NULL),
133 REGULATOR_SUPPLY("avdd_pllm", NULL),
134 REGULATOR_SUPPLY("avdd_pllu", NULL),
135 REGULATOR_SUPPLY("avdd_pllx", NULL),
136 REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
137 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
138 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
139 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
140 REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
141 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
142 REGULATOR_SUPPLY("avddio_usb", NULL),
145 static struct regulator_consumer_supply as3720_sd5_supply[] = {
146 REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
147 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
148 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
149 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
150 REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
151 REGULATOR_SUPPLY("pwrdet_hv", NULL),
152 REGULATOR_SUPPLY("vdd_bt_3v3", NULL),
153 REGULATOR_SUPPLY("vdd_wifi_3v3", NULL),
156 static struct regulator_consumer_supply as3720_sd6_supply[] = {
157 REGULATOR_SUPPLY("vddio_ddr", NULL),
158 REGULATOR_SUPPLY("vddio_ddr0", NULL),
159 REGULATOR_SUPPLY("vddio_ddr1", NULL),
162 static struct regulator_init_data as3720_ldo0 = {
166 .valid_modes_mask = REGULATOR_MODE_NORMAL
167 | REGULATOR_MODE_STANDBY,
168 .valid_ops_mask = REGULATOR_CHANGE_MODE
169 | REGULATOR_CHANGE_STATUS
170 | REGULATOR_CHANGE_VOLTAGE,
175 .consumer_supplies = as3720_ldo0_supply,
176 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo0_supply),
179 static struct regulator_init_data as3720_ldo1 = {
183 .valid_modes_mask = REGULATOR_MODE_NORMAL
184 | REGULATOR_MODE_STANDBY,
185 .valid_ops_mask = REGULATOR_CHANGE_MODE
186 | REGULATOR_CHANGE_STATUS
187 | REGULATOR_CHANGE_VOLTAGE,
192 .consumer_supplies = as3720_ldo1_supply,
193 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo1_supply),
196 static struct regulator_init_data as3720_ldo2 = {
200 .valid_modes_mask = REGULATOR_MODE_NORMAL
201 | REGULATOR_MODE_STANDBY,
202 .valid_ops_mask = REGULATOR_CHANGE_MODE
203 | REGULATOR_CHANGE_STATUS
204 | REGULATOR_CHANGE_VOLTAGE,
209 .consumer_supplies = as3720_ldo2_supply,
210 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo2_supply),
213 static struct regulator_init_data as3720_ldo3 = {
217 .valid_modes_mask = REGULATOR_MODE_NORMAL
218 | REGULATOR_MODE_STANDBY,
219 .valid_ops_mask = REGULATOR_CHANGE_MODE
220 | REGULATOR_CHANGE_STATUS
221 | REGULATOR_CHANGE_VOLTAGE,
226 .consumer_supplies = as3720_ldo3_supply,
227 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo3_supply),
230 static struct regulator_init_data as3720_ldo5 = {
234 .valid_modes_mask = REGULATOR_MODE_NORMAL
235 | REGULATOR_MODE_STANDBY,
236 .valid_ops_mask = REGULATOR_CHANGE_MODE
237 | REGULATOR_CHANGE_STATUS
238 | REGULATOR_CHANGE_VOLTAGE,
243 .consumer_supplies = as3720_ldo5_supply,
244 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo5_supply),
246 static struct regulator_init_data as3720_ldo6 = {
250 .valid_modes_mask = REGULATOR_MODE_NORMAL
251 | REGULATOR_MODE_STANDBY,
252 .valid_ops_mask = REGULATOR_CHANGE_MODE
253 | REGULATOR_CHANGE_STATUS
254 | REGULATOR_CHANGE_VOLTAGE,
259 .consumer_supplies = as3720_ldo6_supply,
260 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo6_supply),
263 static struct regulator_init_data as3720_ldo8 = {
267 .valid_modes_mask = REGULATOR_MODE_NORMAL
268 | REGULATOR_MODE_STANDBY,
269 .valid_ops_mask = REGULATOR_CHANGE_MODE
270 | REGULATOR_CHANGE_STATUS
271 | REGULATOR_CHANGE_VOLTAGE,
276 .consumer_supplies = as3720_ldo8_supply,
277 .num_consumer_supplies = ARRAY_SIZE(as3720_ldo8_supply),
280 static struct regulator_init_data as3720_sd0 = {
284 .valid_modes_mask = REGULATOR_MODE_NORMAL
285 | REGULATOR_MODE_STANDBY,
286 .valid_ops_mask = REGULATOR_CHANGE_MODE
287 | REGULATOR_CHANGE_STATUS
288 | REGULATOR_CHANGE_VOLTAGE,
293 .consumer_supplies = as3720_sd0_supply,
294 .num_consumer_supplies = ARRAY_SIZE(as3720_sd0_supply),
297 static struct regulator_init_data as3720_sd1 = {
301 .valid_modes_mask = REGULATOR_MODE_NORMAL
302 | REGULATOR_MODE_STANDBY,
303 .valid_ops_mask = REGULATOR_CHANGE_MODE
304 | REGULATOR_CHANGE_STATUS
305 | REGULATOR_CHANGE_VOLTAGE,
310 .consumer_supplies = as3720_sd1_supply,
311 .num_consumer_supplies = ARRAY_SIZE(as3720_sd1_supply),
314 static struct regulator_init_data as3720_sd2 = {
318 .valid_modes_mask = REGULATOR_MODE_NORMAL
319 | REGULATOR_MODE_STANDBY,
320 .valid_ops_mask = REGULATOR_CHANGE_MODE
321 | REGULATOR_CHANGE_STATUS
322 | REGULATOR_CHANGE_VOLTAGE,
327 .consumer_supplies = as3720_sd2_supply,
328 .num_consumer_supplies = ARRAY_SIZE(as3720_sd2_supply),
331 static struct regulator_init_data as3720_sd3 = {
335 .valid_modes_mask = REGULATOR_MODE_NORMAL
336 | REGULATOR_MODE_STANDBY,
337 .valid_ops_mask = REGULATOR_CHANGE_MODE
338 | REGULATOR_CHANGE_STATUS
339 | REGULATOR_CHANGE_VOLTAGE,
344 .consumer_supplies = as3720_sd3_supply,
345 .num_consumer_supplies = ARRAY_SIZE(as3720_sd3_supply),
348 static struct regulator_init_data as3720_sd4 = {
352 .valid_modes_mask = REGULATOR_MODE_NORMAL
353 | REGULATOR_MODE_STANDBY,
354 .valid_ops_mask = REGULATOR_CHANGE_MODE
355 | REGULATOR_CHANGE_STATUS
356 | REGULATOR_CHANGE_VOLTAGE,
361 .consumer_supplies = as3720_sd4_supply,
362 .num_consumer_supplies = ARRAY_SIZE(as3720_sd4_supply),
365 static struct regulator_init_data as3720_sd5 = {
369 .valid_modes_mask = REGULATOR_MODE_NORMAL
370 | REGULATOR_MODE_STANDBY,
371 .valid_ops_mask = REGULATOR_CHANGE_MODE
372 | REGULATOR_CHANGE_STATUS
373 | REGULATOR_CHANGE_VOLTAGE,
378 .consumer_supplies = as3720_sd5_supply,
379 .num_consumer_supplies = ARRAY_SIZE(as3720_sd5_supply),
382 static struct regulator_init_data as3720_sd6 = {
386 .valid_modes_mask = REGULATOR_MODE_NORMAL
387 | REGULATOR_MODE_STANDBY,
388 .valid_ops_mask = REGULATOR_CHANGE_MODE
389 | REGULATOR_CHANGE_STATUS
390 | REGULATOR_CHANGE_VOLTAGE,
395 .consumer_supplies = as3720_sd6_supply,
396 .num_consumer_supplies = ARRAY_SIZE(as3720_sd6_supply),
399 static struct as3720_reg_init as3720_core_init_data[] = {
400 /* disable all regulators */
401 AS3720_REG_INIT(AS3720_SD_CONTROL_REG, 0x7f),
402 AS3720_REG_INIT(AS3720_LDOCONTROL0_REG, 0xef),
403 AS3720_REG_INIT(AS3720_LDOCONTROL1_REG, 0x01),
404 /* set to lowest voltage output */
405 /* set to OTP settings */
406 AS3720_REG_INIT(AS3720_SD0_VOLTAGE_REG, 0x32),
407 AS3720_REG_INIT(AS3720_SD1_VOLTAGE_REG, 0x32),
408 AS3720_REG_INIT(AS3720_SD2_VOLTAGE_REG, 0xFF),
409 AS3720_REG_INIT(AS3720_SD3_VOLTAGE_REG, 0xD0),
410 AS3720_REG_INIT(AS3720_SD4_VOLTAGE_REG, 0xA4),
411 AS3720_REG_INIT(AS3720_SD5_VOLTAGE_REG, 0xFE),
412 AS3720_REG_INIT(AS3720_SD6_VOLTAGE_REG, 0x52),
413 AS3720_REG_INIT(AS3720_LDO0_VOLTAGE_REG, 0x90),
414 AS3720_REG_INIT(AS3720_LDO1_VOLTAGE_REG, 0x43),
415 AS3720_REG_INIT(AS3720_LDO2_VOLTAGE_REG, 0x43),
416 AS3720_REG_INIT(AS3720_LDO3_VOLTAGE_REG, 0xA8),
417 AS3720_REG_INIT(AS3720_LDO4_VOLTAGE_REG, 0x00),
418 AS3720_REG_INIT(AS3720_LDO5_VOLTAGE_REG, 0xff),
419 AS3720_REG_INIT(AS3720_LDO6_VOLTAGE_REG, 0xff),
420 AS3720_REG_INIT(AS3720_LDO7_VOLTAGE_REG, 0x90),
421 AS3720_REG_INIT(AS3720_LDO8_VOLTAGE_REG, 0x7F),
422 AS3720_REG_INIT(AS3720_LDO9_VOLTAGE_REG, 0x00),
423 AS3720_REG_INIT(AS3720_LDO10_VOLTAGE_REG, 0x00),
424 AS3720_REG_INIT(AS3720_LDO11_VOLTAGE_REG, 0x00),
425 {.reg = AS3720_REG_INIT_TERMINATE},
428 /* config settings are OTP plus initial state
429 * GPIOsignal_out at 20h not configurable through OTP and is initialized to
430 * zero. To enable output, the invert bit must be turned on.
431 * GPIOxcontrol register format
433 * ---------------------
434 * 7 gpiox_invert invert input or output
435 * 6:3 gpiox_iosf 0: normal
436 * 2:0 gpiox_mode 0: input, 1: output push/pull, 3: ADC input (tristate)
441 * 0x3 gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
442 * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
444 * Note: output state should be defined for gpiox_mode = output. Do not change
445 * the state of the invert bit for critical devices such as GPIO 7 which enables
446 * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
447 * register correctly.
448 * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
451 static struct as3720_gpio_config as3720_gpio_cfgs[] = {
454 .gpio = AS3720_GPIO0,
455 .mode = AS3720_GPIO_MODE_ADC_IN,
459 .gpio = AS3720_GPIO1,
460 .mode = AS3720_GPIO_MODE_ADC_IN,
464 .gpio = AS3720_GPIO2,
465 .mode = AS3720_GPIO_MODE_ADC_IN,
468 /* otp = 0x01 => REGEN_3 = LP0 gate (1.8V, 5 V) */
469 .gpio = AS3720_GPIO3,
470 .invert = AS3720_GPIO_CFG_INVERT, /* don't go into LP0 */
471 .mode = AS3720_GPIO_MODE_OUTPUT_VDDH,
472 .output_state = AS3720_GPIO_CFG_OUTPUT_ENABLED,
475 /* otp = 0x81 => on by default
478 .gpio = AS3720_GPIO4,
479 .invert = AS3720_GPIO_CFG_NO_INVERT,
480 .mode = AS3720_GPIO_MODE_OUTPUT_VDDH,
481 .output_state = AS3720_GPIO_CFG_OUTPUT_DISABLED,
484 /* otp = 0x3 EN_MIC_BIAS_L */
485 .gpio = AS3720_GPIO5,
486 .mode = AS3720_GPIO_MODE_ADC_IN,
489 /* otp = 0x3 CAM_LDO1_EN */
490 .gpio = AS3720_GPIO6,
491 .mode = AS3720_GPIO_MODE_ADC_IN,
495 .gpio = AS3720_GPIO7,
496 .invert = AS3720_GPIO_CFG_INVERT,
497 .mode = AS3720_GPIO_MODE_OUTPUT_VDDH,
498 .output_state = AS3720_GPIO_CFG_OUTPUT_ENABLED,
502 static struct as3720_platform_data as3720_pdata = {
503 .reg_init[AS3720_LDO0] = &as3720_ldo0,
504 .reg_init[AS3720_LDO1] = &as3720_ldo1,
505 .reg_init[AS3720_LDO2] = &as3720_ldo2,
506 .reg_init[AS3720_LDO3] = &as3720_ldo3,
507 .reg_init[AS3720_LDO5] = &as3720_ldo5,
508 .reg_init[AS3720_LDO6] = &as3720_ldo6,
509 .reg_init[AS3720_LDO8] = &as3720_ldo8,
510 .reg_init[AS3720_SD0] = &as3720_sd0,
511 .reg_init[AS3720_SD1] = &as3720_sd1,
512 .reg_init[AS3720_SD2] = &as3720_sd2,
513 .reg_init[AS3720_SD3] = &as3720_sd3,
514 .reg_init[AS3720_SD4] = &as3720_sd4,
515 .reg_init[AS3720_SD5] = &as3720_sd5,
516 .reg_init[AS3720_SD6] = &as3720_sd6,
518 .core_init_data = &as3720_core_init_data[0],
519 .gpio_base = AS3720_GPIO_BASE,
520 .rtc_start_year = 2010,
522 .num_gpio_cfgs = ARRAY_SIZE(as3720_gpio_cfgs),
523 .gpio_cfgs = as3720_gpio_cfgs,
526 static struct i2c_board_info __initdata as3720_regulators[] = {
528 I2C_BOARD_INFO("as3720", 0x40),
529 .flags = I2C_CLIENT_WAKE,
530 .irq = INT_EXTERNAL_PMU,
531 .platform_data = &as3720_pdata,
535 int __init pismo_as3720_regulator_init(void)
537 printk(KERN_INFO "%s: i2c_register_board_info\n",
539 i2c_register_board_info(4, as3720_regulators,
540 ARRAY_SIZE(as3720_regulators));
544 static int ac_online(void)
549 static struct resource pismo_pda_resources[] = {
555 static struct pda_power_pdata pismo_pda_data = {
556 .is_ac_online = ac_online,
559 static struct platform_device pismo_pda_power_device = {
562 .resource = pismo_pda_resources,
563 .num_resources = ARRAY_SIZE(pismo_pda_resources),
565 .platform_data = &pismo_pda_data,
569 static struct tegra_suspend_platform_data pismo_suspend_data = {
571 .cpu_off_timer = 2000,
572 .suspend_mode = TEGRA_SUSPEND_NONE,
573 .core_timer = 0x7e7e,
574 .core_off_timer = 2000,
575 .corereq_high = true,
576 .sysclkreq_high = true,
577 .cpu_lp2_min_residency = 1000,
580 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
581 /* board parameters for cpu dfll */
582 static struct tegra_cl_dvfs_cfg_param pismo_cl_dvfs_param = {
583 .sample_rate = 12500,
585 .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
590 .droop_cut_value = 0xF,
591 .droop_restore_ramp = 0x0,
592 .scale_out_ramp = 0x0,
596 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
597 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
598 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
599 static inline void fill_reg_map(void)
602 for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
603 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
604 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
608 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
609 static struct tegra_cl_dvfs_platform_data pismo_cl_dvfs_data = {
610 .dfll_clk_name = "dfll_cpu",
611 .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
617 .vdd_map = pmu_cpu_vdd_map,
618 .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
620 .cfg_param = &pismo_cl_dvfs_param,
623 static int __init pismo_cl_dvfs_init(void)
626 tegra_cl_dvfs_device.dev.platform_data = &pismo_cl_dvfs_data;
627 platform_device_register(&tegra_cl_dvfs_device);
633 static struct regulator_bulk_data pismo_gps_regulator_supply[] = {
635 .supply = "vdd_gps_3v3",
638 .supply = "vdd_gps_1v8",
642 static struct regulator_userspace_consumer_data pismo_gps_regulator_pdata = {
643 .num_supplies = ARRAY_SIZE(pismo_gps_regulator_supply),
644 .supplies = pismo_gps_regulator_supply,
647 static struct platform_device pismo_gps_regulator_device = {
648 .name = "reg-userspace-consumer",
651 .platform_data = &pismo_gps_regulator_pdata,
655 static struct regulator_bulk_data pismo_bt_regulator_supply[] = {
657 .supply = "vdd_bt_3v3",
660 .supply = "vddio_bt_1v8",
664 static struct regulator_userspace_consumer_data pismo_bt_regulator_pdata = {
665 .num_supplies = ARRAY_SIZE(pismo_bt_regulator_supply),
666 .supplies = pismo_bt_regulator_supply,
669 static struct platform_device pismo_bt_regulator_device = {
670 .name = "reg-userspace-consumer",
673 .platform_data = &pismo_bt_regulator_pdata,
677 /* Gated by CAM_LDO1_EN From AMS7230 GPIO6*/
678 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
679 REGULATOR_SUPPLY("dvdd_cam", NULL),
680 REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
681 REGULATOR_SUPPLY("vi2c", "2-0030"),
682 REGULATOR_SUPPLY("vif", "2-0036"),
683 REGULATOR_SUPPLY("dovdd", "2-0010"),
684 REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
687 /* Gated by PMU_REGEN3 From AMS7230 GPIO3*/
688 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
689 REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
693 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
694 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
698 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
699 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
702 /* Macro for defining fixed regulator sub device data */
703 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
704 #define FIXED_REG(_id, _var, _name, _always_on, _boot_on, \
705 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \
706 static struct regulator_init_data ri_data_##_var = \
708 .num_consumer_supplies = \
709 ARRAY_SIZE(fixed_reg_##_name##_supply), \
710 .consumer_supplies = fixed_reg_##_name##_supply, \
712 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
713 REGULATOR_MODE_STANDBY), \
714 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
715 REGULATOR_CHANGE_STATUS | \
716 REGULATOR_CHANGE_VOLTAGE), \
717 .always_on = _always_on, \
718 .boot_on = _boot_on, \
721 static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
723 .supply_name = FIXED_SUPPLY(_name), \
724 .microvolts = _millivolts * 1000, \
726 .gpio_is_open_drain = _open_drain, \
727 .enable_high = _active_high, \
728 .enabled_at_boot = _boot_state, \
729 .init_data = &ri_data_##_var, \
731 static struct platform_device fixed_reg_##_var##_dev = { \
732 .name = "reg-fixed-voltage", \
735 .platform_data = &fixed_reg_##_var##_pdata, \
739 FIXED_REG(1, en_1v8_cam, en_1v8_cam, 0, 0,
740 AS3720_GPIO_BASE + AS3720_GPIO6, false, true, 0, 1800);
742 FIXED_REG(2, vdd_hdmi_5v0, vdd_hdmi_5v0, 0, 0,
743 TEGRA_GPIO_PK1, false, true, 0, 5000);
745 FIXED_REG(3, usb1_vbus, usb1_vbus, 0, 0,
746 -EINVAL, true, true, 1, 5000);
748 FIXED_REG(4, usb3_vbus, usb3_vbus, 0, 0,
749 -EINVAL, true, true, 1, 5000);
752 * Creating the fixed regulator device tables
755 #define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
757 #define PISMO_COMMON_FIXED_REG \
758 ADD_FIXED_REG(usb1_vbus), \
759 ADD_FIXED_REG(usb3_vbus), \
760 ADD_FIXED_REG(vdd_hdmi_5v0), \
761 ADD_FIXED_REG(en_1v8_cam),
763 /* Gpio switch regulator platform data for pluto */
764 static struct platform_device *fixed_reg_devs_pm347[] = {
765 PISMO_COMMON_FIXED_REG
769 static int __init pismo_fixed_regulator_init(void)
772 if (!machine_is_pismo())
775 return platform_add_devices(fixed_reg_devs_pm347,
776 ARRAY_SIZE(fixed_reg_devs_pm347));
779 subsys_initcall_sync(pismo_fixed_regulator_init);
781 int __init pismo_regulator_init(void)
784 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
785 pismo_cl_dvfs_init();
787 pismo_as3720_regulator_init();
789 platform_device_register(&pismo_pda_power_device);
790 platform_device_register(&pismo_bt_regulator_device);
791 platform_device_register(&pismo_gps_regulator_device);
795 int __init pismo_suspend_init(void)
797 tegra_init_suspend(&pismo_suspend_data);
801 int __init pismo_edp_init(void)
803 #ifdef CONFIG_TEGRA_EDP_LIMITS
804 unsigned int regulator_mA;
806 regulator_mA = get_maximum_cpu_current_supported();
808 regulator_mA = 15000;
810 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
812 tegra_init_cpu_edp_limits(regulator_mA);
817 /* place holder for tpdata for as3720 regulator
818 * TODO: fill the correct i2c type, bus, reg_addr and data here:
819 static struct tegra_tsensor_pmu_data tpdata_as3720 = {
824 .i2c_controller_id = ,
825 .poweroff_reg_addr = ,
826 .poweroff_reg_data = ,
830 static struct soctherm_platform_data pismo_soctherm_data = {
834 .passive_delay = 1000,
835 .hotspot_offset = 6000,
839 .cdev_type = "tegra-balanced",
841 .trip_type = THERMAL_TRIP_PASSIVE,
842 .upper = THERMAL_NO_LIMIT,
843 .lower = THERMAL_NO_LIMIT,
846 .cdev_type = "tegra-heavy",
848 .trip_type = THERMAL_TRIP_HOT,
849 .upper = THERMAL_NO_LIMIT,
850 .lower = THERMAL_NO_LIMIT,
853 .cdev_type = "tegra-shutdown",
855 .trip_type = THERMAL_TRIP_CRITICAL,
856 .upper = THERMAL_NO_LIMIT,
857 .lower = THERMAL_NO_LIMIT,
863 .passive_delay = 1000,
864 .hotspot_offset = 6000,
868 .cdev_type = "tegra-balanced",
870 .trip_type = THERMAL_TRIP_PASSIVE,
871 .upper = THERMAL_NO_LIMIT,
872 .lower = THERMAL_NO_LIMIT,
875 .cdev_type = "tegra-heavy",
877 .trip_type = THERMAL_TRIP_HOT,
878 .upper = THERMAL_NO_LIMIT,
879 .lower = THERMAL_NO_LIMIT,
882 .cdev_type = "tegra-shutdown",
884 .trip_type = THERMAL_TRIP_CRITICAL,
885 .upper = THERMAL_NO_LIMIT,
886 .lower = THERMAL_NO_LIMIT,
897 [THROTTLE_DEV_CPU] = {
903 /* ENABLE THIS AFTER correctly setting up tpdata_as3720
904 * .tshut_pmu_trip_data = &tpdata_as3720, */
907 int __init pismo_soctherm_init(void)
909 tegra_platform_edp_init(pismo_soctherm_data.therm[THERM_CPU].trips,
910 &pismo_soctherm_data.therm[THERM_CPU].num_trips,
911 8000); /* edp temperature margin */
912 tegra_add_tj_trips(pismo_soctherm_data.therm[THERM_CPU].trips,
913 &pismo_soctherm_data.therm[THERM_CPU].num_trips);
915 return tegra11_soctherm_init(&pismo_soctherm_data);