ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-norrin-power.c
1 /*
2  * arch/arm/mach-tegra/board-norrin-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-plat.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33 #include <linux/pid_thermal_gov.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-pmu-defines.h"
48 #include "board-ardbeg.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52 #include "iomap.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56 #define AS3722_SUPPLY(_name)    "as3722_"#_name
57
58 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
59         REGULATOR_SUPPLY("avdd_pll_m", NULL),
60         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
61         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
62         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
63         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
64         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
65         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
66         REGULATOR_SUPPLY("avdd_pll_x", NULL),
67         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
68 };
69
70 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
71         REGULATOR_SUPPLY("vddio_cam", "vi"),
72         REGULATOR_SUPPLY("pwrdet_cam", NULL),
73         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
74         REGULATOR_SUPPLY("vif", "2-0010"),
75         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
76         REGULATOR_SUPPLY("vif", "2-0036"),
77         REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
78         REGULATOR_SUPPLY("vi2c", "2-0030"),
79 };
80
81 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
82         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
83         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
84         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
85         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
86         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
87         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
88         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
89         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
90         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
91         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
92 };
93
94 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
95         REGULATOR_SUPPLY("vdd_rtc", NULL),
96 };
97
98 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
99         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
100         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
101         REGULATOR_SUPPLY("vana", "2-0010"),
102 };
103
104 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
105         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
106         REGULATOR_SUPPLY("vdig", "2-0010"),
107         REGULATOR_SUPPLY("vdig", "2-0036"),
108 };
109
110 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
111         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
112         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
113 };
114
115 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
116         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
117         REGULATOR_SUPPLY("imx135_reg2", NULL),
118         REGULATOR_SUPPLY("vdig_lv", "2-0010"),
119         REGULATOR_SUPPLY("dvdd", "2-0010"),
120 };
121
122 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
123         REGULATOR_SUPPLY("avdd", "spi0.0"),
124         REGULATOR_SUPPLY("avdd", "spi2.1"),
125 };
126
127 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
128         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
129         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
130         REGULATOR_SUPPLY("imx135_reg1", NULL),
131         REGULATOR_SUPPLY("vdd", "2-000e"),
132         REGULATOR_SUPPLY("vana", "2-0036"),
133         REGULATOR_SUPPLY("vdd", "2-000c"),
134 };
135
136 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
137         REGULATOR_SUPPLY("vpp_fuse", NULL),
138 };
139
140 static struct regulator_consumer_supply as3722_sd0_supply[] = {
141         REGULATOR_SUPPLY("vdd_cpu", NULL),
142 };
143
144 static struct regulator_consumer_supply as3722_sd1_supply[] = {
145         REGULATOR_SUPPLY("vdd_core", NULL),
146 };
147
148 static struct regulator_consumer_supply as3722_sd2_supply[] = {
149         REGULATOR_SUPPLY("vddio_ddr", NULL),
150         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
151         REGULATOR_SUPPLY("vddio_ddr3", NULL),
152         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
153 };
154
155 static struct regulator_consumer_supply as3722_sd4_supply[] = {
156         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
157         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
158         REGULATOR_SUPPLY("dvddio_pex", NULL),
159         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
160         REGULATOR_SUPPLY("avdd_sata", NULL),
161         REGULATOR_SUPPLY("vdd_sata", NULL),
162         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
163         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
164         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
165 };
166
167 static struct regulator_consumer_supply as3722_sd5_supply[] = {
168         REGULATOR_SUPPLY("vddio_sys", NULL),
169         REGULATOR_SUPPLY("vddio_sys_2", NULL),
170         REGULATOR_SUPPLY("vddio_audio", NULL),
171         REGULATOR_SUPPLY("pwrdet_audio", NULL),
172         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
173         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
174         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
175         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
176         REGULATOR_SUPPLY("vddio_uart", NULL),
177         REGULATOR_SUPPLY("pwrdet_uart", NULL),
178         REGULATOR_SUPPLY("vddio_bb", NULL),
179         REGULATOR_SUPPLY("pwrdet_bb", NULL),
180         REGULATOR_SUPPLY("vddio_gmi", NULL),
181         REGULATOR_SUPPLY("pwrdet_nand", NULL),
182         REGULATOR_SUPPLY("avdd_osc", NULL),
183         /* emmc 1.8v misssing
184         keyboard & touchpad 1.8v missing */
185 };
186
187 static struct regulator_consumer_supply as3722_sd6_supply[] = {
188         REGULATOR_SUPPLY("vdd_gpu", NULL),
189         REGULATOR_SUPPLY("vdd_gpu_simon", NULL),
190 };
191
192 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1,
193                AS3722_EXT_CONTROL_ENABLE2);
194 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1,
195                AS3722_EXT_CONTROL_ENABLE1);
196 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
197 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 1, 1, 1,
198                AS3722_EXT_CONTROL_ENABLE1);
199 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
200 AMS_PDATA_INIT(sd6, NULL, 650000, 1200000, 0, 1, 1, 0);
201 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1,
202                AS3722_EXT_CONTROL_ENABLE1);
203 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
204 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
205 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
206 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
207 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
208 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
209 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1275000, 1275000, 0, 0, 1, 0);
210 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
211 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
212 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
213
214 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
215         AS3722_PIN_CONTROL("gpio0", "gpio", NULL, NULL, NULL, "output-low"),
216         AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
217         AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
218         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
219         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
220         AS3722_PIN_CONTROL("gpio5", "gpio", "pull-down", NULL, "enabled", NULL),
221         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
222         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-high"),
223 };
224
225 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
226         .connection_name = "as3722-extcon",
227         .enable_adc1_continuous_mode = true,
228         .enable_low_voltage_range = true,
229         .adc_channel = 12,
230         .hi_threshold =  0x100,
231         .low_threshold = 0x80,
232 };
233
234 static struct as3722_platform_data as3722_pdata = {
235         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
236         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
237         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
238         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
239         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
240         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
241         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
242         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
243         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
244         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
245         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
246
247         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
248         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
249         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
250         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
251         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
252         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
253
254         .gpio_base = AS3722_GPIO_BASE,
255         .irq_base = AS3722_IRQ_BASE,
256         .use_internal_int_pullup = 0,
257         .use_internal_i2c_pullup = 0,
258         .pinctrl_pdata = as3722_pctrl_pdata,
259         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
260         .enable_clk32k_out = true,
261         .use_power_off = true,
262         .extcon_pdata = &as3722_adc_extcon_pdata,
263         .major_rev = 1,
264         .minor_rev = 1,
265 };
266
267 static struct pca953x_platform_data tca6416_pdata = {
268         .gpio_base = PMU_TCA6416_GPIO_BASE,
269 };
270
271 static const struct i2c_board_info tca6416_expander[] = {
272         {
273                 I2C_BOARD_INFO("tca6416", 0x20),
274                 .platform_data = &tca6416_pdata,
275         },
276 };
277
278 static struct i2c_board_info __initdata as3722_regulators[] = {
279         {
280                 I2C_BOARD_INFO("as3722", 0x40),
281                 .flags = I2C_CLIENT_WAKE,
282                 .irq = INT_EXTERNAL_PMU,
283                 .platform_data = &as3722_pdata,
284         },
285 };
286
287 int __init norrin_as3722_regulator_init(void)
288 {
289         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
290         u32 pmc_ctrl;
291         struct board_info board_info;
292
293         tegra_get_board_info(&board_info);
294
295         /* AS3722: Normal state of INT request line is LOW.
296          * configure the power management controller to trigger PMU
297          * interrupts when HIGH.
298          */
299         pmc_ctrl = readl(pmc + PMC_CTRL);
300         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
301         regulator_has_full_constraints();
302         /* Set vdd_gpu init uV to 1V */
303         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
304
305         /* Set overcurrent of rails. */
306         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
307         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
308
309         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
310         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
311
312         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
313         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
314
315         as3722_ldo3_reg_pdata.enable_tracking = true;
316         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
317
318         if ((board_info.board_id == BOARD_PM374) &&
319                                 (board_info.fab == BOARD_FAB_B))
320                 as3722_pdata.minor_rev = 2;
321         pr_info("%s: i2c_register_board_info\n", __func__);
322         i2c_register_board_info(4, as3722_regulators,
323                         ARRAY_SIZE(as3722_regulators));
324         i2c_register_board_info(0, tca6416_expander,
325                         ARRAY_SIZE(tca6416_expander));
326         return 0;
327 }
328
329 static struct tegra_suspend_platform_data norrin_suspend_data = {
330         .cpu_timer      = 2000,
331         .cpu_off_timer  = 2000,
332         .suspend_mode   = TEGRA_SUSPEND_LP0,
333         .core_timer     = 0x7e7e,
334         .core_off_timer = 2000,
335         .corereq_high   = true,
336         .sysclkreq_high = true,
337         .cpu_lp2_min_residency = 1000,
338 };
339
340 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
341 /* board parameters for cpu dfll */
342 static struct tegra_cl_dvfs_cfg_param norrin_cl_dvfs_param = {
343         .sample_rate = 12500,
344
345         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
346         .cf = 10,
347         .ci = 0,
348         .cg = 2,
349
350         .droop_cut_value = 0xF,
351         .droop_restore_ramp = 0x0,
352         .scale_out_ramp = 0x0,
353 };
354 #endif
355
356 /* Norrin: fixed 10mV steps from 700mV to 1400mV */
357 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
358 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
359 static inline void fill_reg_map(void)
360 {
361         int i;
362         u32 reg_init_value = 0x0a;
363         struct board_info board_info;
364
365         tegra_get_board_info(&board_info);
366         if ((board_info.board_id == BOARD_PM374) &&
367                         (board_info.fab == 0x01))
368                 reg_init_value = 0x1e;
369
370         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
371                 pmu_cpu_vdd_map[i].reg_value = i + reg_init_value;
372                 pmu_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
373         }
374 }
375
376 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
377 static struct tegra_cl_dvfs_platform_data norrin_cl_dvfs_data = {
378         .dfll_clk_name = "dfll_cpu",
379         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
380         .u.pmu_i2c = {
381                 .fs_rate = 400000,
382                 .slave_addr = 0x80,
383                 .reg = 0x00,
384         },
385         .vdd_map = pmu_cpu_vdd_map,
386         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
387
388         .cfg_param = &norrin_cl_dvfs_param,
389 };
390
391 static int __init norrin_cl_dvfs_init(void)
392 {
393         fill_reg_map();
394         norrin_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
395         tegra_cl_dvfs_device.dev.platform_data = &norrin_cl_dvfs_data;
396         platform_device_register(&tegra_cl_dvfs_device);
397
398         return 0;
399 }
400 #endif
401
402 /* Always ON /Battery regulator */
403 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
404         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
405         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
406 };
407
408 /* Always ON 1.8v */
409 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
410         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
411         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
412         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
413 };
414
415 /* Always ON 3.3v */
416 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
417         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
418         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
419 };
420
421 /* Always ON 1v2 */
422 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
423         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
424 };
425
426 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
427 static struct regulator_consumer_supply fixed_reg_usb0_vbus_supply[] = {
428         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
429         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
430         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
431 };
432
433 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
434 static struct regulator_consumer_supply fixed_reg_usb1_usb2_vbus_supply[] = {
435         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
436         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
437         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
438         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
439 };
440
441 /* Gated by GPIO_PK6 */
442 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
443         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
444 };
445
446 /* Gated by GPIO_PH7 */
447 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
448         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
449 };
450
451 /* VDD_LCD_BL DAP3_DOUT */
452 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
453         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
454 };
455
456 /* LCD_BL_EN GMI_AD10 */
457 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
458         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
459 };
460
461 /* AS3722 GPIO1*/
462 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
463         REGULATOR_SUPPLY("hvdd_pex", NULL),
464         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
465         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
466         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
467         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
468         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
469         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
470         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
471         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
472         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
473         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
474         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
475         REGULATOR_SUPPLY("vdd", "1-004c"),
476         REGULATOR_SUPPLY("vdd", "0-0048"),
477         REGULATOR_SUPPLY("vdd", "0-0069"),
478         REGULATOR_SUPPLY("vdd", "0-000c"),
479         REGULATOR_SUPPLY("vdd", "0-0077"),
480         REGULATOR_SUPPLY("vin", "2-0030"),
481 };
482
483 /* AS3722 GPIO1*/
484 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
485         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
486         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
487         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
488 };
489
490 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
491         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
492         REGULATOR_SUPPLY("dvdd_lcd", NULL),
493         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
494         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
495         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
496         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
497         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
498         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
499         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
500         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
501         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
502         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
503         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
504         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
505         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
506         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
507         REGULATOR_SUPPLY("dvdd", "spi0.0"),
508         REGULATOR_SUPPLY("dvdd", "spi2.1"),
509         REGULATOR_SUPPLY("vlogic", "0-0069"),
510         REGULATOR_SUPPLY("vid", "0-000c"),
511         REGULATOR_SUPPLY("vddio", "0-0077"),
512         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
513         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
514         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
515         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
516         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
517 };
518
519 /* gated by TCA6416 GPIO EXP GPIO0 */
520 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
521         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
522 };
523
524 /* AMS GPIO2 */
525 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
526         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
527         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
528         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
529         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
530         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
531         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
532         REGULATOR_SUPPLY("pwrdet_hv", NULL),
533         REGULATOR_SUPPLY("hvdd_sata", NULL),
534 };
535
536 /* gated by AS3722 GPIO4 */
537 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
538         REGULATOR_SUPPLY("avdd_lcd", NULL),
539 };
540
541 /* gated by GPIO_PR0 */
542 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
543         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
544         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
545 };
546
547 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
548         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
549 };
550
551 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
552         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
553 };
554
555 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
556         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
557 };
558
559 /* Macro for defining fixed regulator sub device data */
560 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
561 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
562         _always_on, _boot_on, _gpio_nr, _open_drain,            \
563         _active_high, _boot_state, _millivolts, _sdelay)        \
564 static struct regulator_init_data ri_data_##_var =              \
565 {                                                               \
566         .supply_regulator = _in_supply,                         \
567         .num_consumer_supplies =                                \
568         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
569         .consumer_supplies = fixed_reg_##_name##_supply,        \
570         .constraints = {                                        \
571                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
572                                 REGULATOR_MODE_STANDBY),        \
573                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
574                                 REGULATOR_CHANGE_STATUS |       \
575                                 REGULATOR_CHANGE_VOLTAGE),      \
576                 .always_on = _always_on,                        \
577                 .boot_on = _boot_on,                            \
578         },                                                      \
579 };                                                              \
580 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
581 {                                                               \
582         .supply_name = FIXED_SUPPLY(_name),                     \
583         .microvolts = _millivolts * 1000,                       \
584         .gpio = _gpio_nr,                                       \
585         .gpio_is_open_drain = _open_drain,                      \
586         .enable_high = _active_high,                            \
587         .enabled_at_boot = _boot_state,                         \
588         .init_data = &ri_data_##_var,                           \
589         .startup_delay = _sdelay,                               \
590 };                                                              \
591 static struct platform_device fixed_reg_##_var##_dev = {        \
592         .name = "reg-fixed-voltage",                            \
593         .id = _id,                                              \
594         .dev = {                                                \
595                 .platform_data = &fixed_reg_##_var##_pdata,     \
596         },                                                      \
597 }
598
599 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
600                 -1,     false, true,    0,      8400,   0);
601
602 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
603                 -1,     false, true,    0,      1800,   0);
604
605 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
606                 -1,     false, true,    0,      3300,   0);
607
608 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
609                 -1,     false, true,    0,      1200,   0);
610
611 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
612                 TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
613
614 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
615                 0,      0,
616                 TEGRA_GPIO_PH7, false,  false,  0,      3300,   0);
617
618 FIXED_REG(6,    usb0_vbus,      usb0_vbus,      NULL,   0,      0,
619                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
620
621 FIXED_REG(7,    usb1_usb2_vbus, usb1_usb2_vbus, NULL,   0,      0,
622                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
623
624 FIXED_REG(8,    vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
625                 TEGRA_GPIO_PP2, false,  true,   0,      3300, 0);
626
627 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
628                 TEGRA_GPIO_PH2, false,  true,   0,      5000,   0);
629
630 FIXED_REG(10,   3v3,            3v3,            NULL,   0,      0,
631                 -1,     false,  true,   0,      3300,   0);
632
633 FIXED_REG(11,   5v0,            5v0,            NULL,   0,      0,
634                 -1,     false,  true,   0,      5000,   0);
635
636 FIXED_REG(12,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
637                 -1,     false,  true,   0,      1800,   0);
638
639 FIXED_REG(13,   dcdc_1v2,       dcdc_1v2,       NULL,   0,      0,
640                 PMU_TCA6416_GPIO_BASE,  false,  true,   0,      1200,
641                 0);
642
643 FIXED_REG(14,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      true,
644                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  true,   true,
645                 3300,   0);
646
647 FIXED_REG(15,   lcd,            lcd,            NULL,   0,      0,
648                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,
649                 3300,   0);
650
651 FIXED_REG(16,   sdmmc_en,       sdmmc_en,       NULL,   0,      0,
652                 TEGRA_GPIO_PR0, false,  true,   0,      3300,   0);
653
654 FIXED_REG(17,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,
655                 0,      PMU_TCA6416_GPIO(2),    false,  true,   0,
656                 1200,   250000);
657
658 FIXED_REG(18,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,
659                 0,      PMU_TCA6416_GPIO(3),    false,  true,   0,
660                 1200,   0);
661
662 FIXED_REG(19,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
663                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300,   0);
664
665 /*
666  * Creating the fixed regulator device tables
667  */
668
669 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
670
671 #define NORRIN_COMMON_FIXED_REG                 \
672         ADD_FIXED_REG(battery),                 \
673         ADD_FIXED_REG(aon_1v8),                 \
674         ADD_FIXED_REG(aon_3v3),                 \
675         ADD_FIXED_REG(aon_1v2),                 \
676         ADD_FIXED_REG(vdd_hdmi_5v0),            \
677         ADD_FIXED_REG(vdd_hdmi),                \
678         ADD_FIXED_REG(vdd_lcd_bl),              \
679         ADD_FIXED_REG(lcd_bl_en),               \
680         ADD_FIXED_REG(3v3),                     \
681         ADD_FIXED_REG(5v0),                     \
682         ADD_FIXED_REG(dcdc_1v8),                \
683         ADD_FIXED_REG(as3722_gpio2),            \
684         ADD_FIXED_REG(lcd),                     \
685         ADD_FIXED_REG(sdmmc_en),                \
686         ADD_FIXED_REG(usb0_vbus),               \
687         ADD_FIXED_REG(usb1_usb2_vbus),          \
688         ADD_FIXED_REG(dcdc_1v2),                \
689         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
690         ADD_FIXED_REG(vdd_amp_shut_aud),        \
691         ADD_FIXED_REG(vdd_dsi_mux)
692
693 /* Gpio switch regulator platform data for Norrin ERS*/
694 static struct platform_device *fixed_reg_devs[] = {
695         NORRIN_COMMON_FIXED_REG,
696 };
697
698 static int __init norrin_fixed_regulator_init(void)
699 {
700         if (!of_machine_is_compatible("nvidia,norrin"))
701                 return 0;
702
703         return platform_add_devices(fixed_reg_devs,
704                         ARRAY_SIZE(fixed_reg_devs));
705
706         return 0;
707 }
708
709 subsys_initcall_sync(norrin_fixed_regulator_init);
710
711 int __init norrin_regulator_init(void)
712 {
713
714 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
715         norrin_cl_dvfs_init();
716 #endif
717         norrin_as3722_regulator_init();
718
719         return 0;
720 }
721
722 int __init norrin_suspend_init(void)
723 {
724         tegra_init_suspend(&norrin_suspend_data);
725         return 0;
726 }
727
728 int __init norrin_edp_init(void)
729 {
730         unsigned int regulator_mA;
731
732         regulator_mA = get_maximum_cpu_current_supported();
733         if (!regulator_mA)
734                 regulator_mA = 15000;
735
736         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
737
738         tegra_init_cpu_edp_limits(regulator_mA);
739
740         /* gpu maximum current */
741         regulator_mA = 8000;
742         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
743
744         tegra_init_gpu_edp_limits(regulator_mA);
745         return 0;
746 }
747
748 static struct pid_thermal_gov_params soctherm_pid_params = {
749         .max_err_temp = 9000,
750         .max_err_gain = 1000,
751
752         .gain_p = 1000,
753         .gain_d = 0,
754
755         .up_compensation = 20,
756         .down_compensation = 20,
757 };
758
759 static struct thermal_zone_params soctherm_tzp = {
760         .governor_name = "pid_thermal_gov",
761         .governor_params = &soctherm_pid_params,
762 };
763
764 static struct soctherm_platform_data norrin_soctherm_data = {
765         .therm = {
766                 [THERM_CPU] = {
767                         .zone_enable = true,
768                         .passive_delay = 1000,
769                         .hotspot_offset = 6000,
770                         .num_trips = 3,
771                         .trips = {
772                                 {
773                                         .cdev_type = "tegra-shutdown",
774                                         .trip_temp = 103000,
775                                         .trip_type = THERMAL_TRIP_CRITICAL,
776                                         .upper = THERMAL_NO_LIMIT,
777                                         .lower = THERMAL_NO_LIMIT,
778                                 },
779                                 {
780                                         .cdev_type = "tegra-heavy",
781                                         .trip_temp = 101000,
782                                         .trip_type = THERMAL_TRIP_HOT,
783                                         .upper = THERMAL_NO_LIMIT,
784                                         .lower = THERMAL_NO_LIMIT,
785                                 },
786                                 {
787                                         .cdev_type = "tegra-balanced",
788                                         .trip_temp = 91000,
789                                         .trip_type = THERMAL_TRIP_PASSIVE,
790                                         .upper = THERMAL_NO_LIMIT,
791                                         .lower = THERMAL_NO_LIMIT,
792                                 },
793                         },
794                         .tzp = &soctherm_tzp,
795                 },
796                 [THERM_GPU] = {
797                         .zone_enable = true,
798                         .passive_delay = 1000,
799                         .hotspot_offset = 6000,
800                         .num_trips = 3,
801                         .trips = {
802                                 {
803                                         .cdev_type = "tegra-shutdown",
804                                         .trip_temp = 104000,
805                                         .trip_type = THERMAL_TRIP_CRITICAL,
806                                         .upper = THERMAL_NO_LIMIT,
807                                         .lower = THERMAL_NO_LIMIT,
808                                 },
809                                 {
810                                         .cdev_type = "tegra-balanced",
811                                         .trip_temp = 92000,
812                                         .trip_type = THERMAL_TRIP_PASSIVE,
813                                         .upper = THERMAL_NO_LIMIT,
814                                         .lower = THERMAL_NO_LIMIT,
815                                 },
816 /*
817                                 {
818                                         .cdev_type = "gk20a_cdev",
819                                         .trip_temp = 102000,
820                                         .trip_type = THERMAL_TRIP_PASSIVE,
821                                         .upper = THERMAL_NO_LIMIT,
822                                         .lower = THERMAL_NO_LIMIT,
823                                 },
824                                 {
825                                         .cdev_type = "tegra-heavy",
826                                         .trip_temp = 102000,
827                                         .trip_type = THERMAL_TRIP_HOT,
828                                         .upper = THERMAL_NO_LIMIT,
829                                         .lower = THERMAL_NO_LIMIT,
830                                 },
831 */
832                         },
833                         .tzp = &soctherm_tzp,
834                 },
835                 [THERM_MEM] = {
836                         .zone_enable = true,
837                         .num_trips = 1,
838                         .trips = {
839                                 {
840                                         .cdev_type = "tegra-shutdown",
841                                         .trip_temp = 104000, /* = GPU shut */
842                                         .trip_type = THERMAL_TRIP_CRITICAL,
843                                         .upper = THERMAL_NO_LIMIT,
844                                         .lower = THERMAL_NO_LIMIT,
845                                 },
846                         },
847                 },
848                 [THERM_PLL] = {
849                         .zone_enable = true,
850                 },
851         },
852         .throttle = {
853                 [THROTTLE_HEAVY] = {
854                         .priority = 100,
855                         .devs = {
856                                 [THROTTLE_DEV_CPU] = {
857                                         .enable = true,
858                                         .depth = 80,
859                                 },
860                                 [THROTTLE_DEV_GPU] = {
861                                         .enable = false,
862                                         .throttling_depth = "heavy_throttling",
863                                 },
864                         },
865                 },
866         },
867 };
868
869 int __init norrin_soctherm_init(void)
870 {
871         tegra_platform_edp_init(norrin_soctherm_data.therm[THERM_CPU].trips,
872                         &norrin_soctherm_data.therm[THERM_CPU].num_trips,
873                         7000); /* edp temperature margin */
874         tegra_platform_gpu_edp_init(
875                         norrin_soctherm_data.therm[THERM_GPU].trips,
876                         &norrin_soctherm_data.therm[THERM_GPU].num_trips,
877                         7000);
878         tegra_add_cpu_vmax_trips(norrin_soctherm_data.therm[THERM_CPU].trips,
879                         &norrin_soctherm_data.therm[THERM_CPU].num_trips);
880         tegra_add_tgpu_trips(norrin_soctherm_data.therm[THERM_GPU].trips,
881                         &norrin_soctherm_data.therm[THERM_GPU].num_trips);
882         tegra_add_core_vmax_trips(norrin_soctherm_data.therm[THERM_PLL].trips,
883                         &norrin_soctherm_data.therm[THERM_PLL].num_trips);
884
885         return tegra11_soctherm_init(&norrin_soctherm_data);
886 }