ARM: tegra: pcie: Remove dock detect variable
[linux-3.10.git] / arch / arm / mach-tegra / board-norrin-power.c
1 /*
2  * arch/arm/mach-tegra/board-norrin-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-plat.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33 #include <linux/pid_thermal_gov.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-pmu-defines.h"
48 #include "board-ardbeg.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52 #include "iomap.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56 #define AS3722_SUPPLY(_name)    "as3722_"#_name
57
58 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
59         REGULATOR_SUPPLY("avdd_pll_m", NULL),
60         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
61         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
62         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
63         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
64         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
65         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
66         REGULATOR_SUPPLY("avdd_pll_x", NULL),
67         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
68 };
69
70 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
71         REGULATOR_SUPPLY("vddio_cam", "vi"),
72         REGULATOR_SUPPLY("pwrdet_cam", NULL),
73         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
74         REGULATOR_SUPPLY("vif", "2-0010"),
75         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
76         REGULATOR_SUPPLY("vif", "2-0036"),
77         REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
78         REGULATOR_SUPPLY("vi2c", "2-0030"),
79 };
80
81 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
82         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
83         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
84         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
85         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
86         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
87         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
88         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
89         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
90         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
91         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
92 };
93
94 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
95         REGULATOR_SUPPLY("vdd_rtc", NULL),
96 };
97
98 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
99         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
100         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
101         REGULATOR_SUPPLY("vana", "2-0010"),
102 };
103
104 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
105         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
106         REGULATOR_SUPPLY("vdig", "2-0010"),
107         REGULATOR_SUPPLY("vdig", "2-0036"),
108 };
109
110 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
111         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
112         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
113 };
114
115 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
116         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
117         REGULATOR_SUPPLY("imx135_reg2", NULL),
118         REGULATOR_SUPPLY("vdig_lv", "2-0010"),
119         REGULATOR_SUPPLY("dvdd", "2-0010"),
120 };
121
122 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
123         REGULATOR_SUPPLY("avdd", "spi0.0"),
124         REGULATOR_SUPPLY("avdd", "spi2.1"),
125 };
126
127 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
128         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
129         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
130         REGULATOR_SUPPLY("imx135_reg1", NULL),
131         REGULATOR_SUPPLY("vdd", "2-000e"),
132         REGULATOR_SUPPLY("vana", "2-0036"),
133         REGULATOR_SUPPLY("vdd", "2-000c"),
134 };
135
136 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
137         REGULATOR_SUPPLY("vpp_fuse", NULL),
138 };
139
140 static struct regulator_consumer_supply as3722_sd0_supply[] = {
141         REGULATOR_SUPPLY("vdd_cpu", NULL),
142 };
143
144 static struct regulator_consumer_supply as3722_sd1_supply[] = {
145         REGULATOR_SUPPLY("vdd_core", NULL),
146 };
147
148 static struct regulator_consumer_supply as3722_sd2_supply[] = {
149         REGULATOR_SUPPLY("vddio_ddr", NULL),
150         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
151         REGULATOR_SUPPLY("vddio_ddr3", NULL),
152         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
153 };
154
155 static struct regulator_consumer_supply as3722_sd4_supply[] = {
156         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
157         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
158         REGULATOR_SUPPLY("dvddio_pex", NULL),
159         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
160         REGULATOR_SUPPLY("avdd_sata", NULL),
161         REGULATOR_SUPPLY("vdd_sata", NULL),
162         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
163         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
164         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
165 };
166
167 static struct regulator_consumer_supply as3722_sd5_supply[] = {
168         REGULATOR_SUPPLY("vddio_sys", NULL),
169         REGULATOR_SUPPLY("vddio_sys_2", NULL),
170         REGULATOR_SUPPLY("vddio_audio", NULL),
171         REGULATOR_SUPPLY("pwrdet_audio", NULL),
172         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
173         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
174         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
175         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
176         REGULATOR_SUPPLY("vddio_uart", NULL),
177         REGULATOR_SUPPLY("pwrdet_uart", NULL),
178         REGULATOR_SUPPLY("vddio_bb", NULL),
179         REGULATOR_SUPPLY("pwrdet_bb", NULL),
180         REGULATOR_SUPPLY("vddio_gmi", NULL),
181         REGULATOR_SUPPLY("pwrdet_nand", NULL),
182         REGULATOR_SUPPLY("avdd_osc", NULL),
183         /* emmc 1.8v misssing
184         keyboard & touchpad 1.8v missing */
185 };
186
187 static struct regulator_consumer_supply as3722_sd6_supply[] = {
188         REGULATOR_SUPPLY("vdd_gpu", NULL),
189 };
190
191 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1,
192                AS3722_EXT_CONTROL_ENABLE2);
193 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1,
194                AS3722_EXT_CONTROL_ENABLE1);
195 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
196 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 1, 1, 1,
197                AS3722_EXT_CONTROL_ENABLE1);
198 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
199 AMS_PDATA_INIT(sd6, NULL, 650000, 1200000, 0, 1, 1, 0);
200 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1,
201                AS3722_EXT_CONTROL_ENABLE1);
202 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
203 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
204 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
205 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
206 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
207 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
208 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1275000, 1275000, 0, 0, 1, 0);
209 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
210 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
211 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
212
213 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
214         AS3722_PIN_CONTROL("gpio0", "gpio", NULL, NULL, NULL, "output-low"),
215         AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
216         AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
217         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
218         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
219         AS3722_PIN_CONTROL("gpio5", "gpio", "pull-down", NULL, "enabled", NULL),
220         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
221         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-high"),
222 };
223
224 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
225         .connection_name = "as3722-extcon",
226         .enable_adc1_continuous_mode = true,
227         .enable_low_voltage_range = true,
228         .adc_channel = 12,
229         .hi_threshold =  0x100,
230         .low_threshold = 0x80,
231 };
232
233 static struct as3722_platform_data as3722_pdata = {
234         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
235         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
236         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
237         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
238         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
239         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
240         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
241         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
242         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
243         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
244         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
245
246         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
247         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
248         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
249         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
250         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
251         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
252
253         .gpio_base = AS3722_GPIO_BASE,
254         .irq_base = AS3722_IRQ_BASE,
255         .use_internal_int_pullup = 0,
256         .use_internal_i2c_pullup = 0,
257         .pinctrl_pdata = as3722_pctrl_pdata,
258         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
259         .enable_clk32k_out = true,
260         .use_power_off = true,
261         .extcon_pdata = &as3722_adc_extcon_pdata,
262         .major_rev = 1,
263         .minor_rev = 1,
264 };
265
266 static struct pca953x_platform_data tca6416_pdata = {
267         .gpio_base = PMU_TCA6416_GPIO_BASE,
268 };
269
270 static const struct i2c_board_info tca6416_expander[] = {
271         {
272                 I2C_BOARD_INFO("tca6416", 0x20),
273                 .platform_data = &tca6416_pdata,
274         },
275 };
276
277 static struct i2c_board_info __initdata as3722_regulators[] = {
278         {
279                 I2C_BOARD_INFO("as3722", 0x40),
280                 .flags = I2C_CLIENT_WAKE,
281                 .irq = INT_EXTERNAL_PMU,
282                 .platform_data = &as3722_pdata,
283         },
284 };
285
286 int __init norrin_as3722_regulator_init(void)
287 {
288         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
289         u32 pmc_ctrl;
290         struct board_info board_info;
291
292         tegra_get_board_info(&board_info);
293
294         /* AS3722: Normal state of INT request line is LOW.
295          * configure the power management controller to trigger PMU
296          * interrupts when HIGH.
297          */
298         pmc_ctrl = readl(pmc + PMC_CTRL);
299         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
300         regulator_has_full_constraints();
301         /* Set vdd_gpu init uV to 1V */
302         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
303
304         /* Set overcurrent of rails. */
305         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
306         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
307
308         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
309         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
310
311         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
312         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
313
314         as3722_ldo3_reg_pdata.enable_tracking = true;
315         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
316
317         if ((board_info.board_id == BOARD_PM374) &&
318                                 (board_info.fab == BOARD_FAB_B))
319                 as3722_pdata.minor_rev = 2;
320         pr_info("%s: i2c_register_board_info\n", __func__);
321         i2c_register_board_info(4, as3722_regulators,
322                         ARRAY_SIZE(as3722_regulators));
323         i2c_register_board_info(0, tca6416_expander,
324                         ARRAY_SIZE(tca6416_expander));
325         return 0;
326 }
327
328 static struct tegra_suspend_platform_data norrin_suspend_data = {
329         .cpu_timer      = 2000,
330         .cpu_off_timer  = 2000,
331         .suspend_mode   = TEGRA_SUSPEND_LP0,
332         .core_timer     = 0x7e7e,
333         .core_off_timer = 2000,
334         .corereq_high   = true,
335         .sysclkreq_high = true,
336         .cpu_lp2_min_residency = 1000,
337 };
338
339 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
340 /* board parameters for cpu dfll */
341 static struct tegra_cl_dvfs_cfg_param norrin_cl_dvfs_param = {
342         .sample_rate = 12500,
343
344         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
345         .cf = 10,
346         .ci = 0,
347         .cg = 2,
348
349         .droop_cut_value = 0xF,
350         .droop_restore_ramp = 0x0,
351         .scale_out_ramp = 0x0,
352 };
353 #endif
354
355 /* Norrin: fixed 10mV steps from 700mV to 1400mV */
356 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
357 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
358 static inline void fill_reg_map(void)
359 {
360         int i;
361         u32 reg_init_value = 0x0a;
362         struct board_info board_info;
363
364         tegra_get_board_info(&board_info);
365         if ((board_info.board_id == BOARD_PM374) &&
366                         (board_info.fab == 0x01))
367                 reg_init_value = 0x1e;
368
369         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
370                 pmu_cpu_vdd_map[i].reg_value = i + reg_init_value;
371                 pmu_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
372         }
373 }
374
375 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
376 static struct tegra_cl_dvfs_platform_data norrin_cl_dvfs_data = {
377         .dfll_clk_name = "dfll_cpu",
378         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
379         .u.pmu_i2c = {
380                 .fs_rate = 400000,
381                 .slave_addr = 0x80,
382                 .reg = 0x00,
383         },
384         .vdd_map = pmu_cpu_vdd_map,
385         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
386
387         .cfg_param = &norrin_cl_dvfs_param,
388 };
389
390 static int __init norrin_cl_dvfs_init(void)
391 {
392         fill_reg_map();
393         norrin_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
394         tegra_cl_dvfs_device.dev.platform_data = &norrin_cl_dvfs_data;
395         platform_device_register(&tegra_cl_dvfs_device);
396
397         return 0;
398 }
399 #endif
400
401 /* Always ON /Battery regulator */
402 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
403         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
404         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
405 };
406
407 /* Always ON 1.8v */
408 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
409         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
410         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
411         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
412 };
413
414 /* Always ON 3.3v */
415 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
416         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
417         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
418 };
419
420 /* Always ON 1v2 */
421 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
422         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
423 };
424
425 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
426 static struct regulator_consumer_supply fixed_reg_usb0_vbus_supply[] = {
427         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
428         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
429         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
430 };
431
432 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
433 static struct regulator_consumer_supply fixed_reg_usb1_usb2_vbus_supply[] = {
434         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
435         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
436         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
437         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
438 };
439
440 /* Gated by GPIO_PK6 */
441 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
442         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
443 };
444
445 /* Gated by GPIO_PH7 */
446 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
447         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
448 };
449
450 /* VDD_LCD_BL DAP3_DOUT */
451 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
452         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
453 };
454
455 /* LCD_BL_EN GMI_AD10 */
456 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
457         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
458 };
459
460 /* AS3722 GPIO1*/
461 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
462         REGULATOR_SUPPLY("hvdd_pex", NULL),
463         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
464         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
465         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
466         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
467         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
468         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
469         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
470         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
471         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
472         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
473         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
474         REGULATOR_SUPPLY("vdd", "1-004c"),
475         REGULATOR_SUPPLY("vdd", "0-0048"),
476         REGULATOR_SUPPLY("vdd", "0-0069"),
477         REGULATOR_SUPPLY("vdd", "0-000c"),
478         REGULATOR_SUPPLY("vdd", "0-0077"),
479         REGULATOR_SUPPLY("vin", "2-0030"),
480 };
481
482 /* AS3722 GPIO1*/
483 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
484         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
485         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
486         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
487 };
488
489 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
490         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
491         REGULATOR_SUPPLY("dvdd_lcd", NULL),
492         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
493         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
494         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
495         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
496         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
497         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
498         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
499         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
500         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
501         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
502         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
503         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
504         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
505         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
506         REGULATOR_SUPPLY("dvdd", "spi0.0"),
507         REGULATOR_SUPPLY("dvdd", "spi2.1"),
508         REGULATOR_SUPPLY("vlogic", "0-0069"),
509         REGULATOR_SUPPLY("vid", "0-000c"),
510         REGULATOR_SUPPLY("vddio", "0-0077"),
511         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
512         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
513         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
514         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
515         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
516 };
517
518 /* gated by TCA6416 GPIO EXP GPIO0 */
519 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
520         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
521 };
522
523 /* AMS GPIO2 */
524 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
525         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
526         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
527         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
528         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
529         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
530         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
531         REGULATOR_SUPPLY("pwrdet_hv", NULL),
532         REGULATOR_SUPPLY("hvdd_sata", NULL),
533 };
534
535 /* gated by AS3722 GPIO4 */
536 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
537         REGULATOR_SUPPLY("avdd_lcd", NULL),
538 };
539
540 /* gated by GPIO_PR0 */
541 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
542         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
543         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
544 };
545
546 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
547         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
548 };
549
550 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
551         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
552 };
553
554 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
555         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
556 };
557
558 /* Macro for defining fixed regulator sub device data */
559 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
560 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
561         _always_on, _boot_on, _gpio_nr, _open_drain,            \
562         _active_high, _boot_state, _millivolts, _sdelay)        \
563 static struct regulator_init_data ri_data_##_var =              \
564 {                                                               \
565         .supply_regulator = _in_supply,                         \
566         .num_consumer_supplies =                                \
567         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
568         .consumer_supplies = fixed_reg_##_name##_supply,        \
569         .constraints = {                                        \
570                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
571                                 REGULATOR_MODE_STANDBY),        \
572                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
573                                 REGULATOR_CHANGE_STATUS |       \
574                                 REGULATOR_CHANGE_VOLTAGE),      \
575                 .always_on = _always_on,                        \
576                 .boot_on = _boot_on,                            \
577         },                                                      \
578 };                                                              \
579 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
580 {                                                               \
581         .supply_name = FIXED_SUPPLY(_name),                     \
582         .microvolts = _millivolts * 1000,                       \
583         .gpio = _gpio_nr,                                       \
584         .gpio_is_open_drain = _open_drain,                      \
585         .enable_high = _active_high,                            \
586         .enabled_at_boot = _boot_state,                         \
587         .init_data = &ri_data_##_var,                           \
588         .startup_delay = _sdelay,                               \
589 };                                                              \
590 static struct platform_device fixed_reg_##_var##_dev = {        \
591         .name = "reg-fixed-voltage",                            \
592         .id = _id,                                              \
593         .dev = {                                                \
594                 .platform_data = &fixed_reg_##_var##_pdata,     \
595         },                                                      \
596 }
597
598 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
599                 -1,     false, true,    0,      8400,   0);
600
601 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
602                 -1,     false, true,    0,      1800,   0);
603
604 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
605                 -1,     false, true,    0,      3300,   0);
606
607 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
608                 -1,     false, true,    0,      1200,   0);
609
610 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
611                 TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
612
613 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
614                 0,      0,
615                 TEGRA_GPIO_PH7, false,  false,  0,      3300,   0);
616
617 FIXED_REG(6,    usb0_vbus,      usb0_vbus,      NULL,   0,      0,
618                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
619
620 FIXED_REG(7,    usb1_usb2_vbus, usb1_usb2_vbus, NULL,   0,      0,
621                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
622
623 FIXED_REG(8,    vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
624                 TEGRA_GPIO_PP2, false,  true,   0,      3300, 0);
625
626 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
627                 TEGRA_GPIO_PH2, false,  true,   0,      5000,   0);
628
629 FIXED_REG(10,   3v3,            3v3,            NULL,   0,      0,
630                 -1,     false,  true,   0,      3300,   0);
631
632 FIXED_REG(11,   5v0,            5v0,            NULL,   0,      0,
633                 -1,     false,  true,   0,      5000,   0);
634
635 FIXED_REG(12,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
636                 -1,     false,  true,   0,      1800,   0);
637
638 FIXED_REG(13,   dcdc_1v2,       dcdc_1v2,       NULL,   0,      0,
639                 PMU_TCA6416_GPIO_BASE,  false,  true,   0,      1200,
640                 0);
641
642 FIXED_REG(14,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      true,
643                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  true,   true,
644                 3300,   0);
645
646 FIXED_REG(15,   lcd,            lcd,            NULL,   0,      0,
647                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,
648                 3300,   0);
649
650 FIXED_REG(16,   sdmmc_en,       sdmmc_en,       NULL,   0,      0,
651                 TEGRA_GPIO_PR0, false,  true,   0,      3300,   0);
652
653 FIXED_REG(17,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,
654                 0,      PMU_TCA6416_GPIO(2),    false,  true,   0,
655                 1200,   250000);
656
657 FIXED_REG(18,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,
658                 0,      PMU_TCA6416_GPIO(3),    false,  true,   0,
659                 1200,   0);
660
661 FIXED_REG(19,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
662                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300,   0);
663
664 /*
665  * Creating the fixed regulator device tables
666  */
667
668 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
669
670 #define NORRIN_COMMON_FIXED_REG                 \
671         ADD_FIXED_REG(battery),                 \
672         ADD_FIXED_REG(aon_1v8),                 \
673         ADD_FIXED_REG(aon_3v3),                 \
674         ADD_FIXED_REG(aon_1v2),                 \
675         ADD_FIXED_REG(vdd_hdmi_5v0),            \
676         ADD_FIXED_REG(vdd_hdmi),                \
677         ADD_FIXED_REG(vdd_lcd_bl),              \
678         ADD_FIXED_REG(lcd_bl_en),               \
679         ADD_FIXED_REG(3v3),                     \
680         ADD_FIXED_REG(5v0),                     \
681         ADD_FIXED_REG(dcdc_1v8),                \
682         ADD_FIXED_REG(as3722_gpio2),            \
683         ADD_FIXED_REG(lcd),                     \
684         ADD_FIXED_REG(sdmmc_en),                \
685         ADD_FIXED_REG(usb0_vbus),               \
686         ADD_FIXED_REG(usb1_usb2_vbus),          \
687         ADD_FIXED_REG(dcdc_1v2),                \
688         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
689         ADD_FIXED_REG(vdd_amp_shut_aud),        \
690         ADD_FIXED_REG(vdd_dsi_mux)
691
692 /* Gpio switch regulator platform data for Norrin ERS*/
693 static struct platform_device *fixed_reg_devs[] = {
694         NORRIN_COMMON_FIXED_REG,
695 };
696
697 static int __init norrin_fixed_regulator_init(void)
698 {
699         if (!of_machine_is_compatible("nvidia,norrin"))
700                 return 0;
701
702         return platform_add_devices(fixed_reg_devs,
703                         ARRAY_SIZE(fixed_reg_devs));
704
705         return 0;
706 }
707
708 subsys_initcall_sync(norrin_fixed_regulator_init);
709
710 int __init norrin_regulator_init(void)
711 {
712
713 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
714         norrin_cl_dvfs_init();
715 #endif
716         norrin_as3722_regulator_init();
717
718         return 0;
719 }
720
721 int __init norrin_suspend_init(void)
722 {
723         tegra_init_suspend(&norrin_suspend_data);
724         return 0;
725 }
726
727 int __init norrin_edp_init(void)
728 {
729         unsigned int regulator_mA;
730
731         regulator_mA = get_maximum_cpu_current_supported();
732         if (!regulator_mA)
733                 regulator_mA = 15000;
734
735         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
736
737         tegra_init_cpu_edp_limits(regulator_mA);
738
739         /* gpu maximum current */
740         regulator_mA = 8000;
741         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
742
743         tegra_init_gpu_edp_limits(regulator_mA);
744         return 0;
745 }
746
747 static struct pid_thermal_gov_params soctherm_pid_params = {
748         .max_err_temp = 9000,
749         .max_err_gain = 1000,
750
751         .gain_p = 1000,
752         .gain_d = 0,
753
754         .up_compensation = 20,
755         .down_compensation = 20,
756 };
757
758 static struct thermal_zone_params soctherm_tzp = {
759         .governor_name = "pid_thermal_gov",
760         .governor_params = &soctherm_pid_params,
761 };
762
763 static struct soctherm_platform_data norrin_soctherm_data = {
764         .therm = {
765                 [THERM_CPU] = {
766                         .zone_enable = true,
767                         .passive_delay = 1000,
768                         .hotspot_offset = 6000,
769                         .num_trips = 3,
770                         .trips = {
771                                 {
772                                         .cdev_type = "tegra-shutdown",
773                                         .trip_temp = 103000,
774                                         .trip_type = THERMAL_TRIP_CRITICAL,
775                                         .upper = THERMAL_NO_LIMIT,
776                                         .lower = THERMAL_NO_LIMIT,
777                                 },
778                                 {
779                                         .cdev_type = "tegra-heavy",
780                                         .trip_temp = 101000,
781                                         .trip_type = THERMAL_TRIP_HOT,
782                                         .upper = THERMAL_NO_LIMIT,
783                                         .lower = THERMAL_NO_LIMIT,
784                                 },
785                                 {
786                                         .cdev_type = "tegra-balanced",
787                                         .trip_temp = 91000,
788                                         .trip_type = THERMAL_TRIP_PASSIVE,
789                                         .upper = THERMAL_NO_LIMIT,
790                                         .lower = THERMAL_NO_LIMIT,
791                                 },
792                         },
793                         .tzp = &soctherm_tzp,
794                 },
795                 [THERM_GPU] = {
796                         .zone_enable = true,
797                         .passive_delay = 1000,
798                         .hotspot_offset = 6000,
799                         .num_trips = 3,
800                         .trips = {
801                                 {
802                                         .cdev_type = "tegra-shutdown",
803                                         .trip_temp = 104000,
804                                         .trip_type = THERMAL_TRIP_CRITICAL,
805                                         .upper = THERMAL_NO_LIMIT,
806                                         .lower = THERMAL_NO_LIMIT,
807                                 },
808                                 {
809                                         .cdev_type = "tegra-balanced",
810                                         .trip_temp = 92000,
811                                         .trip_type = THERMAL_TRIP_PASSIVE,
812                                         .upper = THERMAL_NO_LIMIT,
813                                         .lower = THERMAL_NO_LIMIT,
814                                 },
815 /*
816                                 {
817                                         .cdev_type = "gk20a_cdev",
818                                         .trip_temp = 102000,
819                                         .trip_type = THERMAL_TRIP_PASSIVE,
820                                         .upper = THERMAL_NO_LIMIT,
821                                         .lower = THERMAL_NO_LIMIT,
822                                 },
823                                 {
824                                         .cdev_type = "tegra-heavy",
825                                         .trip_temp = 102000,
826                                         .trip_type = THERMAL_TRIP_HOT,
827                                         .upper = THERMAL_NO_LIMIT,
828                                         .lower = THERMAL_NO_LIMIT,
829                                 },
830 */
831                         },
832                         .tzp = &soctherm_tzp,
833                 },
834                 [THERM_MEM] = {
835                         .zone_enable = true,
836                         .num_trips = 1,
837                         .trips = {
838                                 {
839                                         .cdev_type = "tegra-shutdown",
840                                         .trip_temp = 104000, /* = GPU shut */
841                                         .trip_type = THERMAL_TRIP_CRITICAL,
842                                         .upper = THERMAL_NO_LIMIT,
843                                         .lower = THERMAL_NO_LIMIT,
844                                 },
845                         },
846                 },
847                 [THERM_PLL] = {
848                         .zone_enable = true,
849                 },
850         },
851         .throttle = {
852                 [THROTTLE_HEAVY] = {
853                         .priority = 100,
854                         .devs = {
855                                 [THROTTLE_DEV_CPU] = {
856                                         .enable = true,
857                                         .depth = 80,
858                                 },
859                                 [THROTTLE_DEV_GPU] = {
860                                         .enable = false,
861                                         .throttling_depth = "heavy_throttling",
862                                 },
863                         },
864                 },
865         },
866 };
867
868 int __init norrin_soctherm_init(void)
869 {
870         tegra_platform_edp_init(norrin_soctherm_data.therm[THERM_CPU].trips,
871                         &norrin_soctherm_data.therm[THERM_CPU].num_trips,
872                         7000); /* edp temperature margin */
873         tegra_platform_gpu_edp_init(
874                         norrin_soctherm_data.therm[THERM_GPU].trips,
875                         &norrin_soctherm_data.therm[THERM_GPU].num_trips,
876                         7000);
877         tegra_add_cpu_vmax_trips(norrin_soctherm_data.therm[THERM_CPU].trips,
878                         &norrin_soctherm_data.therm[THERM_CPU].num_trips);
879         tegra_add_tgpu_trips(norrin_soctherm_data.therm[THERM_GPU].trips,
880                         &norrin_soctherm_data.therm[THERM_GPU].num_trips);
881         tegra_add_core_vmax_trips(norrin_soctherm_data.therm[THERM_PLL].trips,
882                         &norrin_soctherm_data.therm[THERM_PLL].num_trips);
883
884         return tegra11_soctherm_init(&norrin_soctherm_data);
885 }