2 * arch/arm/mach-tegra/board-macallan-power.c
4 * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/power/bq2419x-charger.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/power/power_supply_extcon.h>
32 #include <linux/gpio.h>
33 #include <linux/interrupt.h>
34 #include <linux/regulator/userspace-consumer.h>
35 #include <linux/edp.h>
36 #include <linux/edpdev.h>
37 #include <linux/platform_data/tegra_edp.h>
38 #include <linux/pid_thermal_gov.h>
39 #include <linux/tegra-soc.h>
41 #include <asm/mach-types.h>
42 #include <linux/power/sbs-battery.h>
44 #include <mach/irqs.h>
46 #include <mach/gpio-tegra.h>
48 #include "cpu-tegra.h"
50 #include "tegra-board-id.h"
51 #include "board-pmu-defines.h"
53 #include "gpio-names.h"
54 #include "board-common.h"
55 #include "board-macallan.h"
56 #include "tegra_cl_dvfs.h"
58 #include "tegra11_soctherm.h"
59 #include "tegra3_tsensor.h"
61 #include "battery-ini-model-data.h"
64 #define PMC_CTRL_INTR_LOW (1 << 17)
66 /* BQ2419X VBUS regulator */
67 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
68 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
69 REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
72 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
73 REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
76 static struct bq2419x_vbus_platform_data macallan_bq2419x_vbus_pdata = {
77 .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
78 .consumer_supplies = bq2419x_vbus_supply,
81 struct bq2419x_charger_platform_data macallan_bq2419x_charger_pdata = {
82 .max_charge_current_mA = 3000,
83 .charging_term_current_mA = 100,
84 .consumer_supplies = bq2419x_batt_supply,
85 .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
87 .rtc_alarm_time = 3600,
88 .chg_restart_time = 1800,
91 struct max17048_platform_data macallan_max17048_pdata = {
92 .model_data = &macallan_yoku_4100mA_max17048_battery,
95 static struct i2c_board_info __initdata macallan_max17048_boardinfo[] = {
97 I2C_BOARD_INFO("max17048", 0x36),
98 .platform_data = &macallan_max17048_pdata,
102 struct bq2419x_platform_data macallan_bq2419x_pdata = {
103 .vbus_pdata = &macallan_bq2419x_vbus_pdata,
104 .bcharger_pdata = &macallan_bq2419x_charger_pdata,
107 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
109 I2C_BOARD_INFO("bq2419x", 0x6b),
110 .platform_data = &macallan_bq2419x_pdata,
114 static struct power_supply_extcon_plat_data psy_extcon_pdata = {
115 .extcon_name = "tegra-udc",
118 static struct platform_device psy_extcon_device = {
119 .name = "power-supply-extcon",
122 .platform_data = &psy_extcon_pdata,
126 /************************ Macallan based regulator ****************/
127 static struct regulator_consumer_supply palmas_smps123_supply[] = {
128 REGULATOR_SUPPLY("vdd_cpu", NULL),
131 static struct regulator_consumer_supply palmas_smps45_supply[] = {
132 REGULATOR_SUPPLY("vdd_core", NULL),
133 REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
134 REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
137 static struct regulator_consumer_supply palmas_smps6_supply[] = {
138 REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
139 REGULATOR_SUPPLY("avdd_lcd", NULL),
140 REGULATOR_SUPPLY("avdd", "spi0.0"),
143 static struct regulator_consumer_supply palmas_smps7_supply[] = {
144 REGULATOR_SUPPLY("vddio_ddr", NULL),
147 static struct regulator_consumer_supply palmas_smps8_supply[] = {
148 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
149 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
150 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
151 REGULATOR_SUPPLY("avdd_osc", NULL),
152 REGULATOR_SUPPLY("vddio_sys", NULL),
153 REGULATOR_SUPPLY("vddio_bb", NULL),
154 REGULATOR_SUPPLY("pwrdet_bb", NULL),
155 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
156 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
157 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
158 REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
159 REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
160 REGULATOR_SUPPLY("vddio_audio", NULL),
161 REGULATOR_SUPPLY("pwrdet_audio", NULL),
162 REGULATOR_SUPPLY("vddio_uart", NULL),
163 REGULATOR_SUPPLY("pwrdet_uart", NULL),
164 REGULATOR_SUPPLY("vddio_gmi", NULL),
165 REGULATOR_SUPPLY("pwrdet_nand", NULL),
166 REGULATOR_SUPPLY("vlogic", "0-0069"),
167 REGULATOR_SUPPLY("vid", "0-000d"),
168 REGULATOR_SUPPLY("vddio", "0-0078"),
169 REGULATOR_SUPPLY("vdd", "0-004c"),
172 static struct regulator_consumer_supply palmas_smps9_supply[] = {
173 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
174 REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
175 REGULATOR_SUPPLY("pwrdet_hv", NULL),
178 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
181 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
182 REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
183 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
184 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
185 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
186 REGULATOR_SUPPLY("avdd_pllm", NULL),
187 REGULATOR_SUPPLY("avdd_pllu", NULL),
188 REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
189 REGULATOR_SUPPLY("avdd_pllx", NULL),
190 REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
191 REGULATOR_SUPPLY("avdd_plle", NULL),
194 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
195 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
196 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
197 REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
198 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
199 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
200 REGULATOR_SUPPLY("pwrdet_mipi", NULL),
203 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
204 REGULATOR_SUPPLY("vpp_fuse", NULL),
207 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
208 REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
209 REGULATOR_SUPPLY("dvdd", "2-0010"),
210 REGULATOR_SUPPLY("vdig", "2-0036"),
213 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
214 REGULATOR_SUPPLY("avdd_cam2", NULL),
215 REGULATOR_SUPPLY("avdd", "2-0010"),
218 static struct regulator_consumer_supply palmas_ldo5_e1569_supply[] = {
219 REGULATOR_SUPPLY("avdd_cam2", NULL),
220 REGULATOR_SUPPLY("avdd", "2-0010"),
221 REGULATOR_SUPPLY("vdd_af_cam1", NULL),
222 REGULATOR_SUPPLY("vdd", "2-000e"),
225 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
226 REGULATOR_SUPPLY("vdd", "0-0069"),
227 REGULATOR_SUPPLY("vdd", "0-000d"),
228 REGULATOR_SUPPLY("vdd", "0-0078"),
231 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
232 REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
233 REGULATOR_SUPPLY("vdd_af_cam1", NULL),
234 REGULATOR_SUPPLY("avdd_cam1", NULL),
235 REGULATOR_SUPPLY("vana", "2-0036"),
236 REGULATOR_SUPPLY("vdd", "2-000e"),
239 static struct regulator_consumer_supply palmas_ldo7_e1569_supply[] = {
240 REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
241 REGULATOR_SUPPLY("avdd_cam1", NULL),
242 REGULATOR_SUPPLY("vana", "2-0036"),
245 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
246 REGULATOR_SUPPLY("vdd_rtc", NULL),
248 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
249 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
250 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
252 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
253 REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
256 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
257 REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
258 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
259 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
260 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
261 REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
265 static struct regulator_consumer_supply palmas_regen1_supply[] = {
268 static struct regulator_consumer_supply palmas_regen2_supply[] = {
271 PALMAS_REGS_PDATA(smps123, 900, 1350, NULL, 0, 0, 0, 0,
272 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
273 PALMAS_REGS_PDATA(smps45, 900, 1400, NULL, 0, 0, 0, 0,
274 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
275 PALMAS_REGS_PDATA(smps6, 3200, 3200, NULL, 0, 0, 1, NORMAL,
277 PALMAS_REGS_PDATA(smps7, 1350, 1350, NULL, 0, 0, 1, NORMAL,
279 PALMAS_REGS_PDATA(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL,
281 PALMAS_REGS_PDATA(smps9, 2900, 2900, NULL, 1, 0, 1, NORMAL,
283 PALMAS_REGS_PDATA(smps10_out1, 5000, 5000, NULL, 0, 0, 0, 0,
285 PALMAS_REGS_PDATA(ldo1, 1050, 1050, palmas_rails(smps7), 1, 0, 1, 0,
286 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
287 PALMAS_REGS_PDATA(ldo2, 1200, 1200, palmas_rails(smps7), 0, 1, 1, 0,
289 PALMAS_REGS_PDATA(ldo3, 1800, 1800, NULL, 0, 0, 1, 0,
291 PALMAS_REGS_PDATA(ldo4, 1200, 1200, palmas_rails(smps8), 0, 0, 1, 0,
293 PALMAS_REGS_PDATA(ldo5, 2800, 2800, palmas_rails(smps9), 0, 0, 1, 0,
295 PALMAS_REGS_PDATA(ldo6, 2850, 2850, palmas_rails(smps9), 1, 1, 1, 0,
297 PALMAS_REGS_PDATA(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0,
299 PALMAS_REGS_PDATA(ldo8, 950, 950, NULL, 1, 1, 1, 0,
301 PALMAS_REGS_PDATA(ldo9, 1800, 2900, palmas_rails(smps9), 0, 0, 1, 0,
303 PALMAS_REGS_PDATA(ldoln, 3300, 3300, NULL, 0, 0, 1, 0,
305 PALMAS_REGS_PDATA(ldousb, 3300, 3300, NULL, 0, 0, 1, 0,
306 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
307 PALMAS_REGS_PDATA(regen1, 4200, 4200, NULL, 0, 0, 0, 0,
309 PALMAS_REGS_PDATA(regen2, 4200, 4200, palmas_rails(smps8), 0, 0, 0, 0,
312 #define PALMAS_REG_PDATA(_sname) (®_idata_##_sname)
313 static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = {
315 PALMAS_REG_PDATA(smps123),
317 PALMAS_REG_PDATA(smps45),
319 PALMAS_REG_PDATA(smps6),
320 PALMAS_REG_PDATA(smps7),
321 PALMAS_REG_PDATA(smps8),
322 PALMAS_REG_PDATA(smps9),
324 PALMAS_REG_PDATA(smps10_out1),
325 PALMAS_REG_PDATA(ldo1),
326 PALMAS_REG_PDATA(ldo2),
327 PALMAS_REG_PDATA(ldo3),
328 PALMAS_REG_PDATA(ldo4),
329 PALMAS_REG_PDATA(ldo5),
330 PALMAS_REG_PDATA(ldo6),
331 PALMAS_REG_PDATA(ldo7),
332 PALMAS_REG_PDATA(ldo8),
333 PALMAS_REG_PDATA(ldo9),
334 PALMAS_REG_PDATA(ldoln),
335 PALMAS_REG_PDATA(ldousb),
336 PALMAS_REG_PDATA(regen1),
337 PALMAS_REG_PDATA(regen2),
343 #define PALMAS_REG_INIT_DATA(_sname) (®_init_data_##_sname)
344 static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = {
346 PALMAS_REG_INIT_DATA(smps123),
348 PALMAS_REG_INIT_DATA(smps45),
350 PALMAS_REG_INIT_DATA(smps6),
351 PALMAS_REG_INIT_DATA(smps7),
352 PALMAS_REG_INIT_DATA(smps8),
353 PALMAS_REG_INIT_DATA(smps9),
355 PALMAS_REG_INIT_DATA(smps10_out1),
356 PALMAS_REG_INIT_DATA(ldo1),
357 PALMAS_REG_INIT_DATA(ldo2),
358 PALMAS_REG_INIT_DATA(ldo3),
359 PALMAS_REG_INIT_DATA(ldo4),
360 PALMAS_REG_INIT_DATA(ldo5),
361 PALMAS_REG_INIT_DATA(ldo6),
362 PALMAS_REG_INIT_DATA(ldo7),
363 PALMAS_REG_INIT_DATA(ldo8),
364 PALMAS_REG_INIT_DATA(ldo9),
365 PALMAS_REG_INIT_DATA(ldoln),
366 PALMAS_REG_INIT_DATA(ldousb),
367 PALMAS_REG_INIT_DATA(regen1),
368 PALMAS_REG_INIT_DATA(regen2),
374 static struct palmas_pmic_platform_data pmic_platform = {
375 .disable_smps10_boost_suspend = true,
378 static struct palmas_pinctrl_config palmas_pincfg[] = {
379 PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
380 PALMAS_PINMUX("vac", "vac", NULL, NULL),
381 PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
382 PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL),
383 PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
384 PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
385 PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
386 PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
387 PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
388 PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
391 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
392 .pincfg = palmas_pincfg,
393 .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
394 .dvfs1_enable = true,
395 .dvfs2_enable = false,
398 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
399 .connection_name = "palmas-extcon",
400 .enable_vbus_detection = true,
401 .enable_id_pin_detection = true,
404 static struct palmas_platform_data palmas_pdata = {
405 .gpio_base = PALMAS_TEGRA_GPIO_BASE,
406 .irq_base = PALMAS_TEGRA_IRQ_BASE,
407 .pmic_pdata = &pmic_platform,
408 .pinctrl_pdata = &palmas_pinctrl_pdata,
409 .extcon_pdata = &palmas_extcon_pdata,
412 static struct i2c_board_info palma_device[] = {
414 I2C_BOARD_INFO("tps65913", 0x58),
415 .irq = INT_EXTERNAL_PMU,
416 .platform_data = &palmas_pdata,
420 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
421 REGULATOR_SUPPLY("dvdd_lcd", NULL),
424 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
425 REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
428 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
429 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
430 REGULATOR_SUPPLY("dvdd", "spi0.0"),
433 /* ENABLE 5v0 for HDMI */
434 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
435 REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
438 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
439 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
442 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
443 REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
444 REGULATOR_SUPPLY("vi2c", "2-0030"),
445 REGULATOR_SUPPLY("vif", "2-0036"),
446 REGULATOR_SUPPLY("dovdd", "2-0010"),
447 REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
448 REGULATOR_SUPPLY("vddio_cam", "vi"),
449 REGULATOR_SUPPLY("pwrdet_cam", NULL),
452 /* Macro for defining fixed regulator sub device data */
453 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
454 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \
455 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \
456 static struct regulator_init_data ri_data_##_var = \
458 .supply_regulator = _in_supply, \
459 .num_consumer_supplies = \
460 ARRAY_SIZE(fixed_reg_##_name##_supply), \
461 .consumer_supplies = fixed_reg_##_name##_supply, \
463 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
464 REGULATOR_MODE_STANDBY), \
465 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
466 REGULATOR_CHANGE_STATUS | \
467 REGULATOR_CHANGE_VOLTAGE), \
468 .always_on = _always_on, \
469 .boot_on = _boot_on, \
472 static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
474 .supply_name = FIXED_SUPPLY(_name), \
475 .microvolts = _millivolts * 1000, \
477 .gpio_is_open_drain = _open_drain, \
478 .enable_high = _active_high, \
479 .enabled_at_boot = _boot_state, \
480 .init_data = &ri_data_##_var, \
482 static struct platform_device fixed_reg_##_var##_dev = { \
483 .name = "reg-fixed-voltage", \
486 .platform_data = &fixed_reg_##_var##_pdata, \
491 * Creating the fixed regulator device table
494 FIXED_REG(1, dvdd_lcd_1v8, dvdd_lcd_1v8,
495 palmas_rails(smps8), 0, 1,
496 PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4, false, true, 1, 1800);
498 FIXED_REG(2, vdd_lcd_bl_en, vdd_lcd_bl_en,
500 TEGRA_GPIO_PH2, false, true, 1, 3700);
502 FIXED_REG(3, dvdd_ts, dvdd_ts,
503 palmas_rails(smps8), 0, 0,
504 TEGRA_GPIO_PH4, false, false, 1, 1800);
506 FIXED_REG(4, vdd_hdmi_5v0, vdd_hdmi_5v0,
507 palmas_rails(smps10_out1), 0, 0,
508 TEGRA_GPIO_PK6, true, true, 0, 5000);
510 FIXED_REG(5, vddio_sd_slot, vddio_sd_slot,
511 palmas_rails(smps9), 0, 0,
512 TEGRA_GPIO_PK1, false, true, 0, 2900);
514 FIXED_REG(6, vd_cam_1v8, vd_cam_1v8,
515 palmas_rails(smps8), 0, 0,
516 PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 1800);
518 #define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
520 /* Gpio switch regulator platform data for Macallan E1545 */
521 static struct platform_device *fixed_reg_devs[] = {
522 ADD_FIXED_REG(dvdd_lcd_1v8),
523 ADD_FIXED_REG(vdd_lcd_bl_en),
524 ADD_FIXED_REG(dvdd_ts),
525 ADD_FIXED_REG(vdd_hdmi_5v0),
526 ADD_FIXED_REG(vddio_sd_slot),
527 ADD_FIXED_REG(vd_cam_1v8),
531 int __init macallan_palmas_regulator_init(void)
533 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
536 struct board_info board_info;
538 /* TPS65913: Normal state of INT request line is LOW.
539 * configure the power management controller to trigger PMU
540 * interrupts when HIGH.
542 pmc_ctrl = readl(pmc + PMC_CTRL);
543 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
545 /* Tracking configuration */
546 reg_init_data_ldo8.config_flags =
547 PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
548 PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
550 tegra_get_board_info(&board_info);
551 if (board_info.board_id == BOARD_E1569) {
552 reg_idata_ldo5.consumer_supplies = palmas_ldo5_e1569_supply;
553 reg_idata_ldo5.num_consumer_supplies =
554 ARRAY_SIZE(palmas_ldo5_e1569_supply);
555 reg_idata_ldo7.consumer_supplies = palmas_ldo7_e1569_supply;
556 reg_idata_ldo7.num_consumer_supplies =
557 ARRAY_SIZE(palmas_ldo7_e1569_supply);
560 for (i = 0; i < PALMAS_NUM_REGS ; i++) {
561 pmic_platform.reg_data[i] = macallan_reg_data[i];
562 pmic_platform.reg_init[i] = macallan_reg_init[i];
565 i2c_register_board_info(4, palma_device,
566 ARRAY_SIZE(palma_device));
571 static int ac_online(void)
576 static struct resource macallan_pda_resources[] = {
582 static struct pda_power_pdata macallan_pda_data = {
583 .is_ac_online = ac_online,
586 static struct platform_device macallan_pda_power_device = {
589 .resource = macallan_pda_resources,
590 .num_resources = ARRAY_SIZE(macallan_pda_resources),
592 .platform_data = &macallan_pda_data,
596 static struct tegra_suspend_platform_data macallan_suspend_data = {
598 .cpu_off_timer = 300,
599 .suspend_mode = TEGRA_SUSPEND_LP0,
600 .core_timer = 0x157e,
601 .core_off_timer = 2000,
602 .corereq_high = true,
603 .sysclkreq_high = true,
604 .cpu_lp2_min_residency = 1000,
605 .min_residency_crail = 20000,
606 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
607 .lp1_lowvolt_support = false,
611 .lp1_core_volt_low_cold = 0,
612 .lp1_core_volt_low = 0,
613 .lp1_core_volt_high = 0,
616 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
617 /* board parameters for cpu dfll */
618 static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = {
619 .sample_rate = 12500,
621 .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
626 .droop_cut_value = 0xF,
627 .droop_restore_ramp = 0x0,
628 .scale_out_ramp = 0x0,
632 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
633 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
634 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
635 static inline void fill_reg_map(void)
638 for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
639 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
640 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
644 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
645 static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = {
646 .dfll_clk_name = "dfll_cpu",
647 .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
653 .vdd_map = pmu_cpu_vdd_map,
654 .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
655 .pmu_undershoot_gb = 100,
657 .cfg_param = &macallan_cl_dvfs_param,
660 static int __init macallan_cl_dvfs_init(void)
663 if (tegra_revision < TEGRA_REVISION_A02)
664 macallan_cl_dvfs_data.flags =
665 TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
666 tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data;
667 platform_device_register(&tegra_cl_dvfs_device);
673 static int __init macallan_fixed_regulator_init(void)
675 if (!of_machine_is_compatible("nvidia,macallan"))
678 return platform_add_devices(fixed_reg_devs,
679 ARRAY_SIZE(fixed_reg_devs));
681 subsys_initcall_sync(macallan_fixed_regulator_init);
683 int __init macallan_regulator_init(void)
685 struct board_info board_info;
686 tegra_get_board_info(&board_info);
688 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
689 macallan_cl_dvfs_init();
691 macallan_palmas_regulator_init();
693 if (board_info.board_id == BOARD_E1569) {
694 if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY) {
695 /* Disable charger when adapter is power source. */
696 macallan_bq2419x_pdata.bcharger_pdata = NULL;
698 /* Only register fuel gauge when using battery. */
699 i2c_register_board_info(0, macallan_max17048_boardinfo,
703 /* forced make null to prevent charging for E1545. */
704 macallan_bq2419x_pdata.bcharger_pdata = NULL;
707 bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
708 i2c_register_board_info(0, bq2419x_boardinfo,
709 ARRAY_SIZE(bq2419x_boardinfo));
711 platform_device_register(&psy_extcon_device);
712 platform_device_register(&macallan_pda_power_device);
717 int __init macallan_suspend_init(void)
719 tegra_init_suspend(&macallan_suspend_data);
723 int __init macallan_edp_init(void)
725 unsigned int regulator_mA;
727 regulator_mA = get_maximum_cpu_current_supported();
729 regulator_mA = 15000;
731 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
732 tegra_init_cpu_edp_limits(regulator_mA);
734 regulator_mA = get_maximum_core_current_supported();
738 pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
739 tegra_init_core_edp_limits(regulator_mA);
744 static struct pid_thermal_gov_params soctherm_cpu_pid_params = {
745 .max_err_temp = 9000,
746 .max_err_gain = 1000,
751 .up_compensation = 20,
752 .down_compensation = 20,
755 static struct thermal_zone_params macallan_soctherm_therm_cpu_tzp = {
756 .governor_name = "pid_thermal_gov",
757 .governor_params = &soctherm_cpu_pid_params,
760 static struct tegra_tsensor_pmu_data tpdata_palmas = {
763 .controller_type = 0,
764 .pmu_i2c_addr = 0x58,
765 .i2c_controller_id = 4,
766 .poweroff_reg_addr = 0xa0,
767 .poweroff_reg_data = 0x0,
770 static struct soctherm_platform_data macallan_soctherm_data = {
771 .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
772 .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
776 .passive_delay = 1000,
777 .hotspot_offset = 6000,
781 .cdev_type = "tegra-balanced",
783 .trip_type = THERMAL_TRIP_PASSIVE,
784 .upper = THERMAL_NO_LIMIT,
785 .lower = THERMAL_NO_LIMIT,
788 .cdev_type = "tegra-heavy",
790 .trip_type = THERMAL_TRIP_HOT,
791 .upper = THERMAL_NO_LIMIT,
792 .lower = THERMAL_NO_LIMIT,
795 .cdev_type = "tegra-shutdown",
797 .trip_type = THERMAL_TRIP_CRITICAL,
798 .upper = THERMAL_NO_LIMIT,
799 .lower = THERMAL_NO_LIMIT,
802 .tzp = &macallan_soctherm_therm_cpu_tzp,
806 .passive_delay = 1000,
807 .hotspot_offset = 6000,
811 .cdev_type = "tegra-balanced",
813 .trip_type = THERMAL_TRIP_PASSIVE,
814 .upper = THERMAL_NO_LIMIT,
815 .lower = THERMAL_NO_LIMIT,
818 .cdev_type = "tegra-heavy",
820 .trip_type = THERMAL_TRIP_HOT,
821 .upper = THERMAL_NO_LIMIT,
822 .lower = THERMAL_NO_LIMIT,
825 .cdev_type = "tegra-shutdown",
827 .trip_type = THERMAL_TRIP_CRITICAL,
828 .upper = THERMAL_NO_LIMIT,
829 .lower = THERMAL_NO_LIMIT,
832 .tzp = &macallan_soctherm_therm_cpu_tzp,
842 [THROTTLE_DEV_CPU] = {
846 [THROTTLE_DEV_GPU] = {
857 [THROTTLE_DEV_CPU] = {
861 [THROTTLE_DEV_GPU] = {
868 .tshut_pmu_trip_data = &tpdata_palmas,
871 int __init macallan_soctherm_init(void)
873 struct board_info board_info;
874 tegra_get_board_info(&board_info);
875 if (board_info.board_id == BOARD_E1545)
876 tegra_add_cdev_trips(
877 macallan_soctherm_data.therm[THERM_CPU].trips,
878 &macallan_soctherm_data.therm[THERM_CPU].num_trips);
879 tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
880 &macallan_soctherm_data.therm[THERM_CPU].num_trips,
881 6000); /* edp temperature margin */
882 tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
883 &macallan_soctherm_data.therm[THERM_CPU].num_trips);
885 return tegra11_soctherm_init(&macallan_soctherm_data);
888 static struct edp_manager macallan_sysedp_manager = {
893 void __init macallan_sysedp_init(void)
895 struct edp_governor *g;
898 if (!IS_ENABLED(CONFIG_EDP_FRAMEWORK))
901 if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY)
902 macallan_sysedp_manager.max = INT_MAX;
904 r = edp_register_manager(&macallan_sysedp_manager);
909 /* start with priority governor */
910 g = edp_get_governor("priority");
915 r = edp_set_governor(&macallan_sysedp_manager, g);
919 static unsigned int macallan_psydepl_states[] = {
920 18000, 17000, 16000, 15000, 14000, 13000, 12000, 11000,
921 9900, 9600, 9300, 9000, 8700, 8400, 8100, 7800,
922 7500, 7200, 6900, 6600, 6300, 6000, 5800, 5600,
923 5400, 5200, 5000, 4800, 4600, 4400, 4200, 4000,
924 3800, 3600, 3400, 3200, 3000, 2800, 2600, 2400,
925 2200, 2000, 1900, 1800, 1700, 1600, 1500, 1400,
926 1300, 1200, 1100, 1000, 900, 800, 700, 600,
927 500, 400, 300, 200, 100, 0
930 static struct psy_depletion_ibat_lut macallan_ibat_lut[] = {
937 static struct psy_depletion_rbat_lut macallan_rbat_lut[] = {
941 static struct psy_depletion_platform_data macallan_psydepl_pdata = {
942 .power_supply = "battery",
943 .states = macallan_psydepl_states,
944 .num_states = ARRAY_SIZE(macallan_psydepl_states),
950 .ibat_lut = macallan_ibat_lut,
951 .rbat_lut = macallan_rbat_lut
954 static struct platform_device macallan_psydepl_device = {
955 .name = "psy_depletion",
957 .dev = { .platform_data = &macallan_psydepl_pdata }
960 void __init macallan_sysedp_psydepl_init(void)
964 r = platform_device_register(&macallan_psydepl_device);
968 static struct tegra_sysedp_corecap macallan_sysedp_corecap[] = {
969 { 1000, { 1000, 240000, 204000}, { 1000, 240000, 204000 } },
970 { 2000, { 1000, 240000, 204000}, { 1000, 240000, 204000 } },
971 { 3000, { 1000, 240000, 204000}, { 1000, 240000, 204000 } },
972 { 4000, { 1000, 240000, 204000}, { 1000, 240000, 204000 } },
973 { 5000, { 1000, 240000, 204000}, { 1000, 240000, 312000 } },
974 { 6000, { 1679, 240000, 312000}, { 1679, 240000, 312000 } },
975 { 7000, { 1843, 240000, 624000}, { 1975, 324000, 408000 } },
976 { 8000, { 2843, 240000, 624000}, { 2306, 420000, 624000 } },
977 { 9000, { 3843, 240000, 624000}, { 2606, 420000, 792000 } },
978 { 10000, { 4565, 240000, 792000}, { 3398, 528000, 792000 } },
979 { 11000, { 5565, 240000, 792000}, { 4398, 528000, 792000 } },
980 { 12000, { 6565, 240000, 792000}, { 4277, 600000, 792000 } },
981 { 13000, { 7565, 240000, 792000}, { 5277, 600000, 792000 } },
982 { 14000, { 8565, 240000, 792000}, { 6277, 600000, 792000 } },
983 { 15000, { 9565, 240000, 792000}, { 7277, 600000, 792000 } },
984 { 16000, { 10565, 240000, 792000}, { 8277, 600000, 792000 } },
985 { 17000, { 11565, 240000, 792000}, { 9277, 600000, 792000 } },
986 { 18000, { 12565, 240000, 792000}, { 10277, 600000, 792000 } },
987 { 19000, { 13565, 240000, 792000}, { 11277, 600000, 792000 } },
988 { 20000, { 14565, 240000, 792000}, { 12277, 600000, 792000 } },
989 { 23000, { 14565, 600000, 792000}, { 14565, 600000, 792000 } }
992 static struct tegra_sysedp_platform_data macallan_sysedp_platdata = {
993 .corecap = macallan_sysedp_corecap,
994 .corecap_size = ARRAY_SIZE(macallan_sysedp_corecap),
996 .init_req_watts = 20000
999 static struct platform_device macallan_sysedp_device = {
1000 .name = "tegra_sysedp",
1002 .dev = { .platform_data = &macallan_sysedp_platdata }
1005 void __init macallan_sysedp_core_init(void)
1009 macallan_sysedp_platdata.cpufreq_lim = tegra_get_system_edp_entries(
1010 &macallan_sysedp_platdata.cpufreq_lim_size);
1011 if (!macallan_sysedp_platdata.cpufreq_lim) {
1016 r = platform_device_register(&macallan_sysedp_device);