2 * arch/arm/mach-tegra/board-macallan-power.c
4 * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/mfd/bq2419x.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/gpio.h>
32 #include <linux/interrupt.h>
33 #include <linux/regulator/userspace-consumer.h>
35 #include <asm/mach-types.h>
36 #include <linux/power/sbs-battery.h>
38 #include <mach/irqs.h>
39 #include <mach/hardware.h>
41 #include <mach/gpio-tegra.h>
43 #include "cpu-tegra.h"
45 #include "tegra-board-id.h"
46 #include "board-pmu-defines.h"
48 #include "gpio-names.h"
49 #include "board-common.h"
50 #include "board-macallan.h"
51 #include "tegra_cl_dvfs.h"
53 #include "tegra11_soctherm.h"
54 #include "tegra3_tsensor.h"
58 #define PMC_CTRL_INTR_LOW (1 << 17)
60 /* BQ2419X VBUS regulator */
61 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
62 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
65 static struct regulator_init_data bq2419x_init_data = {
67 .name = "bq2419x_vbus",
70 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
71 REGULATOR_MODE_STANDBY),
72 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
73 REGULATOR_CHANGE_STATUS |
74 REGULATOR_CHANGE_VOLTAGE),
76 .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
77 .consumer_supplies = bq2419x_vbus_supply,
80 static struct bq2419x_regulator_platform_data bq2419x_reg_pdata = {
81 .reg_init_data = &bq2419x_init_data,
82 .gpio_otg_iusb = TEGRA_GPIO_PI4,
83 .power_off_on_suspend = true,
86 struct bq2419x_platform_data macallan_bq2419x_pdata = {
87 .reg_pdata = &bq2419x_reg_pdata,
88 .disable_watchdog = true,
91 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
93 I2C_BOARD_INFO("bq2419x", 0x6b),
94 .platform_data = &macallan_bq2419x_pdata,
99 /************************ Macallan based regulator ****************/
100 static struct regulator_consumer_supply palmas_smps123_supply[] = {
101 REGULATOR_SUPPLY("vdd_cpu", NULL),
104 static struct regulator_consumer_supply palmas_smps45_supply[] = {
105 REGULATOR_SUPPLY("vdd_core", NULL),
108 static struct regulator_consumer_supply palmas_smps6_supply[] = {
109 REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
110 REGULATOR_SUPPLY("avdd_lcd", NULL),
111 REGULATOR_SUPPLY("avdd", "spi0.0"),
114 static struct regulator_consumer_supply palmas_smps7_supply[] = {
115 REGULATOR_SUPPLY("vddio_ddr", NULL),
118 static struct regulator_consumer_supply palmas_smps8_supply[] = {
119 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
120 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
121 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
122 REGULATOR_SUPPLY("avdd_osc", NULL),
123 REGULATOR_SUPPLY("vddio_sys", NULL),
124 REGULATOR_SUPPLY("vddio_bb", NULL),
125 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
126 REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
127 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
128 REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
129 REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
130 REGULATOR_SUPPLY("vddio_audio", NULL),
131 REGULATOR_SUPPLY("pwrdet_audio", NULL),
132 REGULATOR_SUPPLY("vddio_uart", NULL),
133 REGULATOR_SUPPLY("pwrdet_uart", NULL),
134 REGULATOR_SUPPLY("vddio_gmi", NULL),
135 REGULATOR_SUPPLY("vlogic", "0-0069"),
136 REGULATOR_SUPPLY("vid", "0-000d"),
137 REGULATOR_SUPPLY("vddio", "0-0078"),
140 static struct regulator_consumer_supply palmas_smps9_supply[] = {
141 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
144 static struct regulator_consumer_supply palmas_smps10_supply[] = {
147 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
148 REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
149 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
150 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
151 REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
152 REGULATOR_SUPPLY("avdd_pllm", NULL),
153 REGULATOR_SUPPLY("avdd_pllu", NULL),
154 REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
155 REGULATOR_SUPPLY("avdd_pllx", NULL),
156 REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
157 REGULATOR_SUPPLY("avdd_plle", NULL),
160 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
161 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
162 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
163 REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
164 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
165 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
168 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
169 REGULATOR_SUPPLY("vpp_fuse", NULL),
172 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
173 REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
174 REGULATOR_SUPPLY("dvdd", "2-0010"),
175 REGULATOR_SUPPLY("vdig", "2-0036"),
178 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
179 REGULATOR_SUPPLY("avdd_cam2", NULL),
180 REGULATOR_SUPPLY("avdd", "2-0010"),
183 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
184 REGULATOR_SUPPLY("vdd", "0-0069"),
185 REGULATOR_SUPPLY("vdd", "0-000d"),
186 REGULATOR_SUPPLY("vdd", "0-0078"),
189 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
190 REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
191 REGULATOR_SUPPLY("vdd_af_cam1", NULL),
192 REGULATOR_SUPPLY("avdd_cam1", NULL),
193 REGULATOR_SUPPLY("vana", "2-0036"),
194 REGULATOR_SUPPLY("vdd", "2-000e"),
197 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
198 REGULATOR_SUPPLY("vdd_rtc", NULL),
200 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
201 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
202 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
204 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
205 REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
208 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
209 REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
210 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
211 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
212 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
213 REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
217 static struct regulator_consumer_supply palmas_regen1_supply[] = {
220 static struct regulator_consumer_supply palmas_regen2_supply[] = {
223 PALMAS_PDATA_INIT(smps123, 900, 1300, NULL, 0, 0, 0, 0);
224 PALMAS_PDATA_INIT(smps45, 900, 1400, NULL, 0, 0, 0, 0);
225 PALMAS_PDATA_INIT(smps6, 3200, 3200, NULL, 0, 0, 1, NORMAL);
226 PALMAS_PDATA_INIT(smps7, 1350, 1350, NULL, 0, 0, 1, NORMAL);
227 PALMAS_PDATA_INIT(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL);
228 PALMAS_PDATA_INIT(smps9, 2900, 2900, NULL, 1, 0, 1, NORMAL);
229 PALMAS_PDATA_INIT(smps10, 5000, 5000, NULL, 0, 0, 0, 0);
230 PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps7), 1, 0, 1, 0);
231 PALMAS_PDATA_INIT(ldo2, 1200, 1200, palmas_rails(smps7), 0, 1, 1, 0);
232 PALMAS_PDATA_INIT(ldo3, 1800, 1800, NULL, 0, 0, 0, 0);
233 PALMAS_PDATA_INIT(ldo4, 1200, 1200, palmas_rails(smps8), 0, 0, 0, 0);
234 PALMAS_PDATA_INIT(ldo5, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0);
235 PALMAS_PDATA_INIT(ldo6, 2850, 2850, palmas_rails(smps9), 1, 1, 1, 0);
236 PALMAS_PDATA_INIT(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0);
237 PALMAS_PDATA_INIT(ldo8, 950, 950, NULL, 1, 1, 1, 0);
238 PALMAS_PDATA_INIT(ldo9, 1800, 2900, palmas_rails(smps9), 0, 0, 1, 0);
239 PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 0, 0, 1, 0);
240 PALMAS_PDATA_INIT(ldousb, 3300, 3300, NULL, 0, 0, 1, 0);
241 PALMAS_PDATA_INIT(regen1, 4200, 4200, NULL, 0, 0, 0, 0);
242 PALMAS_PDATA_INIT(regen2, 4200, 4200, palmas_rails(smps8), 0, 0, 0, 0);
244 #define PALMAS_REG_PDATA(_sname) (®_idata_##_sname)
245 static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = {
247 PALMAS_REG_PDATA(smps123),
249 PALMAS_REG_PDATA(smps45),
251 PALMAS_REG_PDATA(smps6),
252 PALMAS_REG_PDATA(smps7),
253 PALMAS_REG_PDATA(smps8),
254 PALMAS_REG_PDATA(smps9),
255 PALMAS_REG_PDATA(smps10),
256 PALMAS_REG_PDATA(ldo1),
257 PALMAS_REG_PDATA(ldo2),
258 PALMAS_REG_PDATA(ldo3),
259 PALMAS_REG_PDATA(ldo4),
260 PALMAS_REG_PDATA(ldo5),
261 PALMAS_REG_PDATA(ldo6),
262 PALMAS_REG_PDATA(ldo7),
263 PALMAS_REG_PDATA(ldo8),
264 PALMAS_REG_PDATA(ldo9),
265 PALMAS_REG_PDATA(ldoln),
266 PALMAS_REG_PDATA(ldousb),
267 PALMAS_REG_PDATA(regen1),
268 PALMAS_REG_PDATA(regen2),
274 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep, \
276 static struct palmas_reg_init reg_init_data_##_name = { \
277 .warm_reset = _warm_reset, \
278 .roof_floor = _roof_floor, \
279 .mode_sleep = _mode_sleep, \
284 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
285 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
286 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
287 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
288 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
289 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
290 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
291 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
292 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
293 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
294 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
295 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
296 PALMAS_REG_INIT(ldo3, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
297 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
298 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
299 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
300 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
301 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
302 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
303 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
304 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
306 #define PALMAS_REG_INIT_DATA(_sname) (®_init_data_##_sname)
307 static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = {
308 PALMAS_REG_INIT_DATA(smps12),
309 PALMAS_REG_INIT_DATA(smps123),
310 PALMAS_REG_INIT_DATA(smps3),
311 PALMAS_REG_INIT_DATA(smps45),
312 PALMAS_REG_INIT_DATA(smps457),
313 PALMAS_REG_INIT_DATA(smps6),
314 PALMAS_REG_INIT_DATA(smps7),
315 PALMAS_REG_INIT_DATA(smps8),
316 PALMAS_REG_INIT_DATA(smps9),
317 PALMAS_REG_INIT_DATA(smps10),
318 PALMAS_REG_INIT_DATA(ldo1),
319 PALMAS_REG_INIT_DATA(ldo2),
320 PALMAS_REG_INIT_DATA(ldo3),
321 PALMAS_REG_INIT_DATA(ldo4),
322 PALMAS_REG_INIT_DATA(ldo5),
323 PALMAS_REG_INIT_DATA(ldo6),
324 PALMAS_REG_INIT_DATA(ldo7),
325 PALMAS_REG_INIT_DATA(ldo8),
326 PALMAS_REG_INIT_DATA(ldo9),
327 PALMAS_REG_INIT_DATA(ldoln),
328 PALMAS_REG_INIT_DATA(ldousb),
331 static struct palmas_pmic_platform_data pmic_platform = {
332 .enable_ldo8_tracking = true,
333 .disabe_ldo8_tracking_suspend = true,
334 .disable_smps10_boost_suspend = true,
337 static struct palmas_pinctrl_config palmas_pincfg[] = {
338 PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
339 PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
340 PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
341 PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
342 PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
343 PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
344 PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
345 PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
346 PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
347 PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
350 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
351 .pincfg = palmas_pincfg,
352 .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
353 .dvfs1_enable = true,
354 .dvfs2_enable = false,
357 struct palmas_extcon_platform_data palmas_extcon_pdata = {
358 .connection_name = "palmas-extcon",
359 .enable_vbus_detection = true,
360 .enable_id_pin_detection = false,
363 static struct palmas_platform_data palmas_pdata = {
364 .gpio_base = PALMAS_TEGRA_GPIO_BASE,
365 .irq_base = PALMAS_TEGRA_IRQ_BASE,
366 .pmic_pdata = &pmic_platform,
367 .use_power_off = true,
368 .pinctrl_pdata = &palmas_pinctrl_pdata,
369 .extcon_pdata = &palmas_extcon_pdata,
372 static struct i2c_board_info palma_device[] = {
374 I2C_BOARD_INFO("tps65913", 0x58),
375 .irq = INT_EXTERNAL_PMU,
376 .platform_data = &palmas_pdata,
380 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
381 REGULATOR_SUPPLY("dvdd_lcd", NULL),
384 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
385 REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
388 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
389 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
390 REGULATOR_SUPPLY("dvdd", "spi0.0"),
393 /* ENABLE 5v0 for HDMI */
394 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
395 REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
398 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
399 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
402 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
403 REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
404 REGULATOR_SUPPLY("vi2c", "2-0030"),
405 REGULATOR_SUPPLY("vif", "2-0036"),
406 REGULATOR_SUPPLY("dovdd", "2-0010"),
407 REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
410 /* Macro for defining fixed regulator sub device data */
411 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
412 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \
413 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \
414 static struct regulator_init_data ri_data_##_var = \
416 .supply_regulator = _in_supply, \
417 .num_consumer_supplies = \
418 ARRAY_SIZE(fixed_reg_##_name##_supply), \
419 .consumer_supplies = fixed_reg_##_name##_supply, \
421 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
422 REGULATOR_MODE_STANDBY), \
423 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
424 REGULATOR_CHANGE_STATUS | \
425 REGULATOR_CHANGE_VOLTAGE), \
426 .always_on = _always_on, \
427 .boot_on = _boot_on, \
430 static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
432 .supply_name = FIXED_SUPPLY(_name), \
433 .microvolts = _millivolts * 1000, \
435 .gpio_is_open_drain = _open_drain, \
436 .enable_high = _active_high, \
437 .enabled_at_boot = _boot_state, \
438 .init_data = &ri_data_##_var, \
440 static struct platform_device fixed_reg_##_var##_dev = { \
441 .name = "reg-fixed-voltage", \
444 .platform_data = &fixed_reg_##_var##_pdata, \
449 * Creating the fixed regulator device table
452 FIXED_REG(1, dvdd_lcd_1v8, dvdd_lcd_1v8,
453 palmas_rails(smps8), 0, 1,
454 PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4, false, true, 1, 1800);
456 FIXED_REG(2, vdd_lcd_bl_en, vdd_lcd_bl_en,
458 TEGRA_GPIO_PH2, false, true, 1, 3700);
460 FIXED_REG(3, dvdd_ts, dvdd_ts,
461 palmas_rails(smps8), 0, 0,
462 TEGRA_GPIO_PH4, false, false, 1, 1800);
464 FIXED_REG(4, vdd_hdmi_5v0, vdd_hdmi_5v0,
465 palmas_rails(smps10), 0, 0,
466 TEGRA_GPIO_PK6, false, true, 0, 5000);
468 FIXED_REG(5, vddio_sd_slot, vddio_sd_slot,
469 palmas_rails(smps9), 0, 0,
470 TEGRA_GPIO_PK1, false, true, 0, 2900);
472 FIXED_REG(6, vd_cam_1v8, vd_cam_1v8,
473 palmas_rails(smps8), 0, 0,
474 PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 1800);
476 #define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
478 /* Gpio switch regulator platform data for Macallan E1545 */
479 static struct platform_device *fixed_reg_devs[] = {
480 ADD_FIXED_REG(dvdd_lcd_1v8),
481 ADD_FIXED_REG(vdd_lcd_bl_en),
482 ADD_FIXED_REG(dvdd_ts),
483 ADD_FIXED_REG(vdd_hdmi_5v0),
484 ADD_FIXED_REG(vddio_sd_slot),
485 ADD_FIXED_REG(vd_cam_1v8),
489 int __init macallan_palmas_regulator_init(void)
491 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
495 /* TPS65913: Normal state of INT request line is LOW.
496 * configure the power management controller to trigger PMU
497 * interrupts when HIGH.
499 pmc_ctrl = readl(pmc + PMC_CTRL);
500 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
501 for (i = 0; i < PALMAS_NUM_REGS ; i++) {
502 pmic_platform.reg_data[i] = macallan_reg_data[i];
503 pmic_platform.reg_init[i] = macallan_reg_init[i];
506 i2c_register_board_info(4, palma_device,
507 ARRAY_SIZE(palma_device));
508 i2c_register_board_info(0, bq2419x_boardinfo,
509 ARRAY_SIZE(bq2419x_boardinfo));
514 static int ac_online(void)
519 static struct resource macallan_pda_resources[] = {
525 static struct pda_power_pdata macallan_pda_data = {
526 .is_ac_online = ac_online,
529 static struct platform_device macallan_pda_power_device = {
532 .resource = macallan_pda_resources,
533 .num_resources = ARRAY_SIZE(macallan_pda_resources),
535 .platform_data = &macallan_pda_data,
539 static struct tegra_suspend_platform_data macallan_suspend_data = {
541 .cpu_off_timer = 300,
542 .suspend_mode = TEGRA_SUSPEND_LP0,
543 .core_timer = 0x157e,
544 .core_off_timer = 2000,
545 .corereq_high = true,
546 .sysclkreq_high = true,
547 .cpu_lp2_min_residency = 1000,
548 .min_residency_crail = 20000,
549 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
550 .lp1_lowvolt_support = false,
554 .lp1_core_volt_low = 0,
555 .lp1_core_volt_high = 0,
558 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
559 /* board parameters for cpu dfll */
560 static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = {
561 .sample_rate = 12500,
563 .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
568 .droop_cut_value = 0xF,
569 .droop_restore_ramp = 0x0,
570 .scale_out_ramp = 0x0,
574 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
575 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
576 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
577 static inline void fill_reg_map(void)
580 for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
581 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
582 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
586 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
587 static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = {
588 .dfll_clk_name = "dfll_cpu",
589 .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
595 .vdd_map = pmu_cpu_vdd_map,
596 .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
598 .cfg_param = &macallan_cl_dvfs_param,
601 static int __init macallan_cl_dvfs_init(void)
604 if (tegra_revision < TEGRA_REVISION_A02)
605 macallan_cl_dvfs_data.out_quiet_then_disable = true;
606 tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data;
607 platform_device_register(&tegra_cl_dvfs_device);
613 static int __init macallan_fixed_regulator_init(void)
615 if (!machine_is_macallan())
618 return platform_add_devices(fixed_reg_devs,
619 ARRAY_SIZE(fixed_reg_devs));
621 subsys_initcall_sync(macallan_fixed_regulator_init);
623 int __init macallan_regulator_init(void)
626 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
627 macallan_cl_dvfs_init();
629 macallan_palmas_regulator_init();
631 platform_device_register(&macallan_pda_power_device);
636 int __init macallan_suspend_init(void)
638 tegra_init_suspend(&macallan_suspend_data);
642 int __init macallan_edp_init(void)
644 unsigned int regulator_mA;
646 regulator_mA = get_maximum_cpu_current_supported();
648 regulator_mA = 15000;
650 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
651 tegra_init_cpu_edp_limits(regulator_mA);
653 regulator_mA = get_maximum_core_current_supported();
657 pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
658 tegra_init_core_edp_limits(regulator_mA);
663 static struct thermal_zone_params macallan_soctherm_therm_cpu_tzp = {
664 .governor_name = "pid_thermal_gov",
667 static struct tegra_tsensor_pmu_data tpdata_palmas = {
670 .controller_type = 0,
671 .pmu_i2c_addr = 0x58,
672 .i2c_controller_id = 4,
673 .poweroff_reg_addr = 0xa0,
674 .poweroff_reg_data = 0x0,
677 static struct soctherm_platform_data macallan_soctherm_data = {
681 .passive_delay = 1000,
682 .hotspot_offset = 6000,
686 .cdev_type = "tegra-balanced",
688 .trip_type = THERMAL_TRIP_PASSIVE,
689 .upper = THERMAL_NO_LIMIT,
690 .lower = THERMAL_NO_LIMIT,
693 .cdev_type = "tegra-heavy",
695 .trip_type = THERMAL_TRIP_HOT,
696 .upper = THERMAL_NO_LIMIT,
697 .lower = THERMAL_NO_LIMIT,
700 .cdev_type = "tegra-shutdown",
702 .trip_type = THERMAL_TRIP_CRITICAL,
703 .upper = THERMAL_NO_LIMIT,
704 .lower = THERMAL_NO_LIMIT,
707 .tzp = &macallan_soctherm_therm_cpu_tzp,
711 .hotspot_offset = 6000,
720 [THROTTLE_DEV_CPU] = {
726 .tshut_pmu_trip_data = &tpdata_palmas,
729 int __init macallan_soctherm_init(void)
731 struct board_info board_info;
732 tegra_get_board_info(&board_info);
733 if (board_info.board_id == BOARD_E1545)
734 tegra_add_cdev_trips(
735 macallan_soctherm_data.therm[THERM_CPU].trips,
736 &macallan_soctherm_data.therm[THERM_CPU].num_trips);
737 tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
738 &macallan_soctherm_data.therm[THERM_CPU].num_trips,
740 tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
741 &macallan_soctherm_data.therm[THERM_CPU].num_trips);
742 tegra_add_vc_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
743 &macallan_soctherm_data.therm[THERM_CPU].num_trips);
746 return tegra11_soctherm_init(&macallan_soctherm_data);