arm: tegra: macallan: create board file
[linux-3.10.git] / arch / arm / mach-tegra / board-macallan-power.c
1 /*
2  * arch/arm/mach-tegra/board-macallan-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/gpio.h>
30 #include <linux/interrupt.h>
31 #include <linux/regulator/userspace-consumer.h>
32
33 #include <asm/mach-types.h>
34 #include <linux/power/sbs-battery.h>
35
36 #include <mach/irqs.h>
37 #include <mach/hardware.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-macallan.h"
48 #include "tegra_cl_dvfs.h"
49 #include "devices.h"
50 #include "tegra11_soctherm.h"
51 #include "tegra3_tsensor.h"
52 #include "iomap.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56
57 /************************ Macallan based regulator ****************/
58 static struct regulator_consumer_supply palmas_smps123_supply[] = {
59         REGULATOR_SUPPLY("vdd_cpu", NULL),
60 };
61
62 static struct regulator_consumer_supply palmas_smps45_supply[] = {
63         REGULATOR_SUPPLY("vdd_core", NULL),
64 };
65
66 static struct regulator_consumer_supply palmas_smps6_supply[] = {
67         REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
68         REGULATOR_SUPPLY("avdd_lcd", NULL),
69         REGULATOR_SUPPLY("avdd", "spi0.0"),
70 };
71
72 static struct regulator_consumer_supply palmas_smps7_supply[] = {
73         REGULATOR_SUPPLY("vddio_ddr", NULL),
74 };
75
76 static struct regulator_consumer_supply palmas_smps8_supply[] = {
77         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
78         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
79         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
80         REGULATOR_SUPPLY("avdd_osc", NULL),
81         REGULATOR_SUPPLY("vddio_sys", NULL),
82         REGULATOR_SUPPLY("vddio_bb", NULL),
83         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
84         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
85         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
86         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
87         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
88         REGULATOR_SUPPLY("vddio_audio", NULL),
89         REGULATOR_SUPPLY("pwrdet_audio", NULL),
90         REGULATOR_SUPPLY("vddio_uart", NULL),
91         REGULATOR_SUPPLY("pwrdet_uart", NULL),
92         REGULATOR_SUPPLY("vddio_gmi", NULL),
93 };
94
95 static struct regulator_consumer_supply palmas_smps9_supply[] = {
96         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
97 };
98
99 static struct regulator_consumer_supply palmas_smps10_supply[] = {
100 };
101
102 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
103         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
104         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
105         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
106         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
107         REGULATOR_SUPPLY("avdd_pllm", NULL),
108         REGULATOR_SUPPLY("avdd_pllu", NULL),
109         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
110         REGULATOR_SUPPLY("avdd_pllx", NULL),
111         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
112         REGULATOR_SUPPLY("avdd_plle", NULL),
113 };
114
115 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
116         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
117         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
118         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
119         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
120         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
121 };
122
123 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
124         REGULATOR_SUPPLY("vpp_fuse", NULL),
125 };
126
127 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
128 };
129
130 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
131 };
132
133 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
134 };
135
136 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
137 };
138 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
139         REGULATOR_SUPPLY("vdd_rtc", NULL),
140 };
141 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
142         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
143         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
144 };
145 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
146         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
147 };
148
149 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
150         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
151         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
152         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
153         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
154         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
155
156 };
157
158 static struct regulator_consumer_supply palmas_regen1_supply[] = {
159 };
160
161 static struct regulator_consumer_supply palmas_regen2_supply[] = {
162 };
163
164 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
165         _boot_on, _apply_uv)                                            \
166         static struct regulator_init_data reg_idata_##_name = {         \
167                 .constraints = {                                        \
168                         .name = palmas_rails(_name),                    \
169                         .min_uV = (_minmv)*1000,                        \
170                         .max_uV = (_maxmv)*1000,                        \
171                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
172                                         REGULATOR_MODE_STANDBY),        \
173                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
174                                         REGULATOR_CHANGE_STATUS |       \
175                                         REGULATOR_CHANGE_VOLTAGE),      \
176                         .always_on = _always_on,                        \
177                         .boot_on = _boot_on,                            \
178                         .apply_uV = _apply_uv,                          \
179                 },                                                      \
180                 .num_consumer_supplies =                                \
181                         ARRAY_SIZE(palmas_##_name##_supply),            \
182                 .consumer_supplies = palmas_##_name##_supply,           \
183                 .supply_regulator = _supply_reg,                        \
184         }
185
186 PALMAS_PDATA_INIT(smps123, 900,  1300, NULL, 0, 0, 0);
187 PALMAS_PDATA_INIT(smps45, 900,  1400, NULL, 0, 0, 0);
188 PALMAS_PDATA_INIT(smps6, 2800,  3000, NULL, 0, 0, 0);
189 PALMAS_PDATA_INIT(smps7, 1350,  1350, NULL, 0, 0, 1);
190 PALMAS_PDATA_INIT(smps8, 1800,  1800, NULL, 1, 1, 1);
191 PALMAS_PDATA_INIT(smps9, 2900,  2900, NULL, 1, 0, 1);
192 PALMAS_PDATA_INIT(smps10, 5000,  5000, NULL, 0, 0, 0);
193 PALMAS_PDATA_INIT(ldo1, 1050,  1050, palmas_rails(smps7), 1, 0, 1);
194 PALMAS_PDATA_INIT(ldo2, 1200,  1200, palmas_rails(smps7), 0, 1, 1);
195 PALMAS_PDATA_INIT(ldo3, 1800,  1800, NULL, 0, 0, 0);
196 PALMAS_PDATA_INIT(ldo4, 1200,  1200, palmas_rails(smps8), 0, 0, 0);
197 PALMAS_PDATA_INIT(ldo5, 2700,  2700, palmas_rails(smps9), 0, 0, 1);
198 PALMAS_PDATA_INIT(ldo6, 2850,  2850, palmas_rails(smps9), 1, 1, 1);
199 PALMAS_PDATA_INIT(ldo7, 2700,  2700, palmas_rails(smps9), 0, 0, 1);
200 PALMAS_PDATA_INIT(ldo8, 1100,  1100, NULL, 1, 1, 1);
201 PALMAS_PDATA_INIT(ldo9, 1800,  2900, palmas_rails(smps9), 0, 0, 1);
202 PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 0, 0, 1);
203 PALMAS_PDATA_INIT(ldousb, 3300,  3300, NULL, 0, 0, 1);
204 PALMAS_PDATA_INIT(regen1, 4200,  4200, NULL, 0, 0, 0);
205 PALMAS_PDATA_INIT(regen2, 4200,  4200, palmas_rails(smps8), 0, 0, 0);
206
207 #define PALMAS_REG_PDATA(_sname) (&reg_idata_##_sname)
208 static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = {
209         NULL,
210         PALMAS_REG_PDATA(smps123),
211         NULL,
212         PALMAS_REG_PDATA(smps45),
213         NULL,
214         PALMAS_REG_PDATA(smps6),
215         PALMAS_REG_PDATA(smps7),
216         PALMAS_REG_PDATA(smps8),
217         PALMAS_REG_PDATA(smps9),
218         PALMAS_REG_PDATA(smps10),
219         PALMAS_REG_PDATA(ldo1),
220         PALMAS_REG_PDATA(ldo2),
221         PALMAS_REG_PDATA(ldo3),
222         PALMAS_REG_PDATA(ldo4),
223         PALMAS_REG_PDATA(ldo5),
224         PALMAS_REG_PDATA(ldo6),
225         PALMAS_REG_PDATA(ldo7),
226         PALMAS_REG_PDATA(ldo8),
227         PALMAS_REG_PDATA(ldo9),
228         PALMAS_REG_PDATA(ldoln),
229         PALMAS_REG_PDATA(ldousb),
230         PALMAS_REG_PDATA(regen1),
231         PALMAS_REG_PDATA(regen2),
232         NULL,
233         NULL,
234         NULL,
235 };
236
237 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
238                 _tstep, _vsel)                                          \
239         static struct palmas_reg_init reg_init_data_##_name = {         \
240                 .warm_reset = _warm_reset,                              \
241                 .roof_floor =   _roof_floor,                            \
242                 .mode_sleep = _mode_sleep,              \
243                 .tstep = _tstep,                        \
244                 .vsel = _vsel,          \
245         }
246
247 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
248 PALMAS_REG_INIT(smps123, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
249 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
250 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
251 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
252 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
253 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
254 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
255 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
256 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
257 PALMAS_REG_INIT(ldo1, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
258 PALMAS_REG_INIT(ldo2, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
259 PALMAS_REG_INIT(ldo3, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
260 PALMAS_REG_INIT(ldo4, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
261 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
262 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
263 PALMAS_REG_INIT(ldo7, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
264 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
265 PALMAS_REG_INIT(ldo9, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
266 PALMAS_REG_INIT(ldoln, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
267 PALMAS_REG_INIT(ldousb, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
268
269 #define PALMAS_REG_INIT_DATA(_sname) (&reg_init_data_##_sname)
270 static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = {
271         PALMAS_REG_INIT_DATA(smps12),
272         PALMAS_REG_INIT_DATA(smps123),
273         PALMAS_REG_INIT_DATA(smps3),
274         PALMAS_REG_INIT_DATA(smps45),
275         PALMAS_REG_INIT_DATA(smps457),
276         PALMAS_REG_INIT_DATA(smps6),
277         PALMAS_REG_INIT_DATA(smps7),
278         PALMAS_REG_INIT_DATA(smps8),
279         PALMAS_REG_INIT_DATA(smps9),
280         PALMAS_REG_INIT_DATA(smps10),
281         PALMAS_REG_INIT_DATA(ldo1),
282         PALMAS_REG_INIT_DATA(ldo2),
283         PALMAS_REG_INIT_DATA(ldo3),
284         PALMAS_REG_INIT_DATA(ldo4),
285         PALMAS_REG_INIT_DATA(ldo5),
286         PALMAS_REG_INIT_DATA(ldo6),
287         PALMAS_REG_INIT_DATA(ldo7),
288         PALMAS_REG_INIT_DATA(ldo8),
289         PALMAS_REG_INIT_DATA(ldo9),
290         PALMAS_REG_INIT_DATA(ldoln),
291         PALMAS_REG_INIT_DATA(ldousb),
292 };
293
294 static struct palmas_pmic_platform_data pmic_platform = {
295         .enable_ldo8_tracking = true,
296         .disabe_ldo8_tracking_suspend = true,
297         .disable_smps10_boost_suspend = true,
298 };
299
300 static struct palmas_platform_data palmas_pdata = {
301         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
302         .irq_base = PALMAS_TEGRA_IRQ_BASE,
303         .pmic_pdata = &pmic_platform,
304         .mux_from_pdata = true,
305         .pad1 = 0,
306         .pad2 = 0,
307         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
308         .use_power_off = true,
309 };
310
311 static struct i2c_board_info palma_device[] = {
312         {
313                 I2C_BOARD_INFO("tps65913", 0x58),
314                 .irq            = INT_EXTERNAL_PMU,
315                 .platform_data  = &palmas_pdata,
316         },
317 };
318
319 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
320         REGULATOR_SUPPLY("dvdd_lcd", NULL),
321 };
322
323 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
324         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
325 };
326
327 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
328 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
329         REGULATOR_SUPPLY("dvdd", "spi0.0"),
330 };
331
332 /* ENABLE 5v0 for HDMI */
333 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
334         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
335 };
336
337 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
338         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
339 };
340
341
342 /* Macro for defining fixed regulator sub device data */
343 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
344 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
345         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
346         static struct regulator_init_data ri_data_##_var =              \
347         {                                                               \
348                 .supply_regulator = _in_supply,                         \
349                 .num_consumer_supplies =                                \
350                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
351                 .consumer_supplies = fixed_reg_##_name##_supply,        \
352                 .constraints = {                                        \
353                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
354                                         REGULATOR_MODE_STANDBY),        \
355                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
356                                         REGULATOR_CHANGE_STATUS |       \
357                                         REGULATOR_CHANGE_VOLTAGE),      \
358                         .always_on = _always_on,                        \
359                         .boot_on = _boot_on,                            \
360                 },                                                      \
361         };                                                              \
362         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
363         {                                                               \
364                 .supply_name = FIXED_SUPPLY(_name),                     \
365                 .microvolts = _millivolts * 1000,                       \
366                 .gpio = _gpio_nr,                                       \
367                 .gpio_is_open_drain = _open_drain,                      \
368                 .enable_high = _active_high,                            \
369                 .enabled_at_boot = _boot_state,                         \
370                 .init_data = &ri_data_##_var,                           \
371         };                                                              \
372         static struct platform_device fixed_reg_##_var##_dev = {        \
373                 .name = "reg-fixed-voltage",                            \
374                 .id = _id,                                              \
375                 .dev = {                                                \
376                         .platform_data = &fixed_reg_##_var##_pdata,     \
377                 },                                                      \
378         }
379
380 /*
381  * Creating the fixed regulator device table
382  */
383
384 FIXED_REG(1,    dvdd_lcd_1v8,   dvdd_lcd_1v8,
385         palmas_rails(smps8),    0,      1,
386         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
387
388 FIXED_REG(2,    vdd_lcd_bl_en,  vdd_lcd_bl_en,
389         NULL,   0,      1,
390         TEGRA_GPIO_PH2, false,  true,   1,      3700);
391
392 FIXED_REG(3,    dvdd_ts,        dvdd_ts,
393         palmas_rails(smps8),    0,      0,
394         TEGRA_GPIO_PH4, false,  false,  1,      1800);
395
396 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
397         palmas_rails(smps10),   0,      0,
398         TEGRA_GPIO_PK6, false,  true,   0,      5000);
399
400 FIXED_REG(5,    vddio_sd_slot,  vddio_sd_slot,
401         palmas_rails(smps9),    0,      0,
402         TEGRA_GPIO_PK1, false,  true,   0,      2900);
403
404 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
405
406 /* Gpio switch regulator platform data for Macallan E1545 */
407 static struct platform_device *fixed_reg_devs[] = {
408         ADD_FIXED_REG(dvdd_lcd_1v8),
409         ADD_FIXED_REG(vdd_lcd_bl_en),
410         ADD_FIXED_REG(dvdd_ts),
411         ADD_FIXED_REG(vdd_hdmi_5v0),
412         ADD_FIXED_REG(vddio_sd_slot),
413 };
414
415
416 int __init macallan_palmas_regulator_init(void)
417 {
418         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
419         u32 pmc_ctrl;
420         int i;
421
422         /* TPS65913: Normal state of INT request line is LOW.
423          * configure the power management controller to trigger PMU
424          * interrupts when HIGH.
425          */
426         pmc_ctrl = readl(pmc + PMC_CTRL);
427         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
428         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
429                 pmic_platform.reg_data[i] = macallan_reg_data[i];
430                 pmic_platform.reg_init[i] = macallan_reg_init[i];
431         }
432
433         i2c_register_board_info(4, palma_device,
434                         ARRAY_SIZE(palma_device));
435         return 0;
436 }
437
438 static int ac_online(void)
439 {
440         return 1;
441 }
442
443 static struct resource macallan_pda_resources[] = {
444         [0] = {
445                 .name   = "ac",
446         },
447 };
448
449 static struct pda_power_pdata macallan_pda_data = {
450         .is_ac_online   = ac_online,
451 };
452
453 static struct platform_device macallan_pda_power_device = {
454         .name           = "pda-power",
455         .id             = -1,
456         .resource       = macallan_pda_resources,
457         .num_resources  = ARRAY_SIZE(macallan_pda_resources),
458         .dev    = {
459                 .platform_data  = &macallan_pda_data,
460         },
461 };
462
463 static struct tegra_suspend_platform_data macallan_suspend_data = {
464         .cpu_timer      = 300,
465         .cpu_off_timer  = 300,
466         .suspend_mode   = TEGRA_SUSPEND_LP0,
467         .core_timer     = 0x157e,
468         .core_off_timer = 2000,
469         .corereq_high   = true,
470         .sysclkreq_high = true,
471         .min_residency_crail = 20000,
472 };
473 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
474 /* board parameters for cpu dfll */
475 static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = {
476         .sample_rate = 12500,
477
478         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
479         .cf = 10,
480         .ci = 0,
481         .cg = 2,
482
483         .droop_cut_value = 0xF,
484         .droop_restore_ramp = 0x0,
485         .scale_out_ramp = 0x0,
486 };
487 #endif
488
489 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
490 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
491 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
492 static inline void fill_reg_map(void)
493 {
494         int i;
495         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
496                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
497                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
498         }
499 }
500
501 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
502 static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = {
503         .dfll_clk_name = "dfll_cpu",
504         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
505         .u.pmu_i2c = {
506                 .fs_rate = 400000,
507                 .slave_addr = 0xb0,
508                 .reg = 0x23,
509         },
510         .vdd_map = pmu_cpu_vdd_map,
511         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
512
513         .cfg_param = &macallan_cl_dvfs_param,
514 };
515
516 static int __init macallan_cl_dvfs_init(void)
517 {
518         fill_reg_map();
519         if (tegra_revision < TEGRA_REVISION_A02)
520                 macallan_cl_dvfs_data.out_quiet_then_disable = true;
521         tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data;
522         platform_device_register(&tegra_cl_dvfs_device);
523
524         return 0;
525 }
526 #endif
527
528 static struct regulator_bulk_data macallan_gps_regulator_supply[] = {
529         [0] = {
530                 .supply = "vdd_gps_3v3",
531         },
532         [1] = {
533                 .supply = "vdd_gps_1v8",
534         },
535 };
536
537 static struct regulator_userspace_consumer_data macallan_gps_regulator_pdata = {
538         .num_supplies   = ARRAY_SIZE(macallan_gps_regulator_supply),
539         .supplies       = macallan_gps_regulator_supply,
540 };
541
542 static struct platform_device macallan_gps_regulator_device = {
543         .name   = "reg-userspace-consumer",
544         .id     = 2,
545         .dev    = {
546                         .platform_data = &macallan_gps_regulator_pdata,
547         },
548 };
549
550 static int __init macallan_fixed_regulator_init(void)
551 {
552         if (!machine_is_macallan())
553                 return 0;
554
555         return platform_add_devices(fixed_reg_devs,
556                         ARRAY_SIZE(fixed_reg_devs));
557 }
558 subsys_initcall_sync(macallan_fixed_regulator_init);
559
560 int __init macallan_regulator_init(void)
561 {
562
563 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
564         macallan_cl_dvfs_init();
565 #endif
566         macallan_palmas_regulator_init();
567
568         platform_device_register(&macallan_pda_power_device);
569         platform_device_register(&macallan_gps_regulator_device);
570
571         return 0;
572 }
573
574 int __init macallan_suspend_init(void)
575 {
576         tegra_init_suspend(&macallan_suspend_data);
577         return 0;
578 }
579
580 int __init macallan_edp_init(void)
581 {
582         unsigned int regulator_mA;
583
584         regulator_mA = get_maximum_cpu_current_supported();
585         if (!regulator_mA)
586                 regulator_mA = 15000;
587
588         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
589         tegra_init_cpu_edp_limits(regulator_mA);
590
591         regulator_mA = get_maximum_core_current_supported();
592         if (!regulator_mA)
593                 regulator_mA = 4000;
594
595         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
596         tegra_init_core_edp_limits(regulator_mA);
597
598         return 0;
599 }
600
601 static struct tegra_tsensor_pmu_data tpdata_palmas = {
602         .reset_tegra = 1,
603         .pmu_16bit_ops = 0,
604         .controller_type = 0,
605         .pmu_i2c_addr = 0x58,
606         .i2c_controller_id = 4,
607         .poweroff_reg_addr = 0xa0,
608         .poweroff_reg_data = 0x0,
609 };
610
611 static struct soctherm_platform_data macallan_soctherm_data = {
612         .therm = {
613                 [THERM_CPU] = {
614                         .zone_enable = true,
615                         .passive_delay = 1000,
616                         .num_trips = 3,
617                         .trips = {
618                                 {
619                                         .cdev_type = "tegra-balanced",
620                                         .trip_temp = 90000,
621                                         .trip_type = THERMAL_TRIP_PASSIVE,
622                                         .upper = THERMAL_NO_LIMIT,
623                                         .lower = THERMAL_NO_LIMIT,
624                                 },
625                                 {
626                                         .cdev_type = "tegra-heavy",
627                                         .trip_temp = 100000,
628                                         .trip_type = THERMAL_TRIP_HOT,
629                                         .upper = THERMAL_NO_LIMIT,
630                                         .lower = THERMAL_NO_LIMIT,
631                                 },
632                                 {
633                                         .cdev_type = "tegra-shutdown",
634                                         .trip_temp = 102000,
635                                         .trip_type = THERMAL_TRIP_CRITICAL,
636                                         .upper = THERMAL_NO_LIMIT,
637                                         .lower = THERMAL_NO_LIMIT,
638                                 },
639                         },
640                 },
641                 [THERM_GPU] = {
642                         .zone_enable = true,
643                 },
644                 [THERM_PLL] = {
645                         .zone_enable = true,
646                 },
647         },
648         .throttle = {
649                 [THROTTLE_HEAVY] = {
650                         .devs = {
651                                 [THROTTLE_DEV_CPU] = {
652                                         .enable = 1,
653                                 },
654                         },
655                 },
656         },
657         .tshut_pmu_trip_data = &tpdata_palmas,
658 };
659
660 int __init macallan_soctherm_init(void)
661 {
662         tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
663                         &macallan_soctherm_data.therm[THERM_CPU].num_trips,
664                         8000);
665         tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
666                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
667
668         return tegra11_soctherm_init(&macallan_soctherm_data);
669 }