ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-macallan-power.c
1 /*
2  * arch/arm/mach-tegra/board-macallan-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/power/bq2419x-charger.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/power/power_supply_extcon.h>
32 #include <linux/gpio.h>
33 #include <linux/interrupt.h>
34 #include <linux/regulator/userspace-consumer.h>
35 #include <linux/pid_thermal_gov.h>
36 #include <linux/tegra-soc.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/irqs.h>
42 #include <mach/edp.h>
43 #include <mach/gpio-tegra.h>
44
45 #include "cpu-tegra.h"
46 #include "pm.h"
47 #include "tegra-board-id.h"
48 #include "board-pmu-defines.h"
49 #include "board.h"
50 #include "gpio-names.h"
51 #include "board-common.h"
52 #include "board-macallan.h"
53 #include "tegra_cl_dvfs.h"
54 #include "devices.h"
55 #include "tegra11_soctherm.h"
56 #include "tegra3_tsensor.h"
57 #include "iomap.h"
58 #include "battery-ini-model-data.h"
59
60 #define PMC_CTRL                0x0
61 #define PMC_CTRL_INTR_LOW       (1 << 17)
62
63 /* BQ2419X VBUS regulator */
64 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
65         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
66         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
67 };
68
69 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
70         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
71 };
72
73 static struct bq2419x_vbus_platform_data macallan_bq2419x_vbus_pdata = {
74         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
75         .consumer_supplies = bq2419x_vbus_supply,
76 };
77
78 struct bq2419x_charger_platform_data macallan_bq2419x_charger_pdata = {
79         .max_charge_current_mA = 3000,
80         .charging_term_current_mA = 100,
81         .consumer_supplies = bq2419x_batt_supply,
82         .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
83         .wdt_timeout    = 40,
84         .rtc_alarm_time = 3600,
85         .chg_restart_time = 1800,
86 };
87
88 struct max17048_platform_data macallan_max17048_pdata = {
89         .model_data = &macallan_yoku_4100mA_max17048_battery,
90 };
91
92 static struct i2c_board_info __initdata macallan_max17048_boardinfo[] = {
93         {
94                 I2C_BOARD_INFO("max17048", 0x36),
95                 .platform_data  = &macallan_max17048_pdata,
96         },
97 };
98
99 struct bq2419x_platform_data macallan_bq2419x_pdata = {
100         .vbus_pdata = &macallan_bq2419x_vbus_pdata,
101         .bcharger_pdata = &macallan_bq2419x_charger_pdata,
102 };
103
104 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
105         {
106                 I2C_BOARD_INFO("bq2419x", 0x6b),
107                 .platform_data  = &macallan_bq2419x_pdata,
108         },
109 };
110
111 static struct power_supply_extcon_plat_data psy_extcon_pdata = {
112         .extcon_name = "tegra-udc",
113 };
114
115 static struct platform_device psy_extcon_device = {
116         .name = "power-supply-extcon",
117         .id = -1,
118         .dev = {
119                 .platform_data = &psy_extcon_pdata,
120         },
121 };
122
123 /************************ Macallan based regulator ****************/
124 static struct regulator_consumer_supply palmas_smps123_supply[] = {
125         REGULATOR_SUPPLY("vdd_cpu", NULL),
126 };
127
128 static struct regulator_consumer_supply palmas_smps45_supply[] = {
129         REGULATOR_SUPPLY("vdd_core", NULL),
130         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
131         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
132 };
133
134 static struct regulator_consumer_supply palmas_smps6_supply[] = {
135         REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
136         REGULATOR_SUPPLY("avdd_lcd", NULL),
137         REGULATOR_SUPPLY("avdd", "spi0.0"),
138 };
139
140 static struct regulator_consumer_supply palmas_smps7_supply[] = {
141         REGULATOR_SUPPLY("vddio_ddr", NULL),
142 };
143
144 static struct regulator_consumer_supply palmas_smps8_supply[] = {
145         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
146         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
147         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
148         REGULATOR_SUPPLY("avdd_osc", NULL),
149         REGULATOR_SUPPLY("vddio_sys", NULL),
150         REGULATOR_SUPPLY("vddio_bb", NULL),
151         REGULATOR_SUPPLY("pwrdet_bb", NULL),
152         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
153         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
154         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
155         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
156         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
157         REGULATOR_SUPPLY("vddio_audio", NULL),
158         REGULATOR_SUPPLY("pwrdet_audio", NULL),
159         REGULATOR_SUPPLY("vddio_uart", NULL),
160         REGULATOR_SUPPLY("pwrdet_uart", NULL),
161         REGULATOR_SUPPLY("vddio_gmi", NULL),
162         REGULATOR_SUPPLY("pwrdet_nand", NULL),
163         REGULATOR_SUPPLY("vlogic", "0-0069"),
164         REGULATOR_SUPPLY("vid", "0-000d"),
165         REGULATOR_SUPPLY("vddio", "0-0078"),
166         REGULATOR_SUPPLY("vdd", "0-004c"),
167 };
168
169 static struct regulator_consumer_supply palmas_smps9_supply[] = {
170         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
171         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
172         REGULATOR_SUPPLY("pwrdet_hv", NULL),
173 };
174
175 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
176 };
177
178 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
179         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
180         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
181         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
182         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
183         REGULATOR_SUPPLY("avdd_pllm", NULL),
184         REGULATOR_SUPPLY("avdd_pllu", NULL),
185         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
186         REGULATOR_SUPPLY("avdd_pllx", NULL),
187         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
188         REGULATOR_SUPPLY("avdd_plle", NULL),
189 };
190
191 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
192         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
193         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
194         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
195         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
196         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
197         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
198 };
199
200 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
201         REGULATOR_SUPPLY("vpp_fuse", NULL),
202 };
203
204 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
205         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
206         REGULATOR_SUPPLY("dvdd", "2-0010"),
207         REGULATOR_SUPPLY("vdig", "2-0036"),
208 };
209
210 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
211         REGULATOR_SUPPLY("avdd_cam2", NULL),
212         REGULATOR_SUPPLY("avdd", "2-0010"),
213 };
214
215 static struct regulator_consumer_supply palmas_ldo5_e1569_supply[] = {
216         REGULATOR_SUPPLY("avdd_cam2", NULL),
217         REGULATOR_SUPPLY("avdd", "2-0010"),
218         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
219         REGULATOR_SUPPLY("vdd", "2-000e"),
220 };
221
222 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
223         REGULATOR_SUPPLY("vdd", "0-0069"),
224         REGULATOR_SUPPLY("vdd", "0-000d"),
225         REGULATOR_SUPPLY("vdd", "0-0078"),
226 };
227
228 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
229         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
230         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
231         REGULATOR_SUPPLY("avdd_cam1", NULL),
232         REGULATOR_SUPPLY("vana", "2-0036"),
233         REGULATOR_SUPPLY("vdd", "2-000e"),
234 };
235
236 static struct regulator_consumer_supply palmas_ldo7_e1569_supply[] = {
237         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
238         REGULATOR_SUPPLY("avdd_cam1", NULL),
239         REGULATOR_SUPPLY("vana", "2-0036"),
240 };
241
242 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
243         REGULATOR_SUPPLY("vdd_rtc", NULL),
244 };
245 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
246         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
247         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
248 };
249 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
250         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
251 };
252
253 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
254         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
255         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
256         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
257         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
258         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
259
260 };
261
262 static struct regulator_consumer_supply palmas_regen1_supply[] = {
263 };
264
265 static struct regulator_consumer_supply palmas_regen2_supply[] = {
266 };
267
268 PALMAS_REGS_PDATA(smps123, 900,  1350, NULL, 0, 0, 0, 0,
269         0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
270 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, 0,
271         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
272 PALMAS_REGS_PDATA(smps6, 3200,  3200, NULL, 0, 0, 1, NORMAL,
273         0, 0, 0, 0, 0);
274 PALMAS_REGS_PDATA(smps7, 1350,  1350, NULL, 0, 0, 1, NORMAL,
275         0, 0, 0, 0, 0);
276 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
277         0, 0, 0, 0, 0);
278 PALMAS_REGS_PDATA(smps9, 2900,  2900, NULL, 1, 0, 1, NORMAL,
279         0, 0, 0, 0, 0);
280 PALMAS_REGS_PDATA(smps10_out1, 5000,  5000, NULL, 0, 0, 0, 0,
281         0, 0, 0, 0, 0);
282 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps7), 1, 0, 1, 0,
283         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
284 PALMAS_REGS_PDATA(ldo2, 1200,  1200, palmas_rails(smps7), 0, 1, 1, 0,
285         0, 0, 0, 0, 0);
286 PALMAS_REGS_PDATA(ldo3, 1800,  1800, NULL, 0, 0, 1, 0,
287         0, 0, 0, 0, 0);
288 PALMAS_REGS_PDATA(ldo4, 1200,  1200, palmas_rails(smps8), 0, 0, 1, 0,
289         0, 0, 0, 0, 0);
290 PALMAS_REGS_PDATA(ldo5, 2800,  2800, palmas_rails(smps9), 0, 0, 1, 0,
291         0, 0, 0, 0, 0);
292 PALMAS_REGS_PDATA(ldo6, 2850,  2850, palmas_rails(smps9), 1, 1, 1, 0,
293         0, 0, 0, 0, 0);
294 PALMAS_REGS_PDATA(ldo7, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0,
295         0, 0, 0, 0, 0);
296 PALMAS_REGS_PDATA(ldo8, 950,  950, NULL, 1, 1, 1, 0,
297         0, 0, 0, 0, 0);
298 PALMAS_REGS_PDATA(ldo9, 1800,  2900, palmas_rails(smps9), 0, 0, 1, 0,
299         0, 0, 0, 0, 0);
300 PALMAS_REGS_PDATA(ldoln, 3300,   3300, NULL, 0, 0, 1, 0,
301         0, 0, 0, 0, 0);
302 PALMAS_REGS_PDATA(ldousb, 3300,  3300, NULL, 0, 0, 1, 0,
303         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
304 PALMAS_REGS_PDATA(regen1, 4200,  4200, NULL, 0, 0, 0, 0,
305         0, 0, 0, 0, 0);
306 PALMAS_REGS_PDATA(regen2, 4200,  4200, palmas_rails(smps8), 0, 0, 0, 0,
307         0, 0, 0, 0, 0);
308
309 #define PALMAS_REG_PDATA(_sname) (&reg_idata_##_sname)
310 static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = {
311         NULL,
312         PALMAS_REG_PDATA(smps123),
313         NULL,
314         PALMAS_REG_PDATA(smps45),
315         NULL,
316         PALMAS_REG_PDATA(smps6),
317         PALMAS_REG_PDATA(smps7),
318         PALMAS_REG_PDATA(smps8),
319         PALMAS_REG_PDATA(smps9),
320         NULL,
321         PALMAS_REG_PDATA(smps10_out1),
322         PALMAS_REG_PDATA(ldo1),
323         PALMAS_REG_PDATA(ldo2),
324         PALMAS_REG_PDATA(ldo3),
325         PALMAS_REG_PDATA(ldo4),
326         PALMAS_REG_PDATA(ldo5),
327         PALMAS_REG_PDATA(ldo6),
328         PALMAS_REG_PDATA(ldo7),
329         PALMAS_REG_PDATA(ldo8),
330         PALMAS_REG_PDATA(ldo9),
331         PALMAS_REG_PDATA(ldoln),
332         PALMAS_REG_PDATA(ldousb),
333         PALMAS_REG_PDATA(regen1),
334         PALMAS_REG_PDATA(regen2),
335         NULL,
336         NULL,
337         NULL,
338 };
339
340 #define PALMAS_REG_INIT_DATA(_sname) (&reg_init_data_##_sname)
341 static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = {
342         NULL,
343         PALMAS_REG_INIT_DATA(smps123),
344         NULL,
345         PALMAS_REG_INIT_DATA(smps45),
346         NULL,
347         PALMAS_REG_INIT_DATA(smps6),
348         PALMAS_REG_INIT_DATA(smps7),
349         PALMAS_REG_INIT_DATA(smps8),
350         PALMAS_REG_INIT_DATA(smps9),
351         NULL,
352         PALMAS_REG_INIT_DATA(smps10_out1),
353         PALMAS_REG_INIT_DATA(ldo1),
354         PALMAS_REG_INIT_DATA(ldo2),
355         PALMAS_REG_INIT_DATA(ldo3),
356         PALMAS_REG_INIT_DATA(ldo4),
357         PALMAS_REG_INIT_DATA(ldo5),
358         PALMAS_REG_INIT_DATA(ldo6),
359         PALMAS_REG_INIT_DATA(ldo7),
360         PALMAS_REG_INIT_DATA(ldo8),
361         PALMAS_REG_INIT_DATA(ldo9),
362         PALMAS_REG_INIT_DATA(ldoln),
363         PALMAS_REG_INIT_DATA(ldousb),
364         PALMAS_REG_INIT_DATA(regen1),
365         PALMAS_REG_INIT_DATA(regen2),
366         NULL,
367         NULL,
368         NULL,
369 };
370
371 static struct palmas_pmic_platform_data pmic_platform = {
372         .disable_smps10_boost_suspend = true,
373 };
374
375 static struct palmas_pinctrl_config palmas_pincfg[] = {
376         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
377         PALMAS_PINMUX("vac", "vac", NULL, NULL),
378         PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
379         PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL),
380         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
381         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
382         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
383         PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
384         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
385         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
386 };
387
388 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
389         .pincfg = palmas_pincfg,
390         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
391         .dvfs1_enable = true,
392         .dvfs2_enable = false,
393 };
394
395 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
396         .connection_name = "palmas-extcon",
397         .enable_vbus_detection = true,
398         .enable_id_pin_detection = true,
399 };
400
401 static struct palmas_platform_data palmas_pdata = {
402         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
403         .irq_base = PALMAS_TEGRA_IRQ_BASE,
404         .pmic_pdata = &pmic_platform,
405         .pinctrl_pdata = &palmas_pinctrl_pdata,
406         .extcon_pdata = &palmas_extcon_pdata,
407 };
408
409 static struct i2c_board_info palma_device[] = {
410         {
411                 I2C_BOARD_INFO("tps65913", 0x58),
412                 .irq            = INT_EXTERNAL_PMU,
413                 .platform_data  = &palmas_pdata,
414         },
415 };
416
417 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
418         REGULATOR_SUPPLY("dvdd_lcd", NULL),
419 };
420
421 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
422         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
423 };
424
425 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
426 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
427         REGULATOR_SUPPLY("dvdd", "spi0.0"),
428 };
429
430 /* ENABLE 5v0 for HDMI */
431 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
432         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
433 };
434
435 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
436         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
437 };
438
439 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
440         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
441         REGULATOR_SUPPLY("vi2c", "2-0030"),
442         REGULATOR_SUPPLY("vif", "2-0036"),
443         REGULATOR_SUPPLY("dovdd", "2-0010"),
444         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
445         REGULATOR_SUPPLY("vddio_cam", "vi"),
446         REGULATOR_SUPPLY("pwrdet_cam", NULL),
447 };
448
449 /* Macro for defining fixed regulator sub device data */
450 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
451 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
452         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
453         static struct regulator_init_data ri_data_##_var =              \
454         {                                                               \
455                 .supply_regulator = _in_supply,                         \
456                 .num_consumer_supplies =                                \
457                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
458                 .consumer_supplies = fixed_reg_##_name##_supply,        \
459                 .constraints = {                                        \
460                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
461                                         REGULATOR_MODE_STANDBY),        \
462                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
463                                         REGULATOR_CHANGE_STATUS |       \
464                                         REGULATOR_CHANGE_VOLTAGE),      \
465                         .always_on = _always_on,                        \
466                         .boot_on = _boot_on,                            \
467                 },                                                      \
468         };                                                              \
469         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
470         {                                                               \
471                 .supply_name = FIXED_SUPPLY(_name),                     \
472                 .microvolts = _millivolts * 1000,                       \
473                 .gpio = _gpio_nr,                                       \
474                 .gpio_is_open_drain = _open_drain,                      \
475                 .enable_high = _active_high,                            \
476                 .enabled_at_boot = _boot_state,                         \
477                 .init_data = &ri_data_##_var,                           \
478         };                                                              \
479         static struct platform_device fixed_reg_##_var##_dev = {        \
480                 .name = "reg-fixed-voltage",                            \
481                 .id = _id,                                              \
482                 .dev = {                                                \
483                         .platform_data = &fixed_reg_##_var##_pdata,     \
484                 },                                                      \
485         }
486
487 /*
488  * Creating the fixed regulator device table
489  */
490
491 FIXED_REG(1,    dvdd_lcd_1v8,   dvdd_lcd_1v8,
492         palmas_rails(smps8),    0,      1,
493         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
494
495 FIXED_REG(2,    vdd_lcd_bl_en,  vdd_lcd_bl_en,
496         NULL,   0,      1,
497         TEGRA_GPIO_PH2, false,  true,   1,      3700);
498
499 FIXED_REG(3,    dvdd_ts,        dvdd_ts,
500         palmas_rails(smps8),    0,      0,
501         TEGRA_GPIO_PH4, false,  false,  1,      1800);
502
503 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
504         palmas_rails(smps10_out1),      0,      0,
505         TEGRA_GPIO_PK6, true,   true,   0,      5000);
506
507 FIXED_REG(5,    vddio_sd_slot,  vddio_sd_slot,
508         palmas_rails(smps9),    0,      0,
509         TEGRA_GPIO_PK1, false,  true,   0,      2900);
510
511 FIXED_REG(6,    vd_cam_1v8,     vd_cam_1v8,
512         palmas_rails(smps8),    0,      0,
513         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
514
515 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
516
517 /* Gpio switch regulator platform data for Macallan E1545 */
518 static struct platform_device *fixed_reg_devs[] = {
519         ADD_FIXED_REG(dvdd_lcd_1v8),
520         ADD_FIXED_REG(vdd_lcd_bl_en),
521         ADD_FIXED_REG(dvdd_ts),
522         ADD_FIXED_REG(vdd_hdmi_5v0),
523         ADD_FIXED_REG(vddio_sd_slot),
524         ADD_FIXED_REG(vd_cam_1v8),
525 };
526
527
528 int __init macallan_palmas_regulator_init(void)
529 {
530         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
531         u32 pmc_ctrl;
532         int i;
533         struct board_info board_info;
534
535         /* TPS65913: Normal state of INT request line is LOW.
536          * configure the power management controller to trigger PMU
537          * interrupts when HIGH.
538          */
539         pmc_ctrl = readl(pmc + PMC_CTRL);
540         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
541
542         /* Tracking configuration */
543         reg_init_data_ldo8.config_flags =
544                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
545                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
546
547         tegra_get_board_info(&board_info);
548         if (board_info.board_id == BOARD_E1569) {
549                 reg_idata_ldo5.consumer_supplies = palmas_ldo5_e1569_supply;
550                 reg_idata_ldo5.num_consumer_supplies =
551                         ARRAY_SIZE(palmas_ldo5_e1569_supply);
552                 reg_idata_ldo7.consumer_supplies = palmas_ldo7_e1569_supply;
553                 reg_idata_ldo7.num_consumer_supplies =
554                         ARRAY_SIZE(palmas_ldo7_e1569_supply);
555         }
556
557         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
558                 pmic_platform.reg_data[i] = macallan_reg_data[i];
559                 pmic_platform.reg_init[i] = macallan_reg_init[i];
560         }
561
562         i2c_register_board_info(4, palma_device,
563                         ARRAY_SIZE(palma_device));
564
565         return 0;
566 }
567
568 static int ac_online(void)
569 {
570         return 1;
571 }
572
573 static struct resource macallan_pda_resources[] = {
574         [0] = {
575                 .name   = "ac",
576         },
577 };
578
579 static struct pda_power_pdata macallan_pda_data = {
580         .is_ac_online   = ac_online,
581 };
582
583 static struct platform_device macallan_pda_power_device = {
584         .name           = "pda-power",
585         .id             = -1,
586         .resource       = macallan_pda_resources,
587         .num_resources  = ARRAY_SIZE(macallan_pda_resources),
588         .dev    = {
589                 .platform_data  = &macallan_pda_data,
590         },
591 };
592
593 static void macallan_board_suspend(int state, enum suspend_stage stage)
594 {
595 }
596
597 static struct tegra_suspend_platform_data macallan_suspend_data = {
598         .cpu_timer      = 300,
599         .cpu_off_timer  = 300,
600         .suspend_mode   = TEGRA_SUSPEND_LP0,
601         .core_timer     = 0x157e,
602         .core_off_timer = 2000,
603         .corereq_high   = true,
604         .sysclkreq_high = true,
605         .cpu_lp2_min_residency = 1000,
606         .min_residency_crail = 20000,
607 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
608         .lp1_lowvolt_support = false,
609         .i2c_base_addr = 0,
610         .pmuslave_addr = 0,
611         .core_reg_addr = 0,
612         .lp1_core_volt_low_cold = 0,
613         .lp1_core_volt_low = 0,
614         .lp1_core_volt_high = 0,
615 #endif
616         .board_suspend = macallan_board_suspend,
617 };
618 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
619 /* board parameters for cpu dfll */
620 static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = {
621         .sample_rate = 12500,
622
623         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
624         .cf = 10,
625         .ci = 0,
626         .cg = 2,
627
628         .droop_cut_value = 0xF,
629         .droop_restore_ramp = 0x0,
630         .scale_out_ramp = 0x0,
631 };
632 #endif
633
634 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
635 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
636 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
637 static inline void fill_reg_map(void)
638 {
639         int i;
640         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
641                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
642                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
643         }
644 }
645
646 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
647 static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = {
648         .dfll_clk_name = "dfll_cpu",
649         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
650         .u.pmu_i2c = {
651                 .fs_rate = 400000,
652                 .slave_addr = 0xb0,
653                 .reg = 0x23,
654         },
655         .vdd_map = pmu_cpu_vdd_map,
656         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
657         .pmu_undershoot_gb = 100,
658
659         .cfg_param = &macallan_cl_dvfs_param,
660 };
661
662 static int __init macallan_cl_dvfs_init(void)
663 {
664         fill_reg_map();
665         if (tegra_revision < TEGRA_REVISION_A02)
666                 macallan_cl_dvfs_data.flags =
667                         TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
668         tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data;
669         platform_device_register(&tegra_cl_dvfs_device);
670
671         return 0;
672 }
673 #endif
674
675 static int __init macallan_fixed_regulator_init(void)
676 {
677         if (!of_machine_is_compatible("nvidia,macallan"))
678                 return 0;
679
680         return platform_add_devices(fixed_reg_devs,
681                         ARRAY_SIZE(fixed_reg_devs));
682 }
683 subsys_initcall_sync(macallan_fixed_regulator_init);
684
685 int __init macallan_regulator_init(void)
686 {
687         struct board_info board_info;
688         tegra_get_board_info(&board_info);
689
690 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
691         macallan_cl_dvfs_init();
692 #endif
693         macallan_palmas_regulator_init();
694
695         if (board_info.board_id == BOARD_E1569) {
696                 if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY) {
697                         /* Disable charger when adapter is power source. */
698                         macallan_bq2419x_pdata.bcharger_pdata = NULL;
699                 } else {
700                         /* Only register fuel gauge when using battery. */
701                         i2c_register_board_info(0, macallan_max17048_boardinfo,
702                                                 1);
703                 }
704         } else {
705                 /* forced make null to prevent charging for E1545. */
706                 macallan_bq2419x_pdata.bcharger_pdata = NULL;
707         }
708
709         bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
710         i2c_register_board_info(0, bq2419x_boardinfo,
711                         ARRAY_SIZE(bq2419x_boardinfo));
712
713         platform_device_register(&psy_extcon_device);
714         platform_device_register(&macallan_pda_power_device);
715
716         return 0;
717 }
718
719 int __init macallan_suspend_init(void)
720 {
721         tegra_init_suspend(&macallan_suspend_data);
722         return 0;
723 }
724
725 int __init macallan_edp_init(void)
726 {
727         unsigned int regulator_mA;
728
729         regulator_mA = get_maximum_cpu_current_supported();
730         if (!regulator_mA)
731                 regulator_mA = 15000;
732
733         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
734         tegra_init_cpu_edp_limits(regulator_mA);
735
736         regulator_mA = get_maximum_core_current_supported();
737         if (!regulator_mA)
738                 regulator_mA = 4000;
739
740         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
741         tegra_init_core_edp_limits(regulator_mA);
742
743         return 0;
744 }
745
746 static struct pid_thermal_gov_params soctherm_cpu_pid_params = {
747         .max_err_temp = 9000,
748         .max_err_gain = 1000,
749
750         .gain_p = 1000,
751         .gain_d = 0,
752
753         .up_compensation = 20,
754         .down_compensation = 20,
755 };
756
757 static struct thermal_zone_params macallan_soctherm_therm_cpu_tzp = {
758         .governor_name = "pid_thermal_gov",
759         .governor_params = &soctherm_cpu_pid_params,
760 };
761
762 static struct tegra_tsensor_pmu_data tpdata_palmas = {
763         .reset_tegra = 1,
764         .pmu_16bit_ops = 0,
765         .controller_type = 0,
766         .pmu_i2c_addr = 0x58,
767         .i2c_controller_id = 4,
768         .poweroff_reg_addr = 0xa0,
769         .poweroff_reg_data = 0x0,
770 };
771
772 static struct soctherm_platform_data macallan_soctherm_data = {
773         .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
774         .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
775         .therm = {
776                 [THERM_CPU] = {
777                         .zone_enable = true,
778                         .passive_delay = 1000,
779                         .hotspot_offset = 6000,
780                         .num_trips = 3,
781                         .trips = {
782                                 {
783                                         .cdev_type = "tegra-balanced",
784                                         .trip_temp = 90000,
785                                         .trip_type = THERMAL_TRIP_PASSIVE,
786                                         .upper = THERMAL_NO_LIMIT,
787                                         .lower = THERMAL_NO_LIMIT,
788                                 },
789                                 {
790                                         .cdev_type = "tegra-heavy",
791                                         .trip_temp = 100000,
792                                         .trip_type = THERMAL_TRIP_HOT,
793                                         .upper = THERMAL_NO_LIMIT,
794                                         .lower = THERMAL_NO_LIMIT,
795                                 },
796                                 {
797                                         .cdev_type = "tegra-shutdown",
798                                         .trip_temp = 102000,
799                                         .trip_type = THERMAL_TRIP_CRITICAL,
800                                         .upper = THERMAL_NO_LIMIT,
801                                         .lower = THERMAL_NO_LIMIT,
802                                 },
803                         },
804                         .tzp = &macallan_soctherm_therm_cpu_tzp,
805                 },
806                 [THERM_GPU] = {
807                         .zone_enable = true,
808                         .passive_delay = 1000,
809                         .hotspot_offset = 6000,
810                         .num_trips = 3,
811                         .trips = {
812                                 {
813                                         .cdev_type = "tegra-balanced",
814                                         .trip_temp = 90000,
815                                         .trip_type = THERMAL_TRIP_PASSIVE,
816                                         .upper = THERMAL_NO_LIMIT,
817                                         .lower = THERMAL_NO_LIMIT,
818                                 },
819                                 {
820                                         .cdev_type = "tegra-heavy",
821                                         .trip_temp = 100000,
822                                         .trip_type = THERMAL_TRIP_HOT,
823                                         .upper = THERMAL_NO_LIMIT,
824                                         .lower = THERMAL_NO_LIMIT,
825                                 },
826                                 {
827                                         .cdev_type = "tegra-shutdown",
828                                         .trip_temp = 102000,
829                                         .trip_type = THERMAL_TRIP_CRITICAL,
830                                         .upper = THERMAL_NO_LIMIT,
831                                         .lower = THERMAL_NO_LIMIT,
832                                 },
833                         },
834                         .tzp = &macallan_soctherm_therm_cpu_tzp,
835                 },
836                 [THERM_PLL] = {
837                         .zone_enable = true,
838                 },
839         },
840         .throttle = {
841                 [THROTTLE_HEAVY] = {
842                         .priority = 100,
843                         .devs = {
844                                 [THROTTLE_DEV_CPU] = {
845                                         .enable = true,
846                                         .depth = 80,
847                                 },
848                                 [THROTTLE_DEV_GPU] = {
849                                         .enable = true,
850                                         .depth = 80,
851                                 },
852                         },
853                 },
854                 [THROTTLE_OC4] = {
855                         .throt_mode = BRIEF,
856                         .polarity = 1,
857                         .intr = true,
858                         .devs = {
859                                 [THROTTLE_DEV_CPU] = {
860                                         .enable = true,
861                                         .depth = 50,
862                                 },
863                                 [THROTTLE_DEV_GPU] = {
864                                         .enable = true,
865                                         .depth = 50,
866                                 },
867                         },
868                 },
869         },
870         .tshut_pmu_trip_data = &tpdata_palmas,
871 };
872
873 int __init macallan_soctherm_init(void)
874 {
875         struct board_info board_info;
876         tegra_get_board_info(&board_info);
877         if (board_info.board_id == BOARD_E1545)
878                 tegra_add_all_vmin_trips(
879                         macallan_soctherm_data.therm[THERM_CPU].trips,
880                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
881         tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
882                         &macallan_soctherm_data.therm[THERM_CPU].num_trips,
883                         6000); /* edp temperature margin */
884         tegra_add_cpu_vmax_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
885                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
886         tegra_add_core_edp_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
887                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
888
889         return tegra11_soctherm_init(&macallan_soctherm_data);
890 }