ARM: tegra: add machine check for fix reg init
[linux-3.10.git] / arch / arm / mach-tegra / board-macallan-power.c
1 /*
2  * arch/arm/mach-tegra/board-macallan-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/palmas.h>
29 #include <linux/power/bq2419x-charger.h>
30 #include <linux/max17048_battery.h>
31 #include <linux/gpio.h>
32 #include <linux/interrupt.h>
33 #include <linux/regulator/userspace-consumer.h>
34 #include <linux/edp.h>
35 #include <linux/edpdev.h>
36 #include <linux/platform_data/tegra_edp.h>
37 #include <linux/pid_thermal_gov.h>
38
39 #include <asm/mach-types.h>
40 #include <linux/power/sbs-battery.h>
41
42 #include <mach/irqs.h>
43 #include <mach/hardware.h>
44 #include <mach/edp.h>
45 #include <mach/gpio-tegra.h>
46
47 #include "cpu-tegra.h"
48 #include "pm.h"
49 #include "tegra-board-id.h"
50 #include "board-pmu-defines.h"
51 #include "board.h"
52 #include "gpio-names.h"
53 #include "board-common.h"
54 #include "board-macallan.h"
55 #include "tegra_cl_dvfs.h"
56 #include "devices.h"
57 #include "tegra11_soctherm.h"
58 #include "tegra3_tsensor.h"
59 #include "iomap.h"
60 #include "battery-ini-model-data.h"
61
62 #define PMC_CTRL                0x0
63 #define PMC_CTRL_INTR_LOW       (1 << 17)
64
65 /* BQ2419X VBUS regulator */
66 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
67         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
68 };
69
70 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
71         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
72 };
73
74 static struct bq2419x_vbus_platform_data macallan_bq2419x_vbus_pdata = {
75         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
76         .consumer_supplies = bq2419x_vbus_supply,
77 };
78
79 struct bq2419x_charger_platform_data macallan_bq2419x_charger_pdata = {
80         .max_charge_current_mA = 3000,
81         .charging_term_current_mA = 100,
82         .consumer_supplies = bq2419x_batt_supply,
83         .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
84         .wdt_timeout    = 40,
85         .rtc_alarm_time = 3600,
86         .chg_restart_time = 1800,
87 };
88
89 struct max17048_platform_data macallan_max17048_pdata = {
90         .model_data = &macallan_yoku_4100mA_max17048_battery,
91 };
92
93 static struct i2c_board_info __initdata macallan_max17048_boardinfo[] = {
94         {
95                 I2C_BOARD_INFO("max17048", 0x36),
96                 .platform_data  = &macallan_max17048_pdata,
97         },
98 };
99
100 struct bq2419x_platform_data macallan_bq2419x_pdata = {
101         .vbus_pdata = &macallan_bq2419x_vbus_pdata,
102         .bcharger_pdata = &macallan_bq2419x_charger_pdata,
103 };
104
105 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
106         {
107                 I2C_BOARD_INFO("bq2419x", 0x6b),
108                 .platform_data  = &macallan_bq2419x_pdata,
109         },
110 };
111
112
113 /************************ Macallan based regulator ****************/
114 static struct regulator_consumer_supply palmas_smps123_supply[] = {
115         REGULATOR_SUPPLY("vdd_cpu", NULL),
116 };
117
118 static struct regulator_consumer_supply palmas_smps45_supply[] = {
119         REGULATOR_SUPPLY("vdd_core", NULL),
120         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
121         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
122 };
123
124 static struct regulator_consumer_supply palmas_smps6_supply[] = {
125         REGULATOR_SUPPLY("vdd_lcd_hv", NULL),
126         REGULATOR_SUPPLY("avdd_lcd", NULL),
127         REGULATOR_SUPPLY("avdd", "spi0.0"),
128 };
129
130 static struct regulator_consumer_supply palmas_smps7_supply[] = {
131         REGULATOR_SUPPLY("vddio_ddr", NULL),
132 };
133
134 static struct regulator_consumer_supply palmas_smps8_supply[] = {
135         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
136         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
137         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
138         REGULATOR_SUPPLY("avdd_osc", NULL),
139         REGULATOR_SUPPLY("vddio_sys", NULL),
140         REGULATOR_SUPPLY("vddio_bb", NULL),
141         REGULATOR_SUPPLY("pwrdet_bb", NULL),
142         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
143         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
144         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
145         REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"),
146         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
147         REGULATOR_SUPPLY("vddio_audio", NULL),
148         REGULATOR_SUPPLY("pwrdet_audio", NULL),
149         REGULATOR_SUPPLY("vddio_uart", NULL),
150         REGULATOR_SUPPLY("pwrdet_uart", NULL),
151         REGULATOR_SUPPLY("vddio_gmi", NULL),
152         REGULATOR_SUPPLY("pwrdet_nand", NULL),
153         REGULATOR_SUPPLY("vlogic", "0-0069"),
154         REGULATOR_SUPPLY("vid", "0-000d"),
155         REGULATOR_SUPPLY("vddio", "0-0078"),
156 };
157
158 static struct regulator_consumer_supply palmas_smps9_supply[] = {
159         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
160         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
161         REGULATOR_SUPPLY("pwrdet_hv", NULL),
162 };
163
164 static struct regulator_consumer_supply palmas_smps10_supply[] = {
165 };
166
167 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
168         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
169         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
170         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
171         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
172         REGULATOR_SUPPLY("avdd_pllm", NULL),
173         REGULATOR_SUPPLY("avdd_pllu", NULL),
174         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
175         REGULATOR_SUPPLY("avdd_pllx", NULL),
176         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
177         REGULATOR_SUPPLY("avdd_plle", NULL),
178 };
179
180 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
181         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
182         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
183         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
184         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
185         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
186         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
187 };
188
189 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
190         REGULATOR_SUPPLY("vpp_fuse", NULL),
191 };
192
193 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
194         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
195         REGULATOR_SUPPLY("dvdd", "2-0010"),
196         REGULATOR_SUPPLY("vdig", "2-0036"),
197 };
198
199 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
200         REGULATOR_SUPPLY("avdd_cam2", NULL),
201         REGULATOR_SUPPLY("avdd", "2-0010"),
202 };
203
204 static struct regulator_consumer_supply palmas_ldo5_e1569_supply[] = {
205         REGULATOR_SUPPLY("avdd_cam2", NULL),
206         REGULATOR_SUPPLY("avdd", "2-0010"),
207         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
208         REGULATOR_SUPPLY("vdd", "2-000e"),
209 };
210
211 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
212         REGULATOR_SUPPLY("vdd", "0-0069"),
213         REGULATOR_SUPPLY("vdd", "0-000d"),
214         REGULATOR_SUPPLY("vdd", "0-0078"),
215 };
216
217 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
218         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
219         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
220         REGULATOR_SUPPLY("avdd_cam1", NULL),
221         REGULATOR_SUPPLY("vana", "2-0036"),
222         REGULATOR_SUPPLY("vdd", "2-000e"),
223 };
224
225 static struct regulator_consumer_supply palmas_ldo7_e1569_supply[] = {
226         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
227         REGULATOR_SUPPLY("avdd_cam1", NULL),
228         REGULATOR_SUPPLY("vana", "2-0036"),
229 };
230
231 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
232         REGULATOR_SUPPLY("vdd_rtc", NULL),
233 };
234 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
235         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
236         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
237 };
238 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
239         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
240 };
241
242 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
243         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
244         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
245         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
246         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
247         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
248
249 };
250
251 static struct regulator_consumer_supply palmas_regen1_supply[] = {
252 };
253
254 static struct regulator_consumer_supply palmas_regen2_supply[] = {
255 };
256
257 PALMAS_REGS_PDATA(smps123, 900,  1300, NULL, 0, 0, 0, 0,
258         0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
259 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, 0,
260         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
261 PALMAS_REGS_PDATA(smps6, 3200,  3200, NULL, 0, 0, 1, NORMAL,
262         0, 0, 0, 0, 0);
263 PALMAS_REGS_PDATA(smps7, 1350,  1350, NULL, 0, 0, 1, NORMAL,
264         0, 0, 0, 0, 0);
265 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
266         0, 0, 0, 0, 0);
267 PALMAS_REGS_PDATA(smps9, 2900,  2900, NULL, 1, 0, 1, NORMAL,
268         0, 0, 0, 0, 0);
269 PALMAS_REGS_PDATA(smps10, 5000,  5000, NULL, 0, 0, 0, 0,
270         0, 0, 0, 0, 0);
271 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps7), 1, 0, 1, 0,
272         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
273 PALMAS_REGS_PDATA(ldo2, 1200,  1200, palmas_rails(smps7), 0, 1, 1, 0,
274         0, 0, 0, 0, 0);
275 PALMAS_REGS_PDATA(ldo3, 1800,  1800, NULL, 0, 0, 1, 0,
276         0, 0, 0, 0, 0);
277 PALMAS_REGS_PDATA(ldo4, 1200,  1200, palmas_rails(smps8), 0, 0, 1, 0,
278         0, 0, 0, 0, 0);
279 PALMAS_REGS_PDATA(ldo5, 2800,  2800, palmas_rails(smps9), 0, 0, 1, 0,
280         0, 0, 0, 0, 0);
281 PALMAS_REGS_PDATA(ldo6, 2850,  2850, palmas_rails(smps9), 1, 1, 1, 0,
282         0, 0, 0, 0, 0);
283 PALMAS_REGS_PDATA(ldo7, 2700,  2700, palmas_rails(smps9), 0, 0, 1, 0,
284         0, 0, 0, 0, 0);
285 PALMAS_REGS_PDATA(ldo8, 950,  950, NULL, 1, 1, 1, 0,
286         0, 0, 0, 0, 0);
287 PALMAS_REGS_PDATA(ldo9, 1800,  2900, palmas_rails(smps9), 0, 0, 1, 0,
288         0, 0, 0, 0, 0);
289 PALMAS_REGS_PDATA(ldoln, 3300,   3300, NULL, 0, 0, 1, 0,
290         0, 0, 0, 0, 0);
291 PALMAS_REGS_PDATA(ldousb, 3300,  3300, NULL, 0, 0, 1, 0,
292         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
293 PALMAS_REGS_PDATA(regen1, 4200,  4200, NULL, 0, 0, 0, 0,
294         0, 0, 0, 0, 0);
295 PALMAS_REGS_PDATA(regen2, 4200,  4200, palmas_rails(smps8), 0, 0, 0, 0,
296         0, 0, 0, 0, 0);
297
298 #define PALMAS_REG_PDATA(_sname) (&reg_idata_##_sname)
299 static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = {
300         NULL,
301         PALMAS_REG_PDATA(smps123),
302         NULL,
303         PALMAS_REG_PDATA(smps45),
304         NULL,
305         PALMAS_REG_PDATA(smps6),
306         PALMAS_REG_PDATA(smps7),
307         PALMAS_REG_PDATA(smps8),
308         PALMAS_REG_PDATA(smps9),
309         PALMAS_REG_PDATA(smps10),
310         PALMAS_REG_PDATA(ldo1),
311         PALMAS_REG_PDATA(ldo2),
312         PALMAS_REG_PDATA(ldo3),
313         PALMAS_REG_PDATA(ldo4),
314         PALMAS_REG_PDATA(ldo5),
315         PALMAS_REG_PDATA(ldo6),
316         PALMAS_REG_PDATA(ldo7),
317         PALMAS_REG_PDATA(ldo8),
318         PALMAS_REG_PDATA(ldo9),
319         PALMAS_REG_PDATA(ldoln),
320         PALMAS_REG_PDATA(ldousb),
321         PALMAS_REG_PDATA(regen1),
322         PALMAS_REG_PDATA(regen2),
323         NULL,
324         NULL,
325         NULL,
326 };
327
328 #define PALMAS_REG_INIT_DATA(_sname) (&reg_init_data_##_sname)
329 static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = {
330         NULL,
331         PALMAS_REG_INIT_DATA(smps123),
332         NULL,
333         PALMAS_REG_INIT_DATA(smps45),
334         NULL,
335         PALMAS_REG_INIT_DATA(smps6),
336         PALMAS_REG_INIT_DATA(smps7),
337         PALMAS_REG_INIT_DATA(smps8),
338         PALMAS_REG_INIT_DATA(smps9),
339         PALMAS_REG_INIT_DATA(smps10),
340         PALMAS_REG_INIT_DATA(ldo1),
341         PALMAS_REG_INIT_DATA(ldo2),
342         PALMAS_REG_INIT_DATA(ldo3),
343         PALMAS_REG_INIT_DATA(ldo4),
344         PALMAS_REG_INIT_DATA(ldo5),
345         PALMAS_REG_INIT_DATA(ldo6),
346         PALMAS_REG_INIT_DATA(ldo7),
347         PALMAS_REG_INIT_DATA(ldo8),
348         PALMAS_REG_INIT_DATA(ldo9),
349         PALMAS_REG_INIT_DATA(ldoln),
350         PALMAS_REG_INIT_DATA(ldousb),
351         PALMAS_REG_INIT_DATA(regen1),
352         PALMAS_REG_INIT_DATA(regen2),
353         NULL,
354         NULL,
355         NULL,
356 };
357
358 static struct palmas_pmic_platform_data pmic_platform = {
359         .disable_smps10_boost_suspend = true,
360 };
361
362 static struct palmas_pinctrl_config palmas_pincfg[] = {
363         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
364         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
365         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
366         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
367         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
368         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
369         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
370         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
371         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
372         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
373 };
374
375 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
376         .pincfg = palmas_pincfg,
377         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
378         .dvfs1_enable = true,
379         .dvfs2_enable = false,
380 };
381
382 struct palmas_extcon_platform_data palmas_extcon_pdata = {
383         .connection_name = "palmas-extcon",
384         .enable_vbus_detection = true,
385         .enable_id_pin_detection = true,
386 };
387
388 static struct palmas_platform_data palmas_pdata = {
389         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
390         .irq_base = PALMAS_TEGRA_IRQ_BASE,
391         .pmic_pdata = &pmic_platform,
392         .use_power_off = true,
393         .pinctrl_pdata = &palmas_pinctrl_pdata,
394         .extcon_pdata = &palmas_extcon_pdata,
395 };
396
397 static struct i2c_board_info palma_device[] = {
398         {
399                 I2C_BOARD_INFO("tps65913", 0x58),
400                 .irq            = INT_EXTERNAL_PMU,
401                 .platform_data  = &palmas_pdata,
402         },
403 };
404
405 static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = {
406         REGULATOR_SUPPLY("dvdd_lcd", NULL),
407 };
408
409 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = {
410         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
411 };
412
413 /* EN_1V8_TS From TEGRA_GPIO_PH4 */
414 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
415         REGULATOR_SUPPLY("dvdd", "spi0.0"),
416 };
417
418 /* ENABLE 5v0 for HDMI */
419 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
420         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
421 };
422
423 static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = {
424         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
425 };
426
427 static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = {
428         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
429         REGULATOR_SUPPLY("vi2c", "2-0030"),
430         REGULATOR_SUPPLY("vif", "2-0036"),
431         REGULATOR_SUPPLY("dovdd", "2-0010"),
432         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
433         REGULATOR_SUPPLY("vddio_cam", "vi"),
434         REGULATOR_SUPPLY("pwrdet_cam", NULL),
435 };
436
437 /* Macro for defining fixed regulator sub device data */
438 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
439 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
440         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
441         static struct regulator_init_data ri_data_##_var =              \
442         {                                                               \
443                 .supply_regulator = _in_supply,                         \
444                 .num_consumer_supplies =                                \
445                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
446                 .consumer_supplies = fixed_reg_##_name##_supply,        \
447                 .constraints = {                                        \
448                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
449                                         REGULATOR_MODE_STANDBY),        \
450                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
451                                         REGULATOR_CHANGE_STATUS |       \
452                                         REGULATOR_CHANGE_VOLTAGE),      \
453                         .always_on = _always_on,                        \
454                         .boot_on = _boot_on,                            \
455                 },                                                      \
456         };                                                              \
457         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
458         {                                                               \
459                 .supply_name = FIXED_SUPPLY(_name),                     \
460                 .microvolts = _millivolts * 1000,                       \
461                 .gpio = _gpio_nr,                                       \
462                 .gpio_is_open_drain = _open_drain,                      \
463                 .enable_high = _active_high,                            \
464                 .enabled_at_boot = _boot_state,                         \
465                 .init_data = &ri_data_##_var,                           \
466         };                                                              \
467         static struct platform_device fixed_reg_##_var##_dev = {        \
468                 .name = "reg-fixed-voltage",                            \
469                 .id = _id,                                              \
470                 .dev = {                                                \
471                         .platform_data = &fixed_reg_##_var##_pdata,     \
472                 },                                                      \
473         }
474
475 /*
476  * Creating the fixed regulator device table
477  */
478
479 FIXED_REG(1,    dvdd_lcd_1v8,   dvdd_lcd_1v8,
480         palmas_rails(smps8),    0,      1,
481         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false,  true,   1,      1800);
482
483 FIXED_REG(2,    vdd_lcd_bl_en,  vdd_lcd_bl_en,
484         NULL,   0,      1,
485         TEGRA_GPIO_PH2, false,  true,   1,      3700);
486
487 FIXED_REG(3,    dvdd_ts,        dvdd_ts,
488         palmas_rails(smps8),    0,      0,
489         TEGRA_GPIO_PH4, false,  false,  1,      1800);
490
491 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
492         palmas_rails(smps10),   0,      0,
493         TEGRA_GPIO_PK6, true,   true,   0,      5000);
494
495 FIXED_REG(5,    vddio_sd_slot,  vddio_sd_slot,
496         palmas_rails(smps9),    0,      0,
497         TEGRA_GPIO_PK1, false,  true,   0,      2900);
498
499 FIXED_REG(6,    vd_cam_1v8,     vd_cam_1v8,
500         palmas_rails(smps8),    0,      0,
501         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
502
503 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
504
505 /* Gpio switch regulator platform data for Macallan E1545 */
506 static struct platform_device *fixed_reg_devs[] = {
507         ADD_FIXED_REG(dvdd_lcd_1v8),
508         ADD_FIXED_REG(vdd_lcd_bl_en),
509         ADD_FIXED_REG(dvdd_ts),
510         ADD_FIXED_REG(vdd_hdmi_5v0),
511         ADD_FIXED_REG(vddio_sd_slot),
512         ADD_FIXED_REG(vd_cam_1v8),
513 };
514
515
516 int __init macallan_palmas_regulator_init(void)
517 {
518         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
519         u32 pmc_ctrl;
520         int i;
521         struct board_info board_info;
522
523         /* TPS65913: Normal state of INT request line is LOW.
524          * configure the power management controller to trigger PMU
525          * interrupts when HIGH.
526          */
527         pmc_ctrl = readl(pmc + PMC_CTRL);
528         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
529
530         /* Tracking configuration */
531         reg_init_data_ldo8.config_flags =
532                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
533                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
534
535         tegra_get_board_info(&board_info);
536         if (board_info.board_id == BOARD_E1569) {
537                 reg_idata_ldo5.consumer_supplies = palmas_ldo5_e1569_supply;
538                 reg_idata_ldo5.num_consumer_supplies =
539                         ARRAY_SIZE(palmas_ldo5_e1569_supply);
540                 reg_idata_ldo7.consumer_supplies = palmas_ldo7_e1569_supply;
541                 reg_idata_ldo7.num_consumer_supplies =
542                         ARRAY_SIZE(palmas_ldo7_e1569_supply);
543         }
544
545         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
546                 pmic_platform.reg_data[i] = macallan_reg_data[i];
547                 pmic_platform.reg_init[i] = macallan_reg_init[i];
548         }
549
550         i2c_register_board_info(4, palma_device,
551                         ARRAY_SIZE(palma_device));
552
553         return 0;
554 }
555
556 static int ac_online(void)
557 {
558         return 1;
559 }
560
561 static struct resource macallan_pda_resources[] = {
562         [0] = {
563                 .name   = "ac",
564         },
565 };
566
567 static struct pda_power_pdata macallan_pda_data = {
568         .is_ac_online   = ac_online,
569 };
570
571 static struct platform_device macallan_pda_power_device = {
572         .name           = "pda-power",
573         .id             = -1,
574         .resource       = macallan_pda_resources,
575         .num_resources  = ARRAY_SIZE(macallan_pda_resources),
576         .dev    = {
577                 .platform_data  = &macallan_pda_data,
578         },
579 };
580
581 static struct tegra_suspend_platform_data macallan_suspend_data = {
582         .cpu_timer      = 300,
583         .cpu_off_timer  = 300,
584         .suspend_mode   = TEGRA_SUSPEND_LP0,
585         .core_timer     = 0x157e,
586         .core_off_timer = 2000,
587         .corereq_high   = true,
588         .sysclkreq_high = true,
589         .cpu_lp2_min_residency = 1000,
590         .min_residency_crail = 20000,
591 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
592         .lp1_lowvolt_support = false,
593         .i2c_base_addr = 0,
594         .pmuslave_addr = 0,
595         .core_reg_addr = 0,
596         .lp1_core_volt_low_cold = 0,
597         .lp1_core_volt_low = 0,
598         .lp1_core_volt_high = 0,
599 #endif
600 };
601 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
602 /* board parameters for cpu dfll */
603 static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = {
604         .sample_rate = 12500,
605
606         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
607         .cf = 10,
608         .ci = 0,
609         .cg = 2,
610
611         .droop_cut_value = 0xF,
612         .droop_restore_ramp = 0x0,
613         .scale_out_ramp = 0x0,
614 };
615 #endif
616
617 /* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */
618 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
619 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
620 static inline void fill_reg_map(void)
621 {
622         int i;
623         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
624                 pmu_cpu_vdd_map[i].reg_value = i + 0x10;
625                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
626         }
627 }
628
629 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
630 static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = {
631         .dfll_clk_name = "dfll_cpu",
632         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
633         .u.pmu_i2c = {
634                 .fs_rate = 400000,
635                 .slave_addr = 0xb0,
636                 .reg = 0x23,
637         },
638         .vdd_map = pmu_cpu_vdd_map,
639         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
640
641         .cfg_param = &macallan_cl_dvfs_param,
642 };
643
644 static int __init macallan_cl_dvfs_init(void)
645 {
646         fill_reg_map();
647         if (tegra_revision < TEGRA_REVISION_A02)
648                 macallan_cl_dvfs_data.flags =
649                         TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
650         tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data;
651         platform_device_register(&tegra_cl_dvfs_device);
652
653         return 0;
654 }
655 #endif
656
657 static int __init macallan_fixed_regulator_init(void)
658 {
659         if (!of_machine_is_compatible("nvidia,macallan"))
660                 return 0;
661
662         return platform_add_devices(fixed_reg_devs,
663                         ARRAY_SIZE(fixed_reg_devs));
664 }
665 subsys_initcall_sync(macallan_fixed_regulator_init);
666
667 int __init macallan_regulator_init(void)
668 {
669         struct board_info board_info;
670         tegra_get_board_info(&board_info);
671
672 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
673         macallan_cl_dvfs_init();
674 #endif
675         macallan_palmas_regulator_init();
676
677         if (board_info.board_id == BOARD_E1569) {
678                 if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY) {
679                         /* Disable charger when adapter is power source. */
680                         macallan_bq2419x_pdata.bcharger_pdata = NULL;
681                 } else {
682                         /* Only register fuel gauge when using battery. */
683                         i2c_register_board_info(0, macallan_max17048_boardinfo,
684                                                 1);
685                 }
686         } else {
687                 /* forced make null to prevent charging for E1545. */
688                 macallan_bq2419x_pdata.bcharger_pdata = NULL;
689         }
690
691         bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
692         i2c_register_board_info(0, bq2419x_boardinfo,
693                         ARRAY_SIZE(bq2419x_boardinfo));
694
695         platform_device_register(&macallan_pda_power_device);
696
697         return 0;
698 }
699
700 int __init macallan_suspend_init(void)
701 {
702         tegra_init_suspend(&macallan_suspend_data);
703         return 0;
704 }
705
706 int __init macallan_edp_init(void)
707 {
708         unsigned int regulator_mA;
709
710         regulator_mA = get_maximum_cpu_current_supported();
711         if (!regulator_mA)
712                 regulator_mA = 15000;
713
714         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
715         tegra_init_cpu_edp_limits(regulator_mA);
716
717         regulator_mA = get_maximum_core_current_supported();
718         if (!regulator_mA)
719                 regulator_mA = 4000;
720
721         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
722         tegra_init_core_edp_limits(regulator_mA);
723
724         return 0;
725 }
726
727 static struct pid_thermal_gov_params soctherm_cpu_pid_params = {
728         .max_err_temp = 9000,
729         .max_err_gain = 1000,
730
731         .gain_p = 1000,
732         .gain_d = 0,
733
734         .up_compensation = 20,
735         .down_compensation = 20,
736 };
737
738 static struct thermal_zone_params macallan_soctherm_therm_cpu_tzp = {
739         .governor_name = "pid_thermal_gov",
740         .governor_params = &soctherm_cpu_pid_params,
741 };
742
743 static struct tegra_tsensor_pmu_data tpdata_palmas = {
744         .reset_tegra = 1,
745         .pmu_16bit_ops = 0,
746         .controller_type = 0,
747         .pmu_i2c_addr = 0x58,
748         .i2c_controller_id = 4,
749         .poweroff_reg_addr = 0xa0,
750         .poweroff_reg_data = 0x0,
751 };
752
753 static struct soctherm_platform_data macallan_soctherm_data = {
754         .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
755         .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
756         .therm = {
757                 [THERM_CPU] = {
758                         .zone_enable = true,
759                         .passive_delay = 1000,
760                         .hotspot_offset = 6000,
761                         .num_trips = 3,
762                         .trips = {
763                                 {
764                                         .cdev_type = "tegra-balanced",
765                                         .trip_temp = 90000,
766                                         .trip_type = THERMAL_TRIP_PASSIVE,
767                                         .upper = THERMAL_NO_LIMIT,
768                                         .lower = THERMAL_NO_LIMIT,
769                                 },
770                                 {
771                                         .cdev_type = "tegra-heavy",
772                                         .trip_temp = 100000,
773                                         .trip_type = THERMAL_TRIP_HOT,
774                                         .upper = THERMAL_NO_LIMIT,
775                                         .lower = THERMAL_NO_LIMIT,
776                                 },
777                                 {
778                                         .cdev_type = "tegra-shutdown",
779                                         .trip_temp = 102000,
780                                         .trip_type = THERMAL_TRIP_CRITICAL,
781                                         .upper = THERMAL_NO_LIMIT,
782                                         .lower = THERMAL_NO_LIMIT,
783                                 },
784                         },
785                         .tzp = &macallan_soctherm_therm_cpu_tzp,
786                 },
787                 [THERM_GPU] = {
788                         .zone_enable = true,
789                         .passive_delay = 1000,
790                         .hotspot_offset = 6000,
791                         .num_trips = 3,
792                         .trips = {
793                                 {
794                                         .cdev_type = "tegra-balanced",
795                                         .trip_temp = 90000,
796                                         .trip_type = THERMAL_TRIP_PASSIVE,
797                                         .upper = THERMAL_NO_LIMIT,
798                                         .lower = THERMAL_NO_LIMIT,
799                                 },
800                                 {
801                                         .cdev_type = "tegra-heavy",
802                                         .trip_temp = 100000,
803                                         .trip_type = THERMAL_TRIP_HOT,
804                                         .upper = THERMAL_NO_LIMIT,
805                                         .lower = THERMAL_NO_LIMIT,
806                                 },
807                                 {
808                                         .cdev_type = "tegra-shutdown",
809                                         .trip_temp = 102000,
810                                         .trip_type = THERMAL_TRIP_CRITICAL,
811                                         .upper = THERMAL_NO_LIMIT,
812                                         .lower = THERMAL_NO_LIMIT,
813                                 },
814                         },
815                         .tzp = &macallan_soctherm_therm_cpu_tzp,
816                 },
817                 [THERM_PLL] = {
818                         .zone_enable = true,
819                 },
820         },
821         .throttle = {
822                 [THROTTLE_HEAVY] = {
823                         .devs = {
824                                 [THROTTLE_DEV_CPU] = {
825                                         .enable = 1,
826                                 },
827                         },
828                 },
829                 [THROTTLE_OC4] = {
830                         .throt_mode = BRIEF,
831                         .polarity = 1,
832                         .intr = true,
833                         .devs = {
834                                 [THROTTLE_DEV_CPU] = {
835                                         .enable = true,
836                                         .depth = 50,
837                                 },
838                                 [THROTTLE_DEV_GPU] = {
839                                         .enable = true,
840                                         .depth = 50,
841                                 },
842                         },
843                 },
844         },
845         .tshut_pmu_trip_data = &tpdata_palmas,
846 };
847
848 int __init macallan_soctherm_init(void)
849 {
850         struct board_info board_info;
851         tegra_get_board_info(&board_info);
852         if (board_info.board_id == BOARD_E1545)
853                 tegra_add_cdev_trips(
854                         macallan_soctherm_data.therm[THERM_CPU].trips,
855                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
856         tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
857                         &macallan_soctherm_data.therm[THERM_CPU].num_trips,
858                         6000); /* edp temperature margin */
859         tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
860                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
861         tegra_add_vc_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
862                         &macallan_soctherm_data.therm[THERM_CPU].num_trips);
863
864
865         return tegra11_soctherm_init(&macallan_soctherm_data);
866 }
867
868 static struct edp_manager macallan_sysedp_manager = {
869         .name = "battery",
870         .max = 27300
871 };
872
873 void __init macallan_sysedp_init(void)
874 {
875         struct edp_governor *g;
876         int r;
877
878         if (!IS_ENABLED(CONFIG_EDP_FRAMEWORK))
879                 return;
880
881         if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY)
882                 macallan_sysedp_manager.max = INT_MAX;
883
884         r = edp_register_manager(&macallan_sysedp_manager);
885         WARN_ON(r);
886         if (r)
887                 return;
888
889         /* start with priority governor */
890         g = edp_get_governor("priority");
891         WARN_ON(!g);
892         if (!g)
893                 return;
894
895         r = edp_set_governor(&macallan_sysedp_manager, g);
896         WARN_ON(r);
897 }
898
899 static unsigned int macallan_psydepl_states[] = {
900         9900, 9600, 9300, 9000, 8700, 8400, 8100, 7800,
901         7500, 7200, 6900, 6600, 6300, 6000, 5800, 5600,
902         5400, 5200, 5000, 4800, 4600, 4400, 4200, 4000,
903         3800, 3600, 3400, 3200, 3000, 2800, 2600, 2400,
904         2200, 2000, 1900, 1800, 1700, 1600, 1500, 1400,
905         1300, 1200, 1100, 1000,  900,  800,  700,  600,
906          500,  400,  300,  200,  100,    0
907 };
908
909 static struct psy_depletion_ibat_lut macallan_ibat_lut[] = {
910         {  60,  500 },
911         {  40, 3900 },
912         {   0, 3900 },
913         { -30,    0 }
914 };
915
916 static struct psy_depletion_rbat_lut macallan_rbat_lut[] = {
917         { 0, 95000 }
918 };
919
920 static struct psy_depletion_platform_data macallan_psydepl_pdata = {
921         .power_supply = "battery",
922         .states = macallan_psydepl_states,
923         .num_states = ARRAY_SIZE(macallan_psydepl_states),
924         .e0_index = 16,
925         .r_const = 55000,
926         .vsys_min = 3250000,
927         .vcharge = 4200000,
928         .ibat_nom = 3900,
929         .ibat_lut = macallan_ibat_lut,
930         .rbat_lut = macallan_rbat_lut
931 };
932
933 static struct platform_device macallan_psydepl_device = {
934         .name = "psy_depletion",
935         .id = -1,
936         .dev = { .platform_data = &macallan_psydepl_pdata }
937 };
938
939 void __init macallan_sysedp_psydepl_init(void)
940 {
941         int r;
942
943         r = platform_device_register(&macallan_psydepl_device);
944         WARN_ON(r);
945 }
946
947 static struct tegra_sysedp_corecap macallan_sysedp_corecap[] = {
948         {  1000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
949         {  2000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
950         {  3000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
951         {  4000, {  1000, 240000, 204000}, {  1000, 240000, 204000 } },
952         {  5000, {  1000, 240000, 204000}, {  1000, 240000, 312000 } },
953         {  6000, {  1679, 240000, 312000}, {  1679, 240000, 312000 } },
954         {  7000, {  1843, 240000, 624000}, {  1975, 324000, 408000 } },
955         {  8000, {  2843, 240000, 624000}, {  2306, 420000, 624000 } },
956         {  9000, {  3843, 240000, 624000}, {  2606, 420000, 792000 } },
957         { 10000, {  4565, 240000, 792000}, {  3398, 528000, 792000 } },
958         { 11000, {  5565, 240000, 792000}, {  4398, 528000, 792000 } },
959         { 12000, {  6565, 240000, 792000}, {  4277, 600000, 792000 } },
960         { 13000, {  7565, 240000, 792000}, {  5277, 600000, 792000 } },
961         { 14000, {  8565, 240000, 792000}, {  6277, 600000, 792000 } },
962         { 15000, {  9565, 240000, 792000}, {  7277, 600000, 792000 } },
963         { 16000, { 10565, 240000, 792000}, {  8277, 600000, 792000 } },
964         { 17000, { 11565, 240000, 792000}, {  9277, 600000, 792000 } },
965         { 18000, { 12565, 240000, 792000}, { 10277, 600000, 792000 } },
966         { 19000, { 13565, 240000, 792000}, { 11277, 600000, 792000 } },
967         { 20000, { 14565, 240000, 792000}, { 12277, 600000, 792000 } },
968         { 23000, { 14565, 600000, 792000}, { 14565, 600000, 792000 } }
969 };
970
971 static struct tegra_sysedp_platform_data macallan_sysedp_platdata = {
972         .corecap = macallan_sysedp_corecap,
973         .corecap_size = ARRAY_SIZE(macallan_sysedp_corecap),
974         .core_gain = 130,
975         .init_req_watts = 20000
976 };
977
978 static struct platform_device macallan_sysedp_device = {
979         .name = "tegra_sysedp",
980         .id = -1,
981         .dev = { .platform_data = &macallan_sysedp_platdata }
982 };
983
984 void __init macallan_sysedp_core_init(void)
985 {
986         int r;
987
988         macallan_sysedp_platdata.cpufreq_lim = tegra_get_system_edp_entries(
989                         &macallan_sysedp_platdata.cpufreq_lim_size);
990         if (!macallan_sysedp_platdata.cpufreq_lim) {
991                 WARN_ON(1);
992                 return;
993         }
994
995         r = platform_device_register(&macallan_sysedp_device);
996         WARN_ON(r);
997 }