2 * arch/arm/mach-tegra/board-loki-power.c
4 * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
24 #include <linux/regulator/fixed.h>
25 #include <linux/mfd/palmas.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
29 #include <linux/regulator/tegra-dfll-bypass-regulator.h>
30 #include <linux/power/bq2419x-charger.h>
31 #include <linux/power/bq27441_battery.h>
32 #include <linux/power/power_supply_extcon.h>
33 #include <linux/tegra-fuse.h>
35 #include <mach/irqs.h>
37 #include <mach/pinmux-t12.h>
39 #include <linux/pid_thermal_gov.h>
41 #include <asm/mach-types.h>
45 #include "tegra-board-id.h"
46 #include "board-common.h"
47 #include "board-loki.h"
48 #include "board-pmu-defines.h"
51 #include "tegra-board-id.h"
53 #include "tegra_cl_dvfs.h"
54 #include "tegra11_soctherm.h"
55 #include "tegra3_tsensor.h"
58 #define PMC_CTRL_INTR_LOW (1 << 17)
60 static struct regulator_consumer_supply palmas_smps123_supply[] = {
61 REGULATOR_SUPPLY("vdd_gpu", NULL),
64 static struct regulator_consumer_supply palmas_smps45_supply[] = {
65 REGULATOR_SUPPLY("vdd_core", NULL),
68 static struct regulator_consumer_supply palmas_smps6_supply[] = {
69 REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
72 static struct regulator_consumer_supply palmas_smps7_supply[] = {
73 REGULATOR_SUPPLY("vddio_ddr", NULL),
74 REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
77 static struct regulator_consumer_supply palmas_smps8_supply[] = {
78 REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
79 REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
80 REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
81 REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
82 REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
83 REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
84 REGULATOR_SUPPLY("avdd_osc", NULL),
85 REGULATOR_SUPPLY("vddio_sys", NULL),
86 REGULATOR_SUPPLY("vddio_sys_2", NULL),
87 REGULATOR_SUPPLY("vddio_gmi", NULL),
88 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
89 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
90 REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
91 REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
92 REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
93 REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
94 REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
95 REGULATOR_SUPPLY("vddio_audio", NULL),
96 REGULATOR_SUPPLY("vddio_uart", NULL),
97 REGULATOR_SUPPLY("vddio_bb", NULL),
98 REGULATOR_SUPPLY("vdd_dtv", NULL),
99 REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
100 REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
101 REGULATOR_SUPPLY("vddio_cam", "vi"),
102 REGULATOR_SUPPLY("vlogic", "0-0068"),
103 REGULATOR_SUPPLY("vid", "0-000c"),
104 REGULATOR_SUPPLY("vddio", "0-0077"),
105 REGULATOR_SUPPLY("vif", "2-0048"),
108 static struct regulator_consumer_supply palmas_smps9_supply[] = {
109 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
112 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
113 REGULATOR_SUPPLY("vdd_5v0_cam", NULL),
114 REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
115 REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
118 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
119 REGULATOR_SUPPLY("avdd_pll_m", NULL),
120 REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
121 REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
122 REGULATOR_SUPPLY("avdd_pll_c4", NULL),
123 REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
124 REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
125 REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
126 REGULATOR_SUPPLY("avdd_pll_x", NULL),
127 REGULATOR_SUPPLY("avdd_pll_cg", NULL),
128 REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
129 REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
130 REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
131 REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
132 REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
133 REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
134 REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
137 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
138 REGULATOR_SUPPLY("avdd_lcd", NULL),
139 REGULATOR_SUPPLY("vana", "2-0048"),
142 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
143 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
144 REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
145 REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
146 REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
147 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
148 REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
149 REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
152 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
153 REGULATOR_SUPPLY("vpp_fuse", NULL),
156 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
157 REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
160 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
161 REGULATOR_SUPPLY("vdd_snsr", NULL),
162 REGULATOR_SUPPLY("vdd", "0-000c"),
163 REGULATOR_SUPPLY("vdd", "0-0077"),
164 REGULATOR_SUPPLY("vdd", "0-004c"),
165 REGULATOR_SUPPLY("vdd", "0-0068"),
168 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
169 REGULATOR_SUPPLY("vdd_rtc", NULL),
172 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
173 REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
174 REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
177 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
178 REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
179 REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
180 REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
181 REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
182 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
183 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
184 REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
185 REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
186 REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
187 REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
188 REGULATOR_SUPPLY("hvdd_sata", "tegra-sata.0"),
191 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
193 Check if LDOLN has better jitter on HDMI pll, than LDO5
197 static struct regulator_consumer_supply palmas_regen1_supply[] = {
199 Backup/Boost for smps6: vdd_3v3_sys
203 static struct regulator_consumer_supply palmas_regen2_supply[] = {
205 Backup/Boost for smps10: vdd_5v0_sys
209 PALMAS_REGS_PDATA(smps123, 650, 1400, NULL, 0, 1, 1, NORMAL,
211 PALMAS_REGS_PDATA(smps45, 700, 1250, NULL, 0, 0, 0, NORMAL,
212 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 2500, 0);
213 PALMAS_REGS_PDATA(smps6, 3300, 3300, NULL, 1, 1, 1, NORMAL,
215 PALMAS_REGS_PDATA(smps7, 1350, 1350, NULL, 1, 1, 1, NORMAL,
217 PALMAS_REGS_PDATA(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL,
219 PALMAS_REGS_PDATA(smps9, 2800, 2800, NULL, 0, 0, 1, NORMAL,
221 PALMAS_REGS_PDATA(smps10_out1, 5000, 5000, NULL, 1, 1, 1, 0,
223 PALMAS_REGS_PDATA(ldo1, 1050, 1050, NULL, 0, 0, 1, 0,
224 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
225 PALMAS_REGS_PDATA(ldo2, 2800, 3000, palmas_rails(smps6), 0, 0, 1, 0,
227 PALMAS_REGS_PDATA(ldo3, 1200, 1200, palmas_rails(smps8), 0, 0, 1, 0,
229 PALMAS_REGS_PDATA(ldo4, 1800, 1800, palmas_rails(smps6), 0, 0, 1, 0,
231 PALMAS_REGS_PDATA(ldo5, 1200, 1200, palmas_rails(smps8), 0, 0, 1, 0,
233 PALMAS_REGS_PDATA(ldo6, 2800, 3300, palmas_rails(smps6), 0, 0, 1, 0,
235 PALMAS_REGS_PDATA(ldo8, 900, 900, NULL, 1, 1, 1, 0,
237 PALMAS_REGS_PDATA(ldo9, 1800, 3300, palmas_rails(smps6), 0, 0, 1, 0,
239 PALMAS_REGS_PDATA(ldoln, 2800, 3300, NULL, 0, 0, 1, 0,
241 PALMAS_REGS_PDATA(ldousb, 2300, 3300, NULL, 0, 0, 1, 0,
243 PALMAS_REGS_PDATA(regen1, 3300, 3300, NULL, 0, 0, 0, 0,
245 PALMAS_REGS_PDATA(regen2, 5000, 5000, NULL, 1, 1, 0, 0,
249 #define PALMAS_REG_PDATA(_sname) ®_idata_##_sname
250 static struct regulator_init_data *loki_reg_data[PALMAS_NUM_REGS] = {
252 PALMAS_REG_PDATA(smps123),
254 PALMAS_REG_PDATA(smps45),
256 PALMAS_REG_PDATA(smps6),
257 PALMAS_REG_PDATA(smps7),
258 PALMAS_REG_PDATA(smps8),
259 PALMAS_REG_PDATA(smps9),
261 PALMAS_REG_PDATA(smps10_out1),
262 PALMAS_REG_PDATA(ldo1),
263 PALMAS_REG_PDATA(ldo2),
264 PALMAS_REG_PDATA(ldo3),
265 PALMAS_REG_PDATA(ldo4),
266 PALMAS_REG_PDATA(ldo5),
267 PALMAS_REG_PDATA(ldo6),
269 PALMAS_REG_PDATA(ldo8),
270 PALMAS_REG_PDATA(ldo9),
276 PALMAS_REG_PDATA(ldoln),
277 PALMAS_REG_PDATA(ldousb),
278 PALMAS_REG_PDATA(regen1),
279 PALMAS_REG_PDATA(regen2),
285 #define PALMAS_REG_INIT_DATA(_sname) ®_init_data_##_sname
286 static struct palmas_reg_init *loki_reg_init[PALMAS_NUM_REGS] = {
288 PALMAS_REG_INIT_DATA(smps123),
290 PALMAS_REG_INIT_DATA(smps45),
292 PALMAS_REG_INIT_DATA(smps6),
293 PALMAS_REG_INIT_DATA(smps7),
294 PALMAS_REG_INIT_DATA(smps8),
295 PALMAS_REG_INIT_DATA(smps9),
297 PALMAS_REG_INIT_DATA(smps10_out1),
298 PALMAS_REG_INIT_DATA(ldo1),
299 PALMAS_REG_INIT_DATA(ldo2),
300 PALMAS_REG_INIT_DATA(ldo3),
301 PALMAS_REG_INIT_DATA(ldo4),
302 PALMAS_REG_INIT_DATA(ldo5),
303 PALMAS_REG_INIT_DATA(ldo6),
305 PALMAS_REG_INIT_DATA(ldo8),
306 PALMAS_REG_INIT_DATA(ldo9),
312 PALMAS_REG_INIT_DATA(ldoln),
313 PALMAS_REG_INIT_DATA(ldousb),
314 PALMAS_REG_INIT_DATA(regen1),
315 PALMAS_REG_INIT_DATA(regen2),
321 static struct palmas_pinctrl_config palmas_pincfg[] = {
322 PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
323 PALMAS_PINMUX("vac", "vac", NULL, NULL),
324 PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
325 PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
326 PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
327 PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
328 PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
329 PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
330 PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
331 PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
334 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
335 .pincfg = palmas_pincfg,
336 .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
337 .dvfs1_enable = true,
338 .dvfs2_enable = false,
341 static struct palmas_pmic_platform_data pmic_platform = {
344 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
346 .clk32k_id = PALMAS_CLOCK32KG,
349 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
354 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
355 .connection_name = "palmas-extcon",
356 .enable_vbus_detection = true,
359 static struct palmas_platform_data palmas_pdata = {
360 .gpio_base = PALMAS_TEGRA_GPIO_BASE,
361 .irq_base = PALMAS_TEGRA_IRQ_BASE,
362 .pmic_pdata = &pmic_platform,
363 .pinctrl_pdata = &palmas_pinctrl_pdata,
364 .clk32k_init_data = palmas_clk32k_idata,
365 .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
366 .extcon_pdata = &palmas_extcon_pdata,
369 static struct i2c_board_info palma_device[] = {
371 I2C_BOARD_INFO("tps65913", 0x58),
372 .irq = INT_EXTERNAL_PMU,
373 .platform_data = &palmas_pdata,
377 static struct tegra_suspend_platform_data loki_suspend_data = {
379 .cpu_off_timer = 300,
380 .suspend_mode = TEGRA_SUSPEND_LP0,
381 .core_timer = 0x157e,
382 .core_off_timer = 2000,
383 .corereq_high = true,
384 .sysclkreq_high = true,
385 .cpu_lp2_min_residency = 1000,
386 .min_residency_crail = 20000,
389 int __init loki_suspend_init(void)
391 tegra_init_suspend(&loki_suspend_data);
395 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
396 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
397 REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
400 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
401 REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
404 static struct bq2419x_vbus_platform_data bq2419x_vbus_pdata = {
405 .gpio_otg_iusb = TEGRA_GPIO_PI4,
406 .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
407 .consumer_supplies = bq2419x_vbus_supply,
410 struct bq2419x_charger_platform_data bq2419x_charger_pdata = {
411 .max_charge_current_mA = 3000,
412 .charging_term_current_mA = 100,
413 .consumer_supplies = bq2419x_batt_supply,
414 .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
416 .rtc_alarm_time = 3600,
417 .chg_restart_time = 1800,
420 struct bq2419x_platform_data bq2419x_pdata = {
421 .vbus_pdata = &bq2419x_vbus_pdata,
422 .bcharger_pdata = &bq2419x_charger_pdata,
425 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
427 I2C_BOARD_INFO("bq2419x", 0x6b),
428 .irq = TEGRA_GPIO_PJ0,
429 .platform_data = &bq2419x_pdata,
433 static struct bq27441_platform_data bq27441_pdata = {
434 .full_capacity_in_mAh = 7350,
435 .tz_name = "battery-temp",
438 static struct i2c_board_info loki_i2c_board_info_bq27441[] = {
440 I2C_BOARD_INFO("bq27441", 0x55),
441 .platform_data = &bq27441_pdata,
445 static struct power_supply_extcon_plat_data extcon_pdata = {
446 .extcon_name = "tegra-udc",
449 static struct platform_device power_supply_extcon_device = {
450 .name = "power-supply-extcon",
453 .platform_data = &extcon_pdata,
457 /* Macro for defining fixed regulator sub device data */
458 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
459 #define FIXED_REG(_id, _var, _name, _in_supply, \
460 _always_on, _boot_on, _gpio_nr, _open_drain, \
461 _active_high, _boot_state, _millivolts, _sdelay) \
462 static struct regulator_init_data ri_data_##_var = \
464 .supply_regulator = _in_supply, \
465 .num_consumer_supplies = \
466 ARRAY_SIZE(fixed_reg_en_##_name##_supply), \
467 .consumer_supplies = fixed_reg_en_##_name##_supply, \
469 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
470 REGULATOR_MODE_STANDBY), \
471 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
472 REGULATOR_CHANGE_STATUS | \
473 REGULATOR_CHANGE_VOLTAGE), \
474 .always_on = _always_on, \
475 .boot_on = _boot_on, \
478 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
480 .supply_name = FIXED_SUPPLY(_name), \
481 .microvolts = _millivolts * 1000, \
483 .gpio_is_open_drain = _open_drain, \
484 .enable_high = _active_high, \
485 .enabled_at_boot = _boot_state, \
486 .init_data = &ri_data_##_var, \
487 .startup_delay = _sdelay \
489 static struct platform_device fixed_reg_en_##_var##_dev = { \
490 .name = "reg-fixed-voltage", \
493 .platform_data = &fixed_reg_en_##_var##_pdata, \
497 /* Always ON Battery regulator */
498 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
499 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
500 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
501 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
502 REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
505 static struct regulator_consumer_supply fixed_reg_en_modem_3v3_supply[] = {
506 REGULATOR_SUPPLY("vdd_wwan_mdm", NULL),
509 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
510 REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
513 static struct regulator_consumer_supply fixed_reg_en_vdd_sd_slot_supply[] = {
514 REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
517 static struct regulator_consumer_supply fixed_reg_en_1v8_ts_supply[] = {
518 REGULATOR_SUPPLY("dvdd", "spi0.0"),
521 static struct regulator_consumer_supply fixed_reg_en_3v3_ts_supply[] = {
522 REGULATOR_SUPPLY("avdd", "spi0.0"),
525 static struct regulator_consumer_supply fixed_reg_en_1v8_display_supply[] = {
526 REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
529 static struct regulator_consumer_supply fixed_reg_en_vdd_cpu_fixed_supply[] = {
530 REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
533 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_supply[] = {
534 REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
537 /* VDD_3V3_COM controled by Wifi */
538 static struct regulator_consumer_supply fixed_reg_en_com_3v3_supply[] = {
539 REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
540 REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
543 /* VDD_1v8_COM controled by Wifi */
544 static struct regulator_consumer_supply fixed_reg_en_com_1v8_supply[] = {
545 REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
546 REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
549 /* EN_1V8_DISPLAY From TEGRA_GPIO_PU4 */
550 static struct regulator_consumer_supply fixed_reg_en_dvdd_lcd_supply[] = {
551 REGULATOR_SUPPLY("dvdd_lcd", NULL),
554 FIXED_REG(0, battery, battery, NULL,
556 false, true, 0, 3300, 0);
558 FIXED_REG(1, modem_3v3, modem_3v3, palmas_rails(smps10_out1),
559 0, 0, TEGRA_GPIO_PS2,
560 false, true, 0, 3700, 0);
562 FIXED_REG(2, vdd_hdmi_5v0, vdd_hdmi_5v0, palmas_rails(smps6),
563 0, 0, TEGRA_GPIO_PS5,
564 false, true, 0, 5000, 5000);
566 FIXED_REG(3, vdd_sd_slot, vdd_sd_slot, palmas_rails(smps6),
567 0, 0, TEGRA_GPIO_PR0,
568 false, true, 0, 3300, 0);
570 FIXED_REG(4, 1v8_ts, 1v8_ts, palmas_rails(smps8),
571 0, 0, TEGRA_GPIO_PK1,
572 false, true, 0, 1800, 0);
574 FIXED_REG(5, 3v3_ts, 3v3_ts, palmas_rails(smps6),
575 0, 0, TEGRA_GPIO_PH0,
576 false, true, 0, 3300, 0);
578 FIXED_REG(6, 1v8_display, 1v8_display, NULL,
580 false, true, 0, 1800, 0);
582 FIXED_REG(7, vdd_cpu_fixed, vdd_cpu_fixed, NULL,
584 false, true, 0, 1000, 0);
586 FIXED_REG(8, lcd_bl, lcd_bl,
588 TEGRA_GPIO_PH2, false, true, 1, 5000, 1000);
590 FIXED_REG(9, com_3v3, com_3v3,
591 palmas_rails(smps6), 0, 0,
592 TEGRA_GPIO_PX1, false, true, 0, 3300, 1000);
594 FIXED_REG(10, com_1v8, com_1v8,
595 palmas_rails(smps8), 0, 0,
596 TEGRA_GPIO_PX7, false, true, 0, 1800, 1000);
598 FIXED_REG(11, dvdd_lcd, dvdd_lcd,
599 palmas_rails(smps8), 0, 0,
600 TEGRA_GPIO_PU4, false, true, 1, 1800, 0);
603 * Creating fixed regulator device tables
605 #define ADD_FIXED_REG(_name) (&fixed_reg_en_##_name##_dev)
606 #define LOKI_E2545_FIXED_REG \
607 ADD_FIXED_REG(battery), \
608 ADD_FIXED_REG(modem_3v3), \
609 ADD_FIXED_REG(vdd_hdmi_5v0), \
610 ADD_FIXED_REG(vdd_sd_slot), \
611 ADD_FIXED_REG(1v8_ts), \
612 ADD_FIXED_REG(3v3_ts), \
613 ADD_FIXED_REG(1v8_display), \
614 ADD_FIXED_REG(vdd_cpu_fixed), \
615 ADD_FIXED_REG(lcd_bl), \
616 ADD_FIXED_REG(com_3v3), \
617 ADD_FIXED_REG(com_1v8), \
618 ADD_FIXED_REG(dvdd_lcd),
621 static struct platform_device *fixed_reg_devs_e2545[] = {
624 /************************ LOKI CL-DVFS DATA *********************/
625 #define LOKI_CPU_VDD_MAP_SIZE 33
626 #define LOKI_CPU_VDD_MIN_UV 704000
627 #define LOKI_CPU_VDD_STEP_UV 19200
628 #define LOKI_CPU_VDD_STEP_US 80
630 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
631 /* loki board parameters for cpu dfll */
632 static struct tegra_cl_dvfs_cfg_param loki_cl_dvfs_param = {
633 .sample_rate = 50000,
635 .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
640 .droop_cut_value = 0xF,
641 .droop_restore_ramp = 0x0,
642 .scale_out_ramp = 0x0,
645 /* loki RT8812C volatge map */
646 static struct voltage_reg_map loki_cpu_vdd_map[LOKI_CPU_VDD_MAP_SIZE];
647 static inline int loki_fill_reg_map(int nominal_mv)
649 int i, uv, nominal_uv = 0;
650 for (i = 0; i < LOKI_CPU_VDD_MAP_SIZE; i++) {
651 loki_cpu_vdd_map[i].reg_value = i;
652 loki_cpu_vdd_map[i].reg_uV = uv =
653 LOKI_CPU_VDD_MIN_UV + LOKI_CPU_VDD_STEP_UV * i;
654 if (!nominal_uv && uv >= nominal_mv * 1000)
660 /* loki dfll bypass device for legacy dvfs control */
661 static struct regulator_consumer_supply loki_dfll_bypass_consumers[] = {
662 REGULATOR_SUPPLY("vdd_cpu", NULL),
664 DFLL_BYPASS(loki, LOKI_CPU_VDD_MIN_UV, LOKI_CPU_VDD_STEP_UV,
665 LOKI_CPU_VDD_MAP_SIZE, LOKI_CPU_VDD_STEP_US, -1);
667 static struct tegra_cl_dvfs_platform_data loki_cl_dvfs_data = {
668 .dfll_clk_name = "dfll_cpu",
669 .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
671 .pwm_rate = 12750000,
672 .pwm_bus = TEGRA_CL_DVFS_PWM_1WIRE_BUFFER,
673 .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
674 .out_gpio = TEGRA_GPIO_PU6,
675 .out_enable_high = false,
676 #ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
677 .dfll_bypass_dev = &loki_dfll_bypass_dev,
680 .vdd_map = loki_cpu_vdd_map,
681 .vdd_map_size = LOKI_CPU_VDD_MAP_SIZE,
683 .cfg_param = &loki_cl_dvfs_param,
686 static void loki_suspend_dfll_bypass(void)
688 __gpio_set_value(TEGRA_GPIO_PU6, 1); /* tristate external PWM buffer */
691 static void loki_resume_dfll_bypass(void)
693 __gpio_set_value(TEGRA_GPIO_PU6, 0); /* enable PWM buffer operations */
695 static int __init loki_cl_dvfs_init(void)
697 struct tegra_cl_dvfs_platform_data *data = NULL;
698 int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
701 v = loki_fill_reg_map(v);
702 data = &loki_cl_dvfs_data;
703 if (data->u.pmu_pwm.dfll_bypass_dev) {
704 /* this has to be exact to 1uV level from table */
705 loki_dfll_bypass_init_data.constraints.init_uV = v;
706 loki_suspend_data.suspend_dfll_bypass =
707 loki_suspend_dfll_bypass;
708 loki_suspend_data.resume_dfll_bypass =
709 loki_resume_dfll_bypass;
711 (void)loki_dfll_bypass_dev;
717 data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
718 tegra_cl_dvfs_device.dev.platform_data = data;
719 platform_device_register(&tegra_cl_dvfs_device);
724 static inline int loki_cl_dvfs_init()
728 int __init loki_rail_alignment_init(void)
731 tegra12x_vdd_cpu_align(LOKI_CPU_VDD_STEP_UV,
732 LOKI_CPU_VDD_MIN_UV);
736 int __init loki_regulator_init(void)
738 void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
742 /* TPS65913: Normal state of INT request line is LOW.
743 * configure the power management controller to trigger PMU
744 * interrupts when HIGH.
746 pmc_ctrl = readl(pmc + PMC_CTRL);
747 writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
748 for (i = 0; i < PALMAS_NUM_REGS ; i++) {
749 pmic_platform.reg_data[i] = loki_reg_data[i];
750 pmic_platform.reg_init[i] = loki_reg_init[i];
752 /* Set vdd_gpu init uV to 1V */
753 reg_idata_smps123.constraints.init_uV = 1000000;
754 reg_idata_smps9.constraints.enable_time = 250;
756 bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
757 i2c_register_board_info(4, palma_device,
758 ARRAY_SIZE(palma_device));
759 i2c_register_board_info(0, bq2419x_boardinfo, 1);
760 i2c_register_board_info(0, loki_i2c_board_info_bq27441,
761 ARRAY_SIZE(loki_i2c_board_info_bq27441));
762 platform_device_register(&power_supply_extcon_device);
768 static int __init loki_fixed_regulator_init(void)
770 struct board_info pmu_board_info;
771 struct board_info bi;
774 if (!of_machine_is_compatible("nvidia,loki"))
777 tegra_get_board_info(&bi);
778 tegra_get_pmu_board_info(&pmu_board_info);
780 if (bi.board_id == BOARD_P2530) {
781 fixed_reg_en_vdd_hdmi_5v0_pdata.gpio = TEGRA_GPIO_PFF0;
782 fixed_reg_en_vdd_hdmi_5v0_pdata.enable_high = false;
784 if (pmu_board_info.board_id == BOARD_E2545)
785 return platform_add_devices(fixed_reg_devs_e2545,
786 ARRAY_SIZE(fixed_reg_devs_e2545));
791 subsys_initcall_sync(loki_fixed_regulator_init);
792 int __init loki_edp_init(void)
794 unsigned int regulator_mA;
796 regulator_mA = get_maximum_cpu_current_supported();
798 regulator_mA = 16000;
800 pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
801 tegra_init_cpu_edp_limits(regulator_mA);
803 /* gpu maximum current */
804 regulator_mA = 12000;
805 pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
807 tegra_init_gpu_edp_limits(regulator_mA);
811 static struct pid_thermal_gov_params soctherm_pid_params = {
812 .max_err_temp = 9000,
813 .max_err_gain = 1000,
818 .up_compensation = 20,
819 .down_compensation = 20,
822 static struct thermal_zone_params soctherm_tzp = {
823 .governor_name = "pid_thermal_gov",
824 .governor_params = &soctherm_pid_params,
827 static struct tegra_tsensor_pmu_data tpdata_palmas = {
830 .controller_type = 0,
831 .pmu_i2c_addr = 0x58,
832 .i2c_controller_id = 4,
833 .poweroff_reg_addr = 0xa0,
834 .poweroff_reg_data = 0x0,
837 static struct soctherm_platform_data loki_soctherm_data = {
841 .passive_delay = 1000,
842 .hotspot_offset = 6000,
846 .cdev_type = "tegra-shutdown",
848 .trip_type = THERMAL_TRIP_CRITICAL,
849 .upper = THERMAL_NO_LIMIT,
850 .lower = THERMAL_NO_LIMIT,
853 .cdev_type = "tegra-heavy",
855 .trip_type = THERMAL_TRIP_HOT,
856 .upper = THERMAL_NO_LIMIT,
857 .lower = THERMAL_NO_LIMIT,
860 .cdev_type = "tegra-balanced",
862 .trip_type = THERMAL_TRIP_PASSIVE,
863 .upper = THERMAL_NO_LIMIT,
864 .lower = THERMAL_NO_LIMIT,
867 .tzp = &soctherm_tzp,
871 .passive_delay = 1000,
872 .hotspot_offset = 6000,
876 .cdev_type = "tegra-shutdown",
878 .trip_type = THERMAL_TRIP_CRITICAL,
879 .upper = THERMAL_NO_LIMIT,
880 .lower = THERMAL_NO_LIMIT,
883 .cdev_type = "tegra-balanced",
885 .trip_type = THERMAL_TRIP_PASSIVE,
886 .upper = THERMAL_NO_LIMIT,
887 .lower = THERMAL_NO_LIMIT,
891 .cdev_type = "gk20a_cdev",
893 .trip_type = THERMAL_TRIP_PASSIVE,
894 .upper = THERMAL_NO_LIMIT,
895 .lower = THERMAL_NO_LIMIT,
898 .cdev_type = "tegra-heavy",
900 .trip_type = THERMAL_TRIP_HOT,
901 .upper = THERMAL_NO_LIMIT,
902 .lower = THERMAL_NO_LIMIT,
906 .tzp = &soctherm_tzp,
913 .cdev_type = "tegra-shutdown",
914 .trip_temp = 103000, /* = GPU shut */
915 .trip_type = THERMAL_TRIP_CRITICAL,
916 .upper = THERMAL_NO_LIMIT,
917 .lower = THERMAL_NO_LIMIT,
929 [THROTTLE_DEV_CPU] = {
933 [THROTTLE_DEV_GPU] = {
935 .throttling_depth = "heavy_throttling",
940 .tshut_pmu_trip_data = &tpdata_palmas,
943 int __init loki_soctherm_init(void)
945 s32 base_cp, shft_cp;
946 u32 base_ft, shft_ft;
948 /* do this only for supported CP,FT fuses */
949 if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
950 (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
951 tegra_platform_edp_init(
952 loki_soctherm_data.therm[THERM_CPU].trips,
953 &loki_soctherm_data.therm[THERM_CPU].num_trips,
954 8000); /* edp temperature margin */
955 tegra_platform_gpu_edp_init(
956 loki_soctherm_data.therm[THERM_GPU].trips,
957 &loki_soctherm_data.therm[THERM_GPU].num_trips,
960 loki_soctherm_data.therm[THERM_CPU].trips,
961 &loki_soctherm_data.therm[THERM_CPU].num_trips);
962 tegra_add_tgpu_trips(
963 loki_soctherm_data.therm[THERM_GPU].trips,
964 &loki_soctherm_data.therm[THERM_GPU].num_trips);
967 return tegra11_soctherm_init(&loki_soctherm_data);