ARM: tegra12: dvfs: Add core rail Vmax trip-points
[linux-3.10.git] / arch / arm / mach-tegra / board-loki-power.c
1 /*
2  * arch/arm/mach-tegra/board-loki-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/io.h>
24 #include <linux/regulator/fixed.h>
25 #include <linux/mfd/palmas.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
29 #include <linux/regulator/tegra-dfll-bypass-regulator.h>
30 #include <linux/power/bq2419x-charger.h>
31 #include <linux/power/bq27441_battery.h>
32 #include <linux/power/power_supply_extcon.h>
33 #include <linux/tegra-fuse.h>
34
35 #include <mach/irqs.h>
36 #include <mach/edp.h>
37 #include <mach/pinmux-t12.h>
38
39 #include <linux/pid_thermal_gov.h>
40
41 #include <asm/mach-types.h>
42
43 #include "pm.h"
44 #include "board.h"
45 #include "tegra-board-id.h"
46 #include "board-common.h"
47 #include "board-loki.h"
48 #include "board-pmu-defines.h"
49 #include "devices.h"
50 #include "iomap.h"
51 #include "tegra-board-id.h"
52 #include "dvfs.h"
53 #include "tegra_cl_dvfs.h"
54 #include "tegra11_soctherm.h"
55 #include "tegra3_tsensor.h"
56
57 #define PMC_CTRL                0x0
58 #define PMC_CTRL_INTR_LOW       (1 << 17)
59
60 static struct regulator_consumer_supply palmas_smps123_supply[] = {
61         REGULATOR_SUPPLY("vdd_gpu", NULL),
62 };
63
64 static struct regulator_consumer_supply palmas_smps45_supply[] = {
65         REGULATOR_SUPPLY("vdd_core", NULL),
66 };
67
68 static struct regulator_consumer_supply palmas_smps6_supply[] = {
69         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
70 };
71
72 static struct regulator_consumer_supply palmas_smps7_supply[] = {
73         REGULATOR_SUPPLY("vddio_ddr", NULL),
74         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
75 };
76
77 static struct regulator_consumer_supply palmas_smps8_supply[] = {
78         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
79         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
80         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
81         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
82         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
83         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
84         REGULATOR_SUPPLY("avdd_osc", NULL),
85         REGULATOR_SUPPLY("vddio_sys", NULL),
86         REGULATOR_SUPPLY("vddio_sys_2", NULL),
87         REGULATOR_SUPPLY("vddio_gmi", NULL),
88         REGULATOR_SUPPLY("pwrdet_nand", NULL),
89         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
90         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
91         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
92         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
93         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
94         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
95         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
96         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
97         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
98         REGULATOR_SUPPLY("vddio_audio", NULL),
99         REGULATOR_SUPPLY("pwrdet_audio", NULL),
100         REGULATOR_SUPPLY("vddio_uart", NULL),
101         REGULATOR_SUPPLY("pwrdet_uart", NULL),
102         REGULATOR_SUPPLY("vddio_bb", NULL),
103         REGULATOR_SUPPLY("pwrdet_bb", NULL),
104         REGULATOR_SUPPLY("vdd_dtv", NULL),
105         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
106         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
107         REGULATOR_SUPPLY("vddio_cam", "vi"),
108         REGULATOR_SUPPLY("pwrdet_cam", NULL),
109         REGULATOR_SUPPLY("vlogic", "0-0068"),
110         REGULATOR_SUPPLY("vid", "0-000c"),
111         REGULATOR_SUPPLY("vddio", "0-0077"),
112         REGULATOR_SUPPLY("vif", "2-0048"),
113         REGULATOR_SUPPLY("vif2", "2-0021"),
114 };
115
116 static struct regulator_consumer_supply palmas_smps9_supply[] = {
117         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
118 };
119
120 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
121         REGULATOR_SUPPLY("vdd_5v0_cam", NULL),
122         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
123         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
124 };
125
126 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
127         REGULATOR_SUPPLY("avdd_pll_m", NULL),
128         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
129         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
130         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
131         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
132         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
133         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
134         REGULATOR_SUPPLY("avdd_pll_x", NULL),
135         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
136         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
137         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
138         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
139         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
140         REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
141         REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
142         REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
143 };
144
145 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
146         REGULATOR_SUPPLY("avdd_lcd", NULL),
147         REGULATOR_SUPPLY("vana", "2-0048"),
148 };
149
150 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
151         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
152         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
153         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
154         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
155         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
156         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
157         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
158 };
159
160 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
161         REGULATOR_SUPPLY("vpp_fuse", NULL),
162 };
163
164 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
165         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
166 };
167
168 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
169         REGULATOR_SUPPLY("vdd_snsr", NULL),
170         REGULATOR_SUPPLY("vdd", "0-000c"),
171         REGULATOR_SUPPLY("vdd", "0-0077"),
172         REGULATOR_SUPPLY("vdd", "0-004c"),
173         REGULATOR_SUPPLY("vdd", "0-0068"),
174         REGULATOR_SUPPLY("vana", "2-0021"),
175 };
176
177 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
178         REGULATOR_SUPPLY("vdd_rtc", NULL),
179 };
180
181 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
182         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
183         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
184 };
185
186 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
187         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
188         REGULATOR_SUPPLY("pwrdet_hv", NULL),
189         REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
190         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
191         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
192         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
193         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
194         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
195         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
196         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
197         REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
198         REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
199         REGULATOR_SUPPLY("hvdd_sata", "tegra-sata.0"),
200 };
201
202 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
203         /*
204         Check if LDOLN has better jitter on HDMI pll, than LDO5
205         */
206 };
207
208 static struct regulator_consumer_supply palmas_regen1_supply[] = {
209         /*
210         Backup/Boost for smps6: vdd_3v3_sys
211         */
212 };
213
214 static struct regulator_consumer_supply palmas_regen2_supply[] = {
215         /*
216         Backup/Boost for smps10: vdd_5v0_sys
217         */
218 };
219
220 PALMAS_REGS_PDATA(smps123, 650,  1400, NULL, 0, 1, 1, NORMAL,
221                 0, 0, 0, 0, 0);
222 PALMAS_REGS_PDATA(smps45, 700,  1250, NULL, 0, 0, 0, NORMAL,
223                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 2500, 0);
224 PALMAS_REGS_PDATA(smps6, 3300,  3300, NULL, 1, 1, 1, NORMAL,
225                 0, 0, 0, 0, 0);
226 PALMAS_REGS_PDATA(smps7, 1350,  1350, NULL, 1, 1, 1, NORMAL,
227                 0, 0, 0, 0, 0);
228 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
229                 0, 0, 0, 0, 0);
230 PALMAS_REGS_PDATA(smps9, 2800,  2800, NULL, 0, 0, 1, NORMAL,
231                 0, 0, 0, 0, 0);
232 PALMAS_REGS_PDATA(smps10_out1, 5000,  5000, NULL, 1, 1, 1, 0,
233                 0, 0, 0, 0, 0);
234 PALMAS_REGS_PDATA(ldo1, 1050,  1050, NULL, 0, 0, 1, 0,
235                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
236 PALMAS_REGS_PDATA(ldo2, 2800,  3000, palmas_rails(smps6), 0, 0, 1, 0,
237                 0, 0, 0, 0, 0);
238 PALMAS_REGS_PDATA(ldo3, 1200,  1200, palmas_rails(smps8), 0, 0, 1, 0,
239                 0, 0, 0, 0, 0);
240 PALMAS_REGS_PDATA(ldo4, 1800,  1800, palmas_rails(smps6), 0, 0, 1, 0,
241                 0, 0, 0, 0, 0);
242 PALMAS_REGS_PDATA(ldo5, 1200,  1200, palmas_rails(smps8), 0, 0, 1, 0,
243                 0, 0, 0, 0, 0);
244 PALMAS_REGS_PDATA(ldo6, 2800,  2800, palmas_rails(smps6), 0, 0, 1, 0,
245                 0, 0, 0, 0, 0);
246 PALMAS_REGS_PDATA(ldo8, 900,  900, NULL, 1, 1, 1, 0,
247                 0, 0, 0, 0, 0);
248 PALMAS_REGS_PDATA(ldo9, 1800,  3300, palmas_rails(smps6), 0, 0, 1, 0,
249                 0, 0, 0, 0, 0);
250 PALMAS_REGS_PDATA(ldoln, 2800, 3300, NULL, 0, 0, 1, 0,
251                 0, 0, 0, 0, 0);
252 PALMAS_REGS_PDATA(ldousb, 2300,  3300, NULL, 0, 0, 1, 0,
253                 0, 0, 0, 0, 0);
254 PALMAS_REGS_PDATA(regen1, 3300,  3300, NULL, 0, 0, 0, 0,
255                 0, 0, 0, 0, 0);
256 PALMAS_REGS_PDATA(regen2, 5000,  5000, NULL, 1, 1, 0, 0,
257                 0, 0, 0, 0, 0);
258
259
260 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
261 static struct regulator_init_data *loki_reg_data[PALMAS_NUM_REGS] = {
262         NULL,
263         PALMAS_REG_PDATA(smps123),
264         NULL,
265         PALMAS_REG_PDATA(smps45),
266         NULL,
267         PALMAS_REG_PDATA(smps6),
268         PALMAS_REG_PDATA(smps7),
269         PALMAS_REG_PDATA(smps8),
270         PALMAS_REG_PDATA(smps9),
271         NULL,
272         PALMAS_REG_PDATA(smps10_out1),
273         PALMAS_REG_PDATA(ldo1),
274         PALMAS_REG_PDATA(ldo2),
275         PALMAS_REG_PDATA(ldo3),
276         PALMAS_REG_PDATA(ldo4),
277         PALMAS_REG_PDATA(ldo5),
278         PALMAS_REG_PDATA(ldo6),
279         NULL,
280         PALMAS_REG_PDATA(ldo8),
281         PALMAS_REG_PDATA(ldo9),
282         NULL,
283         NULL,
284         NULL,
285         NULL,
286         NULL,
287         PALMAS_REG_PDATA(ldoln),
288         PALMAS_REG_PDATA(ldousb),
289         PALMAS_REG_PDATA(regen1),
290         PALMAS_REG_PDATA(regen2),
291         NULL,
292         NULL,
293         NULL,
294 };
295
296 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
297 static struct palmas_reg_init *loki_reg_init[PALMAS_NUM_REGS] = {
298         NULL,
299         PALMAS_REG_INIT_DATA(smps123),
300         NULL,
301         PALMAS_REG_INIT_DATA(smps45),
302         NULL,
303         PALMAS_REG_INIT_DATA(smps6),
304         PALMAS_REG_INIT_DATA(smps7),
305         PALMAS_REG_INIT_DATA(smps8),
306         PALMAS_REG_INIT_DATA(smps9),
307         NULL,
308         PALMAS_REG_INIT_DATA(smps10_out1),
309         PALMAS_REG_INIT_DATA(ldo1),
310         PALMAS_REG_INIT_DATA(ldo2),
311         PALMAS_REG_INIT_DATA(ldo3),
312         PALMAS_REG_INIT_DATA(ldo4),
313         PALMAS_REG_INIT_DATA(ldo5),
314         PALMAS_REG_INIT_DATA(ldo6),
315         NULL,
316         PALMAS_REG_INIT_DATA(ldo8),
317         PALMAS_REG_INIT_DATA(ldo9),
318         NULL,
319         NULL,
320         NULL,
321         NULL,
322         NULL,
323         PALMAS_REG_INIT_DATA(ldoln),
324         PALMAS_REG_INIT_DATA(ldousb),
325         PALMAS_REG_INIT_DATA(regen1),
326         PALMAS_REG_INIT_DATA(regen2),
327         NULL,
328         NULL,
329         NULL,
330 };
331
332 #define PALMAS_GPADC_IIO_MAP(_ch, _dev_name, _name)             \
333         {                                                       \
334                 .adc_channel_label = PALMAS_DATASHEET_NAME(_ch),\
335                 .consumer_dev_name = _dev_name,                 \
336                 .consumer_channel = _name,                      \
337         }
338
339 static struct iio_map palmas_adc_iio_maps[] = {
340         PALMAS_GPADC_IIO_MAP(IN1, "generic-adc-thermal.0", "thermistor"),
341         PALMAS_GPADC_IIO_MAP(IN3, "generic-adc-thermal.1", "tdiode"),
342         PALMAS_GPADC_IIO_MAP(NULL, NULL, NULL),
343 };
344
345 static struct palmas_gpadc_platform_data palmas_adc_pdata = {
346         /* If ch3_dual_current is true, it will measure ch3 input signal with
347          * ch3_current and the next current of ch3_current.
348          * So this system will use 400uA and 800uA for ch3 measurement. */
349         .ch3_current = 400,     /* 0uA, 10uA, 400uA, 800uA */
350         .ch3_dual_current = true,
351         .extended_delay = true,
352         .iio_maps = palmas_adc_iio_maps,
353 };
354
355 static struct palmas_pinctrl_config palmas_pincfg[] = {
356         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
357         PALMAS_PINMUX("vac", "vac", NULL, NULL),
358         PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
359         PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
360         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
361         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
362         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
363         PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
364         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
365         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
366 };
367
368 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
369         .pincfg = palmas_pincfg,
370         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
371         .dvfs1_enable = true,
372         .dvfs2_enable = false,
373 };
374
375 static struct palmas_pmic_platform_data pmic_platform = {
376 };
377
378 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
379         {
380                 .clk32k_id = PALMAS_CLOCK32KG,
381                 .enable = true,
382         }, {
383                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
384                 .enable = true,
385         },
386 };
387
388 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
389         .connection_name = "palmas-extcon",
390         .enable_vbus_detection = true,
391 };
392
393 static struct palmas_platform_data palmas_pdata = {
394         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
395         .irq_base = PALMAS_TEGRA_IRQ_BASE,
396         .pmic_pdata = &pmic_platform,
397         .gpadc_pdata = &palmas_adc_pdata,
398         .pinctrl_pdata = &palmas_pinctrl_pdata,
399         .clk32k_init_data =  palmas_clk32k_idata,
400         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
401         .extcon_pdata = &palmas_extcon_pdata,
402 };
403
404 static struct i2c_board_info palma_device[] = {
405         {
406                 I2C_BOARD_INFO("tps65913", 0x58),
407                 .irq            = INT_EXTERNAL_PMU,
408                 .platform_data  = &palmas_pdata,
409         },
410 };
411
412 static struct tegra_suspend_platform_data loki_suspend_data = {
413         .cpu_timer      = 2000,
414         .cpu_off_timer  = 300,
415         .suspend_mode   = TEGRA_SUSPEND_LP0,
416         .core_timer     = 0x157e,
417         .core_off_timer = 2000,
418         .corereq_high   = true,
419         .sysclkreq_high = true,
420         .cpu_lp2_min_residency = 1000,
421         .min_residency_crail = 20000,
422 };
423
424 int __init loki_suspend_init(void)
425 {
426         tegra_init_suspend(&loki_suspend_data);
427         return 0;
428 }
429
430 static struct regulator_consumer_supply bq2419x_vbus_supply[] = {
431         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
432         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
433 };
434
435 static struct regulator_consumer_supply bq2419x_batt_supply[] = {
436         REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"),
437 };
438
439 static struct bq2419x_vbus_platform_data bq2419x_vbus_pdata = {
440         .gpio_otg_iusb = TEGRA_GPIO_PI4,
441         .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply),
442         .consumer_supplies = bq2419x_vbus_supply,
443 };
444
445 struct bq2419x_charger_platform_data bq2419x_charger_pdata = {
446         .max_charge_current_mA = 3000,
447         .charging_term_current_mA = 100,
448         .consumer_supplies = bq2419x_batt_supply,
449         .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply),
450         .wdt_timeout    = 40,
451         .rtc_alarm_time = 3600,
452         .chg_restart_time = 1800,
453 };
454
455 struct bq2419x_platform_data bq2419x_pdata = {
456         .vbus_pdata = &bq2419x_vbus_pdata,
457         .bcharger_pdata = &bq2419x_charger_pdata,
458 };
459
460 static struct i2c_board_info __initdata bq2419x_boardinfo[] = {
461         {
462                 I2C_BOARD_INFO("bq2419x", 0x6b),
463                 .irq = TEGRA_GPIO_PJ0,
464                 .platform_data  = &bq2419x_pdata,
465         },
466 };
467
468 static struct bq27441_platform_data bq27441_pdata = {
469         .full_capacity_in_mAh = 7350,
470         .tz_name = "battery-temp",
471 };
472
473 static struct i2c_board_info loki_i2c_board_info_bq27441[] = {
474         {
475                 I2C_BOARD_INFO("bq27441", 0x55),
476                 .platform_data = &bq27441_pdata,
477         },
478 };
479
480 static struct power_supply_extcon_plat_data extcon_pdata = {
481         .extcon_name = "tegra-udc",
482 };
483
484 static struct platform_device power_supply_extcon_device = {
485         .name   = "power-supply-extcon",
486         .id     = -1,
487         .dev    = {
488                 .platform_data = &extcon_pdata,
489         },
490 };
491
492 /* Macro for defining fixed regulator sub device data */
493 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
494 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
495         _always_on, _boot_on, _gpio_nr, _open_drain,            \
496         _active_high, _boot_state, _millivolts, _sdelay)        \
497 static struct regulator_init_data ri_data_##_var =              \
498 {                                                               \
499         .supply_regulator = _in_supply,                         \
500         .num_consumer_supplies =                                \
501         ARRAY_SIZE(fixed_reg_en_##_name##_supply),              \
502         .consumer_supplies = fixed_reg_en_##_name##_supply,     \
503         .constraints = {                                        \
504                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
505                                 REGULATOR_MODE_STANDBY),        \
506                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
507                                 REGULATOR_CHANGE_STATUS |       \
508                                 REGULATOR_CHANGE_VOLTAGE),      \
509                 .always_on = _always_on,                        \
510                 .boot_on = _boot_on,                            \
511         },                                                      \
512 };                                                              \
513 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata =        \
514 {                                                               \
515         .supply_name = FIXED_SUPPLY(_name),                     \
516         .microvolts = _millivolts * 1000,                       \
517         .gpio = _gpio_nr,                                       \
518         .gpio_is_open_drain = _open_drain,                      \
519         .enable_high = _active_high,                            \
520         .enabled_at_boot = _boot_state,                         \
521         .init_data = &ri_data_##_var,                           \
522         .startup_delay = _sdelay                                \
523 };                                                              \
524 static struct platform_device fixed_reg_en_##_var##_dev = {     \
525         .name = "reg-fixed-voltage",                            \
526         .id = _id,                                              \
527         .dev = {                                                \
528                 .platform_data = &fixed_reg_en_##_var##_pdata,  \
529         },                                                      \
530 }
531
532 /* Always ON Battery regulator */
533 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
534                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
535                 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
536                 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
537                 REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
538 };
539
540 static struct regulator_consumer_supply fixed_reg_en_modem_3v3_supply[] = {
541         REGULATOR_SUPPLY("vdd_wwan_mdm", NULL),
542 };
543
544 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
545         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
546 };
547
548 static struct regulator_consumer_supply fixed_reg_en_vdd_sd_slot_supply[] = {
549         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
550 };
551
552 static struct regulator_consumer_supply fixed_reg_en_1v8_ts_supply[] = {
553         REGULATOR_SUPPLY("dvdd", "spi0.0"),
554 };
555
556 static struct regulator_consumer_supply fixed_reg_en_3v3_ts_supply[] = {
557         REGULATOR_SUPPLY("avdd", "spi0.0"),
558 };
559
560 static struct regulator_consumer_supply fixed_reg_en_1v8_display_supply[] = {
561         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
562 };
563
564 static struct regulator_consumer_supply fixed_reg_en_vdd_cpu_fixed_supply[] = {
565         REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
566 };
567
568 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_supply[] = {
569         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
570 };
571
572 /* VDD_3V3_COM controled by Wifi */
573 static struct regulator_consumer_supply fixed_reg_en_com_3v3_supply[] = {
574         REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
575         REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
576 };
577
578 /* VDD_1v8_COM controled by Wifi */
579 static struct regulator_consumer_supply fixed_reg_en_com_1v8_supply[] = {
580         REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
581         REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
582 };
583
584 /* EN_1V8_DISPLAY From TEGRA_GPIO_PU4 */
585 static struct regulator_consumer_supply fixed_reg_en_dvdd_lcd_supply[] = {
586         REGULATOR_SUPPLY("dvdd_lcd", NULL),
587 };
588
589 FIXED_REG(0,    battery,        battery,        NULL,
590         0,      0,      -1,
591         false,  true,   0,      3300, 0);
592
593 FIXED_REG(1,    modem_3v3,      modem_3v3,      palmas_rails(smps10_out1),
594         0,      0,      TEGRA_GPIO_PS2,
595         false,  true,   0,      3700,   0);
596
597 FIXED_REG(2,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   palmas_rails(smps6),
598         0,      0,      TEGRA_GPIO_PS5,
599         false,  true,   0,      5000,   5000);
600
601 FIXED_REG(3,    vdd_sd_slot,    vdd_sd_slot,    palmas_rails(smps6),
602         0,      0,      TEGRA_GPIO_PR0,
603         false,  true,   0,      3300,   0);
604
605 FIXED_REG(4,    1v8_ts, 1v8_ts, palmas_rails(smps8),
606         0,      0,      TEGRA_GPIO_PK1,
607         false,  true,   0,      1800,   0);
608
609 FIXED_REG(5,    3v3_ts, 3v3_ts, palmas_rails(smps6),
610         0,      0,      TEGRA_GPIO_PH0,
611         false,  true,   0,      3300,   0);
612
613 FIXED_REG(6,    1v8_display,    1v8_display,    NULL,
614         0,      0,      -1,
615         false,  true,   0,      1800,   0);
616
617 FIXED_REG(7,   vdd_cpu_fixed,  vdd_cpu_fixed,   NULL,
618         0,      1,      -1,
619         false,  true,   0,      1000,   0);
620
621 FIXED_REG(8,    lcd_bl, lcd_bl,
622         NULL,   0,      0,
623         TEGRA_GPIO_PH2, false,  true,   1,      5000, 1000);
624
625 FIXED_REG(9,    com_3v3,        com_3v3,
626         palmas_rails(smps6),    0,      0,
627         TEGRA_GPIO_PX1, false,  true,   0,      3300, 1000);
628
629 FIXED_REG(10,   com_1v8,        com_1v8,
630         palmas_rails(smps8),    0,      0,
631         TEGRA_GPIO_PX7, false,  true,   0,      1800, 1000);
632
633 FIXED_REG(11,   dvdd_lcd,       dvdd_lcd,
634         palmas_rails(smps8),    0,      0,
635         TEGRA_GPIO_PU4, false,  true,   1,      1800, 0);
636
637 /*
638  * Creating fixed regulator device tables
639  */
640 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
641 #define LOKI_E2545_FIXED_REG            \
642         ADD_FIXED_REG(battery),         \
643         ADD_FIXED_REG(modem_3v3),       \
644         ADD_FIXED_REG(vdd_hdmi_5v0),    \
645         ADD_FIXED_REG(vdd_sd_slot),     \
646         ADD_FIXED_REG(1v8_ts),          \
647         ADD_FIXED_REG(3v3_ts),          \
648         ADD_FIXED_REG(1v8_display),     \
649         ADD_FIXED_REG(vdd_cpu_fixed),   \
650         ADD_FIXED_REG(lcd_bl), \
651         ADD_FIXED_REG(com_3v3), \
652         ADD_FIXED_REG(com_1v8), \
653         ADD_FIXED_REG(dvdd_lcd),
654
655
656 static struct platform_device *fixed_reg_devs_e2545[] = {
657         LOKI_E2545_FIXED_REG
658 };
659 /************************ LOKI CL-DVFS DATA *********************/
660 #define LOKI_CPU_VDD_MAP_SIZE           33
661 #define LOKI_CPU_VDD_MIN_UV             704000
662 #define LOKI_CPU_VDD_STEP_UV            19200
663 #define LOKI_CPU_VDD_STEP_US            80
664
665 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
666 /* loki board parameters for cpu dfll */
667 static struct tegra_cl_dvfs_cfg_param loki_cl_dvfs_param = {
668         .sample_rate = 50000,
669
670         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
671         .cf = 10,
672         .ci = 0,
673         .cg = 2,
674
675         .droop_cut_value = 0xF,
676         .droop_restore_ramp = 0x0,
677         .scale_out_ramp = 0x0,
678 };
679
680 /* loki RT8812C volatge map */
681 static struct voltage_reg_map loki_cpu_vdd_map[LOKI_CPU_VDD_MAP_SIZE];
682 static inline int loki_fill_reg_map(int nominal_mv)
683 {
684         int i, uv, nominal_uv = 0;
685         for (i = 0; i < LOKI_CPU_VDD_MAP_SIZE; i++) {
686                 loki_cpu_vdd_map[i].reg_value = i;
687                 loki_cpu_vdd_map[i].reg_uV = uv =
688                         LOKI_CPU_VDD_MIN_UV + LOKI_CPU_VDD_STEP_UV * i;
689                 if (!nominal_uv && uv >= nominal_mv * 1000)
690                         nominal_uv = uv;
691         }
692         return nominal_uv;
693 }
694
695 /* loki dfll bypass device for legacy dvfs control */
696 static struct regulator_consumer_supply loki_dfll_bypass_consumers[] = {
697         REGULATOR_SUPPLY("vdd_cpu", NULL),
698 };
699 DFLL_BYPASS(loki, LOKI_CPU_VDD_MIN_UV, LOKI_CPU_VDD_STEP_UV,
700             LOKI_CPU_VDD_MAP_SIZE, LOKI_CPU_VDD_STEP_US, -1);
701
702 static struct tegra_cl_dvfs_platform_data loki_cl_dvfs_data = {
703         .dfll_clk_name = "dfll_cpu",
704         .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
705         .u.pmu_pwm = {
706                 .pwm_rate = 12750000,
707                 .pwm_bus = TEGRA_CL_DVFS_PWM_1WIRE_BUFFER,
708                 .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
709                 .out_gpio = TEGRA_GPIO_PU6,
710                 .out_enable_high = false,
711 #ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
712                 .dfll_bypass_dev = &loki_dfll_bypass_dev,
713 #endif
714         },
715         .vdd_map = loki_cpu_vdd_map,
716         .vdd_map_size = LOKI_CPU_VDD_MAP_SIZE,
717
718         .cfg_param = &loki_cl_dvfs_param,
719 };
720
721 static void loki_suspend_dfll_bypass(void)
722 {
723         __gpio_set_value(TEGRA_GPIO_PU6, 1); /* tristate external PWM buffer */
724 }
725
726 static void loki_resume_dfll_bypass(void)
727 {
728         __gpio_set_value(TEGRA_GPIO_PU6, 0); /* enable PWM buffer operations */
729 }
730 static int __init loki_cl_dvfs_init(void)
731 {
732         struct tegra_cl_dvfs_platform_data *data = NULL;
733         int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
734
735         {
736                 v = loki_fill_reg_map(v);
737                 data = &loki_cl_dvfs_data;
738                 if (data->u.pmu_pwm.dfll_bypass_dev) {
739                         /* this has to be exact to 1uV level from table */
740                         loki_dfll_bypass_init_data.constraints.init_uV = v;
741                         loki_suspend_data.suspend_dfll_bypass =
742                                 loki_suspend_dfll_bypass;
743                         loki_suspend_data.resume_dfll_bypass =
744                                 loki_resume_dfll_bypass;
745                 } else {
746                         (void)loki_dfll_bypass_dev;
747                 }
748         }
749
750
751         if (data) {
752                 data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
753                 tegra_cl_dvfs_device.dev.platform_data = data;
754                 platform_device_register(&tegra_cl_dvfs_device);
755         }
756         return 0;
757 }
758 #else
759 static inline int loki_cl_dvfs_init()
760 { return 0; }
761 #endif
762
763 int __init loki_rail_alignment_init(void)
764 {
765
766         tegra12x_vdd_cpu_align(LOKI_CPU_VDD_STEP_UV,
767                         LOKI_CPU_VDD_MIN_UV);
768         return 0;
769 }
770
771 int __init loki_regulator_init(void)
772 {
773         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
774         u32 pmc_ctrl;
775         int i;
776
777         /* TPS65913: Normal state of INT request line is LOW.
778          * configure the power management controller to trigger PMU
779          * interrupts when HIGH.
780          */
781         pmc_ctrl = readl(pmc + PMC_CTRL);
782         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
783         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
784                 pmic_platform.reg_data[i] = loki_reg_data[i];
785                 pmic_platform.reg_init[i] = loki_reg_init[i];
786         }
787         /* Set vdd_gpu init uV to 1V */
788         reg_idata_smps123.constraints.init_uV = 1000000;
789         reg_idata_smps9.constraints.enable_time = 250;
790
791         bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0);
792         i2c_register_board_info(4, palma_device,
793                         ARRAY_SIZE(palma_device));
794         i2c_register_board_info(0, bq2419x_boardinfo, 1);
795         i2c_register_board_info(0, loki_i2c_board_info_bq27441,
796                         ARRAY_SIZE(loki_i2c_board_info_bq27441));
797         platform_device_register(&power_supply_extcon_device);
798
799         loki_cl_dvfs_init();
800         return 0;
801 }
802
803 static int __init loki_fixed_regulator_init(void)
804 {
805         struct board_info pmu_board_info;
806         struct board_info bi;
807
808
809         if (!of_machine_is_compatible("nvidia,loki"))
810                 return 0;
811
812         tegra_get_board_info(&bi);
813         tegra_get_pmu_board_info(&pmu_board_info);
814
815         if (bi.board_id == BOARD_P2530) {
816                 fixed_reg_en_vdd_hdmi_5v0_pdata.gpio = TEGRA_GPIO_PFF0;
817                 fixed_reg_en_vdd_hdmi_5v0_pdata.enable_high = false;
818         }
819         if (pmu_board_info.board_id == BOARD_E2545)
820                 return platform_add_devices(fixed_reg_devs_e2545,
821                         ARRAY_SIZE(fixed_reg_devs_e2545));
822
823         return 0;
824 }
825
826 subsys_initcall_sync(loki_fixed_regulator_init);
827 int __init loki_edp_init(void)
828 {
829         unsigned int regulator_mA;
830
831         regulator_mA = get_maximum_cpu_current_supported();
832         if (!regulator_mA)
833                 regulator_mA = 16000;
834
835         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
836         tegra_init_cpu_edp_limits(regulator_mA);
837
838         /* gpu maximum current */
839         regulator_mA = 12000;
840         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
841
842         tegra_init_gpu_edp_limits(regulator_mA);
843         return 0;
844 }
845
846 static struct pid_thermal_gov_params soctherm_pid_params = {
847         .max_err_temp = 9000,
848         .max_err_gain = 1000,
849
850         .gain_p = 1000,
851         .gain_d = 0,
852
853         .up_compensation = 20,
854         .down_compensation = 20,
855 };
856
857 static struct thermal_zone_params soctherm_tzp = {
858         .governor_name = "pid_thermal_gov",
859         .governor_params = &soctherm_pid_params,
860 };
861
862 static struct tegra_tsensor_pmu_data tpdata_palmas = {
863         .reset_tegra = 1,
864         .pmu_16bit_ops = 0,
865         .controller_type = 0,
866         .pmu_i2c_addr = 0x58,
867         .i2c_controller_id = 4,
868         .poweroff_reg_addr = 0xa0,
869         .poweroff_reg_data = 0x0,
870 };
871
872 static struct soctherm_platform_data loki_soctherm_data = {
873         .therm = {
874                 [THERM_CPU] = {
875                         .zone_enable = true,
876                         .passive_delay = 1000,
877                         .hotspot_offset = 6000,
878                         .num_trips = 3,
879                         .trips = {
880                                 {
881                                         .cdev_type = "tegra-shutdown",
882                                         .trip_temp = 101000,
883                                         .trip_type = THERMAL_TRIP_CRITICAL,
884                                         .upper = THERMAL_NO_LIMIT,
885                                         .lower = THERMAL_NO_LIMIT,
886                                 },
887                                 {
888                                         .cdev_type = "tegra-heavy",
889                                         .trip_temp = 99000,
890                                         .trip_type = THERMAL_TRIP_HOT,
891                                         .upper = THERMAL_NO_LIMIT,
892                                         .lower = THERMAL_NO_LIMIT,
893                                 },
894                                 {
895                                         .cdev_type = "tegra-balanced",
896                                         .trip_temp = 89000,
897                                         .trip_type = THERMAL_TRIP_PASSIVE,
898                                         .upper = THERMAL_NO_LIMIT,
899                                         .lower = THERMAL_NO_LIMIT,
900                                 },
901                         },
902                         .tzp = &soctherm_tzp,
903                 },
904                 [THERM_GPU] = {
905                         .zone_enable = true,
906                         .passive_delay = 1000,
907                         .hotspot_offset = 6000,
908                         .num_trips = 2,
909                         .trips = {
910                                 {
911                                         .cdev_type = "tegra-shutdown",
912                                         .trip_temp = 103000,
913                                         .trip_type = THERMAL_TRIP_CRITICAL,
914                                         .upper = THERMAL_NO_LIMIT,
915                                         .lower = THERMAL_NO_LIMIT,
916                                 },
917                                 {
918                                         .cdev_type = "tegra-balanced",
919                                         .trip_temp = 91000,
920                                         .trip_type = THERMAL_TRIP_PASSIVE,
921                                         .upper = THERMAL_NO_LIMIT,
922                                         .lower = THERMAL_NO_LIMIT,
923                                 },
924 /*
925                                 {
926                                         .cdev_type = "gk20a_cdev",
927                                         .trip_temp = 101000,
928                                         .trip_type = THERMAL_TRIP_PASSIVE,
929                                         .upper = THERMAL_NO_LIMIT,
930                                         .lower = THERMAL_NO_LIMIT,
931                                 },
932                                 {
933                                         .cdev_type = "tegra-heavy",
934                                         .trip_temp = 101000,
935                                         .trip_type = THERMAL_TRIP_HOT,
936                                         .upper = THERMAL_NO_LIMIT,
937                                         .lower = THERMAL_NO_LIMIT,
938                                 },
939 */
940                         },
941                         .tzp = &soctherm_tzp,
942                 },
943                 [THERM_MEM] = {
944                         .zone_enable = true,
945                         .num_trips = 1,
946                         .trips = {
947                                 {
948                                         .cdev_type = "tegra-shutdown",
949                                         .trip_temp = 103000, /* = GPU shut */
950                                         .trip_type = THERMAL_TRIP_CRITICAL,
951                                         .upper = THERMAL_NO_LIMIT,
952                                         .lower = THERMAL_NO_LIMIT,
953                                 },
954                         },
955                 },
956                 [THERM_PLL] = {
957                         .zone_enable = true,
958                         .tzp = &soctherm_tzp,
959                 },
960         },
961         .throttle = {
962                 [THROTTLE_HEAVY] = {
963                         .priority = 100,
964                         .devs = {
965                                 [THROTTLE_DEV_CPU] = {
966                                         .enable = true,
967                                         .depth = 80,
968                                 },
969                                 [THROTTLE_DEV_GPU] = {
970                                         .enable = false,
971                                         .throttling_depth = "heavy_throttling",
972                                 },
973                         },
974                 },
975                 [THROTTLE_OC2] = {
976                         .throt_mode = BRIEF,
977                         .polarity = 1,
978                         .intr = false,
979                         .devs = {
980                                 [THROTTLE_DEV_CPU] = {
981                                         .enable = true,
982                                         .depth = 30,
983                                 },
984                                 [THROTTLE_DEV_GPU] = {
985                                         .enable = false,
986                                         .throttling_depth = "heavy_throttling",
987                                 },
988                         },
989                 },
990         },
991         .tshut_pmu_trip_data = &tpdata_palmas,
992 };
993
994 int __init loki_soctherm_init(void)
995 {
996         s32 base_cp, shft_cp;
997         u32 base_ft, shft_ft;
998
999         /* do this only for supported CP,FT fuses */
1000         if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
1001             (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
1002                 tegra_platform_edp_init(
1003                         loki_soctherm_data.therm[THERM_CPU].trips,
1004                         &loki_soctherm_data.therm[THERM_CPU].num_trips,
1005                         8000); /* edp temperature margin */
1006                 tegra_platform_gpu_edp_init(
1007                         loki_soctherm_data.therm[THERM_GPU].trips,
1008                         &loki_soctherm_data.therm[THERM_GPU].num_trips,
1009                         8000);
1010                 tegra_add_tj_trips(
1011                         loki_soctherm_data.therm[THERM_CPU].trips,
1012                         &loki_soctherm_data.therm[THERM_CPU].num_trips);
1013                 tegra_add_tgpu_trips(
1014                         loki_soctherm_data.therm[THERM_GPU].trips,
1015                         &loki_soctherm_data.therm[THERM_GPU].num_trips);
1016                 tegra_add_vc_trips(
1017                         loki_soctherm_data.therm[THERM_CPU].trips,
1018                         &loki_soctherm_data.therm[THERM_CPU].num_trips);
1019                 tegra_add_tpll_trips(
1020                         loki_soctherm_data.therm[THERM_PLL].trips,
1021                         &loki_soctherm_data.therm[THERM_PLL].num_trips);
1022         }
1023
1024         return tegra11_soctherm_init(&loki_soctherm_data);
1025 }