1a4144e4c8d14175940232134b4f89b3e54e7734
[linux-3.10.git] / arch / arm / mach-tegra / board-loki-power.c
1 /*
2  * arch/arm/mach-tegra/board-loki-power.c
3  *
4  * Copyright (c) 2013-2014 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/io.h>
24 #include <linux/regulator/fixed.h>
25 #include <linux/mfd/palmas.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/irq.h>
28 #include <linux/gpio.h>
29 #include <linux/regulator/tegra-dfll-bypass-regulator.h>
30 #include <linux/power/power_supply_extcon.h>
31 #include <linux/tegra-fuse.h>
32
33 #include <mach/irqs.h>
34 #include <mach/edp.h>
35 #include <mach/pinmux-t12.h>
36
37 #include <linux/pid_thermal_gov.h>
38
39 #include <asm/mach-types.h>
40
41 #include "pm.h"
42 #include "board.h"
43 #include "tegra-board-id.h"
44 #include "board-common.h"
45 #include "board-loki.h"
46 #include "board-pmu-defines.h"
47 #include "devices.h"
48 #include "iomap.h"
49 #include "tegra-board-id.h"
50 #include "dvfs.h"
51 #include "tegra_cl_dvfs.h"
52 #include "tegra11_soctherm.h"
53 #include "tegra3_tsensor.h"
54
55 #define PMC_CTRL                0x0
56 #define PMC_CTRL_INTR_LOW       (1 << 17)
57
58 static struct regulator_consumer_supply palmas_smps123_supply[] = {
59         REGULATOR_SUPPLY("vdd_gpu", NULL),
60         REGULATOR_SUPPLY("vdd_gpu_simon", NULL),
61 };
62
63 static struct regulator_consumer_supply palmas_smps45_supply[] = {
64         REGULATOR_SUPPLY("vdd_core", NULL),
65 };
66
67 static struct regulator_consumer_supply palmas_smps6_supply[] = {
68         REGULATOR_SUPPLY("vdd_3v3_sys", NULL),
69 };
70
71 static struct regulator_consumer_supply palmas_smps7_supply[] = {
72         REGULATOR_SUPPLY("vddio_ddr", NULL),
73         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
74 };
75
76 static struct regulator_consumer_supply palmas_smps7_a01_supply[] = {
77         REGULATOR_SUPPLY("vddio_ddr", NULL),
78         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
79 };
80
81 static struct regulator_consumer_supply palmas_smps8_supply[] = {
82         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
83         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
84         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
85         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
86         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
87         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
88         REGULATOR_SUPPLY("avdd_osc", NULL),
89         REGULATOR_SUPPLY("vddio_sys", NULL),
90         REGULATOR_SUPPLY("vddio_sys_2", NULL),
91         REGULATOR_SUPPLY("vddio_gmi", NULL),
92         REGULATOR_SUPPLY("pwrdet_nand", NULL),
93         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
94         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
95         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
96         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
97         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
98         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
99         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
100         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
101         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
102         REGULATOR_SUPPLY("vddio_audio", NULL),
103         REGULATOR_SUPPLY("pwrdet_audio", NULL),
104         REGULATOR_SUPPLY("vddio_uart", NULL),
105         REGULATOR_SUPPLY("pwrdet_uart", NULL),
106         REGULATOR_SUPPLY("vddio_bb", NULL),
107         REGULATOR_SUPPLY("pwrdet_bb", NULL),
108         REGULATOR_SUPPLY("vdd_dtv", NULL),
109         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
110         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
111         REGULATOR_SUPPLY("vddio_cam", "vi"),
112         REGULATOR_SUPPLY("pwrdet_cam", NULL),
113         REGULATOR_SUPPLY("vlogic", "0-0068"),
114         REGULATOR_SUPPLY("vid", "0-000c"),
115         REGULATOR_SUPPLY("vddio", "0-0077"),
116         REGULATOR_SUPPLY("vif", "2-0048"),
117         REGULATOR_SUPPLY("vif2", "2-0021"),
118 };
119
120 static struct regulator_consumer_supply palmas_smps9_supply[] = {
121         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
122 };
123
124 static struct regulator_consumer_supply palmas_smps10_out1_supply[] = {
125         REGULATOR_SUPPLY("vdd_5v0_cam", NULL),
126         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
127         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
128 };
129
130 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
131         REGULATOR_SUPPLY("avdd_pll_m", NULL),
132         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
133         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
134         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
135         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
136         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
137         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
138         REGULATOR_SUPPLY("avdd_pll_x", NULL),
139         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
140         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
141         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
142         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
143         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
144         REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
145         REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
146         REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo1_a01_supply[] = {
150         REGULATOR_SUPPLY("avdd_pll_m", NULL),
151         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
152         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
153         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
154         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
155         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
156         REGULATOR_SUPPLY("avdd_pll_x", NULL),
157         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
158         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
159         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
160         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
161         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
162         REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
163         REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
164         REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
165         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
166 };
167
168 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
169         REGULATOR_SUPPLY("avdd_lcd", NULL),
170         REGULATOR_SUPPLY("vana", "2-0048"),
171         REGULATOR_SUPPLY("vdd", "0-0039"),
172 };
173
174 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
175         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
176         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
177         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
178         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
179         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
180         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
181         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
182         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
183 };
184
185 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
186         REGULATOR_SUPPLY("vpp_fuse", NULL),
187 };
188
189 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
190         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.0"),
191         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
192 };
193
194 static struct regulator_consumer_supply palmas_ldo5_a01_supply[] = {
195         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
196 };
197
198 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
199         REGULATOR_SUPPLY("vdd_snsr", NULL),
200         REGULATOR_SUPPLY("vdd", "0-000c"),
201         REGULATOR_SUPPLY("vdd", "0-0077"),
202         REGULATOR_SUPPLY("vdd", "0-004c"),
203         REGULATOR_SUPPLY("vdd", "0-0068"),
204         REGULATOR_SUPPLY("vana", "2-0021"),
205 };
206
207 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
208         REGULATOR_SUPPLY("vdd_rtc", NULL),
209 };
210
211 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
212         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
213         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
214 };
215
216 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
217         REGULATOR_SUPPLY("vddio_hv", "tegradc.0"),
218         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
219         REGULATOR_SUPPLY("pwrdet_hv", NULL),
220         REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
221         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
222         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.0"),
223         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
224         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
225         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
226         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
227         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
228         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
229         REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
230         REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
231         REGULATOR_SUPPLY("hvdd_sata", "tegra-sata.0"),
232 };
233
234 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
235         /*
236         Check if LDOLN has better jitter on HDMI pll, than LDO5
237         */
238 };
239
240 static struct regulator_consumer_supply palmas_regen1_supply[] = {
241         /*
242         Backup/Boost for smps6: vdd_3v3_sys
243         */
244 };
245
246 static struct regulator_consumer_supply palmas_regen2_supply[] = {
247         /*
248         Backup/Boost for smps10: vdd_5v0_sys
249         */
250 };
251
252 PALMAS_REGS_PDATA(smps123, 650,  1400, NULL, 0, 1, 1, NORMAL,
253                 0, 0, 0, 0, 0);
254 PALMAS_REGS_PDATA(smps45, 700,  1250, NULL, 0, 0, 0, NORMAL,
255                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 2500, 0);
256 PALMAS_REGS_PDATA(smps6, 3300,  3300, NULL, 1, 1, 1, NORMAL,
257                 0, 0, 0, 0, 0);
258 PALMAS_REGS_PDATA(smps7, 1350,  1350, NULL, 1, 1, 1, NORMAL,
259                 0, 0, 0, 0, 0);
260 PALMAS_REGS_PDATA(smps7_a01, 1500,  1500, NULL, 1, 1, 1, NORMAL,
261                 0, 0, 0, 0, 0);
262 PALMAS_REGS_PDATA(smps8, 1800,  1800, NULL, 1, 1, 1, NORMAL,
263                 0, 0, 0, 0, 0);
264 PALMAS_REGS_PDATA(smps9, 2800,  2800, NULL, 0, 0, 1, FAST,
265                 0, 0, 0, 0, 0);
266 PALMAS_REGS_PDATA(smps10_out1, 5000,  5000, NULL, 1, 1, 1, 0,
267                 0, 0, 0, 0, 0);
268 PALMAS_REGS_PDATA(ldo1, 1050,  1050, palmas_rails(smps8), 0, 0, 1, 0,
269                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
270 PALMAS_REGS_PDATA(ldo1_a01, 1050,  1050, palmas_rails(smps8), 1, 1, 1, 0,
271                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
272 PALMAS_REGS_PDATA(ldo2, 2800,  3000, palmas_rails(smps6), 0, 0, 1, 0,
273                 0, 0, 0, 0, 0);
274 PALMAS_REGS_PDATA(ldo3, 1200,  1200, palmas_rails(smps8), 1, 1, 1, 0,
275                 0, 0, 0, 0, 0);
276 PALMAS_REGS_PDATA(ldo4, 1800,  1800, palmas_rails(smps6), 0, 0, 1, 0,
277                 0, 0, 0, 0, 0);
278 PALMAS_REGS_PDATA(ldo5, 1200,  1200, palmas_rails(smps8), 0, 0, 1, 0,
279                 0, 0, 0, 0, 0);
280 PALMAS_REGS_PDATA(ldo5_a01, 1200,  1200, palmas_rails(smps8), 1, 1, 1, 0,
281                 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
282 PALMAS_REGS_PDATA(ldo6, 2800,  2800, palmas_rails(smps6), 0, 0, 1, 0,
283                 0, 0, 0, 0, 0);
284 PALMAS_REGS_PDATA(ldo8, 900,  900, NULL, 1, 1, 1, 0,
285                 0, 0, 0, 0, 0);
286 PALMAS_REGS_PDATA(ldo9, 1800,  3300, palmas_rails(smps6), 0, 0, 1, 0,
287                 0, 0, 0, 0, 0);
288 PALMAS_REGS_PDATA(ldoln, 2800, 3300, NULL, 0, 0, 1, 0,
289                 0, 0, 0, 0, 0);
290 PALMAS_REGS_PDATA(ldousb, 2300,  3300, NULL, 0, 0, 1, 0,
291                 0, 0, 0, 0, 0);
292 PALMAS_REGS_PDATA(regen1, 3300,  3300, NULL, 0, 0, 0, 0,
293                 0, 0, 0, 0, 0);
294 PALMAS_REGS_PDATA(regen2, 5000,  5000, NULL, 1, 1, 0, 0,
295                 0, 0, 0, 0, 0);
296
297
298 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
299 static struct regulator_init_data *loki_reg_data[PALMAS_NUM_REGS] = {
300         NULL,
301         PALMAS_REG_PDATA(smps123),
302         NULL,
303         PALMAS_REG_PDATA(smps45),
304         NULL,
305         PALMAS_REG_PDATA(smps6),
306         PALMAS_REG_PDATA(smps7),
307         PALMAS_REG_PDATA(smps8),
308         PALMAS_REG_PDATA(smps9),
309         NULL,
310         PALMAS_REG_PDATA(smps10_out1),
311         PALMAS_REG_PDATA(ldo1),
312         PALMAS_REG_PDATA(ldo2),
313         PALMAS_REG_PDATA(ldo3),
314         PALMAS_REG_PDATA(ldo4),
315         PALMAS_REG_PDATA(ldo5),
316         PALMAS_REG_PDATA(ldo6),
317         NULL,
318         PALMAS_REG_PDATA(ldo8),
319         PALMAS_REG_PDATA(ldo9),
320         NULL,
321         NULL,
322         NULL,
323         NULL,
324         NULL,
325         PALMAS_REG_PDATA(ldoln),
326         PALMAS_REG_PDATA(ldousb),
327         PALMAS_REG_PDATA(regen1),
328         PALMAS_REG_PDATA(regen2),
329         NULL,
330         NULL,
331         NULL,
332 };
333
334 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
335 static struct palmas_reg_init *loki_reg_init[PALMAS_NUM_REGS] = {
336         NULL,
337         PALMAS_REG_INIT_DATA(smps123),
338         NULL,
339         PALMAS_REG_INIT_DATA(smps45),
340         NULL,
341         PALMAS_REG_INIT_DATA(smps6),
342         PALMAS_REG_INIT_DATA(smps7),
343         PALMAS_REG_INIT_DATA(smps8),
344         PALMAS_REG_INIT_DATA(smps9),
345         NULL,
346         PALMAS_REG_INIT_DATA(smps10_out1),
347         PALMAS_REG_INIT_DATA(ldo1),
348         PALMAS_REG_INIT_DATA(ldo2),
349         PALMAS_REG_INIT_DATA(ldo3),
350         PALMAS_REG_INIT_DATA(ldo4),
351         PALMAS_REG_INIT_DATA(ldo5),
352         PALMAS_REG_INIT_DATA(ldo6),
353         NULL,
354         PALMAS_REG_INIT_DATA(ldo8),
355         PALMAS_REG_INIT_DATA(ldo9),
356         NULL,
357         NULL,
358         NULL,
359         NULL,
360         NULL,
361         PALMAS_REG_INIT_DATA(ldoln),
362         PALMAS_REG_INIT_DATA(ldousb),
363         PALMAS_REG_INIT_DATA(regen1),
364         PALMAS_REG_INIT_DATA(regen2),
365         NULL,
366         NULL,
367         NULL,
368 };
369
370 #define PALMAS_GPADC_IIO_MAP(_ch, _dev_name, _name)             \
371         {                                                       \
372                 .adc_channel_label = PALMAS_DATASHEET_NAME(_ch),\
373                 .consumer_dev_name = _dev_name,                 \
374                 .consumer_channel = _name,                      \
375         }
376
377 static struct iio_map palmas_adc_iio_maps[] = {
378         PALMAS_GPADC_IIO_MAP(IN1, "generic-adc-thermal.0", "thermistor"),
379         PALMAS_GPADC_IIO_MAP(IN3, "generic-adc-thermal.1", "tdiode"),
380         PALMAS_GPADC_IIO_MAP(NULL, NULL, NULL),
381 };
382
383 static struct palmas_gpadc_platform_data palmas_adc_pdata = {
384         /* If ch3_dual_current is true, it will measure ch3 input signal with
385          * ch3_current and the next current of ch3_current.
386          * So this system will use 400uA and 800uA for ch3 measurement. */
387         .ch3_current = 400,     /* 0uA, 10uA, 400uA, 800uA */
388         .ch3_dual_current = true,
389         .extended_delay = true,
390         .iio_maps = palmas_adc_iio_maps,
391 };
392
393 static struct palmas_pinctrl_config palmas_pincfg[] = {
394         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
395         PALMAS_PINMUX("vac", "vac", NULL, NULL),
396         PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
397         PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
398         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
399         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
400         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
401         PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
402         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
403         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
404 };
405
406 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
407         .pincfg = palmas_pincfg,
408         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
409         .dvfs1_enable = true,
410         .dvfs2_enable = false,
411 };
412
413 static struct palmas_pmic_platform_data pmic_platform = {
414 };
415
416 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
417         {
418                 .clk32k_id = PALMAS_CLOCK32KG,
419                 .enable = true,
420         }, {
421                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
422                 .enable = true,
423         },
424 };
425
426 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
427         .connection_name = "palmas-extcon",
428         .enable_vbus_detection = true,
429 };
430
431 static struct palmas_platform_data palmas_pdata = {
432         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
433         .irq_base = PALMAS_TEGRA_IRQ_BASE,
434         .pmic_pdata = &pmic_platform,
435         .gpadc_pdata = &palmas_adc_pdata,
436         .pinctrl_pdata = &palmas_pinctrl_pdata,
437         .clk32k_init_data =  palmas_clk32k_idata,
438         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
439         .extcon_pdata = &palmas_extcon_pdata,
440 };
441
442 static struct i2c_board_info palma_device[] = {
443         {
444                 I2C_BOARD_INFO("tps65913", 0x58),
445                 .irq            = INT_EXTERNAL_PMU,
446                 .platform_data  = &palmas_pdata,
447         },
448 };
449
450 static struct tegra_suspend_platform_data loki_suspend_data = {
451         .cpu_timer      = 3500,
452         .cpu_off_timer  = 300,
453         .suspend_mode   = TEGRA_SUSPEND_LP0,
454         .core_timer     = 0x157e,
455         .core_off_timer = 2000,
456         .corereq_high   = true,
457         .sysclkreq_high = true,
458         .cpu_lp2_min_residency = 1000,
459         .min_residency_crail = 20000,
460 };
461
462 int __init loki_suspend_init(void)
463 {
464         struct board_info bi;
465         tegra_get_board_info(&bi);
466
467         /* reduce cpu_power_good_time for loki ffd fab a3 or higher */
468         if (bi.board_id == BOARD_P2530 && bi.fab >= 0xa3)
469                 loki_suspend_data.cpu_timer = 500;
470
471         tegra_init_suspend(&loki_suspend_data);
472         return 0;
473 }
474
475 static struct power_supply_extcon_plat_data extcon_pdata = {
476         .extcon_name = "tegra-udc",
477 };
478
479 static struct platform_device power_supply_extcon_device = {
480         .name   = "power-supply-extcon",
481         .id     = -1,
482         .dev    = {
483                 .platform_data = &extcon_pdata,
484         },
485 };
486
487 /* Macro for defining fixed regulator sub device data */
488 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
489 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
490         _always_on, _boot_on, _gpio_nr, _open_drain,            \
491         _active_high, _boot_state, _millivolts, _sdelay)        \
492 static struct regulator_init_data ri_data_##_var =              \
493 {                                                               \
494         .supply_regulator = _in_supply,                         \
495         .num_consumer_supplies =                                \
496         ARRAY_SIZE(fixed_reg_en_##_name##_supply),              \
497         .consumer_supplies = fixed_reg_en_##_name##_supply,     \
498         .constraints = {                                        \
499                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
500                                 REGULATOR_MODE_STANDBY),        \
501                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
502                                 REGULATOR_CHANGE_STATUS |       \
503                                 REGULATOR_CHANGE_VOLTAGE),      \
504                 .always_on = _always_on,                        \
505                 .boot_on = _boot_on,                            \
506         },                                                      \
507 };                                                              \
508 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata =        \
509 {                                                               \
510         .supply_name = FIXED_SUPPLY(_name),                     \
511         .microvolts = _millivolts * 1000,                       \
512         .gpio = _gpio_nr,                                       \
513         .gpio_is_open_drain = _open_drain,                      \
514         .enable_high = _active_high,                            \
515         .enabled_at_boot = _boot_state,                         \
516         .init_data = &ri_data_##_var,                           \
517         .startup_delay = _sdelay                                \
518 };                                                              \
519 static struct platform_device fixed_reg_en_##_var##_dev = {     \
520         .name = "reg-fixed-voltage",                            \
521         .id = _id,                                              \
522         .dev = {                                                \
523                 .platform_data = &fixed_reg_en_##_var##_pdata,  \
524         },                                                      \
525 }
526
527 /* Always ON Battery regulator */
528 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
529                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
530                 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
531                 REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
532                 REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
533 };
534
535 static struct regulator_consumer_supply fixed_reg_en_modem_3v3_supply[] = {
536         REGULATOR_SUPPLY("vdd_wwan_mdm", NULL),
537 };
538
539 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
540         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.0"),
541         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
542 };
543
544 static struct regulator_consumer_supply fixed_reg_en_vdd_sd_slot_supply[] = {
545         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
546 };
547
548 static struct regulator_consumer_supply fixed_reg_en_1v8_ts_supply[] = {
549         REGULATOR_SUPPLY("dvdd", "spi0.0"),
550 };
551
552 static struct regulator_consumer_supply fixed_reg_en_3v3_ts_supply[] = {
553         REGULATOR_SUPPLY("avdd", "spi0.0"),
554 };
555
556 static struct regulator_consumer_supply fixed_reg_en_1v8_display_supply[] = {
557         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
558 };
559
560 static struct regulator_consumer_supply fixed_reg_en_vdd_cpu_fixed_supply[] = {
561         REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
562 };
563
564 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_supply[] = {
565         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
566 };
567
568 /* VDD_3V3_COM controled by Wifi */
569 static struct regulator_consumer_supply fixed_reg_en_com_3v3_supply[] = {
570         REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
571         REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
572 };
573
574 /* VDD_1v8_COM controled by Wifi */
575 static struct regulator_consumer_supply fixed_reg_en_com_1v8_supply[] = {
576         REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
577         REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
578 };
579
580 /* EN_1V8_DISPLAY From TEGRA_GPIO_PU4 */
581 static struct regulator_consumer_supply fixed_reg_en_dvdd_lcd_supply[] = {
582         REGULATOR_SUPPLY("dvdd_lcd", NULL),
583 };
584
585 FIXED_REG(0,    battery,        battery,        NULL,
586         0,      0,      -1,
587         false,  true,   0,      3300, 0);
588
589 FIXED_REG(1,    modem_3v3,      modem_3v3,      palmas_rails(smps10_out1),
590         0,      0,      TEGRA_GPIO_PS2,
591         false,  true,   0,      3700,   0);
592
593 FIXED_REG(2,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   palmas_rails(smps6),
594         0,      0,      TEGRA_GPIO_PS5,
595         false,  true,   0,      5000,   5000);
596
597 FIXED_REG(3,    vdd_sd_slot,    vdd_sd_slot,    palmas_rails(smps6),
598         0,      0,      TEGRA_GPIO_PR0,
599         false,  true,   0,      3300,   0);
600
601 FIXED_REG(4,    1v8_ts, 1v8_ts, palmas_rails(smps8),
602         0,      0,      TEGRA_GPIO_PK1,
603         false,  true,   0,      1800,   0);
604
605 FIXED_REG(5,    3v3_ts, 3v3_ts, palmas_rails(smps6),
606         0,      0,      TEGRA_GPIO_PH0,
607         false,  true,   0,      3300,   0);
608
609 FIXED_REG(6,    1v8_display,    1v8_display,    NULL,
610         0,      0,      -1,
611         false,  true,   0,      1800,   0);
612
613 FIXED_REG(7,   vdd_cpu_fixed,  vdd_cpu_fixed,   NULL,
614         0,      1,      -1,
615         false,  true,   0,      1000,   0);
616
617 FIXED_REG(8,    lcd_bl, lcd_bl,
618         NULL,   0,      0,
619         TEGRA_GPIO_PH2, false,  true,   1,      5000, 1000);
620
621 FIXED_REG(9,    com_3v3,        com_3v3,
622         palmas_rails(smps6),    0,      0,
623         TEGRA_GPIO_PX1, false,  true,   0,      3300, 1000);
624
625 FIXED_REG(10,   com_1v8,        com_1v8,
626         palmas_rails(smps8),    0,      0,
627         TEGRA_GPIO_PX7, false,  true,   0,      1800, 1000);
628
629 FIXED_REG(11,   dvdd_lcd,       dvdd_lcd,
630         palmas_rails(smps8),    0,      0,
631         TEGRA_GPIO_PU4, false,  true,   1,      1800, 0);
632
633 /*
634  * Creating fixed regulator device tables
635  */
636 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
637 #define LOKI_E2545_FIXED_REG            \
638         ADD_FIXED_REG(battery),         \
639         ADD_FIXED_REG(modem_3v3),       \
640         ADD_FIXED_REG(vdd_hdmi_5v0),    \
641         ADD_FIXED_REG(vdd_sd_slot),     \
642         ADD_FIXED_REG(1v8_ts),          \
643         ADD_FIXED_REG(3v3_ts),          \
644         ADD_FIXED_REG(1v8_display),     \
645         ADD_FIXED_REG(vdd_cpu_fixed),   \
646         ADD_FIXED_REG(lcd_bl), \
647         ADD_FIXED_REG(com_3v3), \
648         ADD_FIXED_REG(com_1v8), \
649         ADD_FIXED_REG(dvdd_lcd),
650
651
652 static struct platform_device *fixed_reg_devs_e2545[] = {
653         LOKI_E2545_FIXED_REG
654 };
655 /************************ LOKI CL-DVFS DATA *********************/
656 #define LOKI_CPU_VDD_MAP_SIZE           33
657 #define LOKI_CPU_VDD_MIN_UV             703000
658 #define LOKI_CPU_VDD_STEP_UV            19200
659 #define LOKI_CPU_VDD_STEP_US            80
660
661 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
662 /* loki board parameters for cpu dfll */
663 static struct tegra_cl_dvfs_cfg_param loki_cl_dvfs_param = {
664         .sample_rate = 50000,
665
666         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
667         .cf = 10,
668         .ci = 0,
669         .cg = 2,
670
671         .droop_cut_value = 0xF,
672         .droop_restore_ramp = 0x0,
673         .scale_out_ramp = 0x0,
674 };
675
676 /* loki RT8812C volatge map */
677 static struct voltage_reg_map loki_cpu_vdd_map[LOKI_CPU_VDD_MAP_SIZE];
678 static inline int loki_fill_reg_map(int nominal_mv)
679 {
680         int i, uv, nominal_uv = 0;
681         for (i = 0; i < LOKI_CPU_VDD_MAP_SIZE; i++) {
682                 loki_cpu_vdd_map[i].reg_value = i;
683                 loki_cpu_vdd_map[i].reg_uV = uv =
684                         LOKI_CPU_VDD_MIN_UV + LOKI_CPU_VDD_STEP_UV * i;
685                 if (!nominal_uv && uv >= nominal_mv * 1000)
686                         nominal_uv = uv;
687         }
688         return nominal_uv;
689 }
690
691 /* loki dfll bypass device for legacy dvfs control */
692 static struct regulator_consumer_supply loki_dfll_bypass_consumers[] = {
693         REGULATOR_SUPPLY("vdd_cpu", NULL),
694 };
695 DFLL_BYPASS(loki, LOKI_CPU_VDD_MIN_UV, LOKI_CPU_VDD_STEP_UV,
696             LOKI_CPU_VDD_MAP_SIZE, LOKI_CPU_VDD_STEP_US, -1);
697
698 static struct tegra_cl_dvfs_platform_data loki_cl_dvfs_data = {
699         .dfll_clk_name = "dfll_cpu",
700         .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
701         .u.pmu_pwm = {
702                 .pwm_rate = 12750000,
703                 .pwm_bus = TEGRA_CL_DVFS_PWM_1WIRE_BUFFER,
704                 .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
705                 .out_gpio = TEGRA_GPIO_PU6,
706                 .out_enable_high = false,
707 #ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
708                 .dfll_bypass_dev = &loki_dfll_bypass_dev,
709 #endif
710         },
711         .vdd_map = loki_cpu_vdd_map,
712         .vdd_map_size = LOKI_CPU_VDD_MAP_SIZE,
713
714         .cfg_param = &loki_cl_dvfs_param,
715 };
716
717 static void loki_suspend_dfll_bypass(void)
718 {
719         __gpio_set_value(TEGRA_GPIO_PU6, 1); /* tristate external PWM buffer */
720 }
721
722 static void loki_resume_dfll_bypass(void)
723 {
724         __gpio_set_value(TEGRA_GPIO_PU6, 0); /* enable PWM buffer operations */
725 }
726 static int __init loki_cl_dvfs_init(void)
727 {
728         struct tegra_cl_dvfs_platform_data *data = NULL;
729         int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
730
731         {
732                 v = loki_fill_reg_map(v);
733                 data = &loki_cl_dvfs_data;
734                 if (data->u.pmu_pwm.dfll_bypass_dev) {
735                         /* this has to be exact to 1uV level from table */
736                         loki_dfll_bypass_init_data.constraints.init_uV = v;
737                         loki_suspend_data.suspend_dfll_bypass =
738                                 loki_suspend_dfll_bypass;
739                         loki_suspend_data.resume_dfll_bypass =
740                                 loki_resume_dfll_bypass;
741                 } else {
742                         (void)loki_dfll_bypass_dev;
743                 }
744         }
745
746         data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
747         tegra_cl_dvfs_device.dev.platform_data = data;
748         platform_device_register(&tegra_cl_dvfs_device);
749         return 0;
750 }
751 #else
752 static inline int loki_cl_dvfs_init()
753 { return 0; }
754 #endif
755
756 int __init loki_rail_alignment_init(void)
757 {
758
759         tegra12x_vdd_cpu_align(LOKI_CPU_VDD_STEP_UV,
760                         LOKI_CPU_VDD_MIN_UV);
761         return 0;
762 }
763
764 int __init loki_regulator_init(void)
765 {
766         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
767         u32 pmc_ctrl;
768         int i;
769         struct board_info bi;
770
771         /* TPS65913: Normal state of INT request line is LOW.
772          * configure the power management controller to trigger PMU
773          * interrupts when HIGH.
774          */
775         pmc_ctrl = readl(pmc + PMC_CTRL);
776         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
777         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
778                 pmic_platform.reg_data[i] = loki_reg_data[i];
779                 pmic_platform.reg_init[i] = loki_reg_init[i];
780         }
781         /* Set vdd_gpu init uV to 1V */
782         reg_idata_smps123.constraints.init_uV = 1000000;
783         reg_idata_smps9.constraints.enable_time = 250;
784
785         i2c_register_board_info(4, palma_device,
786                         ARRAY_SIZE(palma_device));
787         tegra_get_board_info(&bi);
788         if (bi.board_id == BOARD_P2530 && bi.fab == 0xa1) {
789                 pmic_platform.reg_data[PALMAS_REG_SMPS7] =
790                         PALMAS_REG_PDATA(smps7_a01);
791                 pmic_platform.reg_init[PALMAS_REG_SMPS7] =
792                         PALMAS_REG_INIT_DATA(smps7_a01);
793                 pmic_platform.reg_data[PALMAS_REG_LDO1] =
794                         PALMAS_REG_PDATA(ldo1_a01);
795                 pmic_platform.reg_init[PALMAS_REG_LDO1] =
796                         PALMAS_REG_INIT_DATA(ldo1_a01);
797                 pmic_platform.reg_data[PALMAS_REG_LDO5] =
798                         PALMAS_REG_PDATA(ldo5_a01);
799                 pmic_platform.reg_init[PALMAS_REG_LDO5] =
800                         PALMAS_REG_INIT_DATA(ldo5_a01);
801         }
802         platform_device_register(&power_supply_extcon_device);
803
804         loki_cl_dvfs_init();
805         return 0;
806 }
807
808 static int __init loki_fixed_regulator_init(void)
809 {
810         struct board_info pmu_board_info;
811         struct board_info bi;
812
813
814         if (!of_machine_is_compatible("nvidia,loki"))
815                 return 0;
816
817         tegra_get_board_info(&bi);
818         tegra_get_pmu_board_info(&pmu_board_info);
819
820         if (bi.board_id == BOARD_P2530) {
821                 fixed_reg_en_vdd_hdmi_5v0_pdata.gpio = TEGRA_GPIO_PFF0;
822                 fixed_reg_en_vdd_hdmi_5v0_pdata.enable_high = false;
823         }
824         if (pmu_board_info.board_id == BOARD_E2545)
825                 return platform_add_devices(fixed_reg_devs_e2545,
826                         ARRAY_SIZE(fixed_reg_devs_e2545));
827
828         return 0;
829 }
830
831 subsys_initcall_sync(loki_fixed_regulator_init);
832 int __init loki_edp_init(void)
833 {
834         unsigned int regulator_mA;
835
836         regulator_mA = get_maximum_cpu_current_supported();
837         if (!regulator_mA)
838                 regulator_mA = 14000;
839
840         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
841         tegra_init_cpu_edp_limits(regulator_mA);
842
843         /* gpu maximum current */
844         regulator_mA = 14000;
845         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
846
847         tegra_init_gpu_edp_limits(regulator_mA);
848         return 0;
849 }
850
851 static struct pid_thermal_gov_params soctherm_pid_params = {
852         .max_err_temp = 9000,
853         .max_err_gain = 1000,
854
855         .gain_p = 1000,
856         .gain_d = 0,
857
858         .up_compensation = 20,
859         .down_compensation = 20,
860 };
861
862 static struct thermal_zone_params soctherm_tzp = {
863         .governor_name = "pid_thermal_gov",
864         .governor_params = &soctherm_pid_params,
865 };
866
867 static struct tegra_tsensor_pmu_data tpdata_palmas = {
868         .reset_tegra = 1,
869         .pmu_16bit_ops = 0,
870         .controller_type = 0,
871         .pmu_i2c_addr = 0x58,
872         .i2c_controller_id = 4,
873         .poweroff_reg_addr = 0xa0,
874         .poweroff_reg_data = 0x0,
875 };
876
877 static struct soctherm_platform_data loki_soctherm_data = {
878         .therm = {
879                 [THERM_CPU] = {
880                         .zone_enable = true,
881                         .passive_delay = 1000,
882                         .hotspot_offset = 6000,
883                         .num_trips = 3,
884                         .trips = {
885                                 {
886                                         .cdev_type = "tegra-shutdown",
887                                         .trip_temp = 101000,
888                                         .trip_type = THERMAL_TRIP_CRITICAL,
889                                         .upper = THERMAL_NO_LIMIT,
890                                         .lower = THERMAL_NO_LIMIT,
891                                 },
892                                 {
893                                         .cdev_type = "tegra-heavy",
894                                         .trip_temp = 98000,
895                                         .trip_type = THERMAL_TRIP_HOT,
896                                         .upper = THERMAL_NO_LIMIT,
897                                         .lower = THERMAL_NO_LIMIT,
898                                 },
899                                 {
900                                         .cdev_type = "tegra-balanced",
901                                         .trip_temp = 88000,
902                                         .trip_type = THERMAL_TRIP_PASSIVE,
903                                         .upper = THERMAL_NO_LIMIT,
904                                         .lower = THERMAL_NO_LIMIT,
905                                 },
906                         },
907                         .tzp = &soctherm_tzp,
908                 },
909                 [THERM_GPU] = {
910                         .zone_enable = true,
911                         .passive_delay = 1000,
912                         .hotspot_offset = 6000,
913                         .num_trips = 3,
914                         .trips = {
915                                 {
916                                         .cdev_type = "tegra-shutdown",
917                                         .trip_temp = 98000,
918                                         .trip_type = THERMAL_TRIP_CRITICAL,
919                                         .upper = THERMAL_NO_LIMIT,
920                                         .lower = THERMAL_NO_LIMIT,
921                                 },
922                                 {
923                                         .cdev_type = "tegra-heavy",
924                                         .trip_temp = 95000,
925                                         .trip_type = THERMAL_TRIP_HOT,
926                                         .upper = THERMAL_NO_LIMIT,
927                                         .lower = THERMAL_NO_LIMIT,
928                                 },
929                                 {
930                                         .cdev_type = "tegra-balanced",
931                                         .trip_temp = 85000,
932                                         .trip_type = THERMAL_TRIP_PASSIVE,
933                                         .upper = THERMAL_NO_LIMIT,
934                                         .lower = THERMAL_NO_LIMIT,
935                                 },
936                         },
937                         .tzp = &soctherm_tzp,
938                 },
939                 [THERM_MEM] = {
940                         .zone_enable = true,
941                         .num_trips = 1,
942                         .trips = {
943                                 {
944                                         .cdev_type = "tegra-shutdown",
945                                         .trip_temp = 103000, /* = GPU shut */
946                                         .trip_type = THERMAL_TRIP_CRITICAL,
947                                         .upper = THERMAL_NO_LIMIT,
948                                         .lower = THERMAL_NO_LIMIT,
949                                 },
950                         },
951                 },
952                 [THERM_PLL] = {
953                         .zone_enable = true,
954                         .tzp = &soctherm_tzp,
955                 },
956         },
957         .throttle = {
958                 [THROTTLE_HEAVY] = {
959                         .priority = 100,
960                         .devs = {
961                                 [THROTTLE_DEV_CPU] = {
962                                         .enable = true,
963                                         .depth = 80,
964                                 },
965                                 [THROTTLE_DEV_GPU] = {
966                                         .enable = true,
967                                         .throttling_depth = "heavy_throttling",
968                                 },
969                         },
970                 },
971                 [THROTTLE_OC2] = {
972                         .throt_mode = BRIEF,
973                         .polarity = 1,
974                         .intr = false,
975                         .devs = {
976                                 [THROTTLE_DEV_CPU] = {
977                                         .enable = true,
978                                         .depth = 30,
979                                 },
980                                 [THROTTLE_DEV_GPU] = {
981                                         .enable = true,
982                                         .throttling_depth = "heavy_throttling",
983                                 },
984                         },
985                 },
986         },
987         .tshut_pmu_trip_data = &tpdata_palmas,
988 };
989
990 int __init loki_soctherm_init(void)
991 {
992         s32 base_cp, shft_cp;
993         u32 base_ft, shft_ft;
994
995         /* do this only for supported CP,FT fuses */
996         if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
997             (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
998                 tegra_platform_edp_init(
999                         loki_soctherm_data.therm[THERM_CPU].trips,
1000                         &loki_soctherm_data.therm[THERM_CPU].num_trips,
1001                         8000); /* edp temperature margin */
1002                 tegra_platform_gpu_edp_init(
1003                         loki_soctherm_data.therm[THERM_GPU].trips,
1004                         &loki_soctherm_data.therm[THERM_GPU].num_trips,
1005                         8000);
1006                 tegra_add_cpu_vmax_trips(
1007                         loki_soctherm_data.therm[THERM_CPU].trips,
1008                         &loki_soctherm_data.therm[THERM_CPU].num_trips);
1009                 tegra_add_tgpu_trips(
1010                         loki_soctherm_data.therm[THERM_GPU].trips,
1011                         &loki_soctherm_data.therm[THERM_GPU].num_trips);
1012                 tegra_add_vc_trips(
1013                         loki_soctherm_data.therm[THERM_CPU].trips,
1014                         &loki_soctherm_data.therm[THERM_CPU].num_trips);
1015                 tegra_add_core_vmax_trips(
1016                         loki_soctherm_data.therm[THERM_PLL].trips,
1017                         &loki_soctherm_data.therm[THERM_PLL].num_trips);
1018                 tegra_add_cpu_vmin_trips(
1019                         loki_soctherm_data.therm[THERM_CPU].trips,
1020                         &loki_soctherm_data.therm[THERM_CPU].num_trips);
1021                 tegra_add_gpu_vmin_trips(
1022                         loki_soctherm_data.therm[THERM_GPU].trips,
1023                         &loki_soctherm_data.therm[THERM_GPU].num_trips);
1024                 /*PLL soctherm is being used for SOC vmin*/
1025                 tegra_add_core_vmin_trips(
1026                         loki_soctherm_data.therm[THERM_PLL].trips,
1027                         &loki_soctherm_data.therm[THERM_PLL].num_trips);
1028         }
1029
1030         return tegra11_soctherm_init(&loki_soctherm_data);
1031 }